PD - 9.1246D IRF7404 HEXFET(R) Power MOSFET l l l l l l l Generation V Technology Ultra Low On-Resistance P-Channel Mosfet Surface Mount Available in Tape & Reel Dynamic dv/dt Rating Fast Switching A D S 1 8 S 2 7 D S 3 6 D G 4 5 D VDSS = -20V RDS(on) = 0.040 Top View Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques. Power dissipation of greater than 0.8W is possible in a typical PCB mount application. SO-8 Absolute Maximum Ratings Parameter ID @ TA = 25C ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C VGS dv/dt TJ, TSTG Max. 10 Sec. Pulsed Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Continuous Drain Current, VGS @ -4.5V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Junction and Storage Temperature Range Units -7.7 -6.7 -5.4 -27 2.5 0.02 12 -5.0 -55 to + 150 A W W/C V V/ns C Thermal Resistance Ratings Parameter RJA www.irf.com Maximum Junction-to-Ambient Typ. Max. Units 50 C/W 1 11/13/06 IRF7404 Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(ON) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Min. -20 -0.70 6.8 Typ. Max. Units Conditions V V GS = 0V, ID = -250A -0.012 V/C Reference to 25C, ID = -1mA 0.040 V GS = -4.5V, ID = -3.2A 0.060 V GS = -2.7V, ID = -2.7A V V DS = VGS, ID = -250A S V DS = -15V, ID = -3.2A -1.0 V DS = -16V, VGS = 0V A -25 V DS = -16V, VGS = 0V, TJ = 125C -100 V GS = -12V nA 100 V GS = 12V 50 I D = -3.2A 5.5 nC V DS = -16V 21 V GS = -4.5V, See Fig. 6 and 12 14 V DD = -10V 32 I D = -3.2A ns 100 R G = 6.0 65 R D = 3.1, See Fig. 10 Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LD Internal Drain Inductance 2.5 LS Internal Source Inductance 4.0 Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance 1500 730 340 IGSS D nH Between lead tip and center of die contact pF V GS = 0V V DS = -15V = 1.0MHz, See Fig. 5 G S Source-Drain Ratings and Characteristics IS I SM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units -3.1 -27 69 71 -1.0 100 110 A V ns C Conditions D MOSFET symbol showing the G integral reverse p-n junction diode. S TJ = 25C, IS = -2.0A, VGS = 0V TJ = 25C, I F = -3.2A di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by Pulse width 300s; duty cycle 2%. ISD -3.2A, di/dt -65A/s, VDD V(BR)DSS, Surface mounted on FR-4 board, t 10sec. max. junction temperature. ( See fig. 11 ) TJ 150C 2 www.irf.com IRF7404 1000 1000 VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM - 1.5V -ID , Drain-to-Source Current (A) -I D , Drain-to-Source Current (A) 100 10 -1.5V 1 20s PULSE WIDTH TJ = 25C A 0.1 0.01 VGS - 7.5V - 5.0V - 4.0V - 3.5V - 3.0V - 2.5V - 2.0V BOTTOM - 1.5V TOP TOP 0.1 1 10 100 10 -1.5V 1 20s PULSE WIDTH TJ = 150C 0.1 0.01 100 0.1 Fig 1. Typical Output Characteristics 2.0 R DS(on) , Drain-to-Source On Resistance (Normalized) -ID , Drain-to-Source Current (A) TJ = 25C TJ = 150C 10 VDS = -15V 20s PULSE WIDTH 2.0 2.5 3.0 3.5 4.0 4.5 -VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com A 100 Fig 2. Typical Output Characteristics 100 1.5 10 -VDS , Drain-to-Source Voltage (V) -VDS , Drain-to-Source Voltage (V) 1 1 5.0 A I D = -5.3A 1.5 1.0 0.5 VGS = -4.5V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 TJ , Junction Temperature (C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF7404 10 V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd -VGS , Gate-to-Source Voltage (V) C, Capacitance (pF) 3000 Ciss 2000 Coss 1000 Crss 0 1 10 100 I D = -3.2A VDS = -16V 8 6 4 2 FOR TEST CIRCUIT SEE FIGURE 12 0 A 0 10 20 30 40 50 60 A Q G , Total Gate Charge (nC) -VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 100 -I SD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) -IID , Drain Current (A) TJ = 150C 10 TJ = 25C 1 VGS = 0V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -V SD , Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 1.6 1ms 10 10ms TA = 25 C TJ = 150 C Single Pulse 1 0.1 1 10 100 -VDS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF7404 8.0 V DS -ID , Drain Current (A) V GS D.U.T. RG 6.0 RD - + VDD -10V -VGS 4.0 Pulse Width 1 s Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit 2.0 td(on) tr t d(off) tf VGS 10% 0.0 25 50 75 100 125 150 TC , Case Temperature ( C) 90% VDS Fig 9. Maximum Drain Current Vs. Ambient Temperature Fig 10b. Switching Time Waveforms Thermal Response (Z thJA ) 100 D = 0.50 10 0.20 0.10 0.05 PDM 0.02 1 0.01 t1 t2 SINGLE PULSE (THERMAL RESPONSE) 0.1 0.0001 0.001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.01 0.1 1 10 100 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF7404 Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F -4.5 V QGS VGS VG -3mA Charge Fig 12a. Basic Gate Charge Waveform 6 D.U.T. QGD +VDS IG ID Current Sampling Resistors Fig 12b. Gate Charge Test Circuit www.irf.com IRF7404 Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + - - + ** RG * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test VGS* + - * VDD * Reverse Polarity for P-Channel ** Use P-Channel Driver for P-Channel Measurements Driver Gate Drive P.W. Period D= P.W. Period VGS=10V [ ] *** D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt [ Re-Applied Voltage Body Diode VDD ] Forward Drop Inductor Curent Ripple 5% [ ISD ] *** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 13. For P-Channel HEXFETS www.irf.com 7 IRF7404 SO-8 Package Outline D DIM B 5 A 8 6 7 6 H E 1 2 3 0.25 [.010] 4 A MIN .0532 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 b .013 .020 0.33 0.51 c .0075 .0098 0.19 0.25 D .189 .1968 4.80 5.00 E .1497 .1574 3.80 4.00 e .050 BASIC 1.27 BAS IC e1 6X e e1 A1 0.25 [.010] MAX .025 BASIC 0.635 BAS IC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 y 0 8 0 8 K x 45 A C 8X b MILLIMET ERS MAX A 5 INCHES MIN y 0.10 [.004] 8X L 8X c 7 C A B FOOT PRINT NOT ES : 1. DIMENS IONING & T OLERANCING PER ASME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 8X 0.72 [.028] 3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. 4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROT RUS IONS NOT T O EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROT RUS IONS NOT T O EXCEED 0.25 [.010]. 6.46 [.255] 7 DIMENS ION IS T HE LENGT H OF LEAD FOR S OLDERING T O A S UBS T RAT E. 3X 1.27 [.050] 8X 1.78 [.070] SO-8 Part Marking EXAMPLE: THIS IS AN IRF7101 (MOS FET) INTERNATIONAL RECT IFIER LOGO XXXX F7101 DATE CODE (YWW) P = DES IGNATES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = AS SEMBLY SIT E CODE LOT CODE PART NUMBER IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 11/06 8 www.irf.com