SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
Copyright 1992, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Members of the Texas Instruments
SCOPE
Family of Testability Products
•Members of the Texas Instruments
Widebus
Family
•Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
•Include D-Type Flip-Flops and Control
Circuitry to Provide Multiplexed
Transmission of Stored and Real-Time Data
•Two Boundary-Scan Cells per I/O for
Greater Flexibility
•State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
•
SCOPE
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, and
P1149.1A CLAMP and HIGHZ
– Parallel Signature Analysis at Inputs With
Masking Option
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
•Packaged in 64-Pin Plastic Shrink Quad Flat
Pack (PM) and 68-Pin Ceramic Quad Flat
Pack (HV)
1B4
1B5
1B6
GND
1B7
1B8
1B9
VCC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
VCC
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
NC
TMS
1CLKBA
1A2
1A1
1OEBA
GND
1SAB
1CLKAB
TDO
NC
TCK
2CLKBA
2SBA
2A9
GND
2OEBA
2SAB
2CLKAB
TDI
2A7
2A8
1SBA
1OEAB
GND
2OEAB
2B9
2B8
GND
1B1
1B2
1B3
19 20
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 22 23 24 25
67 66 65 64 6368 62 60 59 5861
26 27 28 29 30
57 56
18
55 54 53 52
31 32 33 34
SN54ABT18652 . . . HV PACKAGE
(TOP VIEW)
CC
V
CC
NC – No internal connection
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18 19
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21 22 23 24
63 62 61 60 5964 58 56 55 5457
25 26 27 28 29
53 52
17
51 50 49
30 31 32
1OEBA
GND
1CLKAB
TDO
1A2
1A1
1SAB
V
1SBA
1OEAB
1B1
1B2
TMS
1CLKBA
GND
1B3
2A9
GND
2SAB
2CLKAB
2A7
2A8
2OEAB
TDI
2CLKBA
2SBA
2OEAB
2B9
V
TCK
GND
2B8
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
VCC
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B4
1B5
1B6
GND
1B7
1B8
1B9
VCC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
CC
CC
SN74ABT18652 ...PM PACKAGE
(TOP VIEW)
description
The SN54ABT18652 and SN74ABT18652 scan test devices with 18-bit bus transceivers and registers are
members of the T exas Instruments SCOPE testability IC family. This family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed
transmission of data directly from the input bus or from the internal registers. They can be used either as two
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot
samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers and
registers.
Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable
(OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on
the low-to-high transition of CLKAB. When SAB is low , real-time A data is selected for presentation to the B bus
(transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode).
When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state.
Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and OEBA inputs. Since
the OEBA input is active-low, the A outputs are active when OEBA is low and are in the high-impedance state
when OEBA is high. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ′ABT18652.
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can
perform boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally , the test circuitry can perform
other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation
from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each
I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT
instruction is also included to ease the testing of memories and other circuits where a binary count addressing
scheme is useful.
The SN54ABT18652 is characterized over the full military temperature range of –55°C to 125°C. The
SN74ABT18652 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(normal mode, each 9-bit section)
INPUTS DATA I/O
OPERATION OR FUNCTION
OEAB OEBA CLKAB CLKBA SAB SBA A1 THRU A9 B1 THRU B9
OPERATION
OR
FUNCTION
L H L L X X Input disabled Input disabled Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑L X X Input Unspecified†Store A, hold B
H H ↑↑X
‡
X Input Output Store A in both registers
LXL ↑X X Unspecified†Input Hold A, store B
L L ↑↑XX
‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H L X H X Input Output Stored A data to B bus
H L L L H H Output Output Stored A data to B bus and
stored B data to A bus
†The data output functions can be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
‡Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
REAL-TIME TRANSFER
BUS B TO BUS A REAL-TIME TRANSFER
BUS A T O BUS B
STORAGE FROM
A, B, OR A AND B TRANSFER STORED DATA
TO A AND/OR B
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
LL
CLKAB
XCLKBA
XSAB
XSBA
LCLKAB
XCLKBA
XSAB
LSBA
X
HCLKAB CLKBA
XSAB
XSBA
XCLKAB CLKBA SAB SBA
X
HXX
X
X
X
HL L HH
↑↑
↑↑
OEBA
OEBA
HH
OEAB OEBA
OEAB OEBA L
Figure 1. Bus-Management Functions
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Boundary-Scan Register
1 of 9 Channels
1OEAB
1OEBA
1CLKBA
1SBA
1CLKAB
1SAB
1A1 1B1
1D
C1
1D
C1
1 of 9 Channels
2OEAB
2OEBA
2CLKBA
2SBA
2CLKAB
2SAB
2A1 2B1
1D
C1
1D
C1
Boundary-Control
Register
Instruction
Register
TDI
TMS
TCK
TDO
TAP
Controller
VCC
VCC
Bypass Register
Identification
Register
53
62
55
54
59
60
63
30
21
27
28
23
22
10
24
56
26
51
40
58
Pin numbers shown are for the PM package.
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: except I/O ports (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Note 1) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT18652 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT18652 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 885 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. For the SN74ABT18652 (PM package), the power derating factor for ambient temperatures greater than 55°C is –10.5 mW/°C.
recommended operating conditions (see Note 3)
SN54ABT18652 SN74ABT18652
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate 10 10 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 4)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54ABT18652 SN74ABT18652
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
V
VCC = 4.5 V, IOH = – 3 mA 2.5 2.5 2.5
V
VOH
VCC = 5 V, IOH = – 3 mA 3 3 3
V
V
OH
VCC =45V
IOH = – 24 mA 2 2
V
V
CC =
4
.
5
V
IOH = – 32 mA 2* 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55* 0.55
V
IIVCC = 5.5 V,
VI=V
CC or GND
CLK, OEAB,
OEBA, S, TCK ±1±1±1µA
II
V
I =
V
CC or
GND
A or B ports ±100 ±100 ±100
µA
IIH VCC = 5.5 V, VI = VCC TDI, TMS 10 10 10 µA
IIL VCC = 5.5 V, VI = GND TDI, TMS –160 –160 –160 µA
IOZH‡VCC = 5.5 V, VO = 2.7 V 50 50 50 µA
IOZL‡VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
Ioff VCC = 0, VI or VO ≤ 5.5 V ±100 ±450 ±100 µA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
V
CC
= 5.5 V,
AB
Outputs high 4 4 4
ICC
VCC
=
5
.
5
V
,
IO = 0,
VV
A or B ports
Outputs low 80 80 80 mA
O
VI = VCC or
GND
A
or
B
ports
Outputs
disabled 4 4 4
∆ICCVCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1.5 1.5 1.5 mA
CiVI = 2.5 V or 0.5 V Control inputs 4 pF
Cio VO = 2.5 V or 0.5 V A or B ports 10 pF
CoVO = 2.5 V or 0.5 V TDO 8 pF
NOTE 4: Preliminary specifications based on SPICE analysis
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†All typical values are at VCC = 5 V.
‡The parameters IOZH and IOZL include the input leakage current.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
SN54ABT18652 SN74ABT18652
UNIT
MIN MAX MIN MAX
UNIT
fclock Clock frequency CLKAB or CLKBA 0 100 0 100 MHz
twPulse duration CLKAB or CLKBA high or low 3 ns
tsu Setup time A before CLKAB↑ or B before CLKBA↑5 ns
thHold time A after CLKAB↑ or B after CLKBA↑0 ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
SN54ABT18652 SN74ABT18652
UNIT
MIN MAX MIN MAX
UNIT
fclock Clock frequency TCK 0 50 0 50 MHz
twPulse duration TCK high or low 5 ns
Si
A, B, CLK, OEAB, OEBA, or S before TCK↑5
tsu Setup time TDI before TCK↑6ns
su
p
TMS before TCK↑6
Hldi
A, B, CLK, OEAB, OEBA, or S after TCK↑0
thHold time TDI after TCK↑0ns
h
TMS after TCK↑0
tdDelay time Power up to TCK↑50 ns
trRise time VCC power up 1 µs
NOTE 4: Preliminary specifications based on SPICE analysis
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Note 4 and Figure 2)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CSN54ABT18652 SN74ABT18652 UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax CLKAB or CLKBA 100 130 100 100 MHz
tPLH
AorB
BorA
1 6
ns
tPHL
A
or
B
B
or
A
1 6 ns
tPLH
CLKAB or CLKBA
BorA
2 6
ns
tPHL
CLKAB
or
CLKBA
B
or
A
2 6 ns
tPLH
SAB or SBA
BorA
2 8
ns
tPHL
SAB
or
SBA
B
or
A
2 8 ns
tPZH
OEAB or OEBA
BorA
27.5
ns
tPZL OEAB or OEBA
B
or
A
27.5 ns
tPHZ
OEAB or OEBA
BorA
2 7.5
ns
tPLZ
OEAB
or
OEBA
B
or
A
27.5 ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Note 4 and Figure 2)123
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CSN54ABT18652 SN74ABT18652 UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax TCK 50 90 50 50 MHz
tPLH
TCK↓
AorB
312
ns
tPHL
TCK↓
A
or
B
312 ns
tPLH
TCK↓
TDO
2 7
ns
tPHL
TCK↓
TDO
2 7 ns
tPZH
TCK↓
AorB
314
ns
tPZL
TCK↓
A
or
B
314 ns
tPZH
TCK↓
TDO
2 8
ns
tPZL
TCK↓
TDO
2 8 ns
tPHZ
TCK↓
AorB
314
ns
tPLZ
TCK↓
A
or
B
314 ns
tPHZ
TCK↓
TDO
2 8
ns
tPLZ
TCK↓
TDO
2 8 ns
NOTE 4: Preliminary specifications based on SPICE analysis
PRODUCT PREVIEW
SN54ABT18652, SN74ABT18652
SCAN TEST DEVICES WITH
18-BIT BUS TRANSCEIVERS AND REGISTERS
SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
LOAD CIRCUIT FOR OUTPUTS
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V 1.5 V
tw
Input
(see Note A)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NON-INVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
(see Note B)
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note C)
Output
W aveform 2
S1 at Open
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
[
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW
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