1
®
FN8248.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9429
Low Noise/Low Power/2-Wire Bus
Single Digitally Controlled Potentiometer
(XDCP™)
The X9429 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Single Voltage Potentiometer
• 64 Resistor Taps
• 2-wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 150W Typical at 5V
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up.
• Standby Current < 3µA Max
•V
CC : 2.7V to 5.5V Operation
• 2.5kW, 10kW Total Pot Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 14 Ld TSSOP, 16 Ld SOIC
• Low Power CMOS
• Pb-free available (RoHS co mpliant)
Block Diagram
VH/RH
VL/RLVW/RW
POT
VCC
VSS
2-WIRE
BUS
ADDRESS
DATA
STATUS
WRITE
READ
WIPER 64-TAPS
TRANSFER 10kΩ
INC/DEC
CONTROL
INTERFACE
BUS
INTERFACE
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
4 BYTES
AND
Data Sheet October 13, 2008
2FN8248.3
October 13, 2008
Ordering Information
PART
NUMBER PART
MARKING VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)TEMP
RANGE (°C) PACKAGE PKG
DWG. #
X9429WS16* X9429WS 5 ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9429WS16Z* (Note) X9429WS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429WS16I* X9429WS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9429WS16IZ* (Note) X9429WS Z I -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429WV14 X9429 WV 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9429WV14Z* (Note) X9429 WV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429WV14IZ* (Note) X9429 WV Z I -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429WV14I* X9429 WV I -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9429YS16* X9429YS 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9429YS16Z* (Note) X9429YS Z 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429YS16I* X9429YS I -40 to +85 16 Ld SOIC (300 mil) M16.3
X9429YS16IZ* (Note) X9429YS Z I -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429YV14* X9429YV 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9429YV14Z* (Note) X9429 YVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429YV14I* X9429 YVI -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9429YV14IZ* (Note) X9429 YVZ I -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429WS16-2.7* X9429WS F 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3
X9429WS16Z-2.7* (Note) X9429WS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429WS16I-2.7* X9429WS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9429WS16IZ-2.7* (Note) X9429WS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429WV14-2.7* X9429 WVF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9429WV14Z-2.7* (Note) X9429 WVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429WV14I-2.7 X9429 WV G -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9429WV14IZ-2.7* (Note) X9429 WVZ G -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429YS16-2.7* X9429YS F 2.5 0 to +70 16 Ld SOIC (300 mil) M16.3
X9429YS16Z-2.7* (Note) X9429YS ZF 0 to +70 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429YS16I-2.7* X9429YS G -40 to +85 16 Ld SOIC (300 mil) M16.3
X9429YS16IZ-2.7* (Note) X9429YS ZG -40 to +85 16 Ld SOIC (300 mil) (Pb-Free) M16.3
X9429YV14-2.7* X9429 YVF 0 to +70 14 Ld TSSOP (4.4mm) M14.173
X9429YV14Z-2.7* (Note) X9429 YVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
X9429YV14I-2.7* X9429 YVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173
X9429YV14IZ-2.7* (Note) X9429 YVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-Free) M14.173
*Add "T1" suffix for tape and reel. **Add "T1" suffix for tape and reel.Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9429
3FN8248.3
October 13, 2008
Detailed Functional Diagram
Circuit Level Applications
• Vary the Gain of a Voltage Amplifier
• Provide Programmable DC Reference Voltages for
Comparators and Detectors
• Control the V olume in Audio Circuits
• Trim Out the Offset Voltage Error in a Voltage Amplifier
Circuit
• Set the Output Voltage of a Voltage Regulator
• Trim the Resistance in Wheatstone Bridge Circuits
• Control the Gain, Characteristic Frequen cy and
Q-factor in Fi lter Circuits
• Set the Scale Factor and Zero Point in Sensor Signal
Conditioning Circuits
• Vary the Frequency and Duty Cycle of Timer ICs
• Vary the DC Biasing of a Pin Diode Attenuator in RF
Circuits
• Provide a Control Variable (I, V, or R) in Feedback Circuits
System Level Applications
• Adjust the Contrast in LCD Displays
• Control the Power Level of LED Transmitters in
Communication Systems
• Set and Regulate the DC Biasing Point in an RF Power
Amplifier in Wireless Systems
• Control the Gain in Audio and Home Entertainment
Systems
• Provide the Variable DC Bias for Tuners in RF Wireless
Systems
• Set the Operating Points in Temperature Control Systems
• Control the Operating Point for Sensors in Industrial
Systems
• Trim Of fset and Gain Errors in Artificial Intelligent Systems
VCC
VSS
WIPER
COUNTER
REGISTER
(WCR)
RH/VH
RL/VL
DATA
RW/VW
INTERFACE
AND
CONTROL
CIRCUITRY
CONTROL
64--TAPS
10kΩ
POWER-ON RECALL
DR0 DR1
DR2 DR3
A0
SCL
SDA
A2
WP
A3
X9429
4FN8248.3
October 13, 2008
Pinouts X9429
(14 LD TSSOP)
TOP VIEW
X9429
(16 LD SOIC)
TOP VIEW
Pin Assignments
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the
X9429.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output an d may be w ire-ORed
with any number of open drain or open collector output s. An
open drain output requires the use of a pull-up resisto r. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A0, A2, A3)
The Address inputs are used to set the least significant 3 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X942 9. A maximum
of 8 devices may occu py the 2-wire serial bus.
Potentiometer Pins
RH/VH, RL/VL
The RH/VH and RL/VL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer .
RW/VW
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT WP
The WP pin when low prevents nonvolatile writes to the Data
Registers.
Principals of Operation
The X9429 is a highly integrated microcircuit incorporating a
resistor array and its associated registers and counters and
the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9429 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
VCC
RL/VL
VSS
1
2
3
4
5
6
78
14
13
12
11
10
9
NC
RW/VW
SCL
A2
RH/VH
X9429
NC
NC
SDA
A3
WP
A0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X9429
VCC
RL/VL
RW/VW
RH/VH
A3
WP
A0
NC
VSS
SCL
A2
NC
SDA
NC
NC
NC
TSSOP PIN SOIC PIN SYMBOL BRIEF DESCRIPTION
1, 2, 3 12, 3, 7, 15 NC No Connect
4 4 A2 Device Address for 2-wire bus.
5 5 SCL Serial Clock for 2-wire bus.
6 6 SDA Serial Data Input/Output for 2-wire bus.
78V
SS System Ground
89WP
Hardware Write Protect
9 10 A0 Device Address for 2-wire bus.
10 11 A3 Device Address for 2-wire bus.
11 12 RW/VWWiper Terminal of the Potentiomet er.
12 13 RH/VH High Terminal of the Potentiometer.
13 14 RL/VLLow Terminal of the Potentiometer.
14 16 VCC System Supply Voltage
X9429
5FN8248.3
October 13, 2008
bus as a transmitter and the receiving device as the receiver .
The device controlling the transfer is a master and the
device being controlled is the slave. Th e master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefo re, the X9429 will be
considered a slave device in all applications.
Clock and Data Conventions
Data st a tes on the SDA line can cha nge only du rin g SCL
LOW periods (tLOW). SDA state chang es durin g SCL HIGH
are reserved for indicating sta rt and stop conditions.
Start Condition
All commands to the X9429 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (tHIGH). The X9429 continuously mo nitors the
SDA and SCL lines for the start condition and will not
respond to any command until this conditi on is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period, the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9429 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9429 wil l
respond with a final acknowledge.
Array Description
The X9429 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are connected
in series. The physical ends of the array are equivalent to
the fixed terminals of a mechanical potentiometer (VH/RH
and VL/RL inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper (VW/RW)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Coun ter Re gist er (WC R). T he si x bits of the WC R are
decoded to select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier (refer
to Figure 1). For the X9429 this is fixed as 0101[B].
The next four bits of the slave address are the device address.
The physical device address is d efined by the st ate of the A0,
A2, and A3 input s. The X9 429 comp ares th e serial dat a
stream with the address input st a te; a successful compare of
all three address bit s is required for the X9429 to respond with
an acknowledge. The A0, A2, and A3 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
Acknowledge Polling
The disabling of the inputs, during the internal non-volatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the non-volatile write command,
the X9429 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9429
is still busy with the write operation, no ACK will be returned.
If the X9429 has completed the write operation, an ACK will
be returned, and the master can then proceed with the next
operation.
Instruction Structure
The next byte sent to the X9429 contains the instruction and
register pointer information. The fo ur most significant bits are
the instruction. The next four bits point to one of four
associated registers. The format is shown in Figure 2.
The four high order bits define the instruction. The next two
bits (R1 and R0) select one of the four registers that is to be
acted upon when a register oriented instruction is issued.
Bits 0 and 1 are defined to be 0.
100
A3 A2 0 A0
DEVICE TYPE
IDENTIFIER
DEVICE ADDRESS
1
FIGURE 1. SLAVE ADDRESS
I1I2I3 I0 R1 R0 0 0
REGISTER
SELECT
INSTRUCTIONS
FIGURE 2. INSTRUCTION BYTE FORMAT
X9429
6FN8248.3
October 13, 2008
Four of the seven instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register an d one of the Data
Registers. A transfer from a Data Register to a Wiper
Counter Register is essentially a write to a static RAM. The
response of the wiper to this action will be delayed tWRL. A
transfer from the Wiper Counter Register (current wiper
position), to a Data Register is a write to non-volatile
memory and takes a minimum of tWR to complete.
Four instructions require a three-b yte sequence to complete.
These instructions transfer dat a be tw een the host an d the
X9429; either between the host and one of the Dat a Registers
or directly between the host and the Wiper C ounter Register.
These instructions are:
Flow 1. ACK Polling Sequence
NON-VOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ACK
RETURNED?
FURTHER
OPERATION?
ISSUE
INSTRUCTION ISSUE STOP
NO
YES
YES
PROCEED
ISSUE STOP
NO
PROCEED
S
T
A
R
T
0101A3A20A0
A
C
K
I3 I2 I1 I0 R1 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
X9429
7FN8248.3
October 13, 2008
TABLE 1. INSTRUCTION SET
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected nonvolatile
register) and write Data Register (write a new value to the
selected Data Register). The sequence of operations is
shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9429 has responded with an acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
VH/RH terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
NOTE: (1)1/0 = data is one or zero
INSTRUCTION
INSTRUCTION SET
OPERATIONI3I2I1I0R1R0X1X0
Read Wiper Counter Register 1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter Register 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by R1 - R0
Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by R1 - R0
XFR Data Register to Wiper
Counter Register 1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by R1 - R0
to its Wiper Counter Register
XFR Wiper Counter
Register to Dat a Register 1 1 1 0 1/0 1/0 0 0 T ransfer the contents of the Wiper Co unter Register to the Data
Register pointed to by R1 - R0
Increment/Decrement Wiper
Counter Register 0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter Register
S
T
A
R
T
0 1 0 1 A3 A2 0 A0 A
C
K
I3 I2 I1 I0 R1 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
0 0 D5 D4 D3 D2 D1 D0
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
S
T
A
R
T
0101A3A20A0
A
C
K
I3 I2 I1 I0 R0 0 0 A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
R1
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
X9429
8FN8248.3
October 13, 2008
SCL
SDA
VW/RW
INC/DEC
CMD
ISSUED
VOLTAGE OUT
TWRID
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
SCL FROM
DATA OUTPUT
FROM TRANSMITTER
189
START ACKNOWLEDGE
MASTER
DATA OUTPUT
FROM RECEIVER
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
X9429
9FN8248.3
October 13, 2008
Detailed Operation
The potentiometer has a Wiper Counter Register and four
Data Registers. A detailed discussion of the register
organization and array operation follows.
Wiper Counter Register
The X9429 contains a Wiper Counter Register. The Wiper
Counter Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
Increment/Decrement instruction. Finally , it is loaded with the
contents of its Data Register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are lost
when the X9429 is powered-down. Although the register is
automatically loaded with the value in DR0 upon power-up, it
should be noted this may be different from the value present
at power-dow n .
Data Registers
The potentiometer has four nonvolatile Data Registers.
These can be read or written di rectly by the host and data
can be transferred between any of the four Data Registers
and the Wiper Counter Register. It should be noted all
operations changing data in one of these registers is a
nonvolatile opera tion and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be used
as regular memory locations that could possibly store
system parameters or user preference data.
Register Descriptions
DATA REGISTERS, (6-BIT), NON-VOLATILE
FOUR 6-BIT DATA REGISTERS FOR EACH XDCP.
{D5~D0}: These bits are for general purpose not volatile data
storage or for storage of up to four different wiper values.
The contents of Data Re gi ste r 0 are automatically moved to
the Wiper Counter Register on power-up.
WIPER COUNTER REGISTER, (6-BIT), VOLATILE
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCL
UP/DN
VH/RH
VL/RL
VW/RW
IF WCR = 00[H] THEN VW/RW = VL/RL
IF WCR = 3F[H] THEN VW/RW = VH/RH
8 6
C
O
U
N
T
E
R
D
E
C
O
D
E
(WCR)
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM
D5 D4 D3 D2 D1 D0
NV NV NV NV NV NV
(MSB) (LSB)
WP5 WP4 WP3 WP2 WP1 WP0
VVVVVV
(MSB) (LSB)
X9429
10 FN8248.3
October 13, 2008
ONE 6-BIT WIPER COUNTER REGISTER FOR EACH
XDCP.
{D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is loaded on
power-up by the value in Data Register 0. The contents of
the WCR can be loaded from any of the other Data Register
or directly. The contents of the WCR can be saved in a DR.
Instruction Format
NOTES:
1. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
2. A3 ~ A0”: stands for the device addresses sent by the master.
3. X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
4. “I”: stands for the increment operation, SDA held high during
active SCL phase (high).
5. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE S
A
C
K
WIPER POSITION
(SENT BY SLAVE ON SDA) M
A
C
K
S
T
O
P
0101A
3A
20A
010010000 00W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE S
A
C
K
WIPER POSITION
(SENT BY MASTER ON SDA) S
A
C
K
S
T
O
P
0101A
3A
20A
010100000 00W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE REGISTER
ADDRESSES S
A
C
K
WIPER POSITION/DATA
(SENT BY SLAVE ON SDA) M
A
C
K
S
T
O
P
0101A
3A
20A
01011R
1R
000 00W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE REGISTER
ADDRESSES S
A
C
K
WIPER POSITION/DATA
(SENT BY MASTER ON
SDA) S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3A
20A
01100R
1R
000 00W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
X9429
11 FN8248.3
October 13, 2008
XFR Data Register (DR) to Wiper Counter Register (WCR)
XFR Wiper Counter Registe r (WCR) to Data Register (DR)
Increment/Decrement Wiper Counter Register (WCR)
Symbol Table
Guidelines for Calculating Typical V alues of Bus
Pull-Up Resistors
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE REGISTER
ADDRESSES S
A
C
K
S
T
O
P
0101A
3A
20A
01101R
1R
000
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE REGISTER
ADDRESSES S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0101A
3A
20A
01110R
1R
000
S
T
A
R
T
DEVICE TYPE
IDENTIFIER DEVICE
ADDRESSES S
A
C
K
INSTRUCTION
OPCODE S
A
C
K
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA) S
T
O
P
0101A3A20A0 0 0 1 00000 I/
DI/
D....I/
DI/
D
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM LOW TO
HIGH
WILL CHANGE
FROM LOW TO
HIGH
MAY CHANGE
FROM HIGH TO
LOW
WILL CHANGE
FROM HIGH TO
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A CENTER LINE
IS HIGH
IMPEDANCE
120
100
80
40
60
20
20 40 60 80 100 120
00
RESISTANCE (k)
BUS CAPACITANCE (PF)
MIN.
RESISTANCE
MAX.
RESISTANCE
RMAX =CBUS
TR
RMIN = IOL MIN
VCC MAX =1.8kW
X9429
12 FN8248.3
October 13, 2008
Analog Specificatio n s (Over recommended operating conditions unless otherwise stated.)
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)
Absolute Maximum Ratings Thermal Information
Supply Voltage (VCC Limits)
X9429. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9429-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Voltage on SCL, SDA any address input
with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
IW (10 s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Thermal Resistance (Typical, Note 1) θJA (°C/W)
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN.
(Note 7) TYP. MAX.
(Note 7) UNIT
End-to-End Resistance Tolerance -20 +20 %
Power Rating +25°C, each pot 50 mW
IW Wiper Current ±3 mA
RWWiper Resistance Wiper current = VCC/RTOTAL,
VCC = 5V 150 250 Ω
Wiper current = VCC/RTOTAL,
VCC = 3V 400 1000 Ω
VTERM Voltage on Any VH/RH or VL/RL Pin VSS = 0V VSS VCC V
Noise Ref: 1kHz -120 dBV
Resolution (Note 4) 1.6 %
Absolute Linearity (Note 1) Vw(n)(actual) - Vw(n)(expected) ±1 MI
(Note 3)
Relative Linearity (Note 2) Vw(n + 1) - [Vw(n) + MI]±0.2MI
(Note 3)
Temperature Coefficient of RTOTAL ±300 ppm/°C
Ratiometric Temperature Coefficient ±20 ppm/°C
CH/CL/CWPotentiometer Capacitances See Circuit #3, Spice Macromodel 10/10/25 pF
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN.
(Note 7) TYP MAX.
(Note 7) UNIT
ICC1 VCC Supply Current
(nonvolatile write) fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
3.5 mA
ICC2 VCC Supply Current
(move wiper, write, read) fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
170 µA
ISB VCC Current (standby) SCL = SDA = VCC, Addr. = VSS 3µA
ILI Input Leakage Current VIN = VSS to VCC 10 µA
X9429
13 FN8248.3
October 13, 2008
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power-up and Power-down Requirements
There are no restrictions on the power-up or power-down
conditions of VCC and the voltage applied to the
potentiometer pins provid ed that VCC is always more
positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL,
VW. The VCC ramp rate spec is always in effect.
AC Test Conditions
Equivalent AC Load Circuit Circuit #3 SPICE Macro Model
ILO Output Leakage Current VOUT = VSS to VCC 10 µA
VIH Input HIGH Voltage VCC x 0.7 VCC x 0.5 V
VIL Input LOW Voltage -0.5 VCC x 0.1 V
VOL Output LOW voltage IOL = 3mA 0.4 V
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN.
(Note 7) TYP MAX.
(Note 7) UNIT
PARAMETER MIN. UNIT
Minimum Endurance 100,000 Data changes per bit per register
Data Retention 100 Years
SYMBOL TEST TYP UNIT TEST CONDITIONS
CI/O (Note 5) Input/output capacitance (SDA) 8 pF VI/O = 0V
CIN (Note 5) Input capacitance (A0, A2,and A3 and SCL) 6 pF VIN = 0V
SYMBOL PARAMETER MIN TYP MAX UNIT
tRVCC (Note 6) VCC Power-up ramp rate 0.2 50 V/ms
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer . It is
a measure of the error in step size.
3. MI = RTOT/63 or (RH - RL)/63, single pot
4. Typical = individual array resolutions.
5. Limits established by characterization and are not production tested.
6. Sample tested only.
7. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
Input pulse levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
5V
1533Ω
100pF
SDA OUTPUT
2.7V
100pF 10pF
RH
RTOTAL
CH
25pF
CW
CL
10pF
RW
RL
X9429
14 FN8248.3
October 13, 2008
AC TIMING (Over recommended operating conditions)
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL PARAMETER MIN
(Note 7) MAX
(Note 7) UNIT
fSCL Clock Frequency 400 kHz
tCYC Clock Cycle Time 2500 ns
tHIGH Clock High Time 700 ns
tLOW Clock Low Time 1300 ns
tSU:STA Start Setup Time 600 ns
tHD:STA Start Hold Time 600 ns
tSU:STO Stop Setup Time 600 ns
tSU:DAT SDA Data Input Setup Time 100 ns
tHD:DAT SDA Data Input Hold Time 30 ns
tRSCL and SDA Rise Time 300 ns
tF SCL and SDA Fall Time 300 ns
tAA SCL low to SDA Data Output Valid Time 900 ns
tDH SDA Data Output Hold Hime 50 ns
tINoise Suppression Time Constant at SCL and SDA Inputs 50 ns
tBUF Bus Free Time (Prior to Any Transmission) 1300 ns
tSU:WPA WP, A0, A2, A3 Setup Time 0 ns
tHD:WPA WP, A0, A2, A3 Hold Time 0 ns
SYMBOL PARAMETER TYP MAX UNIT
tWR High-Voltage Write Cycle Time (Store Instructions) 5 10 ms
SYMBOL PARAMETER MIN
(Note 7) MAX
(Note 7) UNIT
tWRPO Wiper Response Time After the Third (last) Power Supply is Stable 10 µs
tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs
tWRID Wiper Response Time From an Active SCL/SCK Edge (Increment/Decrement Instruction) 10 µs
X9429
15 FN8248.3
October 13, 2008
Timing Diagrams
Start and Stop Timing
Input Timing
Output Timing
XDCP Timing (for All Load Instructions)
tSU:STA tHD:STA tSU:STO
SCL
SDA
tR
(START) (STOP)
tF
tRtF
SCL
SDA
tHIGH
tLOW
tCYC
tHD:DAT
tSU:DAT tBUF
SCL
SDA
tDH
tAA
SCL
SDA
VW/RW
(STOP)
LSB
tWRL
X9429
16 FN8248.3
October 13, 2008
XDCP Timing (f or Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
Applications information
Basic Configurations of Electronic Potentiometers
SCL
SDA
VW/RW
tWRID
WIPER REGISTER ADDRESS INC/DEC INC/DEC
SDA
SCL
...
...
...
WP
A0, A2, A3
tSU:WPA tHD:WPA
(START) (STOP)
(ANY INSTRUCTION)
VR
VW/RW
+VR
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
X9429
17 FN8248.3
October 13, 2008
Application Circuits
NONINVERTING AMPLIFIER VOLTAGE REGULATOR
OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS
+
–
VS
VO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
100kΩ
10kΩ10kΩ
10kΩ
+5V
TL072
+
–
VS
VO
R2
R1
}
}
X9429
18 FN8248.3
October 13, 2008
Application Circuits (continued)
INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT
+
–
VS
VO
R2
R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
FUNCTION GENERATOR
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
FREQUENCY µR1, R2, C
AMPLITUDE µRA, RB
C
ATTENUATOR FILTER
+
–
VS
VO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2
GO = 1 + R2/R1
fc = 1/(2πRC)
R2
R4All RS = 10kΩ
+
–
VS
R2
R1
R
C
VO
X9429
19 FN8248.3
October 13, 2008
X9429
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8248.3
October 13, 2008
X9429
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number o f terminal positions.
8. Terminal numbers are shown for r eference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
