LM98725 LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation Literature Number: SNAS474D LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/ CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation General Description Features The LM98725 is a fully integrated, high performance 16-Bit, 81 MSPS signal processing solution for digital color copiers, scanners, and other image processing applications. Highspeed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for higher speed CCD or CMOS image sensors). The signal paths utilize 8 bit Programmable Gain Amplifiers (PGA), a +/-9-Bit offset correction DAC and independently controlled Digital Black Level correction loops for each input. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each of the three analog inputs. The signals are then routed to a 81MHz high performance analog-to-digital converter (ADC). The fully differential processing channel shows exceptional noise immunity, having a very low noise floor of -74dB. The 16-bit ADC has excellent dynamic performance making the LM98725 transparent in the image reproduction chain. A very flexible integrated Spread Spectrum Clock Generation (SSCG) modulator is included to assist with EM compliance and reduce system costs. Applications Multi-Function Peripherals High-speed Currency/Check Scanners Flatbed or Handheld Color Scanners High-speed Document Scanners LVDS/CMOS Outputs LVDS/CMOS/Crystal Clock Source with PLL Multiplication Integrated Flexible Spread Spectrum Clock Generation CDS or S/H Processing for CCD or CIS sensors Independent Gain/Offset Correction for Each Channel Automatic per-Channel Gain and Offset Calibration Programmable Input Clamp Voltage Flexible CCD/CIS Sensor Timing Generator Key Specifications Maximum Input Level 1.2 or 2.4 Volt Modes (both with + or - polarity option) ADC Resolution 16-Bit ADC Sampling Rate 81 MSPS INL +17/- 28 LSB (typ) Channel Sampling Rate 30/30/27 MSPS PGA Gain Steps 256 Steps PGA Gain Range 0.62 to 8.3x Analog DAC Resolution +/-9 Bits Analog DAC Range +/-307mV or +/-614mV Digital DAC Resolution +/-6 Bits Digital DAC Range -2048 LSB to + 2016 LSB SNR -74dB (@0dB PGA Gain) Power Dissipation 755mW (LVDS) Operating Temp 0 to 70C Supply Voltage 3.3V Nominal (3.0V to 3.6V range) System Block Diagram 30085370 (c) 2009 National Semiconductor Corporation 300853 www.national.com LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output Integrated Sensor Timing Generator and Spread Spectrum Clock Generation September 24, 2009 LM98725 LM98725 Overall Chip Block Diagram 30085301 FIGURE 1. Chip Block Diagram www.national.com 2 LM98725 LM98725 Pin Out Diagram 30085302 FIGURE 2. LM98725 Pin Out Diagram 3 www.national.com FIGURE 3. Typical Application Diagram 30085373 LM98725 Typical Application Diagram www.national.com 4 LM98725 Pin Descriptions Pin I/O Typ Res 1 PHIC2 Name O D PU Configurable high speed sensor timing output. Description 2 PHIC1 O D PD Configurable high speed sensor timing output. 3 SH1 O D PU Configurable low speed sensor timing output. 4 CE I D Chip Serial Interface Address Setting Input CE Level Address VD 01 Float 10 DGND 00 5 CAL I D PD Initiate calibration sequence. Leave unconnected or tie to DGND if unused. 6 RESET I D PU Active-low master reset. NC when function not being used. 7 SH_R I D PD External request for an SH interval. 8 SDI I D PD Serial Interface Data Input. 9 SDO O D 10 SCLK I D PD Serial Interface shift register clock. 11 SEN I D PU Active-low chip enable for the Serial Interface. 12 VA P Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. 13 AGND P Analog ground return. 14 VA P Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. 15 VREFB O A Bottom of ADC reference. Bypass with a 0.1F capacitor to ground. 16 VREFT O A Top of ADC reference. Bypass with a 0.1F capacitor to ground. 17 VA P Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. 18 AGND P Analog ground return. 19 VCLP A Input Clamp Voltage. Normally bypassed with a 0.1F , and a 4.7F capacitor to AGND. An external reference voltage may be applied to this pin. 20 VA P Analog power supply. Bypass voltage source with 4.7F and pin with 0.1F to AGND. 21 IBIAS A Bias setting pin. Connect a 9.0 kOhm 1% resistor to AGND. 22 AGND P Analog ground return. 23 OSR A Analog input signal. Typically sensor Red output AC-coupled thru a capacitor. 24 AGND P Analog ground return. 25 OSG A Analog input signal. Typically sensor Green output AC-coupled thru a capacitor. 26 AGND P Analog ground return. 27 OSB A Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor. 28 CPOFILT2 A Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1F capacitor to CPOFILT1. 29 DGND P Digital ground return. 30 CPOFILT1 A Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1F capacitor to CPOFILT2. 31 DVB O D Digital Core Voltage bypass. Not an input. Bypass with 0.1F capacitor to DGND. 32 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation. 33 INCLK- I D Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock. 34 DOUT7/ TXCLK+ O D Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode. 35 DOUT6/ TXCLK- O D Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode. 36 DOUT5/ TXOUT2+ O D Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode. IO O I I I Serial Interface Data Output. 5 www.national.com LM98725 Pin Name I/O Typ Res 37 DOUT4/ TXOUT2- O D Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode. 38 DOUT3/ TXOUT1+ O D Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode. 39 DOUT2/ TXOUT1- O D Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode. 40 DOUT1/ TXOUT0+ O D Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode. 41 DOUT0/ TXOUT0- O D Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode. 42 DGND O D 43 VD 44 VC 45 CLKOUT/SH2 O 46 SH3 O D Configurable low speed sensor timing output. 47 RS O D Configurable high speed sensor timing output. 48 CP O D Configurable high speed sensor timing output. 49 PHIA1 O D Configurable high speed sensor timing output. 50 PHIA2 O D Configurable high speed sensor timing output. 51 DGND P Digital ground return. 52 VC P Power supply for the sensor control outputs. Bypass this supply pin with 0.1F capacitor. 53 PHIB1 O D Configurable high speed sensor timing output. 54 PHIB2 O D Configurable high speed sensor timing output. 55 SH4 O D Configurable low speed sensor timing output. 56 SH5 O D Configurable low speed sensor timing output. PD Description Configurable sensor control output. P Power supply for the digital circuits. Bypass this supply pin with 0.1F capacitor. A single 4.7F capacitor should be used between the supply and the VD, VR and VC pins. P Power supply for the sensor control outputs. Bypass this supply pin with 0.1F capacitor. D Output clock for registering output data when using CMOS outputs, or a configurable low speed sensor timing output. (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.). www.national.com 6 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VA,VR,VD,VC) Voltage on Any Input Pin (Not to exceed 4.2V) Voltage on Any Output Pin (execpt DVB and not to exceed 4.2V) DVB Output Pin Voltage Input Current at any pin other than Supply Pins (Note 3) Package Input Current (except Supply Pins) (Note 3) Maximum Junction Temperature (TA) 4.2V -0.3V to (VA + 0.3V) -0.3V to (VA + 0.3V) 2.0V 25 mA Operating Ratings (Note 1, Note 2) Operating Temperature Range 50 mA All Supply Voltage 0C TA +70C +3.0V to +3.6V 150C Electrical Characteristics The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 27MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Symbol Parameter Conditions Min (Note 9) Typ (Note 8) Max (Note 9) Units CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb) VIH Logical "1" Input Voltage VIL Logical "0" Input Voltage VIHYST Logic Input Hysteresis IIH Logical "1" Input Current IIL Logical "0" Input Current 2.0 V 0.8 V 0.6 VIH = VD RESET,SEN SH_R, SCLK, SDI, CAL 100 65 CE 30 nA A nA VIL = DGND RESETSEN -65 SH_R, SCLK, SDI, CAL CE -100 -30 A nA A CMOS Digital Output DC Specifications (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC) VOH Logical "1" Output Voltage IOUT = -0.5mA 3.0 V VOL Logical "0" Output Voltage IOUT = 1.6mA IOS Output Short Circuit Current VOUT = DGND 18 0.21 VOUT= VD -25 IOZ CMOS Output TRI-STATE Current VOUT = DGND 20 VOUT = VD -25 V mA nA CMOS Digital Output DC Specifications (CMOS Data Outputs) VOH Logical "1" Output Voltage IOUT = -0.5mA 2.3 V VOL Logical "0" Output Voltage IOUT = 1.6mA 0.12 V IOS Output Short Circuit Current VOUT = DGND 12 mA VOUT= VD -14 IOZ CMOS Output TRI-STATE Current VOUT = DGND 20 VOUT = VD -25 nA LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins) 7 www.national.com LM98725 <66C/W Thermal Resistance (JA) Package Dissipation at TA = 25C >1.89W (Note 4) ESD Rating (Note 5) Human Body Model 2500V Machine Model 250V Storage Temperature -65C to +150C Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6) Absolute Maximum Ratings (Note 1, Note LM98725 Symbol VIHL Parameter Conditions Differential LVDS Clock RL = 100 High Threshold Voltage VCM (LVDS Input Common Mode Voltage)= 1.25V VILL Differential LVDS Clock Low Threshold Voltage VIHC CMOS Clock High Threshold Voltage VILC CMOS Clock Low Threshold Voltage IIHL CMOS Clock Input High Current IILC CMOS Clock Input Low Current INCLK- = DGND Min (Note 9) Typ (Note 8) Max (Note 9) Units 200 mV -200 mV 2.0 V 230 -135 0.8 V 260 A A -120 LVDS Output DC Specifications VOD Differential Output Voltage VOS LVDS Output Offset Voltage IOS Output Short Circuit Current RL = 100 280 390 490 mV 1.08 1.20 1.33 V VOUT = 0V, RL = 100 8.5 LVDS Output Data Format 152 180 mA LVDS Output Data Format (Powerdown) 3.6 6 mA CMOS Output Data Format (40 MHz) 136 168 mA LVDS Output Data Format 76 94 mA LVDS Output Data Format (Powerdown) 8.5 17 mA CMOS Output Data Format (ATE Loading of CMOS Outputs > 50 pF) (40 MHz) 46 68 mA mA Power Supply Specifications IA ID VA Analog Supply Current VD Digital Output Driver Supply Current IC VC CCD Timing Generator Output Driver Supply Current Typical sensor outputs: SH1-SH5, PHIA, PHIB, PHIC, RS, CP (ATE Loading of CMOS Outputs > 50pF) 1 4 mA PWR Average Power Dissipation LVDS Output Data Format 755 885 mW LVDS Output Data Format (Powerdown) 40 70 mW CMOS Output Data Format (ATE Loading of CMOS Outputs > 50pF) (40 MHz) 600 740 mW CDS Gain=1x, PGA Gain=1x CDS Gain=2x, PGA Gain= 1x 2.3 1.22 Input Sampling Circuit Specifications VIN www.national.com Input Voltage Level 8 Vp-p Parameter Conditions Min (Note 9) Typ (Note 8) Max (Note 9) Units IIN_SH Sample and Hold Mode Input Leakage Current Source Followers Off CDS Gain = 1x OSX = VA (OSX = AGND) 32 (-165) 50 A (-200) Source Followers Off CDS Gain = 2x OSX = VA (OSX = AGND) 55 (-240) 70 A (-290) Source Followers On CDS Gain = 2x OSX = VA (OSX = AGND) 20 (-50) 250 nA (-250) CSH Sample/Hold Mode Equivalent Input Capacitance CDS Gain = 1x CDS Gain = 2x 4 IIN_CDS CDS Mode Input Leakage Current Source Followers Off OSX = VA (OSX = AGND) 10 (-50) 250 nA 16 55 RCLPIN 2.5 (-250) CLPIN Switch Resistance (OSX to VCLP Node) pF pF VCLP Reference Circuit Specifications VCLP Voltage 000 VCLP Voltage Setting = 000 0.85VA V VCLP Voltage 001 VCLP Voltage Setting = 001 0.9VA V VCLP Voltage 010 VCLP Voltage Setting = 010 0.95VA V VCLP Voltage 011 VCLP Voltage Setting = 011 0.6VA V VCLP Voltage 100 VCLP Voltage Setting = 100 0.55VA V VCLP Voltage 101 VCLP Voltage Setting = 101 0.4VA V VCLP Voltage 110 VCLP Voltage Setting = 110 0.35VA V VCLP Voltage 111 VCLP Voltage Setting = 111 0.15VA V VCLP DAC Short Circuit Output Current 0001 xxxxb VCLP Config. Register = 30 mA 10 Bits VVCLP ISC Black Level Offset DAC Specifications Resolution Monotonicity Offset Adjustment Range Referred to AFE Input Guaranteed by characterization CDS Gain = 1x Minimum DAC Code = 0x000 Maximum DAC Code = 0x3FF -614 614 mV CDS Gain = 2x Minimum DAC Code = 0x000 Maximum DAC Code = 0x3FF -307 307 mV Offset Adjustment Range Referred to AFE Output Minimum DAC Code = 0x000 Maximum DAC Code = 0x3FF DAC LSB Step Size CDS Gain = 1x Referred to AFE Output -17500 +16130 -16130 +17500 1.2 (32) LSB mV (LSB) DNL Differential Non-Linearity -0.84 +0.74/ -0.37 +2.4 LSB INL Integral Non-Linearity -2.5 +0.72/ -0.56 +2.5 LSB PGA Specifications Gain Resolution 8 Monotonicity Maximum Gain Bits Guaranteed by characterization CDS Gain = 1x 7.7 8.3 8.8 V/V CDS Gain = 1x 17.7 18.4 18.9 dB 9 www.national.com LM98725 Symbol LM98725 Symbol Parameter Conditions Min (Note 9) Typ (Note 8) Max (Note 9) Units Minimum Gain CDS Gain = 1x 0.58 0.62 0.67 V/V CDS Gain = 1x -4.7 -4.2 -3.5 dB PGA Function Channel Matching Gain (V/V) = (180/(277-PGA Code)) Gain (dB) = 20LOG10(180/(277-PGA Code)) Minimum PGA Gain Maximum PGA Gain 3 12.7 % 2.07 V ADC Specifications VREFT Top of Reference VREFB Bottom of Reference VREFT VREFB Differential Reference Voltage 0.89 1.06 1.18 Overrange Output Code 65535 Underrange Output Code 0 V 1.30 V Digital Offset "DAC" Specifications 7 Bits Digital Offset DAC LSB Step Size Resolution Referred to AFE Output 32 LSB Offset Adjustment Range Referred to AFE Output Min DAC Code =7b0000000 Mid DAC Code =7b1000000 Max DAC Code = 7b1111111 -2048 0 +2016 LSB Full Channel Performance Specifications DNL Differential Non-Linearity INL Integral Non-Linearity SNR Total Output Noise Channel to Channel Crosstalk www.national.com (Note 10) -0.999 +0.8/-0.7 2.5 LSB (Note 10) -75 +18/-25 75 LSB 26 LSB RMS Minimum PGA Gain (Note 10) -76 Maximum PGA Gain (Note 10) -56 dB 96 LSB RMS Mode 3 26 Mode 2 17 10 10 dB LSB The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 27MHz unless otherwise specified. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25C. Symbol Parameter Conditions Min (Note 9) Typ (Note 8) Max (Note 9) Units 0.66 1 1 27 (Mode 3) 30 (Mode 2) 30 (Mode 1) MHz 2 81 (Mode 3) 60 (Mode 2) 30 (Mode 1) MHz 60/40 % Input Clock Timing Specifications INCLK = PIXCLK (Pixel Rate Clock) fINCLK Tdc Input Clock Frequency INCLK = ADCCLK (ADC Rate Clock) Input Clock Duty Cycle 40/60 50/50 Full Channel Latency Specifications 3 Channel Mode Pipeline Delay tLAT3 2 Channel Mode Pipeline Delay tLAT2 1 Channel Mode Pipeline Delay tLAT1 PIXPHASE0 24 PIXPHASE1 23 1/2 PIXPHASE2 23 PIXPHASE3 22 1/2 PIXPHASE0 21 PIXPHASE1 20 1/2 PIXPHASE2 20 PIXPHASE3 19 1/2 PIXPHASE0 19 PIXPHASE1 18 1/2 PIXPHASE2 18 PIXPHASE3 17 1/2 TADC TADC TADC SH_R Timing Specifications tSHR_S SH_R Setup Time 2 ns tSHR_H SH_R Hold Time 2 ns LVDS Output Timing Specifications TXpp0 TXCLK to Pulse Position 0 TXpp1 TXpp2 LVDS Output -0.26 0 0.26 ns TXCLK to Pulse Position 1 Specifications not 1.50 1.76 2.02 ns TXCLK to Pulse Position 2 tested in production. 3.26 3.53 3.79 ns TXpp3 TXCLK to Pulse Position 3 Min/Max guaranteed 5.03 5.29 5.55 ns TXpp4 TXCLK to Pulse Position 4 by design, 6.80 7.06 7.32 ns TXpp5 TXCLK to Pulse Position 5 characterization and statistical 8.56 8.82 9.08 ns TXpp6 TXCLK to Pulse Position 6 analysis. 10.32 10.58 10.84 ns 2 4.5 9 ns CMOS Output Timing Specifications tCRDO CLKOUT Rising Edge to CMOS Output Data Transition fINCLK = 40MHz INCLK = ADCCLK (ADC Rate Clock) Serial Interface Timing Specifications 11 www.national.com LM98725 AC Timing Specifications LM98725 Symbol Parameter Min (Note 9) Conditions Typ (Note 8) Max (Note 9) Units 27/30/30 MHz 81/60/30 MHz fSCLK <= fINCLK fSCLK Input Clock Frequency INCLK = PIXCLK (Pixel Rate Clock) Mode 3/2/1 fSCLK <= fINCLK INCLK = ADCCLK (ADC Rate Clock) Mode 3/2/1 SCLK Duty Cycle tIH 50/50 ns Input Hold Time 1.5 ns tIS Input Setup Time 2.5 ns tSENSC SCLK Start Time After SEN Low 1.5 ns tSCSEN SEN High after last SCLK Rising Edge 2.5 ns INCLK present 6 TINCLK tSENW SEN Pulse Width INCLK stopped (Note 11, Note 12) 50 ns tOD Output Delay Time tHZ Data Output to High Z 11 14 ns 0.5 TSCLK Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not recommended. Note 2: All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to two. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX - TA)/JA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through 0. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is limited per note 3. However, input errors will be generated If the input goes above VA and below AGND. 30085371 Note 8: Typical figures are at TA = 25C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not guaranteed. Note 9: Test limis are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: This parameter guaranteed by design and characterization. Note 11: If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter tSENW will be increased by the same factor. Note 12: When the Spread Spectrum Clock Generation feature is enabled, tSENW should be increased by 1. www.national.com 12 LM98725 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead TSSOP NS Package Number MTD56 13 www.national.com LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output Integrated Sensor Timing Generator and Spread Spectrum Clock Generation Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH(R) Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise(R) Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagicTM www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise(R) Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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