MT9D131C12STCES - Micron Technology, Inc.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Features

Preliminary‡

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1/3.2-Inch System-On-A-Chip (SOC) CMOS

Digital Image Sensor

MT9D131C12STC (Color, Pb-Free)

Features

•Micron

® DigitalClarity® CMOS imaging technology

• Superior low-light performan ce

• Ultra-low-power,cost-effective

• Internal master cl ock generated by on-chip phase-

locked loop oscillator (PLL)

• Electronic rolling shutter (ERS), progressive scan

• Integrated image flow processor (IFP) for single-die

camera module

• Automatic image correction and enh ance ment,

including lens shading correction

• Arbitrary image decimation with anti-aliasing

• Integrated real-time JPEG encoder

• Integrated microcontroller for flexibility

• Two-wire serial interface providing access to

r egisters and microcontrolle r memory

• Selectable output data format

–ITU-R BT.601 (YCbCr)

–565RGB

–555RGB

–444RGB

–JPEG 4:2:2

–JPEG 4:2:0

–Raw 10-bit

• Output FIFO for data rate equalization

•Programmable I/O slew rate

Applications

• Security surveillance cameras

•ePTZ cameras

• Wireless cameras

• Consumer video products

• Hi gh-resolution security cameras

Ordering Information

Table 1: Key Performance Parameters

Parameter Value

Optical format 1/3.2-inch (4:3)

Active imager size 4.73mm x 3.52mm

Active pixels 1600 x 1200 pixels (UXGA)

Pixel size 2.8µm x 2.8µm

Shutter ty pe Electro nic rolling shutter (ERS)

Maximum frame rate 15 fps at full resolution,

30 fps in preview mode,

(800 x 600)

Maximum data rate/

master clock 80 MB/s

6 MHz to 80 MHz

Supply voltage Analog 2.5−3.1V

Digital 1.7−1.95V

I/O 1.7−3.1V

PLL 2.5−3.1V

ADC resolution 10-bit, on-die

Responsivity 1.0V/lux-sec (550nm)

Dynami c ra nge 71dB

Output gain 16 e-/pix/s at 55°C

Read noise 3.6 e-RMS at 16X

Dark current 30 e-/pix/s at 55°C

SNRMAX 42.3dB

Power consumption 348mW at 15 fps, full resolution

223mW at 30 fps, preview mode

Operating temperature –30°C to +70°C

Package Bare die, 48-pin CLCC

Table 2: Available Part Numbers

Part Number Description

MT9D131C12STC ES 48-pin CLCC (Pb-free) ES

MT9D131C12STCD ES Demo kit

MT9D131C12STCH ES Demo kit headboard

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

General Description

Preliminary

General Description

Micron I maging MT9D131 is a 1/3.2 inch, 2-megapixel CMOS image sensor with an inte-

grated advanced came ra system. The camera system features a microcontroller (MCU)

and a sophisticated image flow processor (IFP) with a real-time JPEG encoder.

The sensor core consists of an active pixel array of 1668 x 1248 pixels, programmable

timing and control circuitry including a PLL, analog signal chain with automatic offset

correction and programmable ga in, and two 10-bit A/D converters (ADC). The entire

system-on-a-chip (SOC) has ultra-low power requirements and superior low-light per-

formance that is particularly suitable for a wide variety of applications.

Feature Overview

The MT9D131 is a color image se ns or with a Bayer color filter arrangement.

The MT9D131 has an embedded phase-locked loop oscillator (PLL) that can be used

with the common w ireless system cl ock. When in use, the PLL adjusts the incoming

clock frequency, allowing the MT9D131 to run at almost any resolution and frame rate.

To reduce power consumption, the PLL can be bypassed and powe red down. The

MT9D131 has numerous power conserving features, including an ultr a-low power

standby mode and the ability to individually shut down unused digital blocks.

Another important consideration for wireless devices is their electrom ag netic emission

or interference (EMI). The MT9D131 has a programmable I/O slew rate to minimize its

EMI and an output FIFO to eliminate output data bursts.

The advanced IFP and flexible progr a mmability of the MT9D131 provide a variety of

ways to enhance and optimize the image sensor performance. Built-in optimization

algorithms enable the MT9D131 to operate at factory settings as a fully automatic, highly

adaptable camera. However, most of its settings are user-pr o grammable by changing

Figure 1 illustrates the MT9D131 quantum efficienc y in relation to wavelength.

Figure 1: MT9D131 Quantum Efficiency

Quantum Efficiency

350 450 550 650 750 850 950 1050

Quantum Efficiency (%)

Blue

Green

Red

vs. Wavelength

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Typical Connection

Preliminary

Typical Connection

Figure 2: Typical Configuration (Connection)

Notes: 1. Resistor value 1.5KΩ is recommended, but may be greater for slower two-wire speed.

2. TEST must be connected to digital ground for normal device operation.

3. All power supply pads must be used.

10µF

1.5KΩ

STANDBY

DATA

SCLK

RESET#

TEST

FRAME_VALID

PIXCLK

LINE_VALID

OUT

0-D

OUT

EXTCLK

ADDR

1KΩ

GND

DD3

PLL

AA3

To CMOS

Camera Port

Two-Wire

Serial Bus

6 MHz–80 MHz

Clock

VAAPIX

PLL

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Signal Description

Preliminary

Signal Description

Table 3: S ignal Description

Name CLCC Pin Type Description

EXTCLK 40 Input Master clock signal (can either drive the on-chip PLL or bypass it).

RESET# 39 Input Master reset signal, active LOW.

STANDBY 38 Input Controls sensor’s standby mode.

TEST 20 Input Reserved for factory test. Tie to digital ground during normal

operation.

SCLK 34 Input Two-wire serial interface clock.

SADDR 35 Input Selects device address for the two-wire serial interface. The

address is 0x90 when SADDR is tied LOW, 0xBA if tied HIGH. See

also R0x0D:0[10].

DOUT[7:0] 8, 9, 10, 11, 14, 15, 16,

17 Input Eight-b it image data output or most significant bits (MSB) of 10-

bit sensor bypass mode.

FRAME_VALID 1 Input Identifies rows in the active image.

LINE_VALID 48 Input Identifies lines in th e active image.

PIXCLK 47 Input Pixel clock. To be used for sampling DOUT, FRAME_VALID, and

LINE_VALID.

SDATA 46 I/O Two-wire serial interface data.

VDD 2, 3, 12, 24, 25, 36 Supply Digital power (1.8V).

VDDPLL 41 Supply PLL power (2.8V).

VAA 32, 33 Supply Analog power (2.8V).

VAAPIX 26, 27 Supply Pixel array power (2.8V).

VDDQ 21, 22, 44, 5 Supply I/O power (nominal 1.8V or 2.8V).

AGND 29, 30, 31 Supply Analog ground.

DGND 4, 6, 7, 13, 18, 19, 23,

28, 37, 42, 43, 45 Supply Digital, I/O, and PLL ground.

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Signal Description

Preliminary

Figure 3: 48-Pin CLCC Pinout

12345644 43

19 20 21 22 23 24 25 2627 28 29 30

GND

OUT

GND

OUT

GND

VDDPLL

EXTCLK

RESET#

STANDBY

GND

SADDR

SCLK

GND

TEST

GND

VAAPIX

GND

VDD

GND

FRAME_VALID

LINE_VALID

PIXCLK

DATA

GND

48 47 4645

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Architecture Overview

Figure 4: Block Diagram

Sensor Core The MT9D131 sensor core is a 2-megapixel CMOS image sensor with a 2.8µm pixel size

designed for an optical format of 1/3.2 inches with a UXGA maximum resolution. The

MT9D131 sensor core includes a phase-locked loop oscillator (PLL), to facilitate camera

integrati on and mini mi z e the system cost for wireless and mobile applications. When in

use, the PLL generates an internal master clock si gnal whose fr equency can be set higher

than the frequency of external clock signal EXTC LK. This allows the MT9D131 to run at

any resolution and frame rate up to the specified maxi mum values, irrespective of the

EXTCLK frequency.

Interpolation

Line Buffers Other JPEG

Memories

JPEG

Line Buffers

Decimator

Line Buffers

Sensor

Core Color Pipeline JPEG

ROM Micron

controller SRAM

Stats Engine PLL

Internal Register Bus

Image Flow Processor

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Color Pipeline

Figure 5: Color Pipeline

Test Pattern During normal operation of MT9D131, a stream of raw image data from the sensor core

is continuously fed into the c o lor pip el ine. For test purposes, this stream can be

replaced with a fixed image gener ated by a special test module in the pi peline. The mod-

ule provides a selection of test patterns sufficient for basic testing of the pipeline.

Test Pattern

Line Buffers

Lens Shading Correction

with Digital Gain

Digital Gain

Defect Correction

Black Level Subtraction

Interpolation and

Edge Detection

Decimator

YUV Processing

Gamma Correction

YUV-to-RGB/YUV Conversion

CCM and Aperture

Correction

Format Output

AE Statistics

MEASUREMENT ENGINE

DATA, SYNC IN

DATA, SYNC OUT

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Black Level Conditioning and Digital Gain

Image stream processing starts with black level conditioning and multiplication of all

pixel values by a programmable digital gain.

Lens Shading Correction

Inexpensive lenses tend to produce images whose brightness is significantly attenuated

near the edges. Chromatic aberration in such l enses can c ause color v ariatio n across the

field of view. There are also other factors causing fixed-pattern signal gradients in

images capture d by image sensors. The cumulativ e result of all these factors is known as

lens shading. The MT9D131 has an emb edded l ens shadi ng correction (LC) module that

can be programme d to precisely counter the shading effect of a lens on each RGB color

signal. The LC module multiplies RGB signals by a 2-dimensional correction function

F(x,y), whose profile in both x and y dir ec ti o n is a piecewise quadratic polynom ial with

coefficients independently programmable for each direction and color.

Line Buffers Several data processing steps following the lens shading correction require access to

pixel values from up to 8 consecutive image lines. F o r these lines to be simultaneousl y

available for processing, they m ust be buffer ed. The IFP includes a number of SRAM line

buffers that are used to perform defect correction, color interpolation, image decima-

tion, and JPEG encoding.

Defect Correction The IFP performs on-the-fly de fec t correction that can mas k p ixel array defects such as

high-dark-current (“hot”) pixels and pi xels that are darker or brighter than their neigh -

bors due to photoresponse nonuniformity. The defect correction algorithm uses several

pixel features to distinguish between normal and defective pixels. After identifying the

latter, it replaces their actual values with values inferred from the va lues of nearest

same-color neighbors.

Color Interpolation and Edge Detection

In the raw da ta stream fed by the sensor core to the IFP, each pixel is represented by a

10-bit integer number, which, to make things simple, can be considered proportional to

the pixel’s response to a one-color light stimulus—red, green, or blue—depend i ng on

the pixel’s position under the color filter array. Initial data processing steps, up to and

including the defect correction, preserve the one-color-per-pixel nature of the data

str eam, but after the defect correction it must be converted to a three-co lors-per -pixel

stream appropriate for standard color processing. The conversion is done by an edge-

sensitive colo r interpolation module. The module pads th e incomplete color informa-

tion available for each pixel with information extracted from an appropriate set of

neighboring pixels. The algorithm used to select this set and extract the information

seeks the best compromise between maintaini n g the sharpness of the image and filter-

ing out high-frequency noise. The simplest interpolation algorithm is to sort the nearest

eight neighbors of every pixel into three sets—r ed, green, and blue, discard the set of

pixels of the same color as the center pixel (if there are any), calculate average pixel val-

ues for the re maining two sets, and use the aver ages ins tead of the missing color data for

the center pixel. Such averaging reduces high-fr equency noise, but it also blurs and dis-

torts sharp transitions (edges) in the image. To avoid this problem, the interpolation

module performs edge detection in the neighborhood of every processed pixel and,

depending on its r esults , extracts color information from nei ghboring pixels in a number

of different ways. In effect, it does low-pass filtering in flat-field image areas and avoids

doing it near edges.

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Color Correction and Aperture Correction

To achieve good color fidelity of IFP output, interpolated RGB values of all pixels are

subjected to color corre ction. The IFP multiplies each vector of thr ee pixel colors b y a

3 x3 color correcti on matrix. The three components of the resulting color vector are all

sums of three 10-bit numbers. S ince such sums can have up to 12 significant bits, the bit

width of the image data stream is widened to 12 bits per color (36 bits per pixel). The

color correction matrix can be either programmed by the user or automatically selected

by the auto white balance (AWB) algorithm implemented in the IFP. Color corr ection

should ideally produce output colors that are independent of the spectral sensitivity and

color cross-talk characteristics of the image sensor. The optimal values of color correc-

tion matrix elements depend on those sensor characteristics and on the spectrum of

light incident on the sensor.

To increase image sharpness , a programmab le aperture correction is applied to color

corrected image data, equally to ea ch of th e 12-b it R, G, and B color channels.

Gamma Correction Like the apertur e correction, gamma correction is applied equall y to each of the 12-bit R,

G, and B color channels . Gamma correction curve is implemented as a piecewise linear

function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit out-

put. The driver variables include two arrays of knee point ordinates defining two sepa-

rate gamma curves for sensor operation contexts A and B.

YUV Processing After the gamma correction, the image data stream undergoes RGB to YUV conversion

and optionally further corrective processing. The first step in this processing is removal

of highlight coloration, also r efe rred to as “color kill.” It affects only pixels whose bright-

ness exceed s a certain pre-programmed thr eshold. The U and V values of those pixels

are attenuated proportionally to the difference betwe en their brightness and the thresh-

old.

Image Cropping and Decimation

To ensure that the size of images output by MT9D131 can be tailored to the needs of all

users, the IFP includes a decimator module. When enabled, this module performs “dec-

imation” of incoming images, that is, shrink s them to arbitrar ily selected width and

height without r educing the field of view and without discarding any pixel values. The

latter point merits underscoring, because the terms “decimator” and “image decima-

tion” suggest image size reduction by deleting columns and/or rows at regular intervals.

Despite the termi nology, no such deletions take place in the decimator module. Instead,

it performs “pixel binning,” that is, d ivides each input image into rectangular bins corre-

sponding to individual pixels of the desired output image, averages pixel values in these

bins,and assembles the output image from the bin averages. Pixels lying on bin bound-

aries contribute to more than one bin average: their values are added to bin-wide sums

of pixel values with fractional weights. The entire procedure preserves all image infor-

mation that can be included in the downsized output image and filters out high-fre -

quency features that could cause aliasing.

The image decimation in the IFP can be prec eded by image cropping and/or image de c-

imation in the sensor core. Image cropping takes place when the sensor core is pro-

grammed to output pixel values from a rectangular portion of its pixel arr ay - a windo w -

smaller than the default 1600 x 1200 window. Pixels outside the selected cropping win-

dow are not read out, which results in narrower field of view than at the default sensor

settings. Irrespective of the size and position of the cropping window, the MT9D131 sen-

sor core can also decim ate outgoing images by s kipping c olumns and/or ro ws of the

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

pixel array, and/or by binning 2 x 2 groups of pixels of the same color. S ince decimation

b y skipping (that is, deletion) can cause aliasing (even if pixel binning is simultaneously

enabled), it is generally better to change image size only by cropping and pixel binning.

The image cropping a nd de c im a tor module can be used to do digital zoom and pan. If

the decimator is programmed to output images smaller than images coming from the

sensor core, zoom effect can be produced by cropping the latter from their maximum

size down to the size of the output images. The ratio of these two sizes determines the

maximum attainable z oom factor. For example, a 1600 x 120 0 image rendered on a

160 x 120 display can be zoomed up to 10 times, since 1600/160 = 1200/120 = 10. Pan-

ning effect can be achie ved by fixing the size of the cropping window and moving it

around the pixel array.

YUV-to-RGB/YUV Conversion and Output Formatting

The YUV data str eam emerging from the decimator module can either exit the color

pipeline as-is or be converted before exit to an alternative YUV or RGB data format.

JPEG Encoder and FIFO

The JPEG compr e ssion eng ine in the MT9D131 is a hig hly integr ated, high-performance

solution that can provide sustained data rates of almost 80 MB/s for image sizes up to

1600 x 1200. Additionally, the solution provides for lo w power consumption and full

programmability of JPEG compression parameters for image quality control.

JPEG Encoding Highlights

1. Sequential DCT (baseline) ISO/IEC 10918-1 JPEG-compliant

2. YCbCr 4:2:2 format compression

3. Programmable quantization tables

• One each for luminance and chrominance (active)

• S upport for three pairs of quantization tables—two pairs serve as a backup for buffer

overflow

4. Programmable Huffman Tables

• 2 AC, 2 DC tables—separate for luminance and chrominance

5. Quality/compression ratio control capability

6. 15 fps MJPEG capability (header processing in external host processor)

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Output Interface

Control (Two-Wire Serial Interface)

Camera control and JPEG configuration/control are accomplished using a two-wire

serial interface. The interface supports individual access to all camera function registers

and JPEG control registers. In particular, all tables located in the JPEG quantization and

Huffman memories are accessible using the two-wir e interface.

Context and Operational Modes

The MT9D131 can operate in several modes, including preview, still capture (snapshot),

and video . All modes of operati on ar e individually configur able and ar e organiz ed as two

contexts—context A and context B . A context is defined by sensor image siz e , fr ame rate,

resolution and other associated parameters. The user can switch between the two con-

texts by sending a command through the two-wire serial interface.

Preview Context A is primarily intended for use in the preview mode. During preview, the sensor

usually outputs low resolution images at a relatively high frame rate, and its po wer con-

sumption is kept to a minimum. Context B can be configured for the still capture or

video mode , as required by the user. For still capture configuration, the user typically

specifies the desired output image size, if JPEG compression, how many frames to cap-

ture, and so on. For video, the user might select a different image size and a fixed frame

rate.

Snapshot To take a snapshot, the user must send a command that changes the context from A to

context B . Typical sequence of events after this command is as follows. First, the camera

exposure and white balance is automatically adjusted to the changed illuminati on of the

scene. Next, the camera enables JPEG compression and capture one or more frames of

desired size. Completing the sequence, the camera automatically returns to context A

and resume running preview.

Video To start video capture, the user has to change relevant context B settings, such as cap-

ture mode , image size and frame ra te, and again send a context change command. U pon

receiving it, the MT9D131 switches to the modified context B settings, while continuing

to output YUV-encoded imag e data. Auto exposure automatically switches to smooth

continuous operation. To exit the video capture mode, the user has to send another con-

text change command causing the sensor to switch back to context A.

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Auto Exposure The auto exposure (AE) algorithm performs automatic adjustments of the image bright-

ness by controlling exposure time and analog gains of the sensor core as well as digital

gains applied to the image.

Two auto exposure algorithm modes are available:

1. preview

2. scene evaluative

Auto exposure is implemented by means of a firmware driver that analyzes image statis-

tics collected by exposure measurement engine, makes a decision and programs the

sensor core and color pipeline to achieve the desired exposure. The measurement

engine subdivides the image in to 16 windows organized as a 4 x 4 grid.

Preview Mode This exposure mode is activated during preview or video capture. It relies on the expo-

sure me asure ment engi ne that tracks speed and amplitude of the change of the overall

luminance in the selected windows of the image.

The backlight compensation is ac hieve d b y we ighting the luminance in the center of the

image higher than the l uminance on the periphe ry. Other algorithm featur es include the

rejection of fast fluctuations in illumination (time averaging), control of speed of

response, and control of the sensitivity to the small changes. While the default settings

are adequate in most situations, the user can program target brightness, measurement

window, and other parameters described above.

Scene Evaluative Algorithm

A scene evaluative AE algorithm is available for use in snapshot mode. The algorithm

performs scene analysis and classification with respect to its brightness, contrast and

composure and then decides to inc rease, decrease or keep original exposu re target. It

makes most difference for backlight and bright outdoor conditions.

Auto White Balance

The MT9D131 has a built-in auto white balance (AWB) algorithm designed to compen-

sate for the effects of changing spectra of the scene illumination on the quality of the

color rendition. This sophisticated algorithm consists of two major parts: a measure-

ment engine performing statistical analysis of the image and a driver performing the

selection of the optimal color correction matrix, digital, and sensor core analog gains.

While default settings of these algorithms are adequate in most situations, the user can

re-pr ogr am base color correction matrices, place limits on color channel gains, and con-

trol the speed of both matrix and gain adjustments. Unlike simple white balancing algo-

rithms found in many PC cameras, the MT9D131 AWB does not require the presence of

gray or white elements in the image for good color r endition. The AWB does not attempt

to locate "brightest" or "grayest" element of the image but instea d performs s ophi st i-

cated image analysis to differentiate between changes in predominant spectra of illumi-

nation and changes in predominant colors of the scene. Whi le defaults are suit able for

most applications, a wide range of algorithm parameters can be overwritten by the user

using the serial interface.

Flicker Detection Flicker occurs when the integration time is not an integer multiple of the period of the

light intensity. The automatic flicker detection block does not compensate for the

flicker, but rather avoids it by detecting the flicker frequency and adjust ing the integra-

tion time. For integration ti mes below the light intensity period (10ms for 50Hz environ-

ment), flicker cannot be avoide d.

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Architecture Overview

Preliminary

Figure 6: Sensor Core Block Diagram

The core of the sensor is an active -pixel array. The timing and control circuitry

sequences throug h th e rows of the array, resetting and then reading each row. In the

time interval between resetting a row and reading that row, the pixels in that row inte-

grate incident light. The exposure is controlled by varying the time interval between

reset and readout. After a row is read, the data from the colu mns is sequenced thro ugh

an analog signal chain (providing offset correction and gain), and then through an ADC.

The output from the ADC is a 10-bit va lue for each pixel in the array. The pixel array con-

tains optically active and light-shielded “black” pixels. The black pixels are used to pro-

vide data for on-chip offset correction algorithms (black level control ).

Die Outline

Figure 7: Optical Center Offset

Note: Figure not to scale.

Active-Pixel Sensor

(APS) Array

UXGA

1600H x 1200V

Serial

I/O

Data

Out

Sync

Signals

Control Register

Analog Processing ADC

Timing and Control

Last Clear Pixel

(Col 1683, Row 1235)

First Clear Pixel

(Col 52, Row 20)

Optical Center

(167.84μm, 2.06μm)

Die Center

(0μm, 0μm)

7845.05μm

(bare die)

8199.35μm

(bare die)

PLL

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Electrical Specifications

Preliminary

Electrical Specifications

Recommended die operating temperature range is from –20° to +55°C. The sensor image quality

may degrade above +55°C.

Table 4: AC Electrical Characteristics

Symbol Definition Conditions Min Type Max Units

fEXTCLK1 Input clock frequency PLL enabled

(MCLK max = 80 MHz) 61064MHz

tEXTCLK1 Input clock period PLL enabled

(MCLK max = 80 MHz) 15.625 100 166.7 ns

fEXTCLK2 Input clock frequency PLL disabled 6 80 MHz

tEXTCLK2 Input clock period PLL disabled 12.5 166.7 ns

tRInput clock rise time 0.5 1 V/ns

tFInput clock fall time 0.5 1 V/ns

Clock duty cycle 40 50 60 %

fPIXCLK PIXCLK frequency Default MHz

tPD PIXCLK to data valid Default –3 3 ns

tPFH PIXCLK to FV HIGH Default –3 3 ns

tPLH PIXCLK to LV HIGH Default –3 3 ns

tPFL PIXCLK to FV LOW Default –3 3 ns

tPLL PIXCLK to LV LOW Default –3 3 ns

CIN Input pin capacitance 3.5 pF

CLOAD Load capacitance 15 20 pF

Table 5: AC Setup Conditions

Symbol Min Typ Max Units

fEXTCLK1 6–64MHz

VDD 1.7 1.8 1.95 V

VDDQ1.7 2.8 3.1 V

VAA 2.5 2.8 3.1 V

VAAPIX 2.5 2.8 3.1 V

VDDPLL 2.5 2.8 3.1 V

Output load –15– –

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Electrical Specifications

Preliminary

Notes: 1. Due to the influence of several variables (scene illumination, output load) maximum val-

ues are not available.

2. Context B: 1600 x 1200, JPEG on, MCLK = MAX, PIXCLK = MAX.

3. Context A: 800 x 600, No JPEG, MCLK = MAX, PIXCLK = MAX.

Table 6: DC Electrical Definitions and Characteristics

Symbol Definition Conditions Min Typ Max Units Note

VDD Core digital vo ltage 1.7 1.8 1.95 V

VDDQ I/O digital voltage 1.7 2.8 3.1 V

VAA Analog voltage 2.5 2.8 3.1 V

VAAPIX Pixel supply voltage 2.5 2.8 3.1 V

VDDPLL PLL supply voltage 2.5 2.8 3.1 V

VIH Input high voltage VDDQ = 2.8V 2.4 VDDQ+0.3 V

VDDQ = 1.8V 1.4 VDDQ+0.3

VIL Input low voltage VDDQ = 2.8V GND – 0.3 0.8 V

VDDQ = 1.8V GND – 0.3 0.5

IIN Input leakage current No pull-up resistor; VIN = VDDQ

or DGND –10 0.5 10 μA

VOH Output high voltage At specified IOH VDDQ – 0.4 V

VOL Output low voltage At specified IOL 0.4 V

IOH Output high cu rrent At spec ified VOH = VDDQ~400MV

AT 1.7V VDDQ–7 x mA

IOL Output low current At specified VOL~ 400MV at 1.7V

VDDQ7xmA

IOz Tri-state output leakage

current VIN = VDDQ or GND –10 +/-0.5 10 μA

IDD1 Digital operating current Context B, 1600 x 1200, JPEG on,

MCLK = MAX, PIXCLK = MAX 92 110 mA

IDDQ1 I/O digita l operating

current Context B, 1600 x 1200, JPEG on,

MCLK = MAX, PIXCLK = MAX 1.5 mA 1

IAA1 Analog operating current Context B, 1600 x 1200, JPEG on,

MCLK = MAX, PIXCLK = MAX 43 55 mA

IAAPIX1 Pixel supply current Context B, 1600 x 1200, JPEG on,

MCLK = MAX, PIXCLK = MAX 2.1 3.5 mA

IDDPLL1 PLL supply current Context B, 1600 x 1200, JPEG on,

MCLK = MAX, PIXCLK = MAX 2.3 3 mA

IDD2 Digital operating current Context A, 800 x 600, No JPEG,

MCLK = MAX, PIXCLK = MAX 48 60 mA

IDDQ2 I/O digita l operating

current Context A, 800 x 600, No JPEG,

MCLK = MAX, PIXCLK = MAX 15 mA 1

IAA2 Analog operating current Context A, 800 x 600, No JPEG,

MCLK = MAX, PIXCLK = MAX 27 35 mA

IAAPIX2 Pixel supply current Context A, 800 x 600, No JPEG,

MCLK = MAX, PIXCLK = MAX 45.5mA

IDDPLL2 PLL supply current Context A, 800 x 600, No JPEG,

MCLK = MAX, PIXCLK = MAX 2.3 3 mA

ISTDBY1 Standby cu rrent PLL

enabled PLL enabled (MCLK = 0Hz, held

at eithe r VIL or VIH)35 100 μA

ISTDBY2 Standby current PLL

disabled PLL disabled (MCLK = 0Hz, held

at VIL or VIH)35 100 μA

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Electrical Specifications

Preliminary

Note: 1Stresses above those listed may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at these or any other co nditions ab ove

those indicated in the product specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VDD Digital power –0.3 2.4 V

VDDQ I/O power –0.3 4.0 V

VDDPLL PLL power –0.3 4.0 V

VAA Analog power (2.8V) –0.3 4.0 V

VAAPIX Pixel array power –0.3 4.0 V

VIN DC input voltage –0.3 VDDQ+0.3 V

VOUT DC output voltage –0.3 VDDQ+0.3 V

TOP Operation temperature –30 70 °C

TSTG1Storage temperature –40 85 °C

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-49 92

Micron, the M logo, the Micr on logo, and DigitalClarity are tr ademarks of Micron Technology, Inc. All other trademarks are

the property of their respective owners. Preliminary: This data sheet contains initial characteri zation limits that are subject

to change upon full characterization of production devices.

MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Package Dimensions

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Preliminary

Package Dimensions

Figure 8: 48-Pin CLCC Package Outline

1.02

TYP 148

11.22

5.61

6.66.03

7.11

2.16 ±0.20

1.02 TYP

48X

0.51 ±0.05

13.6 ±0.1

CTR

13.6 ±0.1

CTR

7.11

14.22

5.61

6.6 Optical area

Maximum rotation of optical area

relative to package edges: 1º

Maximum tilt of optical area

relative to seating plane A : 50 microns

relative to top of cover glass D : 100 microns

Seating

plane

2.3 ±0.2

Lid material: borosilicate glass 0.55 thickness

Wall material: alumina ceramic

Substrate material: alumina ceramic 0.7 thickness

0.90

for reference only

1.400 ±0.125

0.35

for reference only

0.10 A0.05

Image

sensor die:

0.675 thickness

Note: 1. Optical center = package center.

First

clear

pixel

H CTR

Ø0.20 A B C

V CTR

Ø0.20 A B C

Optical

center

47X

1.02 ±0.20

0.24X

Lead finish:

Au plating, 0.50 microns

minimum thickness

over Ni plating, 1.27 microns

minimum thickness

48X R0.19

1.7

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MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor

Revision History

Preliminary

Revision History

Rev.B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/28/2007

• Updated package information