M36P0R9060E0ZACE - STMicroelectronics

July 2006 Rev. 2 1/23

M36P0R9060E0

512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory

64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package

Feature summary

■Multi-Chip Package

– 1 die of 512 Mbit (32Mb x 16, Multiple

Bank, Multi-Level, Burst) Flash memory

–1 die of 64 Mbit (4Mb x16) PSRAM

■Supply voltage

–V

DDF = VCCP = VDDQ = 1.7 to 1.95V

–V

PPF = 9V for fast program

■Electronic signature

– Manufacturer Code: 20 h

– Device Code: 8819

■ECOPACK® package

Flash memory

■Synchronous / asynchronous read

– Synchronous Burst Read mode:

108MHz, 66MHz

– Asynchronous Page Read mode

– Random Access: 96ns

■Programming time

– 4.2µs typical Word program time using

Buffer Enhanced Factory Program

command

■Memory organization

– Multiple Bank memory array: 64 Mbit banks

– F our Extended Fl ash Arr a y (EFA) Blocks of

64 Kbits

■Dual operations

– program/erase in one Bank while re ad in

others

– No delay between read and write

operations

■Security

– 64 bit unique device number

– 2112 bit user programmable OTP Cells

■100,000 Program/erase cycles per block

■Common Flash Interface (CFI)

■Block locking

– All Blocks locked at power-up

– Any combination of Blocks can be locked

with zero latency

–WP

F for Block Lock-Down

– Absolute Write Protection with VPPF = VSS

PSRAM

■User-selectable operating modes

– Asynchronous mo des: Random Read, and

Write, Page Read

– Synchronous modes: NOR-Flash, Full

Synchronou s (Bu rs t Rea d and Write)

■Asynchronous Random Read

– Access time: 70ns

■Asynchronous Page Read

– Page size: 4, 8 or 16 Words

– Subsequent Read withi n Page: 20ns

■Burst Read

– Fixed length (4, 8, 16 or 32 Words) or

Continuous

■Low power cons ump tion

– Active current: < 25mA

– Standby current: 140µA

– Deep Power-Down current: < 10µA

■Low-power features

– Partial Array Self-Refresh (PASR)

– Deep Power-Down (DPD) Mode

– Automatic Temperature-compensated Self-

Refresh

TFBGA107 (ZAC)

FBGA

www.st.com

M36P0R9060E0

2/23

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Flash Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Flash Output Enable inputs (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.8 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.9 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.11 PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.14 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.15 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.16 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 11

2.17 Deep Power-Down input (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.18 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.19 VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.20 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.21 VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.22 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

M36P0R9060E0

3/23

6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

M36P0R9060E0

4/23

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

M36P0R9060E0

5/23

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . 19

1 Summary description M36P0R9060E0

6/23

1 Summary description

The M36P0R9060E0 combines two memory devices in a Multi-Chip Package:

●512-Mbit Multiple Bank Flash memory (the M58PR512J)

●64-Mbit PSRAM (the M69KB096AM)

The purpose of this document is to de scribe ho w the tw o me mory components opera te with

respect to each other. It must be read in conjunction with the M58PRxxxJ and

M69KB096AM datashee ts, where all specifications required to ope rate the Flash memory

and PSRAM components ar e fully detailed. These datasheets are available from the

STMicroelectronics website: www.st.com.

Recommended oper at ing cond itions d o not allo w mo re tha n one memory to be active at the

same time.

The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bits

erased (set to ‘1’).

Figure 1. Logic diagram

AI10994

A0-A24

DQ0-DQ15

VDDQ

M36P0R9060E0

VSS

RPF

WPF

VDDF

DPDF

UBP

LBP

VPPF

VCCP

CRP

WAIT

M36P0R9060E0 1 Summary description

7/23

Table 1. Signal names

A0-A24(1)

1. A22-A24 are Address Inputs for the Flash memory component only.

Address Inputs

DQ0-DQ15 Common Data Input/Output

VDDQ Common Flash and PSRAM Power Supply for I/O Buffers

VPPF Flash Memor y Optional Supply Voltage for Fast Program & Erase

VDDF Flash Memory Power Supply

VCCP PSRAM Power Supply

VSS Ground

LLatch Enable inpu t

K Burst Clock

WAIT Wait Output

NC Not Connected Internally

DU Do Not Use as Internally Connected

Flash Memory

EFChip Enable input

GFOutput Enable Input

WFWrite Enable input

RPFReset input

WPFWrite Protect input

DPDFDeep Power-Down

PSRAM

EPChip Enable Input

GPOutput Enable Input

WP Write En able Input

CRP Configuration Register Enable Input

UBP Upper Byte Enable Input

LBP Low e r Byte Enable Input

1 Summary description M36P0R9060E0

8/23

Figure 2. TFBGA connections (top view through package)

AI11098B

DQ14

DQ0

A16

WAIT

DQ13

DQ8

HDQ7

A17

A22

BA21

87654321

A11

WPA13

A12

JDQ15

VSS

DQ6

DQ12

DQ4

DQ10

VSS

VPPF

A18 VSS

DQ11

DQ1

A23

A24

A19

DQ9

A14

A20

VDDF

DQ3

DQ5

DQ2

DU DU DU DU

NC NC

NC VCCP DPDFVSS

VSS

VDDQ

LBP

EPA9

WPFA10 A15

UBPRPFWF

NC EF

VCCP VDDQ CRP

VSS VDDQ VDDF VSS VSS VSS VSS

M36P0R9060E0 2 Signal descriptions

9/23

2 Signal descriptions

See Figure 1., Logic diagr am and Table 1., Signal names, for a brief ov erview of the signals

connected to this device.

2.1 Address inputs (A0-A24)

Addresses A0- A21 are common inputs for the Flash memory and PSRAM components.

Addresses A22 and A24 are inputs for the Flash memory component only. The Address

Inputs select the cells in the Flash memory array to access during Bus Read operations.

During Bus Write operations they control the commands sent to the Command Interface of

the Flash memory’s Program/Erase Controller.

In the PSRAM the Address Inputs select the cells in the memory arra y to access during Bus

read and write operations.

2.2 Data input/output (DQ0-DQ15)

The Data I/O outp ut the data stored at th e selected address during a Bus Read oper ation or

input a command or the data to be programmed during a Bus Write operation.

F or the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the

data to or from the upper part of the selected address when Upper Byte Enable (UBP) is

driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the

low er part of the selected address whe n Low er Byte Enab le ( LBP) is driv en Lo w. When both

UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance.

2.3 Latch Enable (L)

The Latch Enable pin is common to the Flash memory and PSRAM components.

For details of how the Latch Enable signal behaves, please refer to the da tasheets of the

respective memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the

Flash memory.

2.4 Clock (K)

The Clock input pin is common to th e Flash memory and PSRAM components.

F or details of how the Cloc k signal be ha v es, pl ease ref er to the datashee ts of the respectiv e

memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the Flash

memory.

2 Signal descriptions M36P0R9060E0

10/23

2.5 Wait (WAIT)

W AIT is an output pin commo n to the Flash memory and PSRAM components . How e v er the

WAIT signal does not beha ve in the same way for the PSRAM and the Flash memory.

For details of how it behaves, please refer to the M6 9KB096AM datasheet for the PSRAM

and to the M58PRxxxJ datasheet for the Flash me mory.

2.6 Flash Chip Enable input (EF)

The Chip Enable input activates the cont rol logic, input buffers, decoders and sense

amplifiers of the Flash memory. When Chip Enable is Low, VIL, an d Reset is High, VIH, the

de vice is in activ e mode . When Chip Enable is at VIH the Flash memo ry are deselected, the

outputs are high impedance and the power consumption is reduced to the standb y level.

It is not allowed to have EF at VIL and EP at VIL at the same time. Only one memory

component can be enabled at a time.

2.7 Flash Output Enable inputs (GF)

The Output Enable inp ut controls the data outputs during Flash memory Bus Read

operations.

2.8 Flash Write Enable (WF)

The Write Enable input controls the Bus Write operation of the Flash memory Command

Interface. The data and address input s are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.9 Flash Write Protect (WPF)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-

Down b loc ks cannot be changed. When Write Protect is at High, VIH, Loc k-Do wn is disabled

and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the

M58PRxxxJ datasheet).

2.10 Flash Reset (RPF)

The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the

memory is in Reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset Supply Current IDD2. Refer to the M58PRxxxJ datasheet, for the value

of IDD2. After Reset all blocks are in the Locked state and the Configuration Regis te r is

reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the

device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any addition al circuitry. It can be tied

to VRPH (refer to the M58PRxxxJ datasheet).

M36P0R9060E0 2 Signal descriptions

11/23

2.11 PSRAM Chip Enable input (EP)

The Chip En able input activ ates the PSRAM whe n driven Lo w (asserted). When deasserted

(VIH), the de vice is disabled, and goes automatically in low-power Standby mode or Deep

Power-down mode, according to the RCR (Ref resh Configuration Register) setting.

2.12 PSRAM Write Enable (WP)

Write Enable, WP

, controls the Bus Write operation of the PSRAM. When asserted (VIL), the

device is in Write mode and Write operations can be performed either to the configuration

registers or to the memory array.

2.13 PSRAM Output Enable (GP)

When held Low, VIL, the Output Enable, GP

, enables the Bus Read operations of the

PSRAM.

2.14 PSRAM Upper Byte Enable (UBP)

The Upper Byte En-able, UBP

, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-

DQ15) to or from the upper part of the selected address during a Write or Read operation.

2.15 PSRAM Lower Byte Enable (LBP)

The Lower Byte Enable, LBP

, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-

DQ7) to or from the lower part of the selected address during a Write or Read operation.

If both LBP and UBP are disabl ed (High), the device will disable the data bus from receiving

or transmitting data. Although the device will seem to be deselected, it remains in an active

mode as long as EP remain s Low.

2.16 PSRAM Configuration Register Enable (CRP)

When this signal is driven High, VIH, bus read or write operations access either the value of

the Refresh Configuration Register ( RCR) or the Bus Configuration Register (BCR)

according to the value of A19.

2 Signal descriptions M36P0R9060E0

12/23

2.17 Deep Power-Down input (DPDF)

The Deep Power-Down input is used to put the device in a Deep Pow er-Down mode.

When the de vice is in Standby mo de and the Enhanced Con figuration Register bit ECR15 is

set, asserting the Deep Power-Down input will cause the memory to enter the Deep Power-

Down mode.

When the de vice is in the Deep P o wer-Do wn mode , the memory cannot be modified and the

data is protected.

The polarity of the DPD pin is determined by ECR14. The Deep Power-Down input is acti ve

Low by default.

2.18 VDDF Supply Voltage

VDDF provides the power supply to the internal core of the Flash memory. It is the main

power supply for all Flash memory operations (Read, Program and Erase).

2.19 VCCP Supply Voltage

The VCCP Supply Voltage is the core supply voltage.

2.20 VDDQ Supply Voltage

VDDQ provides the power su pply for the Flash memory and PSRAM I/O pins. This allows all

Outputs to be powered independently of the Flash memory and PSRAM core po wer

supplies, VDDF and VCCP

2.21 VPPF Program Supply Voltage

VPPF is both a control input and a po w er supply pin f or the Flash memory. The two f unctions

are selected by the voltage range applied to the pin.

If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this

case a voltage lower than VPPLK gives an absolute protection against Prog ram or Erase,

while VPPF > VPP1 enables these functions (see the M58PRxxxJ datasheet for the relevant

v al ues). VPPF is only sampled at the beginning of a Program or Erase; a change in its value

after the ope ration has started does not have any effect and Program or Erase operations

continue.

If VPPF is in the range of VPPH it acts as a power supp ly pin. In this condition VPPF must be

stable until the Program/Erase algorithm is completed.

M36P0R9060E0 2 Signal descriptions

13/23

2.22 VSS Ground

VSS is the common ground reference for all voltage measurements in the Flashmemory

(core and I/O Buffers) and PSRAM chip s. It must be connec te d to th e system ground.

Note: Each Flash memory device in a system should have their supply voltage (V DDF) and

the program supply voltage VPPF decoupled with a 0.1µF cer amic capa citor close to th e pin

(high frequency, inherently low inductance capacitors should be as close as possible to the

package). See Figure 5., AC measurement load circuit. The PCB track widths should be

sufficient to carry the required VPPF program and erase currents.

3 Functional description M36P0R9060E0

14/23

3 Functional description

The PSRAM and Flash memory components have separate power supplies but share the

same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory

and EP for the PSRAM.

Recommended operating conditions do not allow more than one device to be activ e at a

time. The most common example is a simultaneous read operations on the Flash memory

and the PSRAM which would result in a data bus contention. Therefore it is recommended

to put the other device in the high impedance state when reading the selected device.

Figure 3. Functional block diagram

Ai10995

CRP

A0-A21

64 Mbit

PSRAM

UBP

LBP

WAIT

VDDQ

VSS

VCCP

512 Mbit

Flash

Memory

VDDF

RPF

WPF

VPPF

A22-A24

DQ0-DQ15

DPDF

M36P0R9060E0 3 Functio nal description

15/23

Table 2. Main operating modes(1)

Operation(2)

(3) EF GFWFLRPFDPDF(4) WAIT

(5) EPCRPGPWPLBP,

UBPA19 A18 A0-A17

A20-

A21

DQ15-

DQ0

Flash Bus

Read VIL VIL VIH VIL(6) VIH de-

asserted(7)

PSRAM must be

disabled.

Flash

Data Out

Flash Bus

Write VIL VIH VIL VIL(6) VIH de-

asserted(7) Flash

Data In

Flash

Address

Latch VIL XV

IH VIL VIH de-

asserted(7) Flash

Data Out

or Hi-Z (8)

Flash Output

Disable VIL VIH VIH XV

IH de-

asserted(7) Hi-Z

Any PSRAM mode is

allowed.

Hi-Z

Flash

Standby VIH XX X V

IH de-

asserted(7) Hi-Z Hi-Z

Flash Reset XXX X V

IL de-

asserted(7) Hi-Z Hi-Z

Flash Deep

Power-Down VIH X X X VIH asserted(9) Hi-Z Hi-Z

PSRAM Read

Flash memory must be disabled

VIL VIL VIL VIH VIL Valid PSRAM

data out

PSRAM Writ e VIL VIL XV

IL VIL Valid PSRAM

data in

PSRAM Read

Configuration

00(RCR)

10(BCR)

X1(DIDR) XPSRAM

data out

PSRAM

Standby

Any Flash memory mode is allowed.

VIH VIL X X X X X X Hi-Z

PSRAM Deep

Power-

Down(10) VIH X X X X X X X Hi-Z

1. X = Don't care

2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in

Standby and Deep Power-Down modes.

3. The PSRAM must have been configu red to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).

4. The DPDF signal polarity depends on the value of the ECR14 bit.

5. WAIT signal polarity is configured using the Set Configuration Register command. See the M58PRxxxJ datasheet for

details.

6. LF can be tied to VIH if the valid address has been previously latched

7. ECR15 has to be set to ‘1’ for the Flash memory device to enter Deep Power-Down.

8. Depends on GF

9. If ECR15 is set to '0', the Flash memory device cannot enter the Deep Power-Down mode, even if DPDF is asserted.

10. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep Power-

Down mode.

4 Maximum rating M36P0R9060E0

16/23

4 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sect ions of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

Min Max

TAAmbient Operating Temperature –30 85 °C

TBIAS Temperature Under Bias –30 85 °C

TSTG Storage Temperature –55 125 °C

VIO Input or Output Voltage –0.2 2.45 V

VDDF Flash Memor y Supply Voltage –1.0 3.00 V

VCCP PSRAM Supply Voltage –0.2 2.45 V

VDDQ Input/Output Supply Voltage –0.2 2.45 V

VPPF Flash Memory Program Voltage –1 11.5 V

IOOutput Short Circuit Current 100 mA

tVPPH Time for VPPF at VPPH 100 hours

M36P0R9060E0 5 DC and AC parameters

17/23

5 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

f ollo w, are deriv ed fr om tests performed under the Measurement Co nditions sum marized in

Table 4., Operating and AC measurement conditions. Designers should check that the

operat ing conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Figure 4. AC measurement I/O waveform

Table 4. Operating and AC measurement conditions

Parameter Flash Memory PSRAM Unit

Min Max Min Max

VDDF Supply Voltage 1.7 1.95 – – V

VCCPSupply Voltage ––1.71.95V

VDDQ Supply Voltage 1.7 1.95 1.7 1.95 V

VPPF Supply Voltage (Factory environment) 8.5 9.5 – – V

VPPF Supply Voltage (Application environment) –0.4 VDDQ +0.4 – – V

Ambient Operati ng Temperature –30 85 –30 85 °C

Load Capacita nce (C L)3030pF

Impedance Output (Z0)50Ω

Output Circuit Protection Resistance (R) 50 Ω

Input Rise and Fall Times 3 2 ns

Input Pulse Voltages 0 to VDDQ 0 to VDDQ V

Input and Output Timing Ref. Voltages VDDQ/2 VDDQ/2 V

AI06161

VDDQ

VDDQ/2

5 DC and AC parameters M36P0R9060E0

18/23

Figure 5. AC measurement load circuit

1. VDD means VDDF = VCCP.

Please refer to the M58PRxxxJ and M69KB096AM datasheets for further DC and AC

characteristics values and illustrations.

Tab le 5. Capacitance(1)

1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V – 14 pF

COUT Output Capacitance VOUT = 0V – 14 pF

AI06162a

VCCQ/2

DEVICE

UNDER

TEST Z0

OUT

M36P0R9060E0 6 Package mechanical

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6 Package mechanical

In order to meet environment al requirements, ST offers these devices in ECOPACK®

pac kages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum r atings related to soldering conditions ar e also marked on the inner bo x label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 6. TFBGA 107 8x11mm - 9x12 active ball array, 0.8mm pitch, pac kage outli ne

1. Drawing is not to scale.

BGA-Z85

ddd

BALL "B1"

6 Package mechanical M36P0R9060E0

20/23

Tab le 6. Stac ked TFBGA107 8x11mm - 9x 12 active ball arra y, 0.8 mm pitch, pac kage

data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.200.047

A1 0.20 0.008

A2 0.85 0.033

b 0.35 0.30 0.40 0.014 0.012 0.016

D 8.00 7.90 8.10 0.315 0.311 0.319

D1 6.40 0.252

ddd 0.10 0.004

E 11.00 10.90 11.10 0.433 0.429 0.437

E1 8.80 0.346

e0.80 0.031

FD 0.80 0.031

FE 1.10 0.043

SE 0.40 0.016

M36P0R9060E0 7 Part numbering

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7 Part numbering

Note: De vices are shipped f rom the factory with the memory content bits erased to ’1’. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this

device, please contact the STMicroelectronics Sales Offi ce nearest to you.

Table 7. Ordering information scheme

Example: M36 P 0 R 9 0 6 0 E 0 ZAC E

Device Type

M36 = Multi-Chip Package (Flash + PSRAM)

Flash 1 Architecture

P = Multi-Level, Multiple Bank, Large Buffer

Flash 2 Architecture

0 = No Die

Operating Voltage

R = VDDF = VCCP = VDDQ = 1.7 to 1.95V

Flash 1 Density

9 = 512 Mbits

Flash 2 Density

0 = No Die

RAM 1 Density

6 = 64 Mbits

RAM 2 Density

0 = No Die

Parameter Blocks Location

E = Even Block Flash Memory Configuration

Pro duct Version

0 = 90nm Flash technology, 96ns speed; 0.11µm PSRAM technology, 70ns speed

Package

ZAC = stac ked TFBGA107 C stacked footprint.

Option

E = ECOPACK Package, Standard packing

F = ECOPACK Package, Tape & Reel packing

8 Revision hist ory M36P0R9060 E 0

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8 Revision history

Tab le 8. Document revision history

Date Revision Changes

28-Nov-2005 1 Initial release.

20-Jul-2006 2

Document status promoted to full Datasheet.

PSRAM part changed. Flash memory component specifications

updated to latest version of M58PRxxxJ datasheet (VPP changed in

Table 3). H9 ball changed to DU in Figure 2: TFBGA connections

(top view through package).

M36P0R9060E0

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