ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS83054I is a low skew, 4:1, Single-ended ICS Multiplexer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS83054I has four selectable singleended clock inputs and one single-ended clock output. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug purposes. The device operates up to 250MHz and is packaged in a 16 TSSOP package. * 4:1 single-ended multiplexer * Q nominal output impedance: 7 (VDDO = 3.3V) * Maximum output frequency: 250MHz * Propagation delay: 3ns (maximum), VDD = VDDO = 3.3V * Input skew: 225ps (maximum), VDD = VDDO = 3.3V * Part-to-part skew: 475ps (maximum), VDD = VDDO = 3.3V * Additive phase jitter, RMS: 0.19ps (typical), 3.3V/3.3V * Operating supply modes: VDD/V DDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT Q nc OE CLK3 GND nc SEL1 CLK2 CLK0 CLK1 Q CLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO nc CLK0 nc VDD nc CLK1 SEL0 CLK3 ICS83054I 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View SEL1 SEL0 OE IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 1 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 Q Output 3 OE Input 4, 8, 10, 14 5 CLK3, CLK2, CLK1, CLK0 GND Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Power 7, 9 SEL1, SEL0 Input 2, 6, 11, 13, 15 nc Unused Power supply ground. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. No connect. 12 VDD Power Power and input supply pin. 16 VDDO Power Output supply pin. Pullup Description Single-ended clock output. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. When HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C IN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) CPD ROUT Output Impedance 51 k VDDO = 3.465V 18 pF VDDO = 2.625V 20 pF VDDO = 1.89V 30 pF VDDO = 3.465V 7 VDDO = 2.625V 7 VDDO = 1.89V 10 TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs SEL1 SEL0 0 0 Input Selected to Q CLK0 0 1 CLK1 1 0 CLK2 1 1 CLK3 IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 2 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 89C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = -40C TO 85C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3. 3 3.465 V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3. 3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter VDD VDDO IDD IDDO Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3. 3 3.465 V Output Supply Voltage 1.71 1.8 1.89 V Power Supply Current 40 mA Output Supply Current 5 mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V 2.375 2. 5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current 35 mA IDDO Output Supply Current 5 mA TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.71 1.8 1.89 V IDD Power Supply Current 35 mA IDDO Output Supply Current 5 mA IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 3 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40C TO 85C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0:CLK3, SEL0, SEL1 OE CLK0:CLK3, SEL0, SEL1 OE Output HighVoltage Output Low Voltage Test Conditions Minimum Maximum Units VDD = 3.3V 5% 2 Typical VDD + 0.3 V VDD = 2.5V 5% 1.7 VDD + 0.3 V VDD = 3.3V 5% -0.3 0.8 V VDD = 2.5V 5% -0.3 0.7 V VDD = 3.3V or 2.5V 5% 150 A VDD = 3.3V or 2.5V 5% 5 A VDD = 3.3V or 2.5V 5% -5 A VDD = 3.3V or 2.5V 5% -150 A VDDO = 3.3V 5%; NOTE 1 2.6 V VDDO = 2.5V 5%; NOTE 1 1.8 V VDDO = 1.8V 5%; NOTE 1 VDD - 0.3 V VDDO = 3.3V 5%; NOTE 1 0.5 V VDDO = 2.5V 5%; NOTE 1 0.45 V VDDO = 1.8V 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 250 MH z tpLH Propagation Delay, Low to High; NOTE 1 2.4 2. 7 3.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.7 2.9 ns t sk(i) 55 225 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 t R / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.19 475 ps 50 500 ps 45 55 % @ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 4 ps dB ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.5 2.8 3.1 ns tpHL Propagation Delay, High to Low; NOTE 1 2.6 2.8 3.0 ns t sk(i) 45 150 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.14 ps 400 ps 50 50 0 ps 45 55 % @ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. dB TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.7 3. 2 3.8 ns tpHL Propagation Delay, High to Low; NOTE 1 2.8 3.3 3.8 ns t sk(i) 50 150 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.16 475 ps 100 700 ps 45 55 % @ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 5 ps dB ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units 250 MHz 3.5 ns fMAX Output Frequency tpLH Propagation Delay, Low to High; NOTE 1 2.5 3.0 tpHL Propagation Delay, High to Low; NOTE 1 2.5 2.9 3.4 ns t sk(i) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 60 175 ps tjit t sk(pp) tR / tF Output Rise/Fall Time odc Output Duty Cycle 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.21 ps 300 ps 100 500 ps 40 60 % @ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. dB TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V -5%, TA = -40C TO 85C Symbol Parameter fMAX Output Frequency Test Conditions Minimum Typical Maximum Units 250 MHz tpLH Propagation Delay, Low to High; NOTE 1 2.6 3.3 4.0 ns tpHL Propagation Delay, High to Low; NOTE 1 2.7 3.3 4.0 ns t sk(i) 50 150 ps t sk(pp) Input Skew; NOTE 2 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 3 Par t-to-Par t Skew; NOTE 2, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tjit 155.52MHz, (12kHz to 20MHz) 20% to 80% 0.17 325 ps 10 0 70 0 ps 40 60 % @ 100MHz 45 MUXISOL MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Driving only one input clock. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 6 ps dB ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Additive Phase Jitter @ 155.52MHz SSB PHASE NOISE dBc/HZ (12kHz to 20MHz) = 0.19ps typical OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 7 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 1.65V5% 1.25V5% SCOPE VDD, VDDO SCOPE VDD, VDDO Qx Qx LVCMOS LVCMOS GND GND -1.65V5% -1.25V5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V5% 2.45% 0.9V5% 1.25V5% SCOPE VDD VDDO SCOPE VDD VDDO Qx GND Qx GND LVCMOS LVCMOS -1.25V5% -0.9V5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 1.6V5% 0.9V5% Part 1 SCOPE VDD VDDO Qx Qx Part 2 GND Qy LVCMOS V DDO 2 V DDO 2 t sk(pp) -0.9V5% 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER PART-TO-PART SKEW 8 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER VDD VDD CLK0:CLK3 VDDO Q 2 tpLH 80% 80% 2 2 VDDO Clock Outputs 2 tpHL PROPAGATION DELAY 20% 20% tR tF OUTPUT RISE/FALL TIME CLKx V DDO 2 Q Q t PW t tPD1 odc = PERIOD t PW x 100% t PERIOD CLKy Q tPD2 tsk(i) = tPD2 - tPD1 INPUT SKEW IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 9 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 10 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W 200 118.2C/W 81.8C/W 500 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83054I is: 874 IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 11 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 12 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83054AGI 83054AGI 16 Lead TSSOP tube -40C to 85C ICS83054AGIT 83054AGI 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS83054AGILF 83054AIL 16 Lead "Lead-Free" TSSOP tube -40C to 85C ICS83054AGILFT 83054AIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 13 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER REVISION HISTORY SHEET Rev Table Page A T8 B T5A - T5E 12 1 4-6 7 Description of Change Ordering Information Table - corrected Par t/Order Numbers. Features Section - added Additive Phase Jitter bullet. AC Characteristics Tables - added tjit row and spec. Added Additive Phase Jitter section. IDT TM / ICSTM 4:1, SINGLE-ENDED MULTIPLEXER 14 Date 1/3/06 01/04/07 ICS83054AGI REV. B JANUARY 4, 2007 ICS83054I 4:1, SINGLE-ENDED MULTIPLEXER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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