SiC401A, SiC401BCD
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15 A microBUCK® SiC401A/B
Integrated Buck Regulator with Programmable LDO
DESCRIPTION
The Vishay Siliconix SiC401A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK MLP55-32L pin package.
The SiC401A/B is capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency and
used to drive external n-channel MOSFETs or other loads.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under-voltage protection, programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC401A/B also provides
an enable input and a power good output.
Note
a. See “High Output Voltage Operation” section
FEATURES
• High efficiency > 93 %
• 15 A continuous output current capability
• Integrated bootstrap switch
• Programmable 200 mA LDO with bypass logic
• Temperature compensated current limit
• All ceramic solution enabled
• Pseudo fixed-frequency adaptive on-time control
• Programmable input UVLO threshold
• Independent enable pin for switcher and LDO
• Selectable ultra-sonic power-save mode (SiC401A)
• Selectable power-save mode (SiC401B)
• Programmable soft-start and soft-shutdown
• 1 % internal reference voltage
• Power good output
• Over-voltage and under-voltage protections
• PowerCAD Simulation software available at
www.vishay.com/power-ics/powercad-list/
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Notebook, desktop and server computers
• Digital HDTV and digital consumer applications
• Networking and telecommunication equipment
• Printers, DSL, and STB applications
• Embedded applications
• Point of load power supplies
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
Typical Application Circuit for SiC401A/B (PowerPAK MLP5x5-32L)
PRODUCT SUMMARY
Input Voltage Range 3 V to 17 V
Output Voltage Range 0.6 V to VIN x 0.75 a
Operating Frequency 200 kHz to 1 MHz
Continuous Output Current 15 A
Peak Efficiency 93 %
Package PowerPAK MLP55-32L
PAD 1
A
GND
LX
PAD 3
LX
PAD 2
V
IN
P
GND
LX
P
GND
P
GND
P
GND
P
GND
P
GND
17
18
19
20
21
T
ON
A
GND
EN\PSV
LX
I
LIM
P
GOOD
BST
V
IN
FBL
A
GND
V
DD
V
OUT
FB 1
2
3
4
5
7
6
8
SS
P
GND
V
IN
V
IN
V
IN
NC
LX
NC
9
10
11
12
13
14
15
16
24 LX
23
22
ENL
V
IN
V
OUT
V
OUT
P
GOOD
EN/PSV (Tri-State)
LDO_EN
P
GND
31 30 29 2526
27
28
32
SiC401A, SiC401BCD
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FUNCTIONAL BLOCK DIAGRAM
SiC401A/B Functional Block Diagram
PIN CONFIGURATION
SiC401A/B Pin Configuration (Top View)
Reference
Soft Start
FB
A
GND
On- time
Generator
Control & Status
PGOOD
Gate Drive
Control
VIN
PGND
TON
VOUT
Zero Cross Detector
Valley Current Limit ILIM
ENL
FBL
VLDO Switchover MUX
A
Y
BLDO
VDD
BST
FB Comparator
-
LX
EN/PSV
Bypass ComparatorBypass Comparator
NC
NC
A
12
8
27
14
32
5
3
2
31
1
26 29
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
D = connect to pins 4, 30, PAD 1
B
C
D
V
IN
VDD
VDD
V
IN
Bootstrap
Switch
Lo-side
MOSFET
Hi-side
MOSFET
LXBST13
LXS
28
DL
DL
VDD
VDD
VDD
SS 7
PAD 1
A
GND
LX
PAD 3
LX
PAD 2
V
IN
P
GND
LX
P
GND
P
GND
P
GND
P
GND
P
GND
17
18
19
20
21
tON
A
GND
EN\PSV
LX
I
LIM
P
GOOD
BST
V
IN
FBL
A
GND
VDD
V
OUT
FB 1
2
3
4
5
7
6
8
SS
P
GND
V
IN
V
IN
V
IN
NC
LX
NC
9
10
11
12
13
14
15
16
P
GND
24 LX
23
22
ENL
31 30 29 25262728
32
SiC401A, SiC401BCD
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Format:
Line 1: P/N
Line 2: Siliconix logo + Lot code + ESD symbol
Line 3: Factory code + Year code + Work week code
PIN DESCRIPTION
PIN NUMBER SYMBOL DESCRIPTION
1FB
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND.
2V
OUT Switcher output voltage sense pin - also the input to the internal switch-over between VOUT and
VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin.
3V
DD Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled.
4, 30, PAD 1 AGND Analog ground
5FBL
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from VDD to AGND.
6, 9 to 11, PAD 2 VIN Input supply voltage
7SS
The soft start ramp will be programmed by an internal current source charging a capacitor on this
pin.
8BST
Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high-side gate drive.
12, 14 NC No connection
13 LXBST LX Boost - connect to the BST capacitor.
23 to 25, PAD3 LX Switching (phase) node
15 to 22 PGND Power ground
26 PGOOD Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required.
27 ILIM Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS.
28 LXS LX sense - connects to RILIM
29 EN/PSV
Enable/power save input for the switching regulator - connect to AGND to disable the switching
regulator, connect to VDD to operate with power-save mode and float to operate in forced
continuous mode.
31 tON On-time programming input - set the on-time by connecting through a resistor to AGND
32 ENL Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic
control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING (LINE 1: P/N)
SiC401ACD-T1-GE3 PowerPAK MLP55-32L SiC401A
SiC401BCD-T1-GE3 PowerPAK MLP55-32L SiC401B
SiC401DB Reference board
SiC401A, SiC401BCD
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Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
ELECTRICAL PARAMETER CONDITIONS LIMITS UNIT
VIN to PGND -0.3 to +20
V
VIN to VDD -0.4 max.
LX to PGND -0.3 to +20
LX (Transient < 100 ns) to PGND -2 to +20
VDD to PGND -0.3 to +6
EN/PSV, PGOOD, ILIM, SS, VOUT, FB, FBL Reference to AGND -0.3 to +(VDD + 0.3)
tON to PGND -0.3 to +(VDD - 1.5)
BST to LX -0.3 to +6
to PGND -0.3 to +25
ENL -0.3 to VIN
AGND to PGND -0.3 to +0.3
Temperature
Maximum Junction Temperature 150 °C
Storage Temperature -65 to 150
Power Dissipation
Junction to Ambient Thermal Impedance (RthJA) bIC Section 50 °C/W
Maximum Power Dissipation Ambient Temperature = 25 °C 3.4 W
Ambient Temperature = 100 °C 1.3
ESD Protection
HBM 2 kV
CDM 1
RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Input Voltage VIN 3-17
VVDD to PGND 3-5.5
Output Voltage VOUT 0.6 - VIN x 0.75
Temperature
Ambient Temperature -40 to +85 °C
SiC401A, SiC401BCD
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ELECTRICAL SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, VDD = 5 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C, typical application circuit
MIN. TYP. MAX. UNIT
Input Power Supplies
Input Supply Voltage VIN 3-17
V
VDD VDD 3-5.5
VIN UVLO Threshold aVUVLO
Sensed at ENL pin, rising 2.4 2.6 2.95
Sensed at ENL pin, falling 2.23 2.4 2.57
VIN UVLO Hysteresis VUVLO, HYS -0.25-
VDD UVLO Threshold VUVLO
Measured at VDD pin, rising 2.5 - 3
Measured at VDD pin, falling 2.4 - 2.9
VDD UVLO Hysteresis VUVLO, HYS -0.2-
VIN Supply Current IIN
ENL, EN/PSV = 0 V , VIN = 17 V - 10 20
μAStandby mode; ENL= VDD, EN/PSV = 0 V - 130 -
VDD Supply Current IDD
ENL, EN/PSV = 0 V - 190 300
SiC401A, EN/PSV = VDD, no load
(fSW = 25 kHz), VFB > 0.6 V b-0.3-
mA
SiC401B, EN/PSV = VDD, no load,
VFB > 0.6 V b-0.7-
VDD = 5 V, fSW = 250 kHz,
EN/PSV = floating, no load b-9-
VDD = 3 V, fSW = 250 kHz,
EN/PSV = floating, no load b-5.5-
FB On-Time Threshold Static VIN and load 0.594 0.600 0.606 V
Frequency Range fSW
Continuous mode operation - - 1000 kHz
Minimum fSW, (SiC401A only) - 25 -
Bootstrap Switch Resistance -10-
Timing
On-Time tON Continuous mode operation VIN = 12 V,
VOUT = 5 V, fSW = 300 kHz, Rton = 133 k999 1110 1220
ns
Minimum On-Time btON, min. -80-
Minimum Off-Time btOFF, min.
VDD = 5 V - 250 -
VDD = 3 V - 370 -
Soft Start
Soft Start Current bISS -3-μA
Soft Start Voltage bVSS When VOUT reaches regulation - 1.5 - V
Analog Inputs/Outputs
VOUT Input Resistance RO-IN - 500 - k
Current Sense
Zero-Crossing Detector Threshold Voltage VSense-th LX-PGND -3 - +3 mV
Power Good
Power Good Threshold PG_VTH_UPPER Upper limit, VFB > internal 600 mV reference - ± 20 - %
PG_VTH_LOWER Lower limit, VFB < internal 600 mV reference - -10 -
Start-Up Delay Time
(between PWM enable and PGOOD high) PG_Td
VDD = 5 V, CSS = 10 nF - 12 - ms
VDD = 3 V, CSS = 10 nF - 7 -
Fault (noise-immunity) Delay Time bPG_ICC -5-μs
Leakage Current PG_ILK --1μA
Power Good On-Resistance PG_RDS_ON -10-
SiC401A, SiC401BCD
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Notes
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
b. Typical value measured on standard evaluation board.
c. SiC401A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout
d. The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT.
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
Fault Protection
Valley Current Limit ILIM
VDD = 5 V, RILIM = 3945, TJ = 0 °C to +125 °C 12.75 15 17.25 A
VDD = 3.3 V, RILIM = 3945 - 13.5 -
ILIM Source Current -10-μA
ILIM Comparator Offset Voltage VILM-LK With respect to AGND -10 0 +10 mV
Output Under-Voltage Fault VOUV_Fault VFB with respect to Internal 600 mV
reference, 8 consecutive clocks --25-
%Smart Power-Save Protection
Threshold Voltage bPSave_VTH VFB with respect to internal 600 mV - +10 -
Over-Voltage Protection Threshold VFB with respect to internal 600 mV - +20 -
Over-Voltage Fault Delay btOV-Delay -5-μs
Over Temperature Shutdown bTShut 10 °C hysteresis - 150 - °C
Logic Inputs/Outputs
Logic Input High Voltage VIH 1--
V
Logic Input Low Voltage VIL --0.4
EN/PSV Input for P-Save Operation bVDD = 5 V 2.2 - 5
EN/PSV Input for Forced Continuous
Operation b1-2
EN/PSV Input for Disabling Switcher 0-0.4
EN/PSV Input Bias Current IEN -10 - +10
μAENL Input Bias Current IENL -815
FBL, FB Input Bias Current FBL_ILK -1 - +1
Linear Dropout Regulator
FBL bVLDO ACC -0.75- V
LDO Current Limit LDO_ILIM
Short-circuit protection,
VIN = 12 V, VDD < 0.75 V -65-
mA
Start-up and foldback, VIN = 12 V,
0.75 < VDD < 90 % of final VDD value - 115 -
Operating current limit, VIN = 12 V,
VDD > 90 % of final VDD value 135 200 -
VLDO to VOUT Switch-over Threshold dVLDO-BPS -130 - +130 mV
VLDO to VOUT Non-switch-over Threshold dVLDO-NBPS -500 - +500
VLDO to VOUT Switch-over Resistance RLDO VOUT = 5 V - 2 -
LDO Drop Out Voltage eFrom VIN to VDD,
VDD = +5 V, IVLDO = 100 mA -1.2- V
ELECTRICAL SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, VDD = 5 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C, typical application circuit
MIN. TYP. MAX. UNIT
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Efficiency/Power Loss vs. Load P-Save
(VDD = 3.3 V, VOUT = 1.5 V, SiC401B)
Efficiency/Power Loss vs. Load P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401B)
Efficiency/Power Loss vs. Load FCM
(VDD = 5 V, VOUT = 1.5 V, SiC401B)
Efficiency/Power Loss-P-Save vs. FCM
(VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V, SiC401B)
Efficiency/Power Loss-P-Save vs. FCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V, SiC401B)
Efficiency/Power Loss-P-Save
(VOUT = 1.5 V, VIN = 12 V, SiC401B)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PLoss(W)
Efficiency(%)
I
OUT
(A)
V
IN
=5V
V
IN
=12V
V
IN
=12V
V
IN
=5V
VIN=17V
V
IN
=17V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
50
55
60
65
70
75
80
85
90
95
100
0123456789101112131415
PLOSS(W)
Efficiency(%)
IOUT (A)
V
IN
=12V
V
IN
=5V
V
IN
=17V
V
IN
=12V
V
IN
=5VV
IN
=5VV
IN
=5V
V
IN
=5V
V
IN
=5VV
IN
=5V
VIN=17V
P
LOSS
(W)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Efficiency(%)
IOUT (A)
VIN=5V
VIN=12V
VIN= 12V
VIN=5V
VIN= 17V
V
IN
=17V
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
50
55
60
65
70
75
80
85
90
95
0 1 2 3 4 5 6 7 8 9 101112131415
P
LOSS
(W)
Efficiency(%)
I
OUT
(A)
PSAVE
FCM
FCM minus PSM
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
50
55
60
65
70
75
80
85
90
95
100
0123456789101112131415
P
LOSS
(W)
Efficiency(%)
IOUT (A)
PSAVE
FCM
FCM minus PSM
-0.15
-0.05
0.05
0.15
0.25
0.35
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P
LOSS
(W)
Efficiency(%)
I
OUT
(A)
3.3V Bias
5V Bias
3.3V min us 5V
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Load Regulation - FCM
(VDD = 5 V, VOUT = 1.5 V, SiC401B)
Load Regulation - P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401B)
Switching Frequency - P-Save Mode vs. FCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V, SiC401B)
Load Regulation - FCM
(VDD = 3.3 V, VOUT = 1.5 V, SiC401B)
Load Regulation - P-Save
(VDD = 3.3 V, VOUT = 1.5 V, SiC401B)
Switching Frequency - P-Save vs. FCM
(VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V, SiC401B)
1.4
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=5V
=12V
IN
V
1.4
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0123456789101112131415
V
OUT
(V)
I
OUT
(A)
V
IN
=5V
V
IN
=12V
0
50
100
150
200
250
300
350
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Switching Frequency(KHz)
I
OUT
(A)
FCM
PSAVE
1.4
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
T
(A)
VIN=5V
VIN=12V
1.4
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=5V
V
IN
=12V
0
50
100
150
200
250
300
350
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Switching Frequency(KHz)
I
OUT
(A)
FCM
PSAVE
FCM
PSAVE
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Load Regulation vs. Temperature - FCM
(VDD = 5 V, VOUT = 1.5 V, SiC401B)
Load Regulation vs. Temperature - P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401B)
Efficiency Variation with VOUT - P-Save
(V
DD
= 5 V, V
IN
= 12 V, L = 2.2 μH (4.6 m
) for V
OUT
= 2.5 V, 3.3 V and 5 V, SiC401B)
Load Regulation vs. Temperature - P-Save
(VDD = 3.3 V, VOUT = 1.5 V, SiC401B)
Load Regulation vs. Temperature - FCM
(VDD = 3.3 V, VOUT = 1.5 V, SiC401B)
Efficiency/Power Loss vs. P-Save
(VOUT = 1.5 V, VIN = 12 V, SiC401B)
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0123456789101112131415
V
OUT
(V)
IOUT (A)
V
IN
=12V,T
A
=25°C
V
IN
=5V,T
A
=25°C
V
IN
=12V,T
A
=
-40 °C
V
IN
=5V,T
A
=-40 °C
V
IN
=12V,T
A
=85°C
V
IN
=5V,T
A
=85 °C
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=12V,T
A
=25
V
IN
=5V,T
A
=25C
V
IN
=12V,T
A
=-40C
V
IN
=5V,T
A
=-40C
V
IN
=12V,T
A
=85C
V
IN
=5V,T
A
=85C
75
80
85
90
95
100
0123456789101112131415
Efficiency(%)
IOUT (A)
V
OUT=
1.5V
V
OUT
=1V
V
OUT
=3.3V
V
OUT
=5V
V
OUT
=2.5V
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
1.53
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=12V,T
A
=25°C
V
IN
=5V,T
A
=25 °C
V
IN
=12V,T
A
=-40°C
V
IN
=5V,T
A
=-40 °C
V
IN
=12V,T
A
=85°C
V
IN
=5V,T
A
=85°C
1.45
1.46
1.47
1.48
1.49
1.5
1.51
1.52
0123456789101112131415
V
OUT
(V)
I
OUT
(A)
V
IN
=12V,T
A
=25
V
IN
=5V,T
A
=25C
V
IN
=12V,T
A
=-40C
V
IN
=5V,T
A
=-40C
V
IN
=12V,T
A
=85C
V
IN
=5V,T
A
=85C
0
0.05
0.1
0.15
0.2
50
55
60
65
70
75
80
85
90
95
0.001 0.01 0.1 1 10 100
P
LOSS
(W)
Efficiency(%)
I
OUT
(A)
External Bias
LDO Bias
LDO minus
External
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Efficiency/Power Loss vs. Load - P-Save
(VDD = 3.3 V, VOUT = 1.5 V, SiC401A)
Efficiency/Power Loss - P-Save vs. FCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V, SiC401A)
Efficiency/Power Loss vs. Load - P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401A)
Efficiency/Power Loss - P-Save vs. FCM
(VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V, SiC401A)
Efficiency/Power Loss - P-Save
(VOUT = 1.5 V, VIN = 12 V, SiC401A)
Load Regulation - P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401A)
PLOSS(W)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Efficiency(%)
IOUT(A)
VIN=5V
VIN=12V
VIN=17V
VIN=17V
VIN=12V
VIN=5V
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Efficiency(%)
I
out
(A)
PSAVE
FCM
FCM minus PSM
P
LOSS
(W)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
50
55
60
65
70
75
80
85
90
95
100
0123456789101112131415
P
LOSS
(W)
Efficiency(%)
I
OUT
(A)
V
IN
-5V
V
IN
=12V
V
IN
=17V
V
IN
=5V
V
IN
=12V
V
IN
=17V
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P
LOSS
(W)
Efficiency(%)
I
OUT
(A)
PSAVE
FCM
FCM minus PSM
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
50
55
60
65
70
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P
LOSS
(W)
Efficiency(%)
I
OUT
(A)
3.3V Bias
3.3V minus 5V
5V Bias
1.445
1.455
1.465
1.475
1.485
1.495
1.505
1.515
1.525
0123456789101112131415
V
OUT
(V)
I
OUT
(A)
V
IN
=12V
V
IN
=5V
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Load Regulation - P-Save
(VDD = 3.3 V, VOUT = 1.5 V, SiC401A)
Load Regulation vs. Temperature - P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401A)
Start-up - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401B)
Load Regulation vs. Temperature - P-Save
(VDD = 5 V, VOUT = 1.5 V, SiC401A)
Shutdown - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 5 A, SiC401B)
1.445
1.455
1.465
1.475
1.485
1.495
1.505
1.515
1.525
1.535
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=12V
V
IN
=5V
1.445
1.455
1.465
1.475
1.485
1.495
1.505
1.515
1.525
1.535
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=12V,T
A
=25C
V
IN
=5V,T
A
=25C
V
IN
=5V,T
A
=-40C
V
IN
=5V,T
A
=85C
V
IN
=12V ,T
A
=85C
V
IN
=12V,T
A
=-40C
Time(1ms/div)
(5V/div)
(1V/div)
(500mV/div)
(5V/div)
EN/PSV
VOUT
SS
LX
1.445
1.455
1.465
1.475
1.485
1.495
1.505
1.515
1.525
1.535
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
V
OUT
(V)
I
OUT
(A)
V
IN
=12V,T
A
=25C
V
IN
=5V,T
A
=25C
V
IN
=5V,T
A
=-40C
V
IN
=5V,T
A
=85C
V
IN
=12V,T
A
=85C
V
IN
=12v,T
A
=-40C
(5V/div)
(1V/div)
(500mV/div)
(5V/div)
Time(50µs/div)
SS
LX
VOUT
EN/PSV
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Start-up (Pre-Bias) - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401B)
Power-Save Mode
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401A)
Transient Response - P-Save Load Rising
(V
DD
= 5 V, V
IN
= 12 V, V
OUT
= 1.5 V, I
OUT
= 0 A to 11 A, SiC401B, dI/dt = 1 A/μs)
Power-Save Mode
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, SiC401B)
Forced Continuous Mode
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 15 A, SiC401B)
Transient Response - P-Save Load Falling
(V
DD
= 5 V, V
IN
= 12 V, V
OUT
= 1.5 V, I
OUT
= 11 A to 0 A, SiC401B, dI/dt = 1 A/μs)
Time(1ms/div)
(5V/div)
(1V/div)
(500mV/div)
(5V/div)
EN/PSV
VOUT
SS
LX
(5V/div)
(100 mV/div)
Time (20µs/div)
VOUT RIPPLE
LX
(5V/div)
(50mV/div)
IOUT :0A-11A
VOUT RIPPLE
LX
(4A/div)
Time(10µs/div)
(5V/div)
(50mV/div)
Time(10ms/div)
VOUT RIPPLE
LX
(5V/div)
(50mV/div)
VOUT RIPPLE
LX SWITCHING MODE
Time(5µs/div)
(5V/div)
(4A/div)
(50mV/div)
Time(10µs/div)
LX
IOUT :11A to 0A
VOUT RIPPLE
SiC401A, SiC401BCD
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ELECTRICAL CHARACTERISTICS
Transient Response - FCM
(V
DD
= 5 V, V
IN
= 12 V, V
OUT
= 1.5 V, I
OUT
= 0 A to 11 A, SiC401B, dI/dt = 1 A/μs)
Transient Response - P-Save Load Rising
(V
DD
= 5 V, V
IN
= 12 V, V
OUT
= 1.5 V, I
OUT
= 0 A to 11 A, SiC401A, dI/dt = 1 A/μs)
Over Current Protection-Under Voltage Prodection
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, SiC401B)
Over Temperature Shutdown at 133.4 °C
(VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A, LDO Mode, SiC401B)
Transient Response - P-Save Load Falling
(V
DD
= 5 V, V
IN
= 12 V, V
OUT
= 1.5 V, I
OUT
= 11 A to 0 A, SiC401A, dI/dt = 1 A/μs)
(5V/div)
(4A/div)
(50mV/div)
IOUT :0A to 11A
LX
Time(20µs/div)
VOUT RIPPLE
(5V/div)
(100mV/div)
VOUT RIPPLE
IOUT:0A to 11A
LX
(4A/div)
Time(10µs/div)
Time(100µs/div)
(5V/div)
(5V/div)(5V/div)
(500mV/div)
(5A/div)
Pgood
VOUT
Inductor
LX
(5V/div)
(2V/div)
Pgood
LX
Time(500µs/div)
(5V/div)
VOUT RIPPLE
Time(20µs/div)
(4A/div)
(100mV/div)
LX
IOUT:0A to 11A
SiC401A, SiC401BCD
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OPERATIONAL DESCRIPTION
Device Overview
The SiC401A/B is a step down synchronous DC/DC
buck converter with integrated power MOSFETs and a
200 mA capable programmable LDO. The device is capable
of 15 A operation at very high efficiency. A space saving
5 mm x 5 mm 32-pin package is used. The programmable
operating frequency of up to 1 MHz enables optimizing the
configuration for PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive
on-time control. This control method allows fast transient
response which permits the use of smaller output
capacitors.
Input Voltage Requirements
The SiC401A/B requires two input supplies for normal
operation: VIN and VDD. VIN operates over a wide range from
3 V to 17 V. VDD requires a 3 V to 5.5 V supply input that can
be an external source or the internal LDO configured to
supply 3 V to 5.5 V from VIN.
Power Up Sequence
When the SiC401A/B uses an external power source at the
VDD pin, the switching regulator initiates the start up when
VIN, VDD, and EN/PSV are above their respective thresholds.
When EN/PSV is at logic high, VDD needs to be applied after
VIN rises. It is also recommended to use a 10 resistor
between an external power source and the VDD pin. To start
up by using the EN/PSV pin when both VDD and VIN are
above their respective thresholds, apply EN/PSV to enable
the start-up process. For SiC401A/B in self-biased mode,
refer to the LDO section for a full description.
Shutdown
The SiC401A/B can be shut-down by pulling either VDD or
EN/PSV below its threshold. When using an external power
source, it is recommended that the VDD voltage ramps down
before the VIN voltage. When VDD is active and EN/PSV at
logic low, the output voltage discharges into the VOUT pin
through an internal FET.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used by the SiC401A/B
is pseudo- fixed frequency, adaptive on-time, as shown
in figure 1. The ripple voltage generated at the output
capacitor ESR is used as a PWM ramp signal. This ripple is
used to trigger the on-time of the controller.
Fig. 1 - Output Ripple and PWM Control Method
The adaptive on-time is determined by an internal one- shot
timer. When the one-shot is triggered by the output ripple,
the device sends a single on-time pulse to the high- side
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
The advantages of adaptive on-time control are:
• Predictable operating frequency compared to other
variable frequency methods.
• Reduced component count by eliminating the error
amplifier and compensation components.
• Reduced component count by removing the need to
sense and control inductor current.
• Fast transient response - the response time is controlled
by a fast comparator instead of a typically slow error
amplifier.
• Reduced output capacitance due to fast transient
response.
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in figure 2. The FB
comparator output goes high when VFB is less than the
internal 600 mV reference. This feeds into the gate drive and
turns on the high-side MOSFET, and also starts the
one-shot timer. The one-shot timer uses an internal
comparator and a capacitor. One comparator input is
connected to VOUT, the other input is connected to the
capacitor. When the on-time begins, the internal capacitor
charges from zero volts through a current which is
proportional to VIN. When the capacitor voltage reaches
VOUT, the on-time is completed and the high-side MOSFET
turns off.
V
IN
C
IN
V
LX
Q1
Q2
L
ESR
+
FB
V
LX
t
ON
V
FB
C
OUT
V
OUT
FB threshold
SiC401A, SiC401BCD
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Fig. 2 - On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN. Under
steady-state conditions, the switching frequency can be
determined from the on-time by the following equation.
The SiC401A/B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide operating frequency up to 1 MHz
using a resistor between the tON pin and ground. The
resistor value is selected by the following equation.
The constant, k, equals 1, when VDD is greater than 3.6 V. If
VDD is less than 3.6 V and VIN is greater than (VDD -1.75) x 10,
k is shown by the following equation.
The maximum RtON value allowed is shown by the following
equation.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
600 mV reference voltage, see figure 3.
Fig. 3 - Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
Enable and Power-Save Inputs
The EN/PSV input is used to enable or disable the switching
regulator. When EN/PSV is low (grounded), the switching
regulator is off and in its lowest power state. When off, the
output of the switching regulator soft-discharges the output
into a 15 internal resistor via the VOUT pin. When EN/PSV
is allowed to float, the pin voltage will float to 33 % of the
voltage at VDD. The switching regulator turns on with
power-save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 44 % of the voltage at VDD), the
switching regulator turns on with power-save enabled. The
SiC401A/B P-Save operation reduces the switching
frequency according to the load for increased efficiency at
light load conditions.
Forced Continuous Mode Operation
The SiC401A/B operates the switcher in FCM (Forced
Continuous Mode) by floating the EN/PSV pin (see figure 4).
In this mode one of the power MOSFETs is always on, with
no intentional dead time other than to avoid
cross-conduction. This feature results in uniform frequency
across the full load range with the trade-off being poor
efficiency at light loads due to the high-frequency switching
of the MOSFETs. DH is gate signal to drive upper MOSFET.
DL is lower gate signal to drive lower MOSFET.
FB
VREF -
+
VOUT
VIN
Rton On-time = K x Rton x (VOUT/VIN)
FB comparator
One-shot
timer
Gate
drives
DH
DL
Q1
Q2
L
Q1
ESR FB
VOUT
COUT
VLX
+
fSW =VOUT
tON x VIN
R
ton
=25 pF
x f
SW
k
(VDD - 1.75) x 10
VIN
k =
Rton_MAX =VIN_MIN
15 µA
VOUT
R1
R2
To FB pin
V
OUT = 0.6 x 1 + R1
R2
VRIPPLE
2
+
VOUT = 0.6 x 1 + R1
R2
VRIPPLE
2
+x
R2 x R1
R2 + R1
ωCTOP
1 +
2
1 + (R1ωCTOP)2
SiC401A, SiC401BCD
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Fig. 4 - Forced Continuous Mode Operation
Ultrasonic Power-Save Operation (SiC401A)
The SiC401A provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed at
slightly under 25 kHz. This is accomplished by using an
internal timer that monitors the time between consecutive
high-side gate pulses. If the time exceeds 40 μs, DL drives
high to turn the low-side MOSFET on. This draws current
from VOUT through the inductor, forcing both VOUT and VFB
to fall. When VFB drops to the 600 mV threshold, the next DH
(the drive signal for the high side FET) on-time is triggered.
After the on-time is completed, the high-side MOSFET is
turned off and the low-side MOSFET turns on. The low-side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low-side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 μs, the frequency will not fall far below
25 kHz. Figure 5 shows ultrasonic power-save operation.
Fig. 5 - Ultrasonic Power-Save Operation
Power-Save Operation (SiC401B)
The SiC401B provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors the
inductor current via the voltage across the low-side
MOSFET during the off-time. If the inductor current falls to
zero for eight consecutive switching cycles, the controller
enters MOSFET on each subsequent cycle provided that the
power-save operation. It will turn off the low-side MOSFET
on each subsequent cycle provided that the current crosses
zero. At this time both MOSFETs remain off until VFB drops
to the 600 mV threshold. Because the MOSFETs are off, the
load is supplied by the output capacitor.
If the inductor current does not reach zero on any switching
cycle, the controller immediately exits power-save and
returns to forced continuous mode.
Figure 6 shows power-save operation at light loads.
Fig. 6 - Power-Save Mode
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in a hard
shut-down. Smart power-save prevents this condition.
When the FB voltage exceeds 10 % above nominal, the
device immediately disables power-save, and DL drives
high to turn on the low-side MOSFET. This draws current
from VOUT through the inductor and causes VOUT to fall.
When VFB drops back to the 600 mV trip point, a normal tON
switching cycle begins. This method prevents a hard OVP
shut-down and also cycles energy from VOUT back to VIN. It
also minimizes operating power by avoiding forced
conduction mode operation. Figure 7 shows typical
waveforms for the Smart Power Save feature.
FB ripple
voltage (VFB)
Inductor
current
DC load current
FB threshold
(600 mV)
DH
DL
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
FB ripple
voltage (VFB)
Inductor
current
(0A)
FB threshold
(600 mV)
DH
DL
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
After the 40 µs time-out, DL drives high if VFB
has not reached the FB threshold.
minimum fSW ~ 25 kHz
40 µs time-out
SiC401A, SiC401BCD
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Fig. 7 - Smart Power-Save
SmartDriveTM
For each DH pulse, the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and the
LX voltage has risen 0.5 V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
Current Limit Protection
The device features programmable current limiting, which is
accomplished by using the RDS-ON of the lower MOSFET for
current sensing. The current limit is set by RILIM resistor. The
RILIM resistor connects from the ILIM pin to the LXS pin which
is also the drain of the low-side MOSFET. When the low-side
MOSFET is on, an internal ~ 10 μA current flows from the ILIM
pin and through the RILIM resistor, creating a voltage drop
across the resistor. While the low-side MOSFET is on, the
inductor current flows through it and creates a voltage
across the RDS-ON. The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage
drop exceeds the voltage across RILIM, the voltage at the ILIM
pin will be negative and current limit will activate. The
current limit then keeps the low-side MOSFET on and will
not allow another high-side on-time, until the current in the
low-side MOSFET reduces enough to bring the ILIM voltage
back up to zero. This method regulates the inductor valley
current at the level shown by ILIM in figure 8.
Fig. 8 - Valley Current Limit
Setting the valley current limit to 15 A results in a peak
inductor current of 15 A plus peak ripple current. In this
situation, the average (load) current through the inductor is
15 A plus one-half the peak-to-peak ripple current.
The internal 10 μA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the RDS-ON.
The RILIM value is calculated by the following equation.
RILIM = 263 x ILIM x [0.112 x (5 V - VDD) + 1]
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note that
because the low-side MOSFET with low RDS-ON is used for
current sensing, the PCB layout, solder connections, and
PCB connection to the LX node must be done carefully to
obtain good results. RILIM should be connected directly to
LXS (pin 28).
Soft-Start of PWM Regulator
SiC401A/B has a programmable soft-start time that is
controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3 μA flowing
through the SS pin to charge the capacitor. During the start
up process (figure 9), 50 % of the voltage at the SS pin is
used as the reference for the FB comparator. The PWM
comparator issues an on-time pulse when the voltage at the
FB pin is less than 40 % of the SS pin. As a result, the output
voltage follows the SS voltage. The output voltage reaches
and maintains regulation when the soft start voltage
is 1.5 V. The time between the first LX pulse and VOUT
reaching regulation is the soft-start time (tSS). The
calculation for the soft-start time is shown by the following
equation.
The voltage at the SS pin continues to ramp up and
eventually equals 64 % of VDD. After the soft start
completes, the FB pin voltage is compared to an internal
reference of 0.6 V. The delay time between the VOUT
regulation point and PGOOD going high is shown by the
following equation.
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold (825 mV)
FB
threshold
DH and DL off
High-side
drive (DH)
Low-side
drive (DL)
Normal VOUT ripple
VOUT discharges via inductor
and low-side MOSFET
Single DH on-time pulse
after DL turn-off
Normal DL pulse after DH
on-time pulse
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
I
PEAK
I
LOAD
I
LIM
Time
Inductor Current
tSS = CSS x 1.5 V
3 μA
tPGOOD-DELAY
= C
SS
x (0.64 x V
DD
- 1.5 V)
3 μA
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Fig. 9 - Soft-Start Timing Diagram
Pre-Bias Start-Up
The SiC401A/B can start up normally even when there is an
existing output voltage present. The soft start time is still the
same as normal start up (when the output voltage starts
from zero). The output voltage starts to ramp up when 40 %
of the voltage at SS pin meets the existing FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents the output voltage from discharging.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the FB
pin is 10 % below the nominal voltage, PGOOD is pulled low.
It is held low until the output voltage returns above -8 % of
nominal.
PGOOD will transition low if the VFB pin exceeds +20 % of
nominal, which is also the over-voltage shutdown threshold.
PGOOD also pulls low if the EN/PSV pin is low when VDD is
present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600 mV +20 %
(720 mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input is
toggled or VDD is cycled. There is a 5 μs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under-Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
450 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V. An
internal POR (Power-On Reset) occurs when VDD exceeds
3 V, which resets the fault latch and a soft-start counter
cycle begins which prepares for soft-start. The SiC401A/B
then begins a soft-start cycle. The PWM will shut off if VDD
falls below 2.4 V.
LDO Regulator
SiC401A/B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND (see figure 10).
The feedback pin (FBL) for the LDO is regulated to 750 mV.
Fig. 10 - LDO Output Voltage Selection
The LDO output voltage is set by the following equation.
A minimum capacitance of 1 μF referenced to AGND is
normally required at the output of the LDO for stability.
Note that if the LDO voltage is set lower than 4.5 V, the
minimum output capacitance for the LDO is 10 μF.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function of
ENL and EN/PSV pins.
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SiC401A/B is self-biased from the
LDO and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN,
ENL and AGND pins. When SiC401A/B has an external bias
voltage at VDD and the ENL pin is used to program the VIN
EN/PSV ENL LDO SWITCHER
Disabled Low, < 0.4 V Off Off
Enabled Low, < 0.4 V Off On
Disabled 1 V < High < 2.6 V On Off
Enabled 1 V < High < 2.6 V On Off
Disabled High, > 2.6 V On Off
Enabled High, > 2.6 V On On
V
LDO = 750 mV x 1 + RLDO1
RLDO2
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UVLO feature, the voltage at FBL needs to be higher than
750 mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO threshold
and stays above 1 V, then the switcher will turn off but the
LDO will remain on.
LDO Start-Up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. VLDO output
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the VDD voltage (which is the LDO output voltage) is less
than 0.75 V, the LDO initiates a current-limited start-up
(typically 65 mA) to charge the output capacitors while
protecting from a short circuit event. When VDD is greater
than 0.75 V but still less than 90 % of its final value (as
sensed at the FBL pin), the LDO current limit is increased to
~115 mA. When VDD has reached 90 % of the final value (as
sensed at the FBL pin), the LDO current limit is increased
to ~200 mA and the LDO output is quickly driven to
the nominal value by the internal LDO regulator. It is
recommended that during LDO start-up to hold the PWM
switching off until the LDO has reached 90 % of the final
value. This prevents overloading the current-limited LDO
output during the LDO start-up.
Due to the initial current limitations on the LDO during power
up (figure 11), any external load attached to the VDD pin must
be limited to less than the start up current before the LDO
has reached 90 % of its final regulation value.
Fig. 11 - LDO Start-Up
LDO Switch-Over Operation
The SiC401A/B includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
by using the more efficient DC/DC converter to power the
LDO output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the VDD pin
directly to the VOUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC401A/B, then after switch-over
the device is self-powered from the switching regulator with
the LDO turned off.
The switch-over starts 32 switching cycles after PGOOD
output goes high. The voltages at the VDD and VOUT pins are
then compared; if the two voltages are within ± 300 mV of
each other, the VDD pin connects to the VOUT pin using an
internal switch, and the LDO is turned off. To avoid
unwanted switch-over, the minimum difference between the
voltages for VOUT and VDD should be ± 500 mV.
It is not recommended to use the switch-over feature for an
output voltage less than VDD UVLO threshold since the
SiC401A/B is not operational below that threshold.
Switch-Over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in figure 12. If the
voltage at the VOUT pin is higher than VDD, then the
respective diode will turn on and the current will flow
through this diode. This has the potential of damaging the
device. Therefore, VOUT must be less than VDD to prevent
damaging the device.
Fig. 12 - Switch-Over MOSFET Parasitic Diodes
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor ripple
current must be specified.
The maximum input voltage (VIN max.) is the highest specified
input voltage. The minimum input voltage (VIN min.) is
determined by the lowest input voltage after evaluating the
voltage drops due to connectors, fuses, switches, and PCB
traces.
The following parameters define the design:
• Nominal output voltage (VOUT)
• Static or DC output tolerance
• Transient response
• Maximum load current (IOUT)
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection of
the inductor and input capacitors. Peak load current
determines instantaneous component stresses and filtering
requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design:
•V
IN = 12 V ± 10 %
•V
OUT = 1.5 V ± 4 %
•f
SW = 300 kHz
• Load = 15 A max.
V
OUT
LDO
Parastic diode
Switchover
MOSFET
Switchover
control
V
DD
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Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 300 kHz which results
from using component selected for optimum size and cost.
A resistor (RtON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
To select RtON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
Substituting for RtON results in the following solution.
RtON = 133.3 kW, use RtON = 130 kW.
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size
but create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current/voltage
and for a given DC resistance are more efficient. However,
larger inductance translates directly into larger packages
and higher cost. Cost, size, output ripple, and efficiency are
all used in the selection process.
The ripple current will also set the boundary for PSave
operation. The switching will typically enter PSave mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A then PSave operation will
typically start for loads less than 2 A. If ripple current is set
at 40 % of maximum load current, then PSave will start for
loads less than 20 % of maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
Example
In this example, the inductor ripple current is set equal to
30 % of the maximum load current. Thus ripple current will
be 30 % x 15 A or 4.5 A. To find the minimum inductance
needed, use the VIN and tON values that correspond to
VINmax.
A slightly larger value of 1 μH is selected. This will decrease
the maximum IRIPPLE to 4.43 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
Capacitor Selection
The output capacitors are chosen based upon required
ESR and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple.
A change in the output ripple voltage will lead to a change in
DC voltage at the output.
The design goal for output voltage ripple is 3 % of 1.5 V or
45 mV. The maximum ESR value allowed is shown by the
following equations.
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current
is at the peak, determines the required capacitance. If the
load release is instantaneous (load changes from maximum
to zero in < 1 μs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
Rton =25 pF x fSW
k
tON =VOUT
VINmax. x fSW
L = (VIN - VOUT) x tON
IRIPPLE
L = (13.2 - 1.5) x 379 ns
4.5 A = 0.99 µH
t
ON_VINmin.
=25 pF x R
tON
x V
OUT
V
INmin.
I
RIPPLE
=(V
IN
- V
OUT
) x t
ON
L
I
RIPPLE_VINmin.
=(10.8 - 1.5) x 451 ns
1 µH = 4.19 A
= 451 ns
ESR
max.
=V
RIPPLE
I
RIPPLEmax.
ESR
max.
= 10.2 mΩ
=45 mV
4.43 A
COUT_min. =
L (IOUT + x IRIPPLEmax.)2
(VPEAK)2 - (VOUT)2
1
2
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Assuming a peak voltage VPEAK of 1.65 V (150 mV rise upon
load release), and a 15 A load release, the required
capacitance is shown by the next equation.
During the load release time, the voltage cross the inductor
is approximately - VOUT. This causes a down-slope or falling
di/dt in the inductor. If the load dI/dt is not much faster than
the dI/dt of the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt.
Peak inductor current is shown by the next equation.
ILPK = Imax. + 1/2 x IRIPPLE max.
ILPK = 10 + 1/2 x 4.43 = 12.215 A
Imax. = maximum load release = 15 A
Example
This would cause the output current to move from 15 A to
0 A in 4 μs, giving the minimum output capacitance
requirement shown in the following equation.
Note that COUT is much smaller in this example, 169 μF
compared to 316 μF based on a worst case load release. To
meet the two design criteria of minimum 316 μF and
maximum 10.2 mW ESR, select one capacitor of 330 μF and
9 mW ESR.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250 ns minimum off-time has expired. In extreme cases the
noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation.
This form of instability can usually be avoided by providing
the FB pin with a smooth, clean ripple signal that is at least
10 mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout as discussed in the Layout Guidelines
section.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 13. This capacitor should be left
unpopulated until it can be confirmed that double-pulsing
exists. Adding the CTOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional
connection on the PCB should be available for this
capacitor.
Fig. 13 - Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10 mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability
the ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
C
OUT_min.
=
1 µH (10 + x 4.43)2
(1.65)2 - (1.5)2
C
OUT_min.
= 316 µF
1
2
Rate of change of load current = dI
LOAD
dt
COUT = ILPK x
L x - x dt
2 (VPK - VOUT)
ILPK
VOUT
Imax.
dlLOAD
dlLOAD
dt =2.5 A
1 µs
COUT = 12.215 x
1 µH x - x 1 µs
2 (1.65 - 1.5)
12.215
1.5
10
2.5
COUT = 169 µF
V
OUT
R
1
R
2
To FB pin
C
TOP
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formula for minimum ESR is shown by the following
equation.
Using Ceramic Output Capacitors
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90°.
Therefore, the converter is easily stabilized. When the
system is using ceramic output capacitors, the ESR value is
normally too small to meet the above ESR criteria. As a
result, the feedback voltage ripple is 180° from the phase
node and behaves in an unstable manner. In this application
it is necessary to add a small virtual ESR network that is
composed of two capacitors and one resistor, as shown in
figure 14.
Fig. 14 - Virtual ESR Ramp Current
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and output ripple voltage.
They are defined in the following equations.
Figure 15 shows the magnitude of the ripple contribution
due to CL at the FB pin.
Fig. 15 - FB Voltage by CL Voltage
It is shown by the following equation.
Figure 16 shows the magnitude of the ripple contribution
due to the output voltage ripple at the FB pin.
Fig. 16 - FB Voltage by Output Voltage
It is shown by the following equation.
It is recommended that R2 be set to 1k.
The purpose of this network is to couple the inductor current
ripple information into the feedback voltage such that the
feedback voltage has 90° phase lag to the switching node
similar to the case of using standard high ESR capacitors.
This is illustrated in figure 17.
Fig. 17 - FB Voltage in Phasor Diagram
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from C
L
, is controlled by the
value of R
1
, R
2
and C
C
. If the corner frequency of (R
1
//R
2
) x C
C
is too high, the ripple magnitude at the FB pin will be smaller,
which can lead to double-pulsing. Conversely, if the corner
frequency of (R
1
//R
2
) x C
C
is too low, the ripple magnitude at
FB pin will be higher. Since the SiC401A/B regulates to the
valley of the ripple voltage at the FB pin, a high ripple
magnitude is undesirable as it significantly impacts the output
voltage regulation. As a result, it is desirable to select a corner
frequency for (R
1
//R
2
) x C
C
to achieve enough, but not
excessive, ripple magnitude and phase margin. The
ESRmin. =3
2 x π x COUT x fSW
VCL =
IL x DCR (s x L/DCR + 1)
S x RL x CL + 1
ΔVOUT = ΔIL
8C x fSW
VFBCL = VCL x (R1//R2) x S x CC
(R1//R2) x S x CC + 1
VFBΔVOUT = ΔVOUT x R2
R1// + R2
S x CC
1
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component values for R
1
, R
2
, and C
C
should be calculated
using the following procedure.
Select CL (typical 10 nF) and RL to match with L and DCR
time constant using the following equation.
Select CC by using the following equation.
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is from
10 pF to 1 nF.
Dropout Performance
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low
input voltages, the duty-factor limit must be calculated using
worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the
FB error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions
it trips when the feedback pin is 600 mV, 1 %.
The on-time pulse from the SiC401A/B in the design
example is calculated to give a pseudo-fixed frequency of
300 kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple voltage.
Because adaptive on-time converters regulate to the valley
of the output ripple, ½ of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with VIN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point.
If the ripple increases to 80 mV with VIN = 17 V, then the
measured DC output will be 40 mV above the comparator
trip. The best way to minimize this effect is to minimize the
output ripple.
The use of 1 % feedback resistors may result in up to 1 %
error. If tighter DC accuracy is required, 0.1 % resistors
should be used.
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor
effect on the DC output voltage. The output ESR also affects
the output ripple and thus has a minor effect on the DC
output voltage.
Switching Frequency Variation
The switching frequency varies with load current as a result
of the power losses in the MOSFETs and DCR of the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. An adaptive on-time converter
must also compensate for the same losses by increasing the
effective duty cycle (more time is spent drawing energy from
VIN as losses increase). The on-time is essentially constant
for a given VOUT/VIN combination, to offset the losses the
off-time will tend to reduce slightly as load increases. The
net effect is that switching frequency increases slightly with
increasing load.
HIGH OUTPUT VOLTAGE OPERATION
For the SiC40X family the recommended maximum output
voltage of no more than 75 % of VIN.
For applications where an output voltage greater than 5 V is
required a resistive network should be used to step down the
output voltage in order to provide the V
OUT_PIN
with 4.5 V.
For example, if an output voltage of V
OUT
= 8.5 V is required,
setting R
2
= 10 k
and V
OUT_PIN
= 4.5 V results in R
1
= 8870
The switching frequency will also need recalculating using a
VOUT_PIN magnitude of 4.5 V.
Fig. 18 - Resistor Divider Network allows 4.5 V at the VOUT Pin
RL = L
DCR x CL
CC ≈1
R1//R2
3
2 x π x fSW
x
DUTY =tON(min.)
tON(min.) x tOFF(max.)
R1 = R2 (VOUT - VOUT_PIN)
VOUT_PIN
f
sw
= V
OUT_PIN
t
ON
x V
IN
SiC40X Cout
Vout
V
OUT_PIN
LX
R1
R2
SiC401A, SiC401BCD
www.vishay.com Vishay Siliconix
S14-2048-Rev. D, 13-Oct-14 24 Document Number: 63835
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
LAYOUT CONSIDERATIONS
The SiC40x family of footprint compatible 15 A, 10 A, and
6 A products offers the designer a scalable buck regulator
solution. If the below layout recommendations are followed,
the same layout can be used to cover a wide range of output
currents and voltages without any changes to the board
design and only minor changes to the component values in
the schematic.
The reference design has a majority of the components
placed on the top layer. This allows for easy assembly and
straightforward layout.
Figure 19 outlines the pointers for the layout considerations
and the explanations follow.
Fig. 19 - Reference Design Pointers
1. Place input ceramic capacitors close to the voltage input
pins with a small 10 nF/100 nF placed as close as the
design rules will allow. This will help reduce the size of
the input high frequency current loop and consequently
reduce the high frequency ripple noise seen at the input
and the LX node.
2. Place the setup and control passive devices logically
around the IC with the intention of placing a quiet ground
plane beneath them on a secondary layer.
3. It is advisable to use ceramic capacitors at the output to
reduce impedance. Place these as close to the IC PGND
and output voltage node as design will allow. Place a
small 10 nF/100 nF ceramic capacitor closest to the IC
and inductor loop.
4. The loop between LX, VOUT and the IC GND should be as
compact as possible. This will lower series resistance
and also make the current loop smaller enabling the high
frequency response of the output capacitors to take
effect.
5. The output impedance should be small when high
current is required; use high current traces, multiple
layers can be used with many vias.
6. Use many vias when multiple layers are involved. This
will have the effect of lowering the resistance between
layers and reducing the via inductance of the PCB nets.
7. If a voltage injection network is needed then place it near
to the inductor LX node.
8. PGND can be used on internal layers if the resistance of
the PCB is to be small; this will also help remove heat.
Use extra vias if needed but be mindful to allow a path
between the vias.
9. A quiet plane should be employed for the AGND, this is
placed under the small signal passives. This can be
placed on multiple layers if needed for heat removal. This
should be connected to the PGND plane near to the input
GND at one connection only of at least 1 mm width.
10. The LX copper can also be used on multiple layers, use
a number of vias.
11. The copper area beneath the inductor has been removed
(on all layers) in this design to reduce the inductive
coupling that occurs between the inductor and the GND
trace. No other voltage planes should be placed under
this area.
0V
VIN
VOUT
LX
4
10
11
2
7
0
V
VIN
VO
U
T
3
6
1
8
9
SiC40X
5
SiC401A, SiC401BCD
www.vishay.com Vishay Siliconix
S14-2048-Rev. D, 13-Oct-14 25 Document Number: 63835
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PCB LAYOUT
Fig. 20 - Top Layer
Fig. 21 - Inner Layer 1
Fig. 22 - Inner Layer 2
Fig. 23 - Bottom Layer
SiC401A, SiC401BCD
www.vishay.com Vishay Siliconix
S14-2048-Rev. D, 13-Oct-14 26 Document Number: 63835
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SCHEMATIC
Note
• If OUT voltage setting 5 VDC, please change R10 and R11 value based on “High Output Voltage Operation” formula calculation.
SiC401A, SiC401BCD
www.vishay.com Vishay Siliconix
S14-2048-Rev. D, 13-Oct-14 27 Document Number: 63835
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63835.
BILL OF MATERIALS (VIN = 12 V, VOUT = 1.5 V, Fsw = 500 kHz)
ITEM QTY REFERENCE PCB
FOOTPRINT VALUE VOLTAGE PART NUMBER MANUFACTURER
1 2 C1, C2 1206 Omit 35 V C3216X5R1V226M160AC TDK
2 2 C3, C4 1206 22 μF 35 V C3216X5R1V226M160AC TDK
3 3 C5, C9, C12 0402 10 nF 50 V GRM155R71H103KA88D Murata
4 1 C6 0402 2.2 μF 10 V C0402C225M8PACTU Kemet
5 2 C7, C10 0402 2.2 nF 50 V GRM155R71H222KA01D Murata
6 1 C8 0402 100 nF 35 V CGA2B3X7R1V104K050BB Vishay
7 5 C13, C14, C15, C16, C17 1206 47 μF 10 V GRM31CR61A476ME15L Murata
8 3 C18, C19, C20 1206 Omit 10 V GRM31CR61A476ME15L Murata
9 2 C21, C22 7343 Omit - - -
10 4 P1, P3, P9, P10 Banana Jack - - 575-4K-ND Keystone
11 5 P2, P4, P5, P7, P8 Header-2 - - 826926-2 AMP (TE)
12 1 P6 Header-3 - - HTSW-103-08-T-S Samtec
13 1 L1 IHLP5050 1 μH - IHLP5050FDER1R0 Vishay
14 1 R1 0402 249K - CRCW0402249KFKED Vishay
15 1 R2 0402 100K - CRCW0402100KFKED Vishay
16 1 R3 0402 169K - CRCW0402169KFKED Vishay
17 1 R4 0402 30K - CRCW040230K0FKED Vishay
18 1 R5 0402 5K11 - CRCW04025K11FKED Vishay
19 1 R6 0402 76K8 - CRCW040276K8FKED Vishay
20 1 R7 0402 10R - CRCW040210R0FKEA Vishay
21 1 R8 0402 10K - CRCW040210K0FKED Vishay
22 1 R9 0805 Omit - - Vishay
23 1 R10 0402 0R - CRCW04020000Z0ED Vishay
24 1 R11 0402 Omit - - Vishay
25 1 R12 0402 1K54 - CRCW04021K54FKED Vishay
26 1 R13 0402 1K - CRCW0402249KFKED Vishay
27 1 R14 0402 10R - CRCW040210R0FKEA Vishay
28 1 R15 0402 10K - CRCW040210K0FKED Vishay
29 1 U1 MLP55-33 SIC401 - - -
Document Number: 64714 www.vishay.com
Revision: 29-Dec-08 1
Package Information
Vishay Siliconix
PowerPAK® MLP55-32L CASE OUTLINE
Notes
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
by marking
E
Pin 1 dot
Top View
D
(5 mm x 5 mm)
32L T/SLP
E2 - 2
(Nd-1) Xe
Ref.
Bottom View
Side View
D2 - 1
R0.200
Pin #1 identification
b
e
D2 - 4 D2 - 3
E2 - 3
D4
9
24
25 32
A
0.10 CB
2x
0.08C
C
A
A2
A1
B
(Nd-1) Xe
Ref.
L
0.36
0.360
56
0.10 CAB
4
D2 - 2
E2 - 1
0.10 CA
2x
8
17
16
0.45
1
MILLIMETERS INCHES
DIM MIN. NOM. MAX. MIN. NOM. MAX.
A 0.80 0.85 0.90 0.031 0.033 0.035
A1(8) 0.00 - 0.05 0.000 - 0.002
A2 0.20 REF. 0.008 REF.
b(4) 0.20 0.25 0.30 0.078 0.098 0.011
D 5.00 BSC 0.196 BSC
e 0.50 BSC 0.019 BSC
E 5.00 BSC 0.196 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N(3) 32 32
Nd(3) 88
Ne(3) 88
D2 - 1 3.43 3.48 3.53 0.135 0.137 0.139
D2 - 2 1.00 1.05 1.10 0.039 0.041 0.043
D2 - 3 1.00 1.05 1.10 0.039 0.041 0.043
D2 - 4 1.92 1.97 2.02 0.075 0.077 0.079
E2 - 1 3.43 3.48 3.53 0.135 0.137 0.139
E2 - 2 1.61 1.66 1.71 0.063 0.065 0.067
E2 - 3 1.43 1.48 1.53 0.056 0.058 0.060
ECN: T-08957-Rev. A, 29-Dec-08
DWG: 5983
Legal Disclaimer Notice
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Revision: 08-Feb-17 1Document Number: 91000
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