DS1832
3.3 Volt MicroMonitor Chip
DS1832
062698 1/7
FEATURES
•Halts and restarts an out–of–control microprocessor
•Holds microprocessor in check during power tran-
sients
•Automatically restarts microprocessor after power
failure
•Monitors pushbutton for external override
•Accurate 10% or 20% microprocessor power
monitoring
•Eliminates need for discrete components
•20% tolerance for use with 3.0 volt systems
•Pin compatible with the DS1232
•Low cost 8–pin DIP, 8–pin SOIC, and space saving
µ–SOP packages available
•Industrial temperature range of –40°C to +85°C
PIN ASSIGNMENT1
2
3
4
8
7
6
5
VCC
ST
RST
RST
PBRST
TD
TOL
GND
DS1832 8–PIN DIP (300 MIL)
See Mech. Drawings Section
1
2
3
45
6
7
8
TD
TOL
GND
PBRST VCC
ST
RST
RST
DS1832S 8–PIN SOIC (150 MIL)
See Mech. Drawings Section
DS1232µ 8–PIN µ–SOP (118 MIL)
See Mech. Drawings Section
VCC
ST
RST
RST
8
7
6
5
1
2
3
4
PBRST
TD
TOL
GND
PIN DESCRIPTION
PBRST – Pushbutton Reset Input
TD – T ime Delay Set
TOL – Selects 10% or 20% VCC Detect
GND – Ground
RST – Active High Reset Output
RST – Active Low Reset Output
ST – Strobe Input
VCC – Power Supply
DESCRIPTION
The DS1832 3.3 V olt MicroMonitor monitors three vital
conditions for a microprocessor: power supply, soft-
ware execution, and external override. First, a precision
temperature–compensated reference and comparator
circuit monitors the status of VCC. When an out–of–tol-
erance condition occurs, an internal power fail signal is
generated which forces the resets to an active state.
When VCC returns to an in–tolerance condition, the
reset signals are kept in the active state for a minimum
of 250 ms to allow the power supply and processor to
stabilize.
The second function the DS1832 performs is pushbut-
ton reset control. The DS1832 debounces the pushbut-
ton input and guarantees an active reset pulse width of
250 ms minimum. The third function is a watchdog
timer . The DS1832 has an internal timer that forces the
reset signals to the active state if the strobe input is not
driven low prior to time–out. The watchdog timer func-
tion can be set to operate on time–out settings of
approximately 150 ms, 600 ms, or 1.2 seconds.
DS1832
062698 2/7
OPERATION – POWER MONITOR
The DS1832 detects out–of–tolerance power supply
conditions and warns a processor–based system of im-
pending power failure. When VCC falls below a preset
level as defined by TOL, the VCC comparator outputs the
signals RST and RST. When TOL is connected to
ground, the RST and RST signals become active as VCC
falls below 2.98 volts. When TOL is connected to VCC,
the RST and RST signals become active as VCC falls be-
low 2.64 volts. The RST and RST are excellent control
signals for a microprocessor, as processing is stopped at
the last possible moments of valid VCC. On power–up,
RST and RST are kept active for a minimum of 250 ms to
allow the power supply and processor to stabilize.
OPERATION – PUSHBUTTON RESET
The DS1832 provides an input pin for direct connection
to a pushbutton reset (see Figure 2). The pushbutton re-
set input requires an active low signal. Internally , this in-
put is debounced and timed such that RST and RST sig-
nals of at least 250 ms minimum are generated. The
250 ms delay commences as the pushbutton reset input
is released from the low level.
OPERATION – WATCHDOG TIMER
The watchdog timer function forces RST and RST sig-
nals active when the ST input is not clocked within the
predetermined time period. The timeout period is deter-
mined by the condition of the TD pin. if TD is connected
to ground the minimum watchdog timeout would be
62.5 ms, TD floating would yield a minimum timeout of
250 ms, and TD connected to VCC would provide a time-
out of 500 ms minimum. Timeout of the watchdog starts
when RST and RST become inactive. If a high–to–low
transition occurs on the ST input pin prior to time–out,
the watchdog timer is reset and begins to time–out
again. If the watchdog timer is allowed to time–out, then
the RST and RST signals are driven active for a mini-
mum of 250 ms. The ST input can be derived from many
microprocessor outputs. The most typical signals used
are the microprocessor address signals, data signals or
control signals. When the microprocessor functions
normally, these signals would, as a matter of routine,
cause the watchdog to be reset prior to time–out. To
guarantee that the watchdog timer does not time–out, a
high–to–low transition must occur at or less than the
minimum times shown in T able 1. A typical circuit exam-
ple is shown in Figure 4.
The DS1832 watchdog function cannot be disabled.
The watchdog strobe input must be strobed to avoid a
watchdog timeout and reset.
MICROMONITOR BLOCK DIAGRAM Figure 1
TOL
T.C. REFERENCE
LEVEL SENSE
VOLTAGE
DIGITAL
TD
TIME-OUT
ST
PBRST
VCC VCC
TOLERANCE
BIAS
AND
DEBOUNCE
SENSE
COMPARATOR
DELAY
+
–VCC
VCC
RST
RST
DS1832
062698 3/7
PUSHBUTTON RESET Figure 2
TD
TOL
GND RST
ALE
RST
RST
ST
PBRST VCC
DS1832
8051
µP
SUPPLY
VOLTAGE
TIMING DIAGRAM: PUSHBUTTON RESET Figure 3
RST
PBRST
RST
VIH
VIL
VOL
VOH
tRST
tPB
tPDLY
WATCHDOG TIMER Figure 4
TD
TOL
GND RST
ADDRESS
RST
ST
PBRST
MREQ
VCC
DS1832
BUS
SUPPLY
VOLTAGE
Z80
RST DECODER
DS1832
062698 4/7
WATCHDOG TIME–OUTS Table 1
TIME–OUT
TD MIN TYP MAX
GND 62.5 ms 150 ms 250 ms
Float 250 ms 600 ms 1000 ms
VCC 500 ms 1200 ms 2000 ms
TIMING DIAGRAM: STROBE INPUT Figure 5
RST
INDETERMINATE
STROBE
INVALID
STROBE
MIN. MAX.
VALID
STROBE
ST
tTD
TIMING DIAGRAM: POWER DOWN Figure 6
tF
RST
RST
VCC
tRPD
VOL
VOH
RST SLEWS WITH VCC
VCCTP(MAX) VCCTP VCCTP(MIN)
DS1832
062698 5/7
TIMING DIAGRAM: POWER UP Figure 7
RST
RST
VCC
tR
VOL
VOH
tRPU
VCCTP(MAX)
VCCTP(MIN)
VCCTP
RST VALID TO 0 VOLTS VCC Figure 8
RST INPUT
100KΩ
OUTPUT VALID CONDITIONS
The RST output uses a push–pull output which can
maintain a valid output down to 0.8 volts VCC. To sink
current below 0.8 volts a resistor can be connected from
RST to Ground (see Figure 8). This arrangement will
maintain a valid value on RST during both power up and
power down but will draw current when RST is in the
high state. A value of about 100KΩ should be adequate
in most situations. The output with a resistor pull–down
can maintain a valid reset down to VCC equal to 0 volts.
DS1832
062698 6/7
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground –0.5V to +7.0V
Voltage on I/O Relative to Ground –0.5V to VCC +0.5V
Operating Temperature –40°C to +85°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (–40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 1.0 5.5 V 1
ST and PBRST Input High Level VIH 2.0 VCC+0.3 V 1, 3
VCC–0.4 1, 4
ST and PBRST Input Low Level VIL –0.3 0.5 V 1
DC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC=1.2V to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Trip Point (TOL = GND) VCCTP 2.80 2.88 2.97 V 1
VCC Trip Point (TOL = VCC) VCCTP 2.47 2.55 2.64 V 1
Input Leakage IIL –1.0 +1.0 µA 2
Output Current @ 2.4V IOH 350 µA 3
Output Current @ 0.4V IOL 10 mA 3
Output Voltage @ –500 uA VOH VCC–0.3V VCC–0.1V V 4
Operating Current ICC 35 µA 5
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5pF
Output Capacitance COUT 7 pF
DS1832
062698 7/7
AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC = 1.2V to 5.5V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
PBRST = VIL tPB 20 ms
RESET Active T ime tRST 250 610 1000 ms
ST Pulse Width tST 20 ns 6, 7
VCC Detect to RST and RST tRPD 5 8 µs 8
VCC Slew Rate tF20 µs
VCC Detect to RST and RST tRPU 250 610 1000 ms 9
VCC Slew Rate tR0 ns
PBRST Stable Low to RST and
RST tPDLY 20 ms
NOTES:
1. All voltages referenced to ground.
2. PBRST is internally pulled up to VCC with an internal impedance of 40KΩ typical.
3. Measured with VCC 2.7V.
4. Measured with VCC < 2.7V.
5. Measured with outputs open, VCC 3.6 volts, and all inputs at VCC or Ground.
6. Must not exceed tTD minimum.
7. The W atchdog cannot be disabled it must be strobed to avoid resets.
8. Noise Immunity – Pulses < 2 µs at VCCTP minimum will not cause a reset.
9. tR = 5 µs.
MARKING INFORMATION:
8–pin DIP – “DS1832”
8–pin SOIC – “DS1832”
8–pin – µ–SOP – “1832”
