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FEATURES
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
INT
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
GND
VCC
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
P10
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RHL PACKAGE
(TOP VIEW)
1 24
12 13
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
SDA
SCL
A0
P17
P16
P15
P14
P13
P12
P11
A1
A2
P00
P01
P02
P03
P04
P05
P06
P07
P10 V
GND
CC
INT
24 23 22 21 20
7 8 9 10 11
1
2
3
4
5
6
18
17
16
15
14
13
RGE PACKAGE
(TOP VIEW)
A2
A1
INT
P10
P11 SDA
P06
P07
GND VCC
19
SCL
12
P12
P00
P01
P03
P03
P04
P05
A0
P17
P16
P15
P14
P13
DESCRIPTION/ORDERING INFORMATION
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
•Low Standby-Current Consumption of •Current Source to V
CC
for Actively Driving a10 µA Max High at the Output•I
2
C to Parallel-Port Expander •Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•Open-Drain Interrupt Output
•ESD Protection Exceeds JESD 22•Compatible With Most Microcontrollers
– 2000-V Human-Body Model (A114-A)•400-kHz Fast I
2
C Bus
– 200-V Machine Model (A115-A)•Address by Three Hardware Address Pins forUse of up to Eight Devices – 1000-V Charged-Device Model (C101)•Latched Outputs With High-Current DriveCapability for Directly Driving LEDs
This 16-bit I/O expander for the two-line bidirectional bus (I
2
C) is designed for 2.5-V to 5.5-V V
CC
operation.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Reel of 2000 PCF8575DBRSSOP – DB PF575Reel of 250 PCF8575DBTQSOP – DBQ Reel of 2500 PCF8575DBQR PCF8575TVSOP – DGV Reel of 2000 PCF8575DGVR PF575Tube of 25 PCF8575DWSOIC – DW PCF8575–40 °C to 85 °C Reel of 2000 PCF8575DWRTube of 60 PCF8575PWTSSOP – PW Reel of 1200 PCF8575PWR PF575Reel of 250 PCF8575PWTQFN – RGE Reel of 3000 PCF8575RGER PF575QFN – RHL Reel of 1000 PCF8575RHLR PF575
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
The PCF8575 provides general-purpose remote I/O expansion for most microcontroller families via the I
2
Cinterface serial clock (SCL) and serial data (SDA).
The device features a 16-bit quasi-bidirectional input/output (I/O) port (P07–P00, P17–P10), including latchedoutputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used asan input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode,only a current source (I
OH
) to V
CC
is active. An additional strong pullup to V
CC
(I
OHT
) allows fast-rising edges intoheavily loaded outputs. This device turns on when an output is written high and is switched off by the negativeedge of SCL. The I/Os should be high before being used as inputs. After power on, as all the I/Os are set high,all of them can be used as inputs. Any change in setting of the I/Os as either input or outputs can be done withthe write mode. If a high is applied externally to an I/O that has been written earlier to low, a large current (I
OL
)will flow to GND.
The PCF8575 provides an open-drain interrupt ( INT) output, which can be connected to the interrupt input of amicrocontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. Aftertime, t
iv
, the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the portis changed to the original setting, or data is read from or written to the port that generated the interrupt.Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in thewrite mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clockpulse can be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of theI/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does notaffect the interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming dataon its ports, without having to communicate via the I
2
C bus. Thus, the PCF8575 can remain a simple slavedevice.
Every data transmission to or from the PCF8575 must consist of an even number of bytes. The first data byte inevery pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). Towrite to the ports (output mode), the master first addresses the slave device, setting the last bit of the bytecontaining the slave address to logic 0. The PCF8575 acknowledges, and the master sends the first data bytefor P07–P00. After the first data byte is acknowledged by the PCF8575, the second data byte (P17–P10) is sentby the master. Once again, the PCF8575 acknowledges the receipt of the data, after which this 16-bit data ispresented on the port lines.
The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data isoverwritten. When the PCF8575 receives the pairs of data bytes, the first byte is referred to as P07–P00 and thesecond byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on.
Before reading from the PCF8575, all ports desired as input should be set to logic 1. To read from the ports(input mode), the master first addresses the slave device, setting the last bit of the byte containing the slaveaddress to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the inputport changes faster than the master can read, this data may be lost.
When power is applied to V
CC
, an internal power-on reset holds the PCF8575 in a reset state until V
CC
hasreached V
POR
. At that time, the reset condition is released, and the device I
2
C-bus state machine initializes thebus to its default state.
The hardware pins (A0, A1, and A2) are used to program and vary the fixed I
2
C address and allow up to eightdevices to share the same I
2
C bus or SMBus. The fixed I
2
C address of the PCF8575 is the same as thePCF8575C, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, toshare the same I
2
C bus or SMBus.
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PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
TERMINAL FUNCTIONS
NO.
DB, DBQ, DGV,
NAME FUNCTIONDW, PW, AND RGERHL
1 22 INT Interrupt output. Connect to V
CC
through a pullup resistor.2 23 A1 Address input 1. Connect directly to V
CC
or ground. Pullup resistors are not needed.3 24 A2 Address input 2. Connect directly to V
CC
or ground. Pullup resistors are not needed.4 1 P00 P-port input/output. Push-pull design structure.5 2 P01 P-port input/output. Push-pull design structure.6 3 P02 P-port input/output. Push-pull design structure.7 4 P03 P-port input/output. Push-pull design structure.8 5 P04 P-port input/output. Push-pull design structure.9 6 P05 P-port input/output. Push-pull design structure.10 7 P06 P-port input/output. Push-pull design structure.11 8 P07 P-port input/output. Push-pull design structure.12 9 GND Ground13 10 P10 P-port input/output. Push-pull design structure.14 11 P11 P-port input/output. Push-pull design structure.15 12 P12 P-port input/output. Push-pull design structure.16 13 P13 P-port input/output. Push-pull design structure.17 14 P14 P-port input/output. Push-pull design structure.18 15 P15 P-port input/output. Push-pull design structure.19 16 P16 P-port input/output. Push-pull design structure.20 17 P17 P-port input/output. Push-pull design structure.21 18 A0 Address input 0. Connect directly to V
CC
or ground. Pullup resistors are not needed.22 19 SCL Serial clock line. Connect to V
CC
through a pullup resistor23 20 SDA Serial data line. Connect to V
CC
through a pullup resistor.24 21 V
CC
Supply voltage
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22
I/O
Port P17−P10
Shift
Register 16 Bits
LP Filter
Interrupt
Logic
Input
Filter
23
Power-On
Reset
Read Pulse
Write Pulse
PCF8575
3
2
21
1
24
12
GND
VCC
SDA
SCL
A2
A1
A0
INT
I2C Bus
Control
P07−P00
To Interrupt
Logic
P07−P00
VCC
GND
CIS
D Q
FF
CIS
D Q
FF
Write Pulse
Data From
Shift Register
Power-On
Reset
Read Pulse
Data To
Shift Register
100 µA
P17−P10
IOH
IOL
IOHT
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT
4
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I
2
C Interface
SDA
SCL
Start Condition
S
Stop Condition
P
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must beconnected to a positive supply via a pullup resistor when connected to the output stages of a device. Datatransfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a Start condition, a high-to-low transition onthe SDA input/output while the SCL input is high (see Figure 1 ). After the Start condition, the device addressbyte is sent, most significant bit (MSB) first, including the data direction bit (R/ W). This device does not respondto the general call address. After receiving the valid address byte, this device responds with an ACK, a low onthe SDA input/output during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slavedevice must not be changed between the Start and Stop conditions.
The data byte follows the address ACK. If the R/ W bit is high, the data from this device are the values read fromthe P port. If the R/ W bit is low, the data are from the master, to be output to the P port. The data byte isfollowed by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, theyare ignored by this device. Data are output only if complete bytes are received and acknowledged. The outputdata is valid at time (t
pv
) after the low-to-high transition of SCL, during the clock cycle for the ACK.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remainstable during the high pulse of the clock period, as changes in the data line at this time are interpreted as controlcommands (Start or Stop) (see Figure 2 ).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by themaster (see Figure 1 ).
The number of data bytes transferred between the Start and Stop conditions from transmitter to receiver is notlimited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before thereceiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master mustgenerate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The devicethat acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable lowduring the high pulse of the ACK-related clock period (see Figure 3 ). Setup and hold times must be taken intoaccount.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) afterthe last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA linehigh. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
Figure 1. Definition of Start and Stop Conditions
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SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Data Output
by Transmitter
SCL from
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
Figure 2. Bit Transfer
Figure 3. Acknowledgment on I
2
C Bus
Interface Definition
BITBYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L H L L A2 A1 A0 R/ WP0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10
6
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A AS 0 1 0 0 A1A2 A0 0
Start
Condition
ACK
From Slave ACK
From Slave
Data to Port 0 Data to Port 1Slave Address (PCF8575C) R/W
P07 P06 1 P00 P17 P10 A
Integral Multiples of Two Bytes
P05
tpv
IOHT
tir
SCL
SDA
Write to
Port
Data Output
Voltage
P05 Output
Voltage
P05 Pullup
Output
Current
INT
ACK
From Slave
Data A0
and B0
Valid
12345678 1234567 8 1 2 3 4 5 6 7 8
IOH
A AS 0 1 0 0 A1
A2 A0 1
ACK
From Slave ACK
From Master
R/W
P07 P06 P00 P17
ACK
From Master
tsu
tir
SCL
SDA
Read From
Port
Data Into
Port
INT
P05 P04 P03 P02 P01 A
P10
tir
tiv
P17 to P10
P07 to P00 P07 to P00 P17 to P10
A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by
a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.
P16 P15 P14 P13 P12 P11
th
P07 P06
12345678 1234567 8 1 2 3 4 5 6 7 8
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
Figure 4 and Figure 5 show the address and timing diagrams for the write and read modes, respectively.
Figure 4. Write Mode (Output)
Figure 5. Read Mode (Input)
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
Address Reference
INPUTS
I
2
C BUS SLAVE ADDRESSA2 A1 A0
L L L 32 (decimal), 20 (hexadecimal)L L H 33 (decimal), 21 (hexadecimal)L H L 34 (decimal), 22 (hexadecimal)L H H 35 (decimal), 23 (hexadecimal)H L L 36 (decimal), 24 (hexadecimal)H L H 37 (decimal), 25 (hexadecimal)H H L 38 (decimal), 26 (hexadecimal)H H H 39 (decimal), 27 (hexadecimal)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 V
CC
+ 0.5 VV
O
Output voltage range
(2)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –20 mAI
OK
Output clamp current V
O
< 0 –20 mAI
OK
Input/output clamp current V
O
< 0 or V
O
> V
CC
–20 mAI
OL
Continuous output low current V
O
= 0 to V
CC
50 mAI
OH
Continuous output high current V
O
= 0 to V
CC
–4 mAContinuous current through V
CC
or GND ±100 mADB package 63DBQ package 61DGV package 86θ
JA
Package thermal impedance
(3)
DW package 46 °C/WPW package 88RGE package 53RHL package 43T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.5 5.5 VV
IH
High-level input voltage 0.7 ×V
CC
V
CC
+ 0.5 VV
IL
Low-level input voltage –0.5 0.3 ×V
CC
VI
OH
P-port high-level output current –1 mAI
OHT
P-port transient pullup current –10 mAI
OL
P-port low-level output current 25 mAT
A
Operating free-air temperature –40 85 °C
8
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Electrical Characteristics
I
2
C Interface Timing Requirements
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= –18 mA 2.5 V to 5.5 V –1.2 VV
POR
Power-on reset voltage
(2)
V
I
= V
CC
or GND, I
O
= 0 V
POR
1.2 1.8 VI
OH
P port V
O
= GND 2.5 V to 5.5 V –30 –300 µAI
OHT
P-port transient pullup current High during ACK, V
OH
= GND 2.5 V –0.5 –1 mASDA V
OL
= 0.4 V 3V
OL
= 0.4 V 5 15I
OL
P port 2.5 V to 5.5 V mAV
OL
= 1 V 10 25INT V
OL
= 0.4 V 1.6SCL, SDA ±5I
I
V
I
= V
CC
or GND 2.5 V to 5.5 V µAA0, A1, A2 ±1I
IHL
P port V
I
≥V
CC
or V
I
≤GND 2.5 V to 5.5 V ±400 µA5.5 V 100 200V
I
= V
CC
or GND, I
O
= 0,Operating mode 3.6 V 30 75f
scl
= 400 kHz
2.7 V 20 50I
CC
µA5.5 V 2.5 10Standby mode V
I
= V
CC
or GND, I
O
= 0, f
scl
= 0 kHz 3.6 V 2.5 102.7 V 2.5 10One input at V
CC
– 0.6 V,∆I
CC
Supply current increase 2.5 V to 5.5 V 200 µAOther inputs at V
CC
or GNDC
I
SCL V
I
= V
CC
or GND 2.5 V to 5.5 V 3 7 pFSDA 3 7C
io
V
IO
= V
CC
or GND 2.5 V to 5.5 V pFP port 4 10
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V
CC
) and T
A
= 25 °C.(2) The power-on reset circuit resets the I
2
C bus logic with V
CC
< V
POR
and sets all I/Os to logic high (with current source to V
CC
).
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6 )
MIN MAX UNIT
f
scl
I
2
C clock frequency 400 kHzt
sch
I
2
C clock high time 0.6 µst
scl
I
2
C clock low time 1.3 µst
sp
I
2
C spike time 50 nst
sds
I
2
C serial data setup time 100 nst
sdh
I
2
C serial data hold time 0 nst
icr
I
2
C input rise time 20 + 0.1C
b
(1)
300 nst
icf
I
2
C input fall time 20 + 0.1C
b
(1)
300 nst
ocf
I
2
C output fall time 10-pF to 400-pF bus 300 nst
buf
I
2
C bus free time between Stop and Start 1.3 µst
sts
I
2
C start or repeated Start condition setup 0.6 µst
sth
I
2
C start or repeated Start condition hold 0.6 µst
sps
I
2
C Stop condition setup 0.6 µst
vd
Valid-data time SCL low to SDA output valid 1.2 µsC
b
I
2
C bus capacitive load 400 pF
(1) C
b
= total bus capacitance of one bus line in pF
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Switching Characteristics
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted) (see Figure 7 and Figure 8 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
t
iv
Interrupt valid time P port INT 4 µst
ir
Interrupt reset delay time SCL INT 4 µst
pv
Output data valid SCL P port 4 µst
su
Input data setup time P port SCL 0 µst
h
Input data hold time P port SCL 4 µs
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TYPICAL OPERATING CHARACTERISTICS
0
5
10
15
20
25
30
35
40
45
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
5
10
15
20
25
30
35
40
45
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
100
200
300
400
500
600
−50 −25 0 25 50 75 100 125
0
5
10
15
20
25
30
35
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0
5
10
15
20
25
0.0 0.1 0.2 0.3 0.4 0.5 0.6
I/O Sink Current
vs Output Low Voltage
VCC = 3.3 V
TA = 25_C
TA = 85_C
TA = −40_C
VOL (V)
0
2
4
6
8
10
12
14
16
18
20
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0
10
20
30
40
50
60
70
80
90
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
10
20
30
40
50
60
70
80
90
−50 −25 0 25 50 75 100 125
0
20
40
60
80
100
120
−50 −25 0 25 50 75 100 125
Supply Current
vs Temperature
Temperature (5C)
Supply Current (mA)
fSCL = 400 kHz
All I/Os unloaded
Temperature (5C)
Supply Current (mA)
Supply Current
vs Supply Voltage
Supply Current (mA)
I/O Sink Current
vs Output Low Voltage I/O Sink Current
vs Output Low Voltage
Temperature (5C)
I/O Source Current
vs Output High Voltage I/O Source Current
vs Output High Voltage
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 2.5 V
SCL = VCC
All I/Os unloaded fSCL = 400 kHz
All I/Os unloaded
VCC = 2.5 V VCC = 5 V
TA = −40_C
TA = 25_C
VCC = 3.3 V
TA = −40_C
TA = 85_C
TA = −40_C
TA = 25_C
TA = 85_C
TA = −40_C
TA = 25_C
TA = 85_C
TA = 25_C
TA = 85_C
VCC = 5 V, ISINK = 10 mA
VCC = 2.5 V, ISINK = 10 mA
VCC = 5 V,
ISINK = 1 mA
VCC = 2.5 V,
ISINK = 1 mA
VCC − VOH (V) VCC − VOH (V)
VOL (V)
ISOURCE (mA)
ISOURCE (mA)
VOL (mV)
ISINK (mA)
ISINK (mA)
Standby Supply Current
vs Temperature
I/O Output Low Voltage
vs Temperature
VCC = 5 V
VCC = 3.3 V
VCC = 2.5 V
Supply Voltage (V)
Vol (V)
ISINK (mA)
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
T
A
= 25 °C (unless otherwise noted)
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0
50
100
150
200
250
300
350
−50 −25 0 25 50 75 100 125
0
5
10
15
20
25
30
35
40
45
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Temperature (5C)
I/O Source Current
vs Output High Voltage I/O High Voltage
vs Temperature
VCC = 5 V TA = −40_C
TA = 85_C
TA = 25_C
VCC − VOH (V)
VCC = 5 V
ISOURCE (mA)
VCC − VOH (V)
VCC = 3.3 V
VCC = 2.5 V
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
12
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PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
VCC
CL = 50 pF
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 10
(LSB)
Stop
Condition
(P)
3 Bytes for Complete Device
Programming
SDA LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDA
0.7 × VCC
0.3 × VCC
0.7 × VCC
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 07
(MSB)
Address
Bit 1
Address
Bit 6
BYTE DESCRIPTION
1
2, 3
I2C address
P-port data
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
Figure 6. I
2
C Interface Load Circuit and Voltage Waveforms
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A
A
A
A
S 0 1 0 0 A1
A2A01Data 1 1 PData 3
Start
Condition 16 Bits
(2 Data Bytes)
From Port Data From PortSlave Address (PCF8575)
R/W
87654321
tir
tir
tsps
tiv
Address Data 1 Data 3
INT
Data
Into
Port
B
B
A
A
PnINT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
INT SCL
View B−BView A−A
tiv
RL = 4.7 kΩ
VCC
CL = 100 pF
INTERRUPT LOAD CONFIGURATION
DUT INT
ACK
From Slave ACK
From Slave
Data 2
Data 2
PCF8575
REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Interrupt Load Circuit and Voltage Waveforms
14
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P00 A 0.7 × VCC
0.3 × VCC
SCL P17
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv
Slave
ACK
Unstable
Data
Last Stable Bit
SDA
Pn
Pn
Write-Mode Timing (R/W = 0)
P00 A 0.7 × VCC
0.3 × VCC
SCL P17
0.7 × VCC
0.3 × VCC
tsu th
Read-Mode Timing (R/W = 1)
DUT
GND
CL = 100 pF
RL = 4.7 kΩ
VCC
SDA LOAD CONFIGURATION INTERRUPT LOAD CONFIGURATION
INT
GND
CL = 50 pF
RL = 1 kΩ
VCC
DUT SDA DUT
GND
CL = 100 pF
P-PORT LOAD CONFIGURATION
Pn
PCF8575REMOTE 16-BIT I
2
C AND SMBus I/O EXPANDERWITH INTERRUPT OUTPUT
SCPS121C – JANUARY 2005 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. P-Port Load Circuits and Voltage Waveforms
15Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCF8575DB PREVIEW SSOP DB 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575DBQR ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCF8575DBQRE4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCF8575DBQRG4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCF8575DBR ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575DBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575DGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575DW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575DWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575PW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575PWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8575RGER ACTIVE QFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1YEAR
PCF8575RHLR PREVIEW QFN RHL 24 1000 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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