FQD5P20 / FQU5P20
FQD5P20 / FQU5P20
200V P-Channel MOSFET
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.
Features
-3.7A, -200V, RDS(on) = 1.4 @VGS = -10 V
Low gate charge ( typical 10 nC)
Low Crss ( typical 12 pF)
Fast switching
100% avalanche tested
Absolute Maximu m Ratings TC = 25°C unless otherwise noted
Thermal Characteristi cs
Symbol Parameter FQD5P20 / FQU5P20 Units
VDSS Drain-Source Voltage -200 V
IDDrain Current - Continuous (TC = 25°C) -3.7 A
- Continuous (TC = 100°C) -2.34 A
IDM Drain Current - Pulsed (Note 1) -14.8 A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 330 mJ
IAR Avalanche Current (Note 1) -3.7 A
EAR Repetitive Avalanche Energy (Note 1) 4.5 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) -5.5 V/ns
PDPower Dissipation (TA = 25°C) * 2.5 W
Power Dissipation (TC = 25°C) 45 W
- Derate above 25°C 0.36 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,
1/8" from case for 5 seconds 300 °C
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 2.78 °C/W
RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W
* When mounted on the minimum pad size recommended (PCB Mount)
I-PAK
FQU Series
D-P AK
FQD Series GS
D
GS
D
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S
D
G
October 2008
QFET
®
RoHS Compliant
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
Elerical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 36.2mH, IAS = -3.7A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD -4.8A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
Symbol Parame ter Test Condit ions Min Typ Max Unit s
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = -250 µA-200 -- -- V
BVDSS
/ TJ
Breakdown Voltage Temperature
Coefficient ID = -250 µA, Referenced to 25°C -- -0.17 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = -200 V, VGS = 0 V -- -- -1 µA
VDS = -160 V, TC = 125°C -- -- -10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = -30 V, VDS = 0 V -- -- -100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = 30 V, VDS = 0 V -- -- 100 nA
On Characteri st ics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA-3.0 -- -5.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = -10 V, ID = -1.85 A -- 1.1 1.4
gFS Forward Transconductance VDS = -40 V, ID = -1.85 A -- 2.2 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
-- 330 430 pF
Coss Output Capacitance -- 75 98 pF
Crss Reverse Transfer Capacitance -- 12 15 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = -100 V, ID = -4.8 A,
RG = 25
-- 9 28 ns
trTurn-On Rise Time -- 70 150 ns
td(off) Turn-Off D e l a y Time -- 12 35 ns
tfTurn -Off Fall Time -- 2 5 60 ns
QgTotal Gate Cha rge VDS = -160 V, ID = -4.8 A,
VGS = -10 V
-- 10 13 nC
Qgs Gate-Source Charge -- 2.8 -- nC
Qgd Gate-Drain Charge -- 5.2 -- nC
Drain-Source Diode Character istics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- -3.7 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- -14.8 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, I S = -3.7 A -- -- -5.0 V
trr Reverse Recovery Time VGS = 0 V, I S = -4.8 A,
dIF / dt = 100 A/µs
-- 175 -- ns
Qrr Reverse Recovery Charge -- 1.07 -- µC
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
0.0 0.5 1.0 1.5 2.0 2.5 3.0
10-1
100
101
150 Notes :
1. VGS = 0V
2. 250μ
s Pulse Test
25
-IDR , R ev e rs e D ra in Curren t [A ]
-VSD , Source-Drain Voltage [V]
246810
10-1
100
101
150
25
-55
Notes :
1. VDS = -40V
2. 250μ
s Pulse Test
-ID , Drain Current [A]
-VGS , Gate-Source Voltage [V]
10-1 100101
10-2
10-1
100
101 VGS
Top : -15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bo ttom : -5.5 V
Notes :
1. 250μ
s Pulse Test
2. TC = 25
-ID, Drain Current [A]
-VDS, Drain-Source Voltage [V]
036912
0.0
0.6
1.2
1.8
2.4
3.0
N o te : TJ = 25
VGS = - 20V
VGS = - 10V
RDS(on) [],
Drain-Source On-Resistance
-ID , Dra in Cu rren t [A]
024681012
0
2
4
6
8
10
12
VDS = -100V
VDS = -40V
VDS = -160V
Note : ID = -4.8 A
-VGS , G ate-Source Voltage [V]
QG, To tal Ga te Charge [nC]
10-1 100101
0
150
300
450
600
750 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Notes :
1. VGS = 0 V
2. f = 1 MH z
Crss
Coss
Ciss
Capacitance [pF]
-VDS, Drain-Source Voltage [V]
Figure 5. C apacitance C haracterist ics Figure 6. Gate Charge Characteristics
Figu re 3. On-Res i stance Variation vs.
Drain Current and Gate Voltage Figure 4. Body Diode Fo rward Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character ist ic s
Typical Characteristics
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
10-5 10-4 10-3 10-2 10-1 100101
10-1
100
No te s :
1 . ZθJC(t) = 2.78 /W M a x .
2 . D u ty F a c t o r, D = t1/t2
3 . TJM - T C = PDM * Z θJC(t)
single puls e
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC
(t), Thermal Response
t1, Sq u a re W a ve P u lse Du ra tio n [s ec ]
25 50 75 100 125 150
0
1
2
3
4
-ID, Drain Current [A]
TC, Case Temperature [
]
100101102
10-1
100
101
DC 10 m s
1 m s
100 µs
Operation in This Area
is Limited by R DS(on)
Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
-ID, Drain Current [A]
-VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
Notes :
1. VGS = -10 V
2. ID = -2.4 A
RDS(ON) , (Norm alized)
Drain-Source On-Resistance
TJ, Junction Temperature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes :
1 . VGS = 0 V
2 . ID = -250 μ
A
-BV DSS , (No rma liz e d )
Drain-Sou rce Breakdow n V oltage
TJ, Junction Tempe rature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figu re 7. Br ea kdown Voltage Variatio n
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Respons e Cur ve
t1
PDM
t2
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
Charge
VGS
-10V Qg
Qgs Qgd
-3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
VGS
-10V Qg
Qgs Qgd
-3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
VDS
VGS 10%
90%
td(on) tr
ton toff
td(off) tf
VDD
-10V
VDS RL
DUT
RG
VGS
VDS
VGS 10%
90%
td(on) tr
ton toff
td(off) tf
VDD
-10V
VDS RL
DUT
RG
VGS
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
-10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
-10V DUT
RG
LL
ID
ID
t p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
Peak Diode Recovery dv/dt Tes t Ci rcuit & Wavefo r m s
DUT
VDS
+
_
Driver
RGCompliment of DUT
(N-Channel)
VGS dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGCompliment of DUT
(N-Channel)
VGS dv/dt controlled by RG
•I
SD con troll ed by pulse period
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
Dimensions in Millimeters
Mechanical Dimensions
D - PAK
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
6.60 ±0.20
0.76 ±0.10
MAX0.96
2.30TYP
[2.30±0.20] 2.30TYP
[2.30±0.20]
0.60 ±0.20
0.80 ±0.10
1.80 ±0.20
9.30 ±0.30
16.10 ±0.30
6.10 ±0.20
0.70 ±0.20
5.34 ±0.20
0.50 ±0.10
0.50 ±0.10
2.30 ±0.20
(0.50) (0.50)(4.34)
IPAK
Mechanical Dimensions
Dimensions in Millimeters
I - PAK
©2008 Fairchild Semiconductor Internationa Rev. A1, October 2008
FQD5P20 / FQU5P20
FQD5P20 / FQU5P20 Rev. A1www.fairchildsemi.com
Rev. I37
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