Automotive Power
Data Sheet
Rev. 1.0, 2010-02-18
TLE7235SE
SPI Driver for Enhanced Relay Control
SPIDER
SPI Driver for Enhanced Relay Control
Data Sheet 2 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Limp Home Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Channels 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Inductive Output Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.6 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Over Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 Over Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5 Loss of Vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Diagnostic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2 Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.4 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents
PG-DSO-20-45
Type Package Marking
TLE7235SE PG-DSO-20-45 TLE7235SE
Data Sheet 3 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
TLE7235SE
1 Overview
Features
• 8 bit SPI for diagnostics and control, providing daisy chain capability
• Very wide range for digital supply voltage
• Two configurable input pins offer complete flexibility for
PWM operation
• Stable behavior at under voltage
• Green Product (RoHS compliant)
•AEC Qualified
Description
The TLE7235SE is an eight channel high-side and low-side power switch in PG-DSO-20-45 package providing
embedded protective functions. It is especially designed for standard relays and LEDs in automotive applications.
The output stages incorporate two low-side, four high-side and two auto configuring high-side or low-side
switches.
A serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the load. For direct control,
there are two input pins available.
The TLE7235SE provides a micro controller fail-safe function which is activated via a high signal at the limp home
input pin. There is a power supply integrated in the device to ensure this functionality even without digital supply
voltage.
The power transistors are built by N-channel power MOSFETs. The device is monolithically integrated in
Smart Power Technology.
Data Sheet 4 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Overview
Protective Functions
• Over load and short circuit protection
• Thermal shutdown
• Electrostatic discharge protection (ESD)
Diagnostic Functions
• Latched diagnostic information via SPI
• Open load detection in OFF-state
• Over load detection in ON-state
• Over temperature
Limp Home / Fail-Safe Functions
• Limp home activation via pin LHI
• Limp home configuration via input pins
Applications
• Especially designed for driving relays and LEDs in automotive applications
• All types of resistive and inductive loads
• Suitable to switch 5 V power supply lines by auto configuring channels
Table 1 Product Summary
Operating range power supply voltage Vbb 5.5 … 28 V
Digital supply voltage VDD 3.0 … 5.5 V
Typical On-State resistance at 25 °CRDS(ON)
high-side: 2 channels (Relay) 0.85 Ω
high-side: 2 channels (Generic, LED) 1.6 Ω
auto configuring: 2 channels (Relay, Supplies) 0.85 Ω
low-side: 2 channels (Relay) 0.85 Ω
Nominal load current (all channels active) IL(nom, min)
Relay 280 mA
LED, Generic 140 mA
Over load switch off threshold IDS(OVL, min) 500 mA
Output leakage current per channel at 25 °CIDS(OFF, max) 1µA
Drain to source clamping voltage VDS(CL, min) 41 V
Source to ground clamping voltage Vbb(CL, max) -40 V
SPI clock frequency fSCLK(max) 5MHz
SPI Driver for Enhanced Relay Control
TLE7235SE
Overview
Data Sheet 5 Rev. 1.0, 2010-02-18
Detailed Description
The TLE7235SE is an eight channel high-side and low-side relay switch providing embedded protective functions.
The output stages incorporate two low-side switches (0.85 Ω per channel), four high-side switches (two channels
with 0.85 Ω and two channels with 1.6 Ω) and two auto-configuring high-side or low-side switches (0.85 Ω per
channel). The auto-configuring switches can be utilized in high-side or low-side configuration just by connecting
the load accordingly. They are also suitable to switch a 5 V supply line in high-side configuration. Protective and
diagnostic functions adjust automatically to the chosen configuration.
The 8 bit serial peripheral interface (SPI) is utilized for control and diagnosis of the device and the loads. The SPI
interface provides daisy chain capability in order to assemble multiple devices in one SPI chain by using the same
number of micro-controller pins.
Furthermore, the TLE7235SE is equipped with two input pins that can be individually routed to the output control
of each channel thus offering complete flexibility in design and PCB-layout. The input multiplexer is controlled via
SPI.
In limp home mode (fail-safe mode), the input pins are directly routed to the configurable output channels 4 and
5. The limp home mode operates independently of digital power supply and is activated via pin LHI.
The device provides full diagnosis of the load via open load, over load and short circuit detection. SPI diagnosis
flags indicate latched fault conditions that may have occurred.
Each output stage is protected against short circuit. In case of over load, the affected channel switches off. There
are temperature sensors available for each channel to protect the device against over temperature.
The device protects itself with a built in reverse polarity protection which prohibits intrinsic current flow through the
logic during reverse polarity. However the output stages still incorporate a reverse diode where current can flow
through during reverse polarity.
The power transistors are built by N-channel power MOSFETs. The inputs are ground referenced CMOS
compatible. The device is monolithically integrated in Smart Power Technology.
Data Sheet 6 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Block Diagram
2 Block Diagram
Figure 1 Block Diagram
Overview_5.emf
reverse polarity protection
CS
SI
SCLK
SO
control,
diagnostic
and
protective
functions
diagnosis register
input register
input mux
IN1
VDD
SPI stand-by
control
IN2
limp home
mode activation
OUT1
OUT0
LHI
power supply
open load
detection
temperature
sensor
high -s ide
gate control
short circuit
detection
low-side
gate control
auto
configuring
gate control
OUT3
OUT2
D4
D5
VBB
GND
S4
S5
OUT7
OUT6
SPI Driver for Enhanced Relay Control
TLE7235SE
Block Diagram
Data Sheet 7 Rev. 1.0, 2010-02-18
2.1 Terms
Figure 2 shows all terms used in this data sheet.
Figure 2 Terms
In all tables of the electrical characteristics is valid:
Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is
valid for VDS0 … VDS7). In order to make the description of output currents easier, the load current IOut is equivalent
to the drain current IOUT_D in low-side configuration and the source current IOUT_S in high-side configuration.
All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. ICR01.INX1). In SPI register description,
the values in bold letters (e.g. 0) are default values.
VCS
VSC L K
VSI ISO
SO
ISC L K
ISI
SCLK
SI
ICS
CS
VSO GND
IGND
VBB
IS
VDD
IDD
IN2
IN1
IIN 2
IIN 1
VIN 1
VDD
VIN 2
LHI
ILHI
VLHI
Terms_5.emf
OUT0
OUT1
OUT2
OUT3
Vbat
VDS3
VDS1
VDS2
VDS0
VDS7
VDS6
D4
OUT6
OUT7
S5
VS5
VS4
VDS4
VS0
VS1
VS2
VS3
D5
S4
VDS5 VD5
VD4
IOUT_S1
IOUT_S3
IOUT_S0
IOUT_S2
IOUT_S5
IOUT_D7
IOUT_D4
IOUT_D6
IOUT_D5
IOUT_S4
TLE7235SE
Data Sheet 8 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
l
Figure 3 Pin Configuration PG-DSO20-45
3.2 Pin Definitions and Functions
Pin Symbol I/O Function
Power Supply
18 VDD - Digital power supply
1 VBB - Power supply
10 GND - Digital, analog and power ground
Power Stages
20 OUT0 O Source of high side power transistor channel 0
2 OUT1 O Source of high side power transistor channel 1
19 OUT2 O Source of high side power transistor channel 2
3 OUT3 O Source of high side power transistor channel 3
13 D4 O Drain of auto configuring power transistor 4
11 S4 O Source of auto configuring power transistor 4
7 D5 O Drain of auto configuring power transistor 5
9 S5 O Source of auto configuring power transistor 5
12 OUT6 O Drain of low side power transistor channel 6
8 OUT7 O Drain of low side power transistor channel 7
Inputs
4 LHI I Limp home activation input pin (pull down)
(top view )
2
3
4
5
6
7
8
9
OUT3
OUT1
OUT7
IN1
IN2
D5
S5
P-DSO20-45.emf
10
GND
1
VBB
19
18
17
16
15
14
13
12
VDD
OUT2
D4
SCLK
SI
SO
OUT6
11
S4
20
OUT0
CS
LHI
SPI Driver for Enhanced Relay Control
TLE7235SE
Pin Configuration
Data Sheet 9 Rev. 1.0, 2010-02-18
5 IN1 I Input multiplexer input 1 pin (pull down)
6 IN2 I Input multiplexer input 2 pin (pull down)
SPI
17 CS I SPI Chip select (pull up)
16 SCLK I Serial clock
15 SI I Serial data in
14 SO O Serial data out
Pin Symbol I/O Function
Data Sheet 10 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Electrical Characteristics
4 Electrical Characteristics
4.1 Absolute Maximum Ratings 1)
Stresses above the ones listed here may affect device reliability or may cause permanent damage to the device.
The values below are not considering combinations of different maximum conditions at one time
1) not subject to production test
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Absolute Maximum Ratings1)
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. max.
Power Supply
4.1.1 Power supply voltage Vbb -40 40 V -40V max. 2 minutes
4.1.2 Digital supply voltage VDD -0.3 5.5 V –
4.1.3 Power supply voltage for short circuit
protection (single pulse)
Vbat(SC) 028V–
Power Stages
4.1.4 Load current ILA–
channel 0, 1, 4, 5, 6, 7 -0.5 0.5
channel 2, 3 -0.25 0.25
4.1.5 Voltage at power transistor VDS –41V–
4.1.6 Power transistor’s source voltage VOut_S -16 – V –
4.1.7 Power transistor’s drain voltage VOut_D –41V–
4.1.8 Max. energy dissipation one channel single
pulse for ch. 0, 1, 4, 5, 6, 7
EAS mJ 2)
–65 Tj(0) = 105 °C
ID(0) = 0.35 A
–50 Tj(0) = 150 °C
ID(0)= 0.250 A
4.1.9 Maximum energy dissipation one channel
repetitive pulses for ch. 0, 1, 4, 5, 6, 7
EAR mJ 2)
1·10
4 cycles – 18 Tj(0) = 105 °C
ID(0) = 0.250 A
1·10
6 cycles – 13 Tj(0) = 105 °C
ID(0) = 0.220 A
4.1.10 Max. energy dissipation one channel single
pulse for ch. 2,3
EAS mJ 2)
–50 Tj(0) = 105 °C
ID(0) = 0.250 A
–30 Tj(0) = 150 °C
ID(0)= 0.250 A
SPI Driver for Enhanced Relay Control
TLE7235SE
Electrical Characteristics
Data Sheet 11 Rev. 1.0, 2010-02-18
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.1.11 Maximum energy dissipation one channel
repetitive pulses for ch. 2,3
EAR mJ 2)
1·10
4 cycles – 12 Tj(0) = 105 °C
ID(0) = 0.180 A
1·10
6 cycles – 11 Tj(0) = 105 °C
ID(0) = 0.180 A
Logic Pins
4.1.12 Voltage at input pins VIN -0.3 VDD + 0.3 V 3)
4.1.13 Voltage at LHI pin VLHI -0.3 5.5 V–
4.1.14 Voltage at chip select pin VCS -0.3 VDD + 0.3 V 3)
4.1.15 Voltage at serial clock pin VSCLK -0.3 VDD + 0.3 V 3)
4.1.16 Voltage at serial input pin VSI -0.3 VDD + 0.3 V 3)
4.1.17 Voltage at serial output pin VSO -0.3 VDD + 0.3 V 3)
Temperatures
4.1.18 Junction Temperature Tj-40 150 °C–
4.1.19 Storage Temperature Tstg -55 150 °C–
ESD Susceptibility
4.1.20 ESD susceptibility on all pins VESD -2 2 kV HBM4)
1) not subject to production test
2) Pulse shape represents inductive switch off: IL(t) = IL(0) * (1 - t/tpulse); 0 < t < tpulse
3) VDD + 0.3 V < 5.5 V
4) ESD susceptibility, HBM according to EIA/JESD 22-A114
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Supply Voltage Range for
Nominal Operation
Vbb(nom) 916V–
4.2.2 upper Supply Voltage Range for
Extended Operation
Vbb(ext),up 16 28 V Parameter
Deviations possible
4.2.3 lower Supply Voltage Range for
Extended Operation
Vbb(ext),low 5.5 9 V Parameter
Deviations possible
4.2.4 Junction Temperature Tj-40 150 °C–
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Absolute Maximum Ratings1)
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. max.
Data Sheet 12 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Electrical Characteristics
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Thermal Resistance1)
1) Not subject to production test
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Case, bottom RthJC,back ––25K/W
2)
2) Specified RthJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).
Ta = 85 °C. Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
4.3.2 Junction to Case, top RthJC,top ––30K/W
2)
4.3.3 Junction to Pin (5,6,15 or 16) RthJPin ––23K/W
2)
4.3.4 Junction to Ambient
(1s0p, min. footprint)
RthJA,min –80–K/W
3)
3) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70 µm thickness.
Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
4.3.5 Junction to Ambient
(1s0p+300mm2Cu)
RthJA,300 –65–K/W
4)
4) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300mm2
and 70 µm thickness. Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
4.3.6 Junction to Ambient
(1s0p+600mm2Cu)
RthJA,600 –60–K/W
5)
5) Specified RthJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm2
and 70 µm thickness. Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
4.3.7 Junction to Ambient (2s2p) RthJA,2s2p –52–K/W
6)
6) Specified RthJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Supply
Data Sheet 13 Rev. 1.0, 2010-02-18
5 Power Supply
The TLE7235SE is supplied by two supply voltages Vbb and VDD. The Vbb supply line is connected to a battery feed
and used by the power switches and by an integrated power supply for the register banks. There is an under
voltage reset function implemented for the Vbb power supply, which is triggered if Vbb is below the undervoltage
threshold. After start-up of the power supply, all SPI registers are reset to their default values and the device is in
sleep mode (standby). Sending the SPI command CMD.WAKE = 1 switches the device to operation mode (ON),
while a command CMD.STB = 1 send the device to sleep mode (standby) again. Please note that the device
needs the time twu(Sleep) to initialize itself. No SPI command should be send after changing the power state via
CMD.WAKE = 1 before this time is elapsed. A SPI frame send during twu(Sleep) could be ignored.
The VDD supply line is used to power the circuitry related to the SPI shift register and for driving the SO line. As a
result, the daisy chain function is available as soon as VDD is provided in the specified range independent of Vbb.
A capacitor between pins VDD and GND is recommended (especially in case of EMI disturbances).
Please see Figure 14 “Application Diagram” on Page 35 for details.
5.1 Operation Modes
There is a limp home functionality implemented in the TLE7235SE, which is activated via pin LHI. Please refer to
Section 5.2 for details.
The device provides a sleep mode (stand by) to minimize current consumption, which also resets the register
banks. It is entered and left by dedicated SPI commands . The sleep mode current is minimized only when limp
home is inactive. After limp home, the device enters sleep mode automatically.
The following table shows the operation modes depending on Vbb, VDD and the limp home input signal LHI.
5.2 Limp Home Mode
The TLE7235SE offers the capability of driving dedicated channels during fail-safe operation of the system. This
limp home mode is activated by a high signal at pin LHI. In limp home mode, the SPI registers are reset and the
input pins are directly routed to the auto configuring channels (channel 4 and 5). As a result, the limp home
operation can be chosen for high-side and low-side driven loads. Due to the integrated power supply, limp home
operation is independent of digital power supply VDD. In case of stand-by, a high signal at pin LHI will wake up the
device. After limp home operation, the device enters sleep mode in any case.
5.3 Reset
There are several reset trigger implemented in the device. A reset switches off all channels and sets the registers
to default values. After any kind of reset, the transmission error flag (TER) is set and the device is in sleep mode.
Under Voltage Reset:
Operation Modes
VBB 0V0V0V12V12V12V12V
VDD 0V5V5V0V0V5V5V
LHI X 0V 5V 0V 5V 0V 5V
Switches operating - - - ✓✓✓✓
Limp Home - - - - ✓ - ✓
SPI & daisy-chain - ✓ ✓ --✓ ✓
Register Banks reset reset reset ✓ reset ✓ reset
Diagnostic functions - - - ✓ - ✓ -
Data Sheet 14 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Supply
During this device condition a read on SPI delivers the Standard Diagnostic Frame with a TER flag, if VDD is above
the under voltage threshold already, if not SPI is not working.
This under voltage reset is released when VDD and Vbb supply voltage levels are above under voltage threshold.
Reset Command: There is a reset command available to reset all register bits of the register bank and the
diagnosis registers. As soon as CMD.RST = 1, a reset is triggered.
Limp Home Mode: In limp home mode, the SPI write-registers are reset. The SPI interface is operating normally,
so the limp home bit LHI as well as the diagnosis flags can be read, but no command is accepted until the device
leaves the Limp home operation.
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Supply
Data Sheet 15 Rev. 1.0, 2010-02-18
5.4 Electrical Characteristics
Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature.
Typical values show the typical parameters expected at Vbb = 13.5 V, VDD = 5.0 V, Tj = 25 °C.
Unless otherwise specified:
VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Power Supply Vbb
5.4.1 Supply Voltage Range for
Nominal Operation
Vbb(nom) 916V–
5.4.2 upper Supply Voltage Range for
Extended Operation
Vbb(ext),up 16 28 V Parameter Deviations possible
5.4.3 lower Supply Voltage Range for
Extended Operation
Vbb(ext),low 5.5 9 V RL = 80 Ω
VDS < 1.5 V
Parameter Deviations possible
5.4.4 Under voltage reset threshold Vbb(UV) ––5.5 VVDD= 0V
5.4.5 Operating current drawn from Vbb IS(ON) ––15mA
1) Vbb = 16 V
––12mA
Vbb = 16 V
all diagnosis off
5.4.6 Sleep mode operating current with
disconnected loads (stand by)
IS(Sleep)
––10
µAVbb = 16 V
VLHI = 0 V ; AWK= 0
Tj = 25 °C1)
1) Not subject to production test, specified by design.
––13 Tj = 85 °C 1)
––20 Tj = 150 °C
Digital Power Supply VDD
5.4.7 Logic supply voltage VDD 3.0 – 5.5 V
5.4.8 Under voltage reset threshold VDD(PO) ––3.0V
5.4.9 Logic supply current IDD(ON) ––0.4mAfSCLK = 0 Hz
AWK= 1
VCS = 0V
5.4.10 Logic supply current during VBB
dropout
IDD(DO) –35mA
1) fSCLK = 0 Hz
Vbb < Vbb(UV)
AWK= 1
VCS = 0V
5.4.11 Logic supply sleep mode current IDD(Sleep)
––20
µAVCS = VDD
AWK = 0
Tj = 25 °C1)
––20 Tj = 85 °C 1)
––40 Tj = 150 °C
Timings
5.4.12 Sleep mode wake-up time twu(Sleep) – – 200 µs1)
5.4.13 Vbb under voltage reset delay time tbb(UVR) ––1µs1)
5.4.14 VDD under voltage reset delay time tDD(UVR) ––1µs1)
Data Sheet 16 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Stages
6 Power Stages
The TLE7235SE is an eight channel high-side and low-side relay switch. The power stages are built by N-channel
vertical power MOSFET transistors. The gates of the high-side switches are controlled by charge pumps.
6.1 Input Circuit
There are two input pins available at TLE7235SE, which can be configured to be used for control of the output
stages. The INXn parameter of the input configuration register provide following possibilities:
• channel is switched off
• channel is switched according to signal level at input pin IN1
• channel is switched according to signal level at input pin IN2
• channel is switched on
Figure 4 shows the input circuit of TLE7235SE.
Figure 4 Input Multiplexer
The current sink to ground ensures that the channels switch off in case of open input pin. The zener diode protects
the input circuit against ESD pulses.
6.2 Channels 4 and 5
The TLE7235SE provides two auto-configuring high-side or low-side switches (channels 4 and 5). They adjust the
diagnostic and protective functions according their potentials at drain and source automatically.
In high-side configuration, the load is connected between ground and source of the power transistors (S4 or S5).
The drain of the power transistors (D4 and D5) can be connected to any potential between GND-pin potential and
VBB-pin potential. When the drain is connected to VBB, the channel behave like the other high side channels. The
drain can also be connected to a 5 V power supply and the source pin will be utilized as switched 5 V supply line.
In low-side configuration, the source of the power transistors are to be connected to GND.
The configuration can be chosen for each of these channels individually, so it is feasible to connect one channel
in low-side and the other in high-side configuration.
Channel 7
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
IN1
IIN1
IN2
IIN2
Channel 0
1
0
INX0
InputLogic.emf
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Stages
Data Sheet 17 Rev. 1.0, 2010-02-18
6.3 Inductive Output Clamp
When switching off inductive loads with low-side switches, the potential at pin OUT rises to VDS(CL) potential,
because the inductance intends to continue driving the current. For the high-side channels, the potential at pin
OUT drops below ground potential to VS(CL). The voltage clamping is necessary to prevent destruction of the
device, see Figure 5 for details. Nevertheless, the maximum allowed load inductance is limited by the max.
clamping energy EAR see electrical characteristics “EAR” on Page 10.
Figure 5 Output Clamp Implementation
Maximum Load Inductance
During demagnetization of inductive loads, energy has to be dissipated in the TLE7235SE. This energy can be
calculated with following equations:
Low-side (1)
High-side (2)
These equations simplify under the assumption of RL = 0:
Low-side (3)
High-side (4)
The maximum energy, which is converted into heat, is limited by the thermal design of the component.
Out put Clamp. emf
high side
channel
GND
V
bb
L,
R
L
V
S
I
S
VBB
OUT
low side
channel L,
R
L
I
D
OUT
V
D
V
S( CL )
V
DS( CL )
GND
V
DS( CL )
I
L
I
L
EV
DS(CL)
Vbb V–DS(CL)
RL
-----------------------------------ln⋅1RLIL
⋅
Vbb V–DS(CL)
-----------------------------------–
IL
+L
RL
------
⋅⋅=
EV
bb VS(CL)
–()
VS(CL)
RL
----------------ln⋅1RLIL
⋅
VS(CL)
----------------–
IL
+L
RL
------
⋅⋅=
E1
2
---LIL
21Vbb
Vbb V–DS(CL)
-----------------------------------–
⋅=
E1
2
---LIL
21Vbb
VS(CL)
----------------–
⋅=
Data Sheet 18 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Stages
6.4 Timing Diagrams
The power transistors are switched on and off with a dedicated slope via the INX bits of the serial peripheral
interface (SPI). The switching times tON and tOFF are designed equally.
Figure 6 Switching a Resistive Load
In input mode, a high signal at the input pin is equivalent to a SPI ON command and a low signal to SPI OFF
command respectively. Please refer to Section 9.3 for details on SPI protocol.
IN
V
DS
t
SwitchOn.emf
t
ON
t
OFF
t
20%
80%
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Stages
Data Sheet 19 Rev. 1.0, 2010-02-18
6.5 Electrical Characteristics
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Output Characteristics
6.5.1 On-State resistance RDS(ON) Ω
channel 0, 1, 4, 5, 6, 7 – 0.85 – IL = 220 mA
Tj = 25 °C
–1.41.8 Tj = 150 °C
channel 2, 3 – 1.6 – IL = 110 mA
Tj = 25 °C
–2.63.8 Tj = 150 °C
6.5.2 Nominal load current IOut(nom) mA all channels on
Ta = 100 °C
Tj,max = 150 °C
based on Rthja
channel 0, 1, 4, 5, 6, 7 280 410 – 1)
1) Not subject to production test, specified by design.
channel 2, 3 140 205 – 1)
6.5.3 Output leakage current in sleep mode IOut(Sleep)
––1
µAVDS = 13.5 V
Tj = 25 °C1)
––2 Tj = 85 °C 1)
––5 Tj = 150 °C
6.5.4 Output clamping voltage VOUT_S(CL) –– -16V–
VOUT_DS(CL) 41––V–
Input Characteristics (IN & LHI)
6.5.5 L level VIN(L) 0–0.6V–
6.5.6 H level VIN(H) 1.8 – 5.5 V –
6.5.7 Input voltage hysteresis ∆VIN –0.1–V
1)
6.5.8 L-input pull-down current IIN(L) 1.5 – – µAVIN = 0.6 V 1)
6.5.9 H-input pull-down current IIN(H) 10 40 80 µAVIN = 5 V
Timings
6.5.10 Turn-on time
VDS = 20% Vbat
tON µsVbb = 13.5 V
resistive load
channel 0, 1,4,5 – – 100 IDS= 250 mA
channel 2, 3 – – 100 IDS= 120 mA
channel 6,7 – – 100 IDS = 250 mA
6.5.11 Turn-off time
VDS = 80% Vbb
tOFF µsVbb = 13.5 V
resistive load
channel 0, 1, 4, 5 – – 100 IDS = 250 mA
channel 2, 3 (HS) – – 100 IDS = 120 mA
channel 6, 7 (LS) – – 100 IDS = 250 mA
Data Sheet 20 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Power Stages
6.6 Command Description
Input Configuration Registers
ICR01 000B
3210
INX1 INX0
rw rw
ICR23 001B
3210
INX3 INX2
rw rw
ICR45 010B
3210
INX5 INX4
rw rw
ICR67 011B
3210
INX7 INX6
rw rw
Field Bits Type Description
INXn
n = 7 to 0
[3:2], [1:0] rw Input Multiplexer Configuration Channel n
00 Channel n is switched off
01 Channel n is switched by input 1
10 Channel n is switched by input 2
11 Channel n is switched on
SPI Driver for Enhanced Relay Control
TLE7235SE
Protection Functions
Data Sheet 21 Rev. 1.0, 2010-02-18
7 Protection Functions
The device provides embedded protective functions. Integrated protection functions are designed to prevent IC
destruction under fault conditions described in this data sheet. Fault conditions are considered as “outside” normal
operating range. Protection functions are not designed for continuous repetitive operation.
7.1 Over Load Protection
The TLE7235SE is protected in case of over load or short circuit of the load. After time tOFF(OVL), the over loaded
channel n switches off and the according diagnosis flag Dn is set. The channel can be switched on after clearing
the protection latch by command CMD.CPL = 1. The CPL command clears itself with the next valid SPI
communication frame. Please refer to Figure 7 for details.
Figure 7 Shut Down at Over Load
7.2 Over Temperature Protection
A temperature sensor for each channel causes an overheated channel to switch off to prevent destruction. The
according diagnosis flag is set. This flag is also set in OFF state, if the regarding channel temperature is too
high.The channel can be only switched on after clearing the protection latch by SPI command CMD.CPL = 1. The
CPL command clears itself with the next valid SPI communication frame. Please refer to “Diagnostic Features”
on Page 23 for information on diagnosis features.
7.3 ESD protection
There is a designed in protection against ESD disturbances up to the specified limit by using the defined model.
Please see electrical characteristics “ESD susceptibility on all pins” on Page 11
7.4 Reverse Polarity Protection
There is a reverse polarity protection implemented in the TLE7235SE. This protection has to be divided into two
parts. First the protection of the control circuits and second in the protection of the power transistors.
The control circuits are reverse polarity protected by protective measures in the ground connection. In case of
reverse polarity, there is no current flow through the control circuits.
The power transistors contain intrinsic body diodes that cause power dissipation. The reverse current through
these intrinsic body diodes has to be limited by the connected loads. The over temperature and over load
protection are not active during reverse polarity.
7.5 Loss of Vbb
In case of loss of Vbb connection in on-state, all inductances of the loads have to be demagnetized through the an
additional path from Vbb to ground. Usually this path is given somewhere in the PCB circuitry, for example, as a
suppressor diode like in the application diagram (see D1 in Figure 14 “Application Diagram” on Page 35).
IN
I
D0
t
t
OverLoad.emf
t
OFF(OV L)
I
D0(OVL)
CPL = 1
b
D0 = 1
b
D0 = 00
b
Data Sheet 22 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Protection Functions
7.6 Electrical Characteristics
Unless otherwise specified:
VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Over Load Protection
7.6.1 Over load detection current at channel
0,1,4,5,6,7
IOut(OVL) 0.5 1.0 A
7.6.2 Over load detection current at channel 2,3 IOut(OVL) 0.22 0.5 A
7.6.3 Over load shut-down delay time tOFF(OVL) 60 µs
Over Temperature Protection
7.6.4 Thermal shut down temperature Tj(SC) 150 1701)
1) Not subject to production test, specified by design
°C
SPI Driver for Enhanced Relay Control
TLE7235SE
Diagnostic Features
Data Sheet 23 Rev. 1.0, 2010-02-18
8 Diagnostic Features
The SPI of TLE7235SE provides diagnosis information about the device and about the load. The diagnosis
information of the protective functions of channel n is latched in the diagnosis flags Dn. It is cleared by the SPI
command CMD.CPL = 1. The CPL command clears itself with the next valid SPI communication frame.
The open load diagnosis of channel n is latched in the diagnosis flag OLn. This flag is cleared by reading the
according diagnosis register.
Following table shows possible failure modes and the according protective and diagnostic action.
Failure Mode Comment
Open Load Diagnosis, when channel n is switched on: none
Diagnosis, when channel n is switched off: according to voltage level at the
output pin, flag OLn is set after time td(OL).
A diagnosis current can be enabled by SPI command DCCR.DCENn = 1.
Over Temperature When over temperature occurs, the according diagnosis flag Dn is set. If the
affected channel n was active it is switched off.
The diagnosis flags are latched until they have been cleared by SPI
command CMD.CPL = 1.
Over Load
(Short Circuit)
When over load is detected at channel n, the affected channel is switched
off after time tOFF(OVL) and the dedicated diagnosis flag Dn is set.
The diagnosis flags are latched until they have been cleared by SPI
command CMD.CPL = 1.
Data Sheet 24 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Diagnostic Features
8.1 Electrical Characteristics
Unless otherwise specified:
VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VBAT = 13.5 V, VDD = 5.0 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Uni
t
Test Conditions
min. typ. max.
OFF State Diagnosis
8.1.1 Open load diagnosis delay time td(OL) 100 – 250 µs–
High Side Channels 0,1,2,3
8.1.2 Open load detection threshold voltage for
Channel 0,1,2,3
VD(OL0..3) 345V
1)
1) Open load detection voltages are referenced to ground
8.1.3 Output diagnosis current channel 0,1,2,3 IL(DC0..3) 100 200 300 µA measured at VD(OL)
threshold
Configurable Channels 4,5
8.1.4 Open load detection threshold voltage for
Channel 4,5 in all configurations
VD(OL4,5) 345V
1)
8.1.5 Output diagnosis current channel 4,5 in
high side configuration
IL(DCHS) 100 200 300 µA measured at VD(OL)
threshold
8.1.6 Output diagnosis current channel 4,5 in
low side configuration
IL(DCLS) 100 200 300 µA measured at VD(OL)
threshold
Low side Channels 6,7
8.1.7 Open load detection threshold voltage for
Channel 6,7
VD(OL6,7) 345V
1)
8.1.8 Output diagnosis current channel 6,7 IL(DC6,7) 100 200 300 µA measured at VOL
threshold
ON State Diagnosis (see also Protection in Chapter 7)
8.1.9 Over load detection current at channel
0,1,4,5,6,7
IL(OVL) 0.5– 1.0A–
8.1.10 Over load detection current at channel
2,3
IL(OVL) 0.22 – 0.5 A –
8.1.11 Over load detection delay time at all
channels
tOFF(OVL) ––60µs–
SPI Driver for Enhanced Relay Control
TLE7235SE
Diagnostic Features
Data Sheet 25 Rev. 1.0, 2010-02-18
8.2 Command Description
Diagnosis Registers (read only, register bank RB = 1)
r/
DR01 00B
3210
OL1 D1 OL0 D0
rrrr
DR23 01B
3210
OL3 D3 OL2 D2
rrrr
DR45 10B
3210
OL5 D5 OL4 D4
rrrr
DR67 11B
3210
OL7 D7 OL6 D6
rrrr
Field Bits Type Description
Dn
n = 7 to 0
2, 0 r Diagnostic Feedback of Channel n
0normal operation
1over load or over temperature switch off occurred
OLn
n = 7 to 0
3, 1 r Open Load Detection of Channel n
0normal operation
1Open load at OFF-state occurred
CMD
Command Register 110B
3210
Wake STB RST CPL
r/w r/w r/w r/w
Field Bits Type Description
CPL 0 r/w please refer to Section 7 for description
RST 1 r/w please refer to Section 5.3 for description
STB 2 r/w please refer to Section 5 for description
Wake 3 r/w please refer to Section 5 for description
Data Sheet 26 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Diagnostic Features
Diagnosis Current Configuration Register
DCCR0 100B
3210
DCEN3 DCEN2 DCEN1 DCEN0
r/w r/w r/w r/w
DCCR1 101B
3210
DCEN7 DCEN6 DCEN5 DCEN5
r/w r/w r/w r/w
Field Bits Type Description
DCENn
n = 7 to 0
3 to 0 r/w Diagnosis Current Enable Channel n
0Diagnosis current disabled
1Diagnosis current enabled
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
Data Sheet 27 Rev. 1.0, 2010-02-18
9 Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
Figure 8 Serial Peripheral Interface
The SPI protocol is described in Section 9.3. It is reset to the default values after reset.
9.1 SPI Signal Description
CS - Chip Select: The system micro controller selects the TLE7235SE by means of the CS pin. Whenever the pin
is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
• SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. For details, please refer to Figure 9. This information stays
available to the first rising edge of SCLK.
Figure 9 Transmission Error Flag on SO Line
LSB654 321
LSB654 321CS MSB
MSB
SO
SI
CS
SCLK
time
SPI.emf
TE R. em f
SI
SPI
OR
TER
0
1
SO
CS
SCLK
S
SO
S
SI
Data Sheet 28 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
CS Low to High transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
• Data from shift register is transferred into the input matrix register.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 9.3
for further information.
SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state
until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please
refer to Section 9.3 for further information.
9.2 Daisy Chain Capability
The SPI of TLE7235SE provides daisy chain capability. In this configuration several devices are activated by the
same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 10),
which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each
device in the chain.
Figure 10 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device #1 has been shifted in to device #2. When using three devices in daisy
chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must go high (see
Figure 11).
SI
device 1
SPI
SCLK
SO
CS
SI
device 2
SPI
SCLK
SO
CS
SI
device 3
SPI
SCLK
SO
CS
MO
MI
MCS
MCLK
SPI _DasyChain.emf
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
Data Sheet 29 Rev. 1.0, 2010-02-18
Figure 11 Data Transfer in Daisy Chain Configuration
9.3 SPI Protocol
The control and diagnosis function of the TLE7235SE is based on two register banks which are accessed via
following SPI protocol. The control register bank contains eight registers (with 4 bit each) addressed by a 3 bit
pointer. The diagnosis register bank contains four registers (with 4 bit each) addressed by a 2 bit pointer. An
additional indication bit is available to differentiate between standard diagnosis information and data read from a
register bank.
Control and Diagnosis Mode
Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame,
the output at SPI signal SO will contain the requested information. Any command can be executed in the
second frame.
CS1)
1) This bit is valid between CS hi -> lo and first SCLK lo -> hi transition.
76543210
Write Register Command
SI 1 ADDR DATA
Read Register Command
SI 0 ADDR x x 0 RB
Read Standard Diagnosis
SI 0xxxxx1x
Standard Diagnosis
S
O
TER 0 AWK LH D67 D45 D23 D01
Second Frame of Read Command
S
O
TER 0 1 ADDR (Diagnosis) DATA
S
O
TER 1 ADDR (Control) DATA
MI
MO
MCS
MCLK
S I devi ce 3 SI device 2 SI device 1
S O devi ce 3 SO device 2 S O devi ce 1
time
SPI _DasyChain2. emf
Data Sheet 30 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
Standard Diagnosis:
9.4 Register Overview
Field Bits Type Description
TER Transmission Error
0 Previous transmission was successful (modulo 8 clocks
received)
1Previous transmission failed or first transmission after reset
RB 0Register Bank
0CONTR Control Register Bank
1DIAG Diagnosis Register Bank (read only)
ADDR 6:4 Address
Pointer to register for read and write command
DATA 3:0 Data
Data written to or read from register selected by address ADDR
Field Bits Type Description
AWK 5Awake, Device active
LH 4Limp home mode active
Dxy 3, 2, 1, 0 Failure mode alert of channel x and y (Overtemp, Overload)
OL ?common open load flag for all channels
Control Register Bank
Name Addr3210default
1)
1) The default values are set after Vbb power-on, STB-command and RST-command
All command bits are cleared at the end of transmission, respectively after execution
type
ICR01 000BINX1 INX0 0Hr/w
ICR23 001BINX3 INX2 0Hr/w
ICR45 010BINX5 INX4 0Hr/w
ICR67 011BINX7 INX6 0Hr/w
DCCR0 100BDCEN3 DCEN2 DCEN1 DCEN0 0Hr/w
DCCR1 101BDCEN7 DCEN6 DCEN5 DCEN4 0Hr/w
CMD 110BWAKE STB RST CPL2)
2) CPL bit needs a valid next SPI communication frame to be cleared
0Hw
unused 111B––––0
H–
Input word (see Chapter 6.6 for detailed description)
Name State 1 0
INX0 - INX7 OFF 0 0
IN1 0 1
IN2 or IN3 1 0
ON 1 1
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
Data Sheet 31 Rev. 1.0, 2010-02-18
9.5 Timing Diagrams
Figure 12 Timing Diagram
Diagnosis Register Bank (read only)
Name Addr3210
DR01 000BOL1 D1 OL0 D0
DR23 001BOL3 D3 OL2 D2
DR45 010BOL5 D5 OL4 D4
DR67 011BOL7 D7 OL6 D6
CS
SCLK
SI
t
CS(lead)
t
CS( td )
t
CS(lag)
t
SCL K( H)
t
SCL K( L)
t
SCL K( P)
t
SI( su)
t
SI( h)
SO
t
SO ( v)
t
SO(en)
t
SO( dis)
0.7V
cc
0.2V
cc
0.7V
cc
0.2V
cc
0.7V
cc
0.2V
cc
0.7V
cc
0.2V
cc
SPI Timing.emf
Data Sheet 32 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
9.6 Electrical Characteristics
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Input Characteristics (CS, SCLK, SI)
9.6.1 L level of pin
CS
SCLK
SI
VCS(L)
VSCLK(L)
VSI(L)
0–0.2*VDD V–
9.6.2 H level of pin
CS
SCLK
SI
VCS(H)
VSCLK(H)
VSI(H)
0.5*VDD –VDD V–
9.6.3 L-input pull-up current through CS ICS(L) 54090µAVCS = 0 V
VDD = 5 V
9.6.4 H-input pull-up current through CS ICS(H) 2.5 – – µA1)
VDD = 5 V
VCS = 0.5*VDD
9.6.5 L-input pull-down current through pin
SCLK
SI
ISCLK(L)
ISI(L)
1.5 – – µA1)
VDD = 5 V
VSCLK = VSI = 0.2*VDD
9.6.6 H-input pull-down current through pin
SCLK
SI
ISCLK(H)
ISI(H) 10 40 80
µA1)
VDD= 5 V
VSCLK = VSI = VDD
Output Characteristics (SO)
9.6.7 L level output voltage VSO(L) 0–0.4VISO = +2 mA
9.6.8 H level output voltage VSO(H) VDD -
0.4 V
–VDD ISO = -1.5 mA
9.6.9 Output tristate leakage current ISO(OFF) -10 – 10 µAVCS = VDD
Timings
9.6.10 Serial clock frequency fSCLK 0–5MHz–
9.6.11 Serial clock period tSCLK(P) 200 – – ns –
9.6.12 Serial clock high time tSCLK(H) 50 – – ns 1)
9.6.13 Serial clock low time tSCLK(L) 50 – – ns 1)
9.6.14 Enable lead time (falling CS to rising
SCLK)
tCS(lead) 250 – – ns 1)
9.6.15 Enable lag time (falling SCLK to rising
CS )
tCS(lag) 250 – – ns 1)
9.6.16 Transfer delay time (rising CS to
falling CS )
tCS(td) 250 – – ns 1)
9.6.17 Data setup time (required time SI to
falling SCLK)
tSI(su) 20 – – ns 1)
9.6.18 Data hold time (falling SCLK to SI) tSI(h) 20 – – ns 1)
SPI Driver for Enhanced Relay Control
TLE7235SE
Serial Peripheral Interface (SPI)
Data Sheet 33 Rev. 1.0, 2010-02-18
9.6.19 Output enable time (falling CS to SO
valid)
tSO(en) ––200nsCL = 20 pF 1)
9.6.20 Output disable time (rising CS to SO
tri-state)
tSO(dis) ––200nsCL = 20 pF 1)
9.6.21 Output data valid time with capacitive
load
tSO(v) ––100nsCL = 20 pF 1)
1) Not subject to production test, specified by design.
Unless otherwise specified: VDD = 3.0 V to 5.5V, VBAT = 9.0 V to 16V, Tj = -40 °C to +150 °C
typical values: VDD = 5.0 V, VBAT = 13.5 V, Tj = 25 °C
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Data Sheet 34 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Package Outlines
10 Package Outlines
Figure 13 PG - DSO20-45 (Plastic Green Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
GPS05094
1.27
0.2 20x
9 x 1.27 = 11.43
0.35+0.15 2)
0.2
-0.1
0.05
12.8 1)
-0.2
110
1120
8˚
8˚
Seating Plane
1.1
STAND OFF
2.65 MAX.
2.45
20x
0.1
-0.2
0.2
-0.1
Ejector Mark
Depth 0.2 MAX.
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion per side
0.35 x 45˚
8˚
-0.21)
7.6
8˚
8˚ MAX.
±0.3
10.3
0.4+0.8
0.23
+0.09
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
SPI Driver for Enhanced Relay Control
TLE7235SE
Application Information
Data Sheet 35 Rev. 1.0, 2010-02-18
11 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 14 shows a simplified application circuit. Vdd need to be externally reverse polarity protected.
Figure 14 Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
The circuit above shows a example of using this device in a automotive target application.
D1 is optional for loss of battery or loss of ground if no other circuit on this battery feed can limit the voltage to the
max. rating of the device (-40 V) .
C2 is for EMC and to stabilize the digital driver, recommended value is 47nF.
There are no resistors to the µC needed due to the internal reverse polarity protection.
For further information you may contact http://www.infineon.com/spider
SO
SCLK
SI
CS
GND
VDD
Application _LG.emf
OUT0
OUT1
OUT6
OUT7
Lowside
Loads
SPI uC
PWM
V
DD
C2
VBB
Highside
Loads
OUT2
OUT3
D4
S4
D5
S5
PWM
LHO
IN2
IN1
LHI
Vbat
D1
Data Sheet 36 Rev. 1.0, 2010-02-18
SPI Driver for Enhanced Relay Control
TLE7235SE
Revision History
12 Revision History
Revision Date Changes
Rev. 1.0 2010-02-18 Datasheet released
Edition 2010-02-18
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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Due to technical requirements, components may contain dangerous substances. For information on the types in
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