70T3399S166BC8 - IDT, Integrated Device Technology Inc

FEBRUARY 2018

DSC-5652/9

HIGH-SPEED 2.5V

512/256/128K X 18

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70T3339/19/99S

Functional Block Diagram

– 1.5ns setup to clock and 0.5ns hold on all control, data,

and address inputs @ 200MHz

– Self-timed write allows fast cycle time

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆Dual Cycle Deselect (DCD) for Pipelined Output Mode

◆2.5V (±100mV) power supply for core

◆LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

◆Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine

pitch Ball Grid Array (fpBGA)

◆Supports JTAG features compliant with IEEE 1149.1

◆Green parts available, see ordering information

Features:

◆True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

◆Selectable Pipelined or Flow-Through output mode

◆Counter enable and repeat features

◆Dual chip enables allow for depth expansion without

additional logic

◆Interrupt and Collision Detection Flags

◆Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– Data input, address, byte enable and control registers

1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

NOTES:

Dout0-8_L

Din_L

R/W

FT/PIPE

L0/1

1b 0b 1a 0a

1/0

0b 1b0a 1a

FT/PIPE

L1/0

REPEAT

CNTEN

ADS

Dout0-8_R

Dout9-17_R

I/O

- I/O

17R

Din_R

ADDR_R

R/W

FT/PIPE

CLK

Counter/

Address

Reg.

FT/PIPE

Counter/

Address

Reg.

CNTEN

ADS

REPEAT

Dout9-17_L

I/O

- I/O

17L

18L

(1)

ADDR_L

5652 drw 01

512/256/128K x 18

MEMORY

ARRAY

CLK

0/1

0a 1a

1/0

1b 0b 1a 0a

1/0

INTERRUPT

COLLISION

DETECTION

LOGIC

INT

COL

INT

COL

CE1L

CE1R

CONTROL

LOGIC

L(2)

R(2)

JTAG

TCK

TRST

TMS

TDO

TDI

18R

(1)

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit

synchronous Dual-Port RAM. The memory array utilizes Dual-Port

memory cells to allow simultaneous access of any address from both ports.

Registers on control, data, and address inputs provide minimal setup and

hold times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times. With an input data register, the

IDT70T3339/19/99 has been optimized for applications having unidirec-

tional or bidirectional data flow in bursts. An automatic power down feature,

controlled by CE0 and CE1, permits the on-chip circuitry of each port to

enter a very low standby power mode.

The IDT70T3339/19/99 can support an operating voltage of either

3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (VDD) is at 2.5V.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

70T3339/19/99BC

BC-256(8)

256-Pin BGA

Top View(9)

Pin Configuration (3,4,5,6,9)

NOTES:

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

3. All VDD pins must be connected to 2.5V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Pins A15 and T15 will be VREFL and VREFR respectively for future HSTL device.

E16

I/O

D16

I/O

C16

I/O

B16

A16

A15

B15

C15

D15

E15

I/O

E14

D14

D13

C12

6L C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

17L(2)

18L(1)

16L

PIPE/

TDO

I/O

TDI

INT

COL

I/O

10R E2

I/O

10L E3

DDQL

I/O

11L F2

DDQL

I/O

12L

DDQR

I/O

12R

DDQR

I/O

13L J2

I/O

14R J3

I/O

13R J4

DDQL

I/O

14L

DDQL

I/O

15L L2

I/O

15R L4

DDQR

I/O

16R M2

I/O

16L M3

DDQR

I/O

17R N3

PIPE/

COL

RP2

I/O

17L P3

TMS

16R

INT

RR2

TRST

18R(1)

TCK

17R(2)

13R

15R

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

14R T14

R14

OPT

P14

P15

R15

T15

T16

R16

P16

I/O

N16

N15

I/O

N14

M16

M15

I/O

M14

I/O

L16

I/O

L15

L14

I/O

K16

I/O

K15

K14

J16

I/O

J15

I/O

J14

I/O

H16

I/O

H15

H14

G16

G15

G14

I/O

F16

I/O

F14

I/O

6R F15

0R R11

REPEAT

11R

11L

B10

R/W

C13

10R

R10

R/W

T10

DD E6

DD E7

SS E9

SS E10

SS E11

DD E12

DD E13

DDQR

DD F6

SS F10

SS F12

F13

DDQR

SS G6

SS G7

SS G9

SS G10

SS G11

G12

SS G13

DDQL

SS H8

SS H9

SS H10

H11

SS H12

SS H13

DDQL

RJ6

SS J7

SS J8

SS J9

SS J10

SS J11

SS J12

LJ13

DDQR

SS K7

DD L6

DD M6

DD M7

DDQR N6

DDQR N7

DDQL

K10

SS K11

K12

SS L10

L11

SS L12

SS M10

SS M11

DD M12

DDQR N10

DDQR N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5652 drw 02d

I/O

11R

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations(con't)(3,4,5,6,9)

1716

1412 13

9876543

21 11

I/O

INT

TDO

CLK

12L

16L

NC OPT

NC V

COL

TDI A

13L

17L(2)

DDQL

I/O

DDQR

PIPE/FT

10L

14L

18L(1)

NC V

I/O

10L

I/O

11L

NC V

DDQR

I/O

10R

I/O

11R

NC V

NC I/O

12L

I/O

12R

REPEATR

NC I/O

14L

DDQR

DDQL

I/O

15R

NC V

NCNC

15L

11L

I/O

DDQL

REPEATL

I/O

ADS

R/W

I/O

16R

I/O

15L

TRST

13R

12R

NC V

CLK

I/O

NC A

17R(2)

TCK

TMS

16R

18R(1)

14R

10R

DDQL

I/O

INT

NC A

15R

11R

DDQL

OPT

70T3339/19/99BF

BF-208

(7)

208-Pin fpBGA

Top View

(8)

5652 drw 02c

I/O

14R

DDQL

DDQR

COL

NC I/O

R/W

ADS

DDQL

I/O

13R

CNTEN L

I/O

13L

I/O

16L

DDQR

I/O

17R

I/O

17L

DDQL

PIPE/FT

CNTEN R

I/O

DDQR

DDQL

DDQR

I/O

DDQR

I/O

DDQR

I/O

DDQL

DDQR

NOTES:

3. All VDD pins must be connected to 2.5V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins

themselves (ZZx) are not affected during sleep mode. It is recommended that

boundry scan not be operated during sleep mode.

5. Address A18x is a NC for the IDT70T3319. Also, Addresses A18x and A17x are

NC's for the IDT70T3399.

6 . Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the

signals take two cycles to deselect.

Left Port Right Port Nam es

Chip Enab le s (Inp ut)

(6)

R/W

Re ad /Write E nab le (Input)

Output Enab le (Input)

- A

18L

(5)

- A

18R

(5)

A dd re s s (Inp ut)

I/O

- I/O

17L

I/O

- I/ O

17R

Data Inp ut/ Ou tp ut

CLK

Clo ck (Inp ut)

PL/FT

Pipeline/Flow-Through (Input)

ADS

Address Strobe Enable (Input)

CNTEN

Co unte r E nab le (Inp ut)

REPEAT

Counter Repeat

(3)

Up p er By te Enab l e (I/ O

- I/O

)

(6)

Lo we r By te Enab l e (I/ O

- I/O

)

(6)

DDQL

DDQR

P owe r (I/O Bus ) (3.3V o r 2.5V )

(1)

(Inp ut)

OPT

Op ti o n fo r se l e c ti ng V

DDQX

(1,2)

(Input)

Sleep Mode pin

(4)

(Inp ut)

Power (2.5V)

(1)

(Input)

Gro und (0V) (Inp ut)

TDI Te st Data Inp ut

TDI Te st Data Outp ut

TCK Test Lo gic Clo c k (10MHz ) (Input)

TMS Test Mode Select (Input)

TRST Re se t (Initiali ze TA P Co ntro lle r) (Inp ut)

INT

Inte r rup t F l ag (O utp u t)

COL

Collisio n Ale rt (Outp ut)

5652 tb l 01

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, REPEAT = X.

3. OE and ZZ are asynchronous input signals.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I—Read/Write and Enable Control (1,2,3,4)

Truth Table II—Address Counter Control (1,2)

NOTES:

1 . "H" = VIH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB, LB and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1, UB and LB.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB and LB.

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

OE CLK CE

UB LB R/WZZ Upper Byte

I/O

9-17

Lower Byte

I/O

0-8

MODE

X↑HXXXX L High-Z High-ZDeselected–Power Down

X↑X L X X X L High-Z High-Z Deselected–Power Down

X↑L H H H X L Hig h-Z Hig h-Z Bo th B yte s De s e le c te d

X↑LHHLLL High-Z D

Wri te to Lo we r By te Onl y

X↑LHLHLL D

High-Z Write to Upper Byte Only

X↑LHLLLL D

Wri te to Bo th By tes

L↑LHHLHL High-Z D

OUT

Re ad Lo we r B yte Onl y

L↑LHLHHL D

OUT

Hig h-Z Re ad Up p e r B yte Onl y

L↑LHLLHL D

OUT

Re ad B o th B yte s

H↑L H L L X L High-Z High-Z Outputs Disabled

XXXXXXXH High-Z High-ZSleep Mode

5652 tbl 02

Address

Internal

Address

Internal

Address

Used CLK ADS CNTEN REPEAT

(6)

I/O

(3)

MODE

An X An ↑ L

(4)

XHD

I/O

(n) External Address Used

XAnAn + 1

↑H L

(5)

I/O

(n+1) Counter Enabled—Internal Address generation

X An + 1 An + 1 ↑HH HD

I/O

(n+1) External Address Blocked—Counter disabled (An + 1 reused)

XXAn

↑XX L

(4)

I/O

(n) Counter Set to last valid ADS load

5652 tbl 03

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended DC Operating

Conditions with VDDQ at 3.3V

Symbol Parameter Min. Typ. Max. Unit

Core Supp ly Vo ltage 2.4 2.5 2.6 V

DDQ

I/ O S up ply Voltag e(3) 3.15 3.3 3.45 V

Ground 0 0 0 V

Inpu t Hi g h Vo l tage

(A d dre s s , Co ntro l

& Data I/ O In p uts )(3) 2.0

____

DDQ

+ 150 mV(2) V

Inpu t Hi g h Vo l tage _

JTAG 1.7

____

+ 100mV (2) V

Inp u t Hi g h Vo l tag e -

ZZ, OPT, PIPE/FT V

- 0. 2V

____

+ 100mV (2) V

Inpu t Lo w Vo l tag e -0.3 (1)

____

0.8 V

Inpu t Lo w Vo l tag e -

ZZ, OPT, PIPE/FT -0.3(1)

____

0.2 V

5652 tb l 05b

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

3 . To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT

pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied

as indicated above.

Recommended DC Operating

Conditions with VDDQ at 2.5V

Symbol Parameter Min. Typ. Max. Unit

Co re Sup p ly Vo ltag e 2. 4 2.5 2.6 V

DDQ

I/ O Sup p l y Vo l tag e

(3)

2.4 2.5 2.6 V

Ground 0 0 0 V

Input High Volltage

(Add re s s , Co ntro l &

Data I/O Inp u ts )

(3)

1.7

____

DDQ

+ 100mV

(2)

Input High Voltage

JTAG 1.7

____

+ 100m V

(2)

Input High Voltage -

ZZ, O P T, P IP E/FT V

- 0.2V

____

+ 100m V

(2)

Input Lo w Vo ltag e -0.3

(1)

____

0.7 V

Input Low Voltage -

ZZ, O P T, P IP E/FT -0.3

(1)

____

0.2 V

5652 tbl 05a

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

3 . To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT

pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as

indicated above.

Maximum Operating

Temperature and Supply Voltage(1)

Grade Ambient

Temperature GND V

Commercial 0OC to + 70 OC0V2.5V

100mV

Industrial -40OC to +85OC0V2.5V

100mV

5652 tb l 04

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings(1)

Symbol Rating Commercial

& Industri al Unit

TERM

Terminal Voltage

wi th Re s p e c t to G ND -0.5 to 3.6 V

TERM

(2)

DDQ

Terminal Voltage

wi th Re s p e c t to G ND -0.3 to V

DDQ

+ 0.3 V

TERM

(2)

(INP UTS and I/ O's ) Input and I/O Te rm inal

Voltage with Respect to GND -0.3 to V

DDQ

+ 0.3 V

BIAS

(3)

Temperature Under Bias -55 to +125

STG

Sto rag e Te mp e rature -65 to + 150

J unctio n Te mp e rature +150

OUT

(Fo r V

DDQ

3. 3V ) DC Outp ut Curre nt 50 mA

OUT

(Fo r V

DDQ

2. 5V ) DC Outp ut Curre nt 40 mA

5652 tb l 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. This is a steady-state DC parameter that applies after the power supply has reached its

nominal operating value. Power sequencing is not necessary; however, the voltage on

any Input or I/O pin cannot exceed VDDQ during power supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

Symbol Parameter Test Conditions

70T3339/19/99S

UnitMin. Max.

| Inp ut Le akag e Curre nt

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

10 µA

| JTAG & ZZ Input Leakag e Curre nt

(1,2)

DD =

Max.

= 0V to V

___

±30 µA

| Outp ut Le ak ag e Curre nt

(1,3)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

10 µA

(3. 3V) Outp ut Lo w Vol ta ge

(1)

= +4mA, V

DDQ

= Min.

___

0.4 V

(3. 3V) Outp ut Hig h Vol tage

(1)

= -4mA, V

DDQ

= Mi n. 2. 4

___

(2. 5V) Outp ut Lo w Vol ta ge

(1)

= +2mA, V

DDQ

= Min.

___

0.4 V

(2. 5V) Outp ut Hig h Vol tage

(1)

= -2mA, V

DDQ

= Mi n. 2. 0

___

5652 tb l 08

NOTES:

1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

Capacitance(1)

(TA = +25°C, f = 1.0MHz) PQFP ONLY

Symbol Parameter Conditions

(2)

Max. Unit

Input Capacitance V

= 3dV 8 pF

OUT

(3)

Outp ut Cap ac itance V

OUT

= 3d V 10. 5 p F

5652 tbl 07

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. COUT also references CI/O.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (3)(VDD = 2.5V ± 100mV)

70T3339/19/99

S200

Com'l Only

(8)

70T3339/19/99

S166

Com'l

& In d

(7)

70T3339/19/99

S133

Com'l

& I nd

Symbol Parameter Test Condi tion Version Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Unit

Dynamic Ope rating

Current (B o th

Ports Active )

and CE

= V

Outputs Disabled,

f = f

MAX

(1)

COM'L S 375 525 320 450 260 370 mA

IND S

___ ___

320 510 260 450

SB1

(6)

Standby Current

(B o th Po rts - TTL

Le v el Inp uts)

= CE

= V

f = f

MAX

(1)

COM'L S 205 270 175 230 140 190 mA

IND S

___ ___

175 275 140 235

SB2

(6)

Standby Current

(One Po rt - TTL

Le v el Inp uts)

"A"

= V

and CE

"B"

= V

(5)

Active Po rt Outputs Disabled ,

f=f

MAX

(1)

COM'L S 300 375 250 325 200 250 mA

IND S

___ ___

250 365 200 310

SB3

Full Standby Current

(Bo th Po rts - CMOS

Le v el Inp uts)

Both Po rts CE

and

> V

DDQ

- 0.2V, V

> V

DDQ

- 0.2V

or V

< 0. 2V, f = 0

(2)

COM'L S 515 5 15 5 15 mA

IND S

___ ___

520520

SB4

(6)

Full Standby Current

(One Po rt - CMOS

Le v el Inp uts)

"A"

< 0. 2V and CE

"B"

> V

DDQ

- 0.2V

(5)

> V

DDQ

- 0.2V o r V

< 0. 2V

Active Port, Outputs Disabled, f = f

MAX

(1)

COM'L S 300 375 250 325 200 250 mA

IND S

___ ___

250 365 200 310

Izz Sleep Mode Current

(B o th Po rts - TTL

Le v el Inp uts)

L =

R =

f=f

MAX

(1)

COM'L S 515 5 15 5 15 mA

IND S

___ ___

520520

5652 tbl 09

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3 . Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V

CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.

7. 166MHz I-Temp is not available in the BF-208 package.

8. 200Mhz is not available in the BF-208 package.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Input Pulse Levels (Address & Controls)

Input P ul s e L e v e l s (I/ Os )

Inp ut Ri se / Fall Time s

Input Tim i ng Re fe ren c e Levels

Outp ut Re fere nce Le ve ls

Outp ut Lo ad

GND to 3

0V/ GND to 2. 4V

GND to 3.0V/ GND to 2.4V

2ns

1.5V/1.25V

Fi gure s 1 and 2

5652 tb l 10

AC T est Conditions (VDDQ - 3.3V/2.5V)

Figure 1. AC Output Test load.

1.5V/1.25

50Ω

5652 drw 03

10pF

(Tester)

DATA

OUT

∆

Capacitance (pF) from AC Test Load

5652 drw 04

∆

tCD

(Typical, ns)

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)

NOTES:

1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)

apply when FT/PIPE = Vss (0V) for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be

treated as DC signals, i.e. steady state during operation.

3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.

4. 166MHz I-Temp is not available in the BF-208 package.

5. 200Mhz is not available in the BF-208 package.

6. Guaranteed by design (not production tested).

70T3339/19/99

S200

Com'l Only

(5)

70T3339/19/99

S166

Com'l

& I nd

(4)

70T3339/19/99

S133

Com'l

& I nd

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

CYC1

Clock Cycle Time (Flo w-Throug h)

(1)

15 ____ 20 ____ 25 ____ ns

CYC2

Clock Cycle Time (Pipelined)

(1)

5____ 6____ 7.5 ____ ns

CH1

Clo c k Hi g h Tim e (Flo w-Thro ug h)

(1)

6____ 8____ 10 ____ ns

CL1

Clo ck Lo w Time (Flo w-Thro ugh)

(1)

6____ 8____ 10 ____ ns

CH2

Clock High Time (Pipelined)

(2)

2____ 2.4 ____ 3____ ns

CL2

Clock Low Time (Pipelined)

(1)

2____ 2.4 ____ 3____ ns

Address Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns

Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns

Chip Enab le Se tup Time 1. 5 ____ 1.7 ____ 1.8 ____ ns

Chip Enab le Ho ld Tim e 0. 5 ____ 0.5 ____ 0.5 ____ ns

Byte Enable Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns

By te E nab le Ho ld Ti me 0. 5 ____ 0.5 ____ 0.5 ____ ns

R/ W Setup Time 1. 5 ____ 1.7 ____ 1.8 ____ ns

R/ W Ho ld Ti me 0. 5 ____ 0.5 ____ 0.5 ____ ns

Inp ut Data S e tup Time 1. 5 ____ 1.7 ____ 1.8 ____ ns

Inp ut Data Ho l d Ti me 0. 5 ____ 0.5 ____ 0.5 ____ ns

SAD

ADS Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns

HAD

ADS Ho ld Ti me 0.5 ____ 0.5 ____ 0.5 ____ ns

SCN

CNTEN Se tup Time 1.5 ____ 1.7 ____ 1.8 ____ ns

HCN

CNTEN Ho l d Time 0.5 ____ 0.5 ____ 0.5 ____ ns

SRPT

REPEAT Setup Time 1.5 ____ 1.7 ____ 1.8 ____ ns

HRPT

REPEAT Hol d Tim e 0.5 ____ 0.5 ____ 0.5 ____ ns

Outp ut E nab le to Data Valid ____ 4.4 ____ 4.4 ____ 4.6 ns

OLZ

(6)

Outp ut Enab le to Outp ut Lo w-Z 1 ____ 1____ 1____ ns

OHZ

(6)

Outp ut Enab le to Outp ut Hig h-Z 1 3. 4 1 3. 6 1 4. 2 ns

CD1

Clo ck to Data Valid (Flow-Thro ug h)

(1)

____ 10 ____ 12 ____ 15 ns

CD2

Clock to Data Valid (Pipelined)

(1)

____ 3.4 ____ 3.6 ____ 4.2 ns

Data Outp ut Ho ld Afte r Clo c k Hi gh 1 ____ 1____ 1____ ns

CKHZ

(6)

Clo c k Hi g h to Outp ut High-Z 1 3. 4 1 3. 6 1 4.2 ns

CKLZ

(6)

Clo c k Hi g h to Outp ut Lo w-Z 1 ____ 1____ 1____ ns

INS

In te rrupt F l ag S e t Ti me ____ 7____ 7____ 7ns

INR

In te rrupt F l ag Res et Ti m e ____ 7____ 7____ 7ns

COLS

Coll isio n Flag Se t Time ____ 3.4 ____ 3.6 ____ 4.2 ns

COLR

Coll isio n Flag Res e t Time ____ 3.4 ____ 3.6 ____ 4.2 ns

ZZSC

Sleep Mode Set Cycles 2 ____ 2____ 2____ cycles

ZZRC

Sleep Mode Recovery Cycles 3 ____ 3____ 3____ cycles

Po rt-to -Po rt Del ay

Clock-to-Clock Offse t 4 ____ 5____ 6____ ns

OFS

Cloc k-to-Clo ck Offse t fo r Coll isio n Dete ction Ple ase re fe r to Co llis io n De te c tio n Timing Table on Pag e 20

5652 tb l 11

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wa vef orm of Read Cyc le for Pipelined Operation

(FT/PIPE'X' = VIH)(2)

Timing Wa veform of Read Cyc le for Flow-through Output

(FT/PIPE"X" = VIL)(2,6)

NOTES:

1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.

2. ADS = VIL, CNTEN and REPEAT = VIH.

3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

An An + 1 An + 2 An + 3

CYC2

CH2

CL2

ADDRESS

CLK

UB,LB

(3)

DATA

OUT

CD2

CKLZ

Qn Qn + 1 Qn + 2

OHZ

OLZ

5652 drw 05

(1)

(4)

(1 Latency)

(5)

An An + 1 An + 2 An + 3

tCYC1

tCH1 tCL1

ADDRESS

DATAOUT

CLK

tSC tHC

tCD1

tCKLZ

Qn Qn + 1 Qn + 2

tOHZ tOLZ

tOE

tCKHZ

5652 drw 06

(5)

(1)

CE1

UB,LB

(3)

tSB tHB

tSW tHW

tSA tHA

tDC

(4)

tSC tHC

tSB tHB

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of a Multi-Device Pipelined Read(1,2)

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3339/19/99 for this waveform,

and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.

2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.

Timing Waveform of a Multi-Device Flow-Through Read(1,2)

CE0(B1)

ADDRESS

(B1)

CLK

DATA

OUT(B1)

CH2

CL2

CYC2

ADDRESS

(B2)

CE0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CKHZ

CKLZ

CD2

5652 drw 07

0(B1)

ADDRESS

(B1)

CLK

5652 drw 08

CD1

CKLZ

CKHZ

(1) (1)

DATA

OUT(B1)

CH1

CL1

CYC1

(1)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD1

CKHZ

CD1

CKLZ

(1)

CKHZ

(1)

CKLZ

(1)

CD1

CKLZ

(1)

CKHZ

(1)

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Wa v eform of Left Port Write to Pipelined Right Port Read(1,2,4)

Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)

NOTES:

1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be

tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will

be tCO + tCD1).

4 . All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

CLK

"A"

R/W

ADDRESS

"A"

DATA

IN"A"

CLK

"B"

R/W

"B"

ADDRESS

"B"

DATA

OUT"B"

(3)

CD2

MATCH

VALID

MATC

VALID

5652 drw 09

DATAIN "A"

CLK "B"

R/W"B"

ADDRESS "A"

R/W"A"

CLK "A"

ADDRESS "B"

MATCH

VALID

tCD1

tDC

DATAOUT "B"

5652 drw 10

VALID

tSW tHW

tSA tHA

tSD tHD

tHW

tCD1

tCO

tDC

tSA

tSW tHA

(3)

NOTES:

1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.

3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be

tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port

will be tCO + tCYC2 + tCD2).

4 . All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = VIL)(2)

Timing Wavefor m of Pipelined Read-to-Write-to-Read (OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATA

Dn + 2

CLK

5652 drw 11

Qn Qn + 3

DATA

OUT

UB,LB

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ NOP READ

(3)

(1)

WRITE

(4) ,

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

DATA

Dn + 3Dn + 2

CLK

5652 drw 12

DATA

OUT

Qn Qn + 4

UB,LB

CH2

CL2

CYC2

CKLZ

CD2

OHZ

CD2

READ WRITE READ

(3)

(1)

(4)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-R ead (OE = VIL)(2)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS An An +1 An + 2 An + 2 An + 3 An + 4

DATA

Dn + 2

CLK

5652 drw 13

DATA

OUT

UB,LB

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ NOP READ

CKLZ

(3)

(1)

WRITE

(4) ,

ADDRESS An An +1 An + 2 An + 3 An + 4 An + 5

(3)

DATA

Dn + 2

CE0

CLK

5652 drw 14

DATA

OUT

UB,LB

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ WRITE READ

CKLZ

(1)

Dn + 3

OHZ

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read with Address Counter Advance(1)

ADDRESS An

CLK

DATA

OUT

Qx - 1(2) Qx Qn Qn + 2(2) Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

5652 drw 15

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS READ WITH COUNTER COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1 ,

NOTES:

1. CE0, OE, UB, LB = VIL; CE1, R/W, and REPEAT = VIH.

2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

Timing Waveform of Flow-Through Read with Address Counter Advance(1)

ADDRESS An

CLK

DATA

OUT

Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4

ADS

CNTEN

CYC1

CH1

CL1

5652 drw 16

SAD

HAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER COUNTER

HOLD

CD1

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs)(1)

Timing Waveform of Counter Repeat(2)

NOTES:

1. CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.

2. CE0, UB, LB = VIL; CE1 = VIH.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.

7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

ADDRESS An

CLK

DATA

Dn Dn + 1 Dn + 1 Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

5652 drw 17

INTERNAL

(3)

ADDRESS An

(7)

An + 1 An + 2 An + 3 An + 4

Dn + 3 Dn + 4

SAD

HAD

WRITE

COUNTER HOLD WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

SCN

ADDRESS An

CH2

CL2

CYC2

LAST

LAST+1

LAST ADS LOAD

CLK

DATA

REPEAT

5652 drw 18

INTERNAL

(3)

ADDRESS

ADS

CNTEN

SRPT

HRPT

EXECUTE

REPEAT WRITE

LAST ADS

ADDRESS

READ

LAST ADS

ADDRESS

READ

LAST ADS

ADDRESS + 1

READ

ADDRESS n

An + 1 An + 2

READ

ADDRESS n+1

DATA

OUT

LAST ADS +1 An An + 1

(4)

(5)

(6)

SAD

HAD

SCN

HCN

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing (2)

NOTES:

1. CE0 = VIL and CE1 = VIH

2. All timing is the same for Left and Right ports.

3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

7FFFF

CLK

(1)

ADDRESS

(3)

7FFFF

INR

CLK

R/W

ADDRESS

(3)

(1)

5652 drw 19

INT

INS

R/W

T ruth T able III — Interrupt Flag (1)

Left Port Right Port

FunctionCLK

R/W

(2)

18L

-A

(3,4,5)

INT

CLK

R/W

(2)

18R

-A

(3,4,5)

INT

↑L L 7FFFF X ↑X X X L S e t Ri g ht INT

Flag

↑XX X X↑H L 7FFFF H Rese t Rig ht INT

Flag

↑XX X L↑L L 7FFFE X S et Le ft INT

Flag

↑H L 7FFFE H ↑X X X X Re s et Le ft INT

Flag

5652 tbl 12

NOTES:

1. INTL and INTR must be initialized at power-up by Resetting the flags.

2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

3. A18X is a NC for IDT70T3319, therefore Interrupt Addresses are 3FFFF and 3FFFE.

4. A18X and A17X are NC's for IDT70T3399, therefore Interrupt Addresses are 1FFFF and 1FFFE.

5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

(3)

COLS

COLR

COLS

COLR

5652 drw 20

COL

(4)

CLK

ADDRESS

OFS

(4)

CLK

ADDRESS

OFS

Wa veform of Collision Timing (1,2)

Both P orts Writing with Left Port Clock Leading

Collision Detection Timing(3,4)

Cyc le T i m e

OFS

(ns)

Region 1 (ns)

(1)

Region 2 (ns)

(2)

5ns 0 - 2.8 2.81 - 4.6

6ns 0 - 3.8 3.81 - 5.6

7.5ns 0 - 5.3 5.31 - 7.1

5652 tbl 13

NOTES:

1. Region 1

Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.

2. Region 2

Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.

while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.

3. All the production units are tested to midpoint of each region.

4. These ranges are based on characterization of a typical device.

Left Port Ri ght Port

FunctionCLK

R/W

(1)

18L

-A

(2)

COL

CLK

R/W

(1)

18R

-A

(2)

COL

↑HLMATCHH↑HLMATCHH

Both po rts reading. Not a valid c ollision.

No flag output on either port.

↑HLMATCHL↑LLMATCHH

Left port reading, Right port writing.

Valid collision, flag output on Left port.

↑LLMATCHH↑HLMATCHL

Right port reading, Left port writing.

Valid collision, flag output on Right port.

↑LLMATCHL↑LLMATCHL

Both po rts writing . Valid co llisio n. Flag

output on both ports.

5652 tbl 14

Truth Table IV — Collision Detection Flag

NOTES:

1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

NOTES:

1. CE0 = VIL, CE1 = VIH.

2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.

3 . Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.

4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

(3)

R/W

DATA

OUT

R/W

(4)

Dn Dn+1

An+1An

(5)

Timing Wa vef orm - Entering Sleep Mode (1,2)

Timing Wa v eform - Exiting Sleep Mode (1,2)

NOTES:

1. CE1 = VIH.

2. All timing is same for Left and Right ports.

3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).

4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).

5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70T3339/19/99 provides a true synchronous Dual-Port Static

RAM interface. Registered inputs provide minimal set-up and hold times

on address, data, and all critical control inputs. All internal registers are

clocked on the rising edge of the clock signal, however, the self-timed

internal write pulse width is independent of the cycle time.

An asynchronous output enable is provided to ease asyn-

chronous bus interfacing. Counter enable inputs are also provided to stall

the operation of the address counters for fast interleaved

memory applications.

A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down

the internal circuitry to reduce static power consumption. Multiple chip

enables allow easier banking of multiple IDT70T3339/19/99s for depth

expansion configurations. Two cycles are required with CE0 LOW and

CE1 HIGH to re-activate the outputs.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt

flag (INTL) is asserted when the right port writes to memory location

7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the

Truth Table. The left port clears the interrupt through access of

address location 7FFFE when CEL = VIL and R/WL = VIH. Likewise, the

right port interrupt flag (INTR) is asserted when the left

port writes to memory location 7FFFF (HEX) and to clear the interrupt

flag (INTR), the right port must read the memory location 7FFFF (3FFFF

or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The

message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319

and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an

addressable SRAM location. If the interrupt function is not used, address

locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and

1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as

part of the random access memory. Refer to Truth Table III for the interrupt

operation.

Collision Detection

Sleep Mode

The IDT70T3339/19/99 is equipped with an optional sleep or low

power mode on both ports. The sleep mode pin on both ports is

asynchronous and active high. During normal operation, the ZZ pin is

pulled low. When ZZ is pulled high, the port will enter sleep mode where

it will meet lowest possible power conditions. The sleep mode timing

diagram shows the modes of operation: Normal Operation, No Read/Write

Allowed and Sleep Mode.

For normal operation all inputs must meet setup and hold times prior

to sleep and after recovering from sleep. Clocks must also meet cycle high

and low times during these periods. Three cycles prior to asserting ZZ

(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device

must be disabled via the chip enable pins. If a write or read operation occurs

during these periods, the memory array may be corrupted. Validity of data

out from the RAM cannot be guaranteed immediately after ZZ is asserted

(prior to being in sleep). When exiting sleep mode, the device must be in

Read mode (R/Wx = VIH)when chip enable is asserted, and the chip

enable must be valid for one full cycle before a read will result in the output

of valid data.

During sleep mode the RAM automatically deselects itself. The RAM

disconnects its internal clock buffer. The external clock may continue to run

without impacting the RAMs sleep current (IZZ). All outputs will remain in

high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM

will not be selected and will not perform any reads or writes.

Collision is defined as an overlap in access between the two ports

resulting in the potential for either reading or writing incorrect data to a

specific address. For the specific cases: (a) Both ports reading - no data

is corrupted, lost, or incorrectly output, so no collision flag is output on either

port. (b) One port writing, the other port reading - the end result of the write

will still be valid. However, the reading port might capture data that is in

a state of transition and hence the reading port’s collision flag is output. (c)

Both ports writing - there is a risk that the two ports will interfere with each

other, and the data stored in memory will not be a valid write from either

port (it may essentially be a random combination of the two). Therefore,

the collision flag is output on both ports. Please refer to Truth Table IV for

all of the above cases.

The alert flag (COLX) is asserted on the 2nd or 3rd rising clock edge

of the affected port following the collision, and remains low for one cycle.

Please refer to Collision Detection Timing table on page 20. During that

next cycle, the internal arbitration is engaged in resetting the alert flag (this

avoids a specific requirement on the part of the user to reset the alert flag).

If two collisions occur on subsequent clock cycles, the second collision may

not generate the appropriate alert flag. A third collision will generate the

alert flag as appropriate. In the event that a user initiates a burst access

on both ports with the same starting address on both ports and one or both

ports writing during each access (i.e., imposes a long string of collisions

on contiguous clock cycles), the alert flag will be asserted and cleared

every other cycle. Please refer to the Collision Detection Timing waveform

on page 20.

Collision detection on the IDT70T3339/19/99 represents a significant

advance in functionality over current sync multi-ports, which have no such

capability. In addition to this functionality the IDT70T3339/19/99 sustains

the key features of bandwidth and flexibility. The collision detection function

is very useful in the case of bursting data, or a string of accesses made to

sequential addresses, in that it indicates a problem within the burst, giving

the user the option of either repeating the burst or continuing to watch the

alert flag to see whether the number of collisions increases above an

acceptable threshold value. Offering this function on chip also allows users

to reduce their need for arbitration circuits, typically done in CPLD’s or

FPGA’s. This reduces board space and design complexity, and gives the

user more flexibility in developing a solution.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Depth and Width Expansion

The IDT70T3339/19/99 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

The IDT70T3339/19/99 can also be used in applications requiring

expanded width, as indicated in Figure 4. Through combining the control

signals, the devices can be grouped as necessary to accommodate

applications needing 36-bits or wider.

NOTE:

1. A19 is for IDT70T3339, A18 is for IDT70T3319, A17 is for IDT70T3399.

5652 drw 23

IDT70T3339/19/99

Control Inputs

Control Inputs UB,LB,

R/W,

OE,

CLK,

ADS,

REPEAT,

CNTEN

18/

17(1)

Figure 4. Depth and Width Expansion with IDT70T3339/19/99

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

JT AG AC Electrical

Characteristics (1,2,3,4)

JTAG Timing Specifications

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

tJCD

tJDC

JRST

tJS tJH

tJCYC

JRSR

JCL

JCH

5652 drw 24

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

70T3339/19/99

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

J TAG Clo c k HIGH 40

____

JCL

JTAG Clock Low 40

____

J TA G Cl o c k Ri se Ti me

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Res et 50

____

JRSR

JTAG Reset Recovery 50

____

JCD

J TAG Da ta Ou tp ut

____

25 ns

JDC

J TA G Da ta Ou tp ut H o ld 0

____

JTAG Setup 15

____

JTAG Ho ld 15

____

5652 tb l 15

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

System Interface Parameters

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

NOTE:

1. Device ID for IDT70T3319 is 0x334. Device ID for IDT70T3399 is 0x335.

Instructi on Field Valu e Description

Revisio n Number (31:28) 0x0 Reserved for version number

IDT Device ID (27:12) 0x333

(1)

Define s IDT part numb er

IDT J E DE C ID ( 11: 1) 0x33 A ll o ws unique i d e nti fi c ati o n o f de v i c e v e nd or as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

5652 tb l 16

Scan Register Sizes

Instruction (IR) 4

Bypass (BYR) 1

Id e ntific ati o n (IDR) 32

Bo und ary S can (B SR) No te (3)

5652 tb l 17

Instruction Code Description

EXTE ST 0000 Fo rce s c o nte nts o f the b o undary sc an ce ll s o nto the d e vic e o utputs

(1)

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

HIGHZ 0100 Places the bypass re gister (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state excep t COLx & INTx outputs.

CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass reg ister (BYR) between TDI and TDO.

SA MP LE/PRE LOAD 0001 P lace s the b o und ary sc an re gis te r (BSR) b e twe e n TDI and TDO.

SAMPLE allows data from device inputs

(2)

to be captured in the

b o undary sc an ce lls and shifte d s eri al ly thro ugh TDO. PRELOA D allo ws

data to be input serially into the boundary scan cells via the TDI.

RESERVE D 0101, 0111, 1000, 1001,

1010, 1011, 1100 Several combinations are reserved. Do not use codes othe r than tho se

identified above.

PRIVATE 0110, 1110,1101 Fo r inte rnal us e only.

5652 tb l 18

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTES:

1. 166MHz I-Temp is not available in the BF-208 package.

2. 200Mhz is not available in the BF-208 package.

3. Green parts available. For specific speeds, packages and powers contact your local sales office.

4. Contact your local sales office for industrial temp range for other speeds, packages and powers.

LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

Power 999

Speed

Package

XXXX

Device

Type

200

166

133

70T3339

70T3319

70T3399

256-pin BGA (BC-256)

208-pin fpBGA (BF-208)

Standard Power

Speed in Megahertz

Commercial Only

)

Commercial & Industrial

)

Commercial & Industrial

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

9Mbit (512K x 18-bit) Synchronous Dual-Port RAM

4Mbit (256K x 18-bit) Synchronous Dual-Port RAM

2Mbit (128K x 18-bit) Synchronous Dual-Port RAM

5652 drw 25

Process/

Temperature

Range

Tube or Tray

Tape & Reel

Blank

Green

A A

Blank

)

IDT Clock Solution for IDT70T3339/19/99 Dual-Port

IDT Dual-Port

Par t Number

Dual-Port I/O Specitications Clock Specifications IDT

PLL

Clock Dev ice

IDT

Non-PLL

Clock Device

Voltage I/O Input

Capacitance

Input Duty

Cycle

Requirement

Maximum

Frequency Jitter

Tolerance

70T3339/19/99 2.5 LVTTL 8pF 40% 200 75ps 5T2010 5T9010

5T905, 5T9050

5T907, 5T9070

5652 tbl 19

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Datasheet Document History

01/20/03: Initial Datasheet

04/25/03: Page 11 Added Capacitance Derating drawing

Page 12 Changed tINS and tINR specs in AC Electrical Characteristics table

11/11/03: Page 10 Updated power numbers in DC Electrical Characteristics table

Page 12 Added tOFS symbol and parameter to AC Electrical Characteristics table

Page 21 Updated Collision Timing waveform

Page 22 Added Collision Detection Timing table and footnotes

Page 26 Updated HIGHZ function in System Interface Parameters table

Page 27 Added IDT Clock Solution table

04/08/04: Page 22 & 23 Clarified Sleep Mode Text and Waveforms

Page 1 & 28 Removed Preliminary status

Page 6 Added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode

02/07/06: Page 1 Added green availability to features

Page 7 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X

Page 27 Added green indicator to ordering information

07/28/08: Page 10 Corrected a typo in the DC Chars table footnotes

01/19/09: Page 28 Removed "IDT" from orderable part number

04/20/10: Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01

06/10/15: Page 3 & 4 Removed the date from all of the pin configurations BC256 & BF208

Page 26 Added T&R indicator and industrial temp footnote to Ordering Information

Product Discontinuation Notice - PDN# SP-17-02

Last time buy expires June 15, 2018

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

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02/08/18: