DS04-27402-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
POWER-VOLTAGE MONITORING IC
WITH WATCHDOG TIMER
MB3793-42
■
■■
■DESCRIPTION
The MB3793 is an integrated circuit to monitor power voltage; it incorporates a watchdog timer.
A reset signal is output when the pow er is cut or falls abruptly. When the power reco vers normally after resetting,
a pow er-on reset signal is output to microprocessor units (MPUs). An internal w atchdog timer with two inputs f or
system operation diagnosis can provide a fail-safe function for various application systems.
There is also a mask option that can detect voltages of 4.9 to 2.4V in 0.1-V steps.
The model number and package code are as shown below.
■
■■
■FEATURES
• Precise detection of power voltage fall: ±2.5%
• Detection voltage with hysteresis
• Low power dispersion: ICC = 27 µA (reference)
• Internal dual-input watchdog timer
• Watchdog timer halt function (by inhibition terminal)
• Independently-set watchdog and reset times
• Mask option for detection voltage (4.9 to 2.4 V, 0.1-V steps)
■
■■
■PACKAGES
Model No. Package code Detection voltage
MB3793-42 3793-A 4.2 V
8-pin plastic DIP 8-pin plastic SOP 8-pin plastic SOL
(DIP-8P-M01) (FPT-8P-M01) (FPT-8P-M02)
MB3793-42
2
■
■■
■PIN ASSIGNMENT
■
■■
■PIN DESCRIPTION
Pin No. Symbol Description Pin No. Symbol Description
1 RESET Outputs reset 5 VCC Power supply
2 CTW Sets monitoring time 6 INH Inhibits watchdog timer function
3 CTP Sets power-on reset hold time 7 CK2 Inputs clock 2
4 GND Ground 8 CK1 Inputs clock 1
RESET
CTW
CTP
GND
CK1
CK2
INH
VCC
(DIP-8P-M01)
(FPT-8P-M01)
(FPT-8P-M02)
(TOP VIEW)
1
2
3
4
8
7
6
5
MB3793-42
3
■
■■
■BLOCK DIAGRAM
CTP
RESET
INH
CTW
CK1
CK2
V
CC
GND
Comp. O
I
1
≅ 3 µAI
2
≅ 30 µA
R
1
≅
590 kΩ
Q
RSFF2
Q
S
R
Q
RSFF1
Q
S
R
Comp. S
−
+
V
S
V
REF
≅ 1.24 V R
2
≅
240 kΩ
+
−
3
1
6
2
8
74
5
To VCC of all blocks
Output
buffer
Pulse generator 1
Pulse generator 2
To GND of all blocks
Watchdog
timer
Reference
voltage
generator
MB3793-42
4
■
■■
■BLOCK FUNCTIONS
1. Comp. S
Comp. S is a comparator with hysteresis to compare the reference voltage with a voltage (VS) that is the result
of dividing the pow er voltage (VCC) by resistors R1 and R2. When VS falls below 1.24 V, a reset signal is output.
This function enables the MB3793 to detect an abnormality within 1 µs when the power is cut or falls abruptly.
2. Comp. O
Comp. O is a comparator to control the reset signal (RESET) output and compares the threshold voltage with
the v oltage at the CTP terminal for setting the po w er-on reset hold time . When the v oltage at the CTP terminal
exceeds the threshold voltage, resetting is canceled.
3. Reset output buffer
Since the reset (RESET) output buffer has CMOS organization, no pull-up resistor is needed.
4. Pulse generator
The pulse generator generates pulses when the voltage at the CK1 and CK2 clock terminals changes to High
from Low level (positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog
timer.
5. Watchdog timer
The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock terminals to monitor a
single clock pulse.
6. Inhibition terminal
The inhibition (INH) ter minal forces the watchdog timer on/off. When this ter minal is High level, the watchdog
timer is stopped.
7. Flip-flop circ uit
The flip-flop circuit RSFF1 controls charging and discharging of the powe r-on reset hold time setting capacity
(CTP). The flip-flop circuit RSFF2 switches the charging accelerator for charging CTP during resetting on/off. This
circuit only functions during resetting and does not function at power-on reset.
MB3793-42
5
■
■■
■ABSOLUTE MAXIMUM RATINGS
*: The power voltage is based on the ground voltage (0 V).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■
■■
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
(Ta = +25°C)
Parameter Symbol Rating Unit
Min. Max.
Power voltage* VCC −0.3 +7V
Input voltage*
CK1 VCK1
−0.3 +7VCK2 VCK2
INH VINH
Reset output voltage
(direct current) RESET IOL
IOH −10 +10 mA
Power dissipation (Ta ≤ +85°C) PD200 mW
Storage temperature Tstg −55 +125 °C
Parameter Symbol Value Unit
Min. Typ. Max.
Power supply voltage VCC 1.2 5.0 6.0 V
Reset (RESET) output current IOL
IOH −5+5mA
Power-on reset hold time setting capacity CTP 0.001 0.1 10 µF
Watchdog timer monitoring time setting capacity CTW 0.001 0.1 1 µF
Watchdog timer monitoring time tWD 0.1 1500 ms
Operating ambient temperature Ta −40 +25 +85 °C
MB3793-42
6
■
■■
■ELECTRICAL CHARACTERISTICS
1. DC Characteristics
*1: At cloc k input terminals CK1 and CK2, the pulse input frequency is 1 kHz and the pulse amplitude is 0 V to VCC.
*2: Inhibition input is at High level.
(VCC = +5 V , Ta = +25°C)
Parameter Symbol Conditions Value Unit
Min. Typ. Max.
Power current ICC1 Watchdog timer operation*127 50 µA
ICC2 Watchdog timer halt*225 45
Detection voltage
VSL VCC falling Ta = +25°C 4.10 4.20 4.30 V
Ta = −40 to +85°C 4.05 4.20 4.35
VSH VCC rising Ta = +25°C 4.20 4.30 4.40 V
Ta = −40 to +85°C 4.15 4.30 4.45
Detection voltage
hysteresis difference VSHYS VSH - VSL 50 100 150 mV
CK input threshold voltage VCIH (1.4) 1.9 (2.5) V
VCIL (0.8) 1.3 (1.8) V
CK input hysteresis VCHYS (0.4) 0.6 (0.8) V
INH input voltage VIIH 3.5 VCC V
VIIL 000.8V
Input current
(CK1,CK2,INH) IIH VCK = VCC 01.0µA
IIL VCK = 0 V −1.0 0 µA
Reset output voltage VOH IRESET = −5 mA 4.5 4.75 V
VOL IRESET = +5 mA 0.12 0.4 V
Reset-output minimum
power voltage VCCL IRESET = +50 µA0.8 1.2 V
MB3793-42
7
2. AC Characteristics
*: The voltage range is 10% to 90% at testing the reset output transition time.
(VCC = +5 V , Ta = +25°C)
Parameter Symbol Conditions Value Unit
Min. Typ. Max.
Power-on reset hold time tPR CTP = 0.1 µF 80 130 180 ms
Watchdog timer monitoring time tWD CTW = 0.01 µF
CTP = 0.1 µF7.5 15 22.5 ms
Watchdog timer reset time tWR CTP = 0.1 µF 5 10 15 ms
CK input pulse duration tCKW 500 ns
CK input pulse cycle tCKT 20 µs
Reset (RESET) output transition time Rising tr* CL = 50pF 500 ns
Falling tf* CL = 50pF 500 ns
MB3793-42
8
■
■■
■TIMING DIAGRAM
1. Basic operation (Positive clock pulse)
CTP
RESET
INH
CTW
CK1
CK2
V
SH
V
CC
V
SL
V
CCL
V
th
V
H
V
L
(1) (2) (3) (4) (5) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14)
t
PR
t
WD
t
PR
t
WR
t
CKW
MB3793-42
9
2. Basic operation (Negative clock pulse)
CTP
RESET
INH
CTW
CK1
CK2
VSH
VCC
VSL
VCCL
Vth
VH
VL
tPR tWD tPR
tWR
tCKW
(1) (2) (3) (4) (5) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14)
MB3793-42
10
3. Single-clock input monitoring (Positive clock pulse)
CTP
RESET
CTW
CK1
Vth
VH
VL
CK2
tWR
tCKW
tCKT
tWD
Note: The MB3793 can monitor only one clock.
The MB3793 checks the clock signal at every other input pulse. Therefore, set watchdog
timer monitor time tWD to the time that allows the MB3793 to monitor the period twice as
long as the input clock pulse.
MB3793-42
11
4. Inhibition operation (Positive clock pulse)
CTP
RESET
INH
CTW
CK1
CK2
VSH
VCC
VSL
VCCL
Vth
VH
VL
tPR tWD tPR
tWR
tCKW
(1) (2) (3) (4) (5) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14)
MB3793-42
12
5. Clock pulse input (Positive clock pulse)
6. Inhibition input rising and falling time
CTW
CK1
CK2
VH
VL
*1
*2
Note: The MB3793 watchdog timer monitors Clock 1 (CK1) and Clock 2 (CK2) pulses al-
ternately. When a CK2 pulse is detected after detecting a CK1 pulse, the monitor-
ing time setting capacity (CTW) switches to charging from discharging.
When two consecutive pulses occur on one side of this alternation before switch-
ing, the second pulse is ignored. In the above figure, pulses *1 and *2 are ignored.
INH
90 %
10 %
90 %
10 %
VCC
0 V
tfitri
MB3793-42
13
■
■■
■OPERATION SEQUENCE
The operation sequence is explained by using “■ TIMING DIAGRAM 1. Basic operation (Positive clock pulse)”.
The following item numbers correspond to the numbers in “■ TIMING DIAGRAM 1. Basic operation (Positive
clock pulse)”.
(1)When the power voltage (VCC) reaches about 0.8 V (VCCL), a reset signal is output.
(2)When VCC exceeds the rising-edge detection voltage (VSH), charging of power-on reset hold time setting
capacitance (CTP) is started. VSH is about 4.3 V.
(3)When the voltage at the CTP ter minal setting the power-on reset hold time exceeds the threshold voltage
(Vth), resetting is canceled and the v oltage at the RESET terminal changes to High le vel to start charging of
the watchdog timer monitoring time setting capacitance (CTW). Vth is about 3.6 V.
The power-on reset hold time (tPR) can be calculated by the following equation.
tPR (ms) ≈ A × CTP (µF)
Where, A is about 1300.
(4)When the voltage at the CTW terminal setting the monitoring time reaches High level (VH), CTW sw itches to
discharging from charging. VH is about 1.24 V (reference value).
(5)When clock pulses are input to the CK2 terminal during CTW discharging after clock pulses are input to the
CK1 terminal—positive-edge trigger, CTW switches to charging.
(6)If clock pulse input does not occur at either the CK1 or CK2 clock terminals during the watchdog timer
monitoring time (tWD), the CTW voltage falls below Lo w level (VL), a reset signal is output, and the voltage at
the RESET terminal changes to Low level. VL is about 0.24 V.
tWD can be calculated from the following equation.
tWD (ms) ≈ B × CTW (µF) + C × CTP (µF)
Where, B is about 1500. C is about 3; it is much smaller than B.
Hence, when CTP / CTW ≤ 10, the calculation can be simplified as follows:
tWD (ms) ≈ B × CTW (µF)
(7)When the v oltage of the CTP terminal exceeds V th again as a result of recharging CTP
, resetting is canceled
and the watchdog timer restarts monitoring.
The watchdog timer reset time (tWR) can be calculated by the following equation.
tWR (ms) ≈ D × CTP (µF)
Where, D is about 100.
(8)When VCC f alls below the rising-edge detection voltage (VSL), the v oltage of the CTP terminal falls and a reset
signal is output, and the voltage at the RESET terminal changes to Low level. VSL is about 4.2 V.
(9)When VCC exceeds VSH, CTP begins charging.
(10)When the voltage of the CTP terminal exceeds Vth, resetting is canceled and the watchdog timer restarts.
(11)When an inhibition signal is input (INH terminal is High level), the watchdog timer is halted forcibly.
In this case, VCC monitoring is continued without the watchdog timer.
The watchdog timer does not function unless this inhibition input is canceled.
(12)When the inhibition input is canceled (INH terminal is Low level), the watchdog timer restarts.
(13)When the VCC voltage falls below VSL after power-off, a reset signal is output.
(14)When the power voltage (VCC) falls below about 0.8 V (VCCL) , a reset signal is released.
Similar operation is also performed for negative clock-pulse input (“■ TIMING DIAGRAM 2. Basic operation
(Negative clock pulse)”).
Shor t-circuit the clock terminals CK1 and CK2 to monitor a single clock. The basic operation is the same but
the clock pulses are monitored at every other pulse (■ TIMING Diagram 3. Single-clock input monitoring).
MB3793-42
14
■
■■
■TYPICAL CHARACTERISTICS
40
35
30
25
20
15
10
MB3793-42
CTW CTP
VINH VCC
0.01 µF0.1 µF
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
(VINH = 0 V)
(VCC < VSH)
Ta = +25 °C
Ta = +85 °C
Ta = −40 °C
0012345678910
100
200
300
400
500 VRESET IRESET
Ta RON
98 mV +5 mA
−40 °C19.6 Ω
135 mV
+25 °C27 Ω
167 mV
+85 °C33.4 Ω
4.0 −20−40 0 20406080100
4.1
4.2
4.3
4.4
4.5
VSH
VSL
Ta = +25 °C
Ta = +85 °C
Ta = −40 °C
4.00−1−2−3−4−5−6−7−8−9−10
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
VRESET IRESET
Ta RON
4.800 V −5 mA
−40 °C40 Ω
4.750 V
+25 °C50 Ω
4.707 V
+85 °C58.6 Ω
Power Current - Power Voltage
Power current
ICC (µA)
Power voltage VCC (V)
Watchdog timer monitoring
Watchdog timer stopping
(VINH = VCC)
Reset Inhibited
Detection Voltage - Ambient Temperature
Detection voltage
VSH and VSL (V)
Ambient temperature Ta (°C)
Reset output current IRESET (mA)
Reset output voltage
VRESET (V)
Reset Output Voltage - Reset Output Current
(P-MOS side) Reset Output Voltage - Reset Output Current
(N-MOS side)
Reset output voltage
VRESET (mV)
Reset output current IRESET(mA)
f = 1 kHz
Duty = 10%
VL = 0 V
VH = VCC
MB3793-42
15
7
6
5
4
3
2
1
001234567
Ta = +85 °C
Ta = +25 °C
Ta = −40 °C
−40 −20 0 20 40 60 80 100
0
20
40
60
80
100
120
140
160
180
200
220
240
260
−40 −20 0 20 40 60 80 100
0
2
4
6
8
10
12
14
16
18
20
22
24
26
−40 −20 0 20 40 60 80 100
0
2
4
6
8
10
12
14
16
18
20
22
24
26
Reset Output Voltage - Power Voltage
Power voltage VCC (V)
Reset output voltage
VRESET (V)
Pull-up resistance: 100 kΩ
Reset-on Reset Time - Ambient Temperature
(when VCC rising)
Ambient temperature Ta (°C)
Power-on reset time
tPR (ms)
Watchdog Timer Reset Time - Ambient Temperature
(when monitoring) Watchdog Timer Monitoring Time - Ambient
Temperature
Ambient temperature Ta (°C) Ambient temperature Ta (°C)
Watchdog timer reset time
tWR (ms)
Watchdog timer monitoring time
tWD (ms)
MB3793-42
16
104
103
102
101
1
10 −1
10−410−310−210−1110
1102
Ta = −40 °C
Ta = +25 °C
Ta = +85 °C
103
102
101
1
10−1
10−410−310−210−1110
1102
10−2
Ta = −40 °C
Ta = +25 °C
Ta = +85 °C
103
102
101
1
10−1
10−410−310−210−1110
1
10−5
Ta = −40 °C
Ta = +25 °C
Ta = +85 °C
104
103
102
101
1
10−1
10−410−310−210−1110
1
10−5
CTP = 0.01 µF
CTP = 0.1 µF
CTP = 1 µF
Power-on Reset Time - CTP Capacitance Reset Time - CTP Capacitance
Power-on reset time
tPR (ms)
Power-on reset time setting capacitance
CTP (µF)
Power-on reset time setting capacitance
CTP (µF)
Watchdog Timer Monitoring Time - CTW Capacitance
(under Ta condition) Watchdog Timer Monitoring Time - CTW Capacitance
Watchdog timer monitoring time
tWD (ms)
Watchdog timer monitoring time setting capacitance
CTW (µF) Watchdog timer monitoring time setting capacitance
CTW (µF)
Watchdog timer monitoring time
tWD (ms) Reset Time
tWR (ms)
MB3793-42
17
■
■■
■STANDARD CONNECTION
Equation of time-setting capacitances (CTP and CTW) and set time
tPR (ms) ≈ A × CTP (µF)
tWD (ms) ≈ B × CTW (µF) + C × CTP (µF)
However, when CTP/CTW ≤ 10,
tWD (ms) ≈ B × CTW (µF)
tWR (ms) ≈ D × CTP (µF)
Value of A, B, C and D
(Example) When CTP = 0.1 µF and CTW = 0.01 µF,
tPR ≈ 130 [ms]
tWD ≈ 15 [ms]
tWR ≈ 10 [ms]
A B C D Remark
1300 1500 3100
VCC
VCC
CTW CTP
CTW
CTP CK1
CK2
INH GND
RESET
RESET VCC
CK
GND
RESET VCC
CK
GND
MB3793
3
5
1
6 4
2
8
7
Micro-
processor 1 Micro-
processor 2
MB3793-42
18
■
■■
■APPLICATION EXAMPLE
1. Monitoring Single Clock
2. Watchdog Timer Stopping
V
CC
V
CC
C
TW
C
TP
CTW
CTP CK1
CK2INH GND
RESET
RESET V
CC
CK
GND
MB3793
5
1
8
7
4
6
3
2
Micro-
processor
VCC
VCC
CTW CTP
CTW
CTP CK1
CK2GND
RESET
RESET VCC
CK
GND
RESET VCC
CK
GND
MB3793
5
1
8
7
4
6
3
2
INH
HALT HALT
Micro-
processor1 Micro-
processor2
MB3793-42
19
■
■■
■ORDERING INFORMATION
Part number Package Remarks
MB3793-42P 8-pin plastic DIP
(DIP-8P-M01)
MB3793-42PF 8-pin plastic SOP
(FPT-8P-M01)
MB3793-42PNF 8-pin plastic SOL
(FPT-8P-M02)
MB3793-42
20
■
■■
■PACKAGE DIMENSIONS
(Continued)
8-pin plastic DIP
(DIP-8P-M01)
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED D08006S-2C-3
0.89 +0.35
–0.30
–0.30
+0.40
9.40
–0
0.99 1.52 +0.30
–0
+.014
–.012
.035
.370 –.012
+.016
.060 –0
+.012
+.012
–0
.039
4.36(.172)MAX
3.00(.118)MIN
2.54(.100)
TYP
0.46±0.08
(.018±.003)
0.25±0.05
(.010±.002)
0.51(.020)MIN
7.62(.300)
TYP
15°MAX
1 PIN INDEX 6.20±0.25
(.244±.010)
+0.30
MB3793-42
21
(Continued)
8-pin plastic SOP
(FPT-8P-M01)
Dimensions in mm (inches)
C
2000 FUJITSU LIMITED F08002S-4C-5
Ø0.13(.005) M
"A"
0.68(.027)MAX
0.18(.007)MAX
0.20(.008)
0.50(.020)
Details of "A" part
0.45±0.10
0.05(.002)MIN
7.80±0.405.30±0.30
0.50±0.20
(.020±.008)
(STAND OFF)
(.018±.004)
(.209±.012) (.307±.016)
.250 –.008
+.010
–0.20
+0.25
6.35
.006 –.001
+.002
–0.02
+0.05
0.15
.268 –.008
+.016
–0.20
+0.40
6.80
INDEX
TYP
1.27(.050)
3.81(.150)REF
2.25(.089)MAX
(Mounting height)
0.10(.004)
MB3793-42
22
(Continued)
8-pin plastic SOL
(FPT-8P-M02)
Dimensions in mm (inches)
C
2000 FUJITSU LIMITED F08004S-2C-5
1.27(.050)TYP 0.42±0.10 0.20±0.05
0.15±0.10
3.90±0.30 6.00±0.40
0.50±.020
5.00±0.30
0.40(.016)
3.81(.150)REF
.199 –.008
+.010
–0.20
+0.25
5.05
Ø0.13(.005) M
(.017±.004) (.008±.002)
(.154±.012) (.236±.016) (.197±.012)
(.006±.004)
"A"
0.65(.026)MAX
0.18(.007)MAX
0.40(.016)
0.20(.008)
Details of "A" part
(.020±.008)
(STAND OFF)
45°
1.55±0.20(.061±.008)
(Mounting height)
0.10(.004)
MB3793-42
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0106
FUJITSU LIMITED Printed in Japan
