Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Stereo 2.7-W Audio Power Amplifier (with DC_Volume Control)
Features
•Low Operating Current with 14mA
•Improved Depop Circuitry to Eliminate
•Turn-on and Turn-off Transients in Outputs
High PSRR
•32 Steps Volume Adjustable by DC Voltage
with Hysteresis
•2W per Channel Output Power into 4ΩLoad
at 5V, BTL Mode
•Two Output Modes Allowable with BTL
and SE Modes Selected by SE/BTL pin
•Low Current Consumption in Shutdown Mode
(50µA)
•Short Circuit Protection
•Power Off Depop Circuit Integration
•PDIP-16 & SOP-16 Packages Available
•Lead Free Available (RoHS Compliant)
Applications
General Description
APA2065 is a monolithic integrated circuit, which
provides precise DC volume control, and a stereo
bridged audio power amplifiers capable of producing
2.7W(2.0W) into 3Ω with less than 10%(1.0%) THD+N.
The attenuator range of the volume control in APA2065
is from 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V)
with 32 steps. The advantage of internal gain setting
can be less components and PCB area. Both of the
depop circuitry and the thermal shutdown protection
circuitry are integrated in APA2065, that reduce pops
and clicks noise during power up or shutdown mode
operation. It also improves the power off pop noise
and protects the chip from being destroyed by over
temperature and short current failure. To simplify the
audio system design, APA2065 combines a stereo
bridge-tied loads (BTL) mode for speaker drive and a
stereo single-end (SE) mode for headphone drive into
a single chip, where both modes are easily switched
by the SE/BTL input control pin signal.
•NoteBook PC
•LCD Monitor or TV
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw2
Block Diagram
Shutdown
ckt
Volume
Control
SE/BTL
LOUT+
LOUT-
ROUT+
ROUT-
LIN-
RIN-
SE/BTL
SHUTDOWN
VOLUME
BYPASS BYPASS
POWER and
Depop circuit GND
VDD
Ordering and Marking Information
APA2065
Handling Code
Temp. Range
Package Code
Package Code
J : PDIP-16 K : SOP-16
Temp. Range
I : - 40 to 85 C
Handling Code
TU : Tube TR : Tape & Reel
TY : Tray
Lead Free Code
L : Lead Free Device Blank : Original Device
°
APA2065 J : APA2065
XXXXX XXXXX - Date Code
Lead Free Code
APA2065 K : APA2065
XXXXX XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw3
Min. Max.
Unit
Supply Voltage, VDD 4.5 5.5 V
SHUTDOWN 2
High level threshold voltage, VIH SE/BTL 4 V
SHUTDOWN 1.0
Low level threshold voltage, VIL SE/BTL 3 V
Common mode input voltage, VICM VDD-1.0
V
Symbol Parameter Value Unit
RTHJA Thermal Resistance from Junction to Ambient in Free Air
PDIP-16
SOP-16
45
60
K/W
K/W
Recommended Operating Conditions
Thermal Characteristics
(Over operating free-air temperature range unless otherwise noted.)
Symbol Parameter Rating Unit
VDD Supply Voltage Range -0.3 to 6 V
VIN Input Voltage Range, SE/BTL,
SHUTDOWN -0.3 to VDD+0.3 V
TA Operating Ambient Temperature Range -40 to 85 °C
TJ Maximum Junction Temperature Intermal Limited*1 °C
TSTG Storage Temperature Range -65 to +150 °C
TS Soldering Temperature,10 seconds 260 °C
VESD Electrostatic Discharge -3000 to 3000*2
-200 to 200*3 V
PD Power Dissipation Intermal Limited
Absolute Maximum Ratings
Note:
1.APA2065 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C
2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses
3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw4
Operating Characteristics, BTL mode VDD=5V,TA=25°C,RL=4Ω, Gain=2V/V (unless otherwise noted)
Electrical Characteristics
Operating Characteristics, SE mode VDD=5V,TA=25°C,RL=4Ω, Gain=1V/V (unless otherwise noted)
APA2065
Symbol
Parameter Test Condition Min.
Typ.
Max.
Unit
THD=10%, RL=8Ω, Fin=1kHz 400
THD=10%, RL=32Ω, Fin=1kHz 110
THD=1%, RL=8Ω, Fin=1kHz 320
PO Maximum Output Power
THD=1%, RL=32Ω, Fin=1kHz 90
mW
PO=250mW, RL=8Ω, Fin=1kHz 0.08
THD+N
Total Harmonic Distortion Plus
Noise PO=75mW, RL=32Ω, Fin=1kHz 0.08
%
PSRR
Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF,
Fin=120Hz 48
dB
Xtalk Channel Separation CB=1µF, RL=32Ω, Fin=1kHz 100
dB
S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_wieght
100
dB
VDD=5V, -20°C<TA<85°C (unless otherwise noted)
APA2065
Symbol
Parameter Test Condition Min.
Typ.
Max.
Unit
VDD Supply Voltage 4.5
5.5
V
SE/BTL=0V 14
25
IDD Supply Current SE/BTL=5V 8.0
15
mA
ISD Supply Current in Shutdown
Mode SE/BTL=5V
SHUTDOWN=0V 50
µA
IIH High input Current 900
nA
IIL Low Input Current 900
nA
VOS Output Differential Voltage 5 mV
APA2065
Symbol
Parameter Test Condition Min.
Typ.
Max.
Unit
THD=10%, RL=3Ω, Fin=1kHz 2.7
THD=10%, RL=4Ω, Fin=1kHz 2.3
THD=10%, RL=8Ω, Fin=1kHz 1.5
THD=1%, RL=3Ω, Fin=1kHz 2.0
THD=1%, RL=4Ω, Fin=1kHz 1.9
PO Maximum Output Power
THD=0.5%, RL=8Ω, Fin=1kHz 1 1.1
W
PO=1.5W, RL=4Ω, Fin=1kHz 0.05
THD+N
Total Harmonic Distortion Plus
Noise PO=1W, RL=8Ω, Fin=1kHz 0.07
%
PSRR
Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF,
Fin=120Hz 60
dB
Xtalk Channel Separation CB=1µF, RL=8Ω, Fin=1kHz 90
dB
S/N Signal to Noise Ratio PO=1.1W, RL=8Ω, A_wieght 95
dB
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw5
Pin Description
Pin Name Config.
Description
GND Ground connection, Connected to thermal pad.
VOLUME I/P Input signal for internal volume gain setting.
LOUT+ O/P Left channel positive output in BTL mode and SE mode.
LIN- I/P Left channel input terminal
LOUT- O/P Left channel negative output in BTL mode and high impedance in SE mode.
BYPASS Bias voltage generator
SE/BTL I/P Output mode control input, high for SE output mode and low for BTL mode.
ROUT- O/P Right channel negative output in BTL mode and high impedance in SE
mode.
VDD Supply voltage for internal circuit excepting power amplifier.
ROUT+ O/P Right channel positive output in BTL mode and SE mode.
SHUTDOWN
I/P It will be into shutdown mode when pull low.
RIN- I/P Right channel input terminal
Pin Function Description
SE/BTL SHUTDOWN Operating mode
X L Shutdown mode
L H BTL out
H H SE out
Control Input Table
14 SE/ BTL
GND 4 13 GND
LIN- 8
GND 5
15 ROUT-
VOLUME 6 12 GND
SHUTDOWN 2
RIN- 3
16 VDD
11 BYPASS
10 LOUT-
LOUT+ 7
ROUT+ 1
9 VDD
APA2065
PDIP-16
10 SE/BTL
16 GND
9 GND
LIN- 4
GND 1
11 ROUT-
VOLUME 2
GND 8
14 SHUTDOWN
15 RIN-
12 VDD
BYPASS 7
LOUT- 6
LOUT+ 3 13 ROUT+
VDD 5 APA2065
SOP-16
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw6
Typical Application Circuit
4Ω
4Ω
Ring
Headphone Jack
Sleeve
Control
Pin
Tip
SE/BTL
2.2µF
1µF
1µF220µF
220µF
1kΩ
1kΩ
L-Ch
input
R-Ch
input
VDD
100kΩ
Shutdown
Signal
VDD
VDD GND
100µF0.1µF
Shutdown
ckt
Volume
Control
SE/BTL
LOUT+
LOUT-
ROUT+
ROUT-
LIN-
RIN-
SE/BTL
SHUTDOWN
VOLUME
BYPASS BYPASS
VDD
50kΩ
100kΩ
Volume Control Table_BTL Mode
Gain(dB) High(V) Low(V) Hysteresis(mV)
Recommended Voltage(V)
20 0.12 0.00 0
18 0.23 0.17 52 0.20
16 0.34 0.28 51 0.31
14 0.46 0.39 50 0.43
12 0.57 0.51 49 0.54
10 0.69 0.62 47 0.65
8 0.80 0.73 46 0.77
6 0.91 0.84 45 0.88
4 1.03 0.96 44 0.99
2 1.14 1.07 43 1.10
0 1.25 1.18 41 1.22
-2 1.37 1.29 40 1.33
-4 1.48 1.41 39 1.44
-6 1.59 1.52 38 1.56
-8 1.71 1.63 37 1.67
Supply Voltage Vdd=5V
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw7
Volume Control Table_BTL Mode (Cont.)
Gain(dB) High(V) Low(V) Hysteresis(mV)
Recommended Voltage(V)
-10 1.82 1.74 35 1.78
-12 1.93 1.85 34 1.89
-14 2.05 1.97 33 2.01
-16 2.16 2.08 32 2.12
-18 2.28 2.19 30 2.23
-20 2.39 2.30 29 2.35
-22 2.50 2.42 28 2.46
-24 2.62 2.53 27 2.57
-26 2.73 2.64 26 2.69
-28 2.84 2.75 24 2.80
-30 2.96 2.87 23 2.91
-32 3.07 2.98 22 3.02
-34 3.18 3.09 21 3.14
-36 3.30 3.20 20 3.25
-38 3.41 3.32 18 3.36
-40 3.52 3.43 17 3.48
-80 5.00 3.54 16 5
Supply Voltage Vdd=5V
0.01
10
0.1
1
20 20k100 1k
Typical Characteristics
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VDD=5V
RL=3Ω
Po=1.75W
BTL
AV=2
AV=5
AV=10
0.01
10
0.1
1
10m 3100m 1 2
THD+N vs. Output Power
Output Power (W)
THD+N (%)
VDD=5V
RL=3Ω
AV=2
BTL
f=20Hz
f=20kHz
f=1kHz
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw8
Typical Characteristics
0.01
10
0.1
1
20 20k50 100 200 500 1k 2k 5k
THD+N vs. Frequency
Frequency (W)
THD+N (%)
VDD=5V
RL=4Ω
Po=1.5W
BTL
0.01
10
0.1
1
100m 3200m 500m 800m 2
THD+N vs. Output Power
Output Power (W)
THD+N (%)
VDD=5V
RL=4Ω
AV=2
BTL
f=20Hz
f=20kHz
f=1kHz
AV=2
AV=5
AV=10
0.01
10
0.1
1
10m 2100m 1
THD+N vs. Output Power
Output Power (W)
THD+N (%)
VDD=5V
RL=8Ω
AV=2
BTL
f=20Hz
f=20kHz
f=1kHz
0.01
10
0.1
1
20 20k100 1k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VDD=5V
RL=8Ω
Po=1.0W
BTL
AV=2
AV=5
AV=10
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw9
0.01
10
0.1
1
20 20k100 1k
Typical Characteristics (Cont.)
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VDD=5V
RL=8Ω
Po=250mW
SE
AV=1AV=5
AV=2.5
0.01
10
0.1
1
10m 500m
100m
THD+N vs. Output Power
Output Power (W)
THD+N (%)
VDD=5V
RL=8Ω
AV=2
BTL
f=20Hz
f=20kHz
f=1kHz
0.01
10
0.1
1
20 20k50 100 200 500 1k 2k 5k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VDD=5V
RL=16Ω
Po=100mW
SE
AV=2AV=1
AV=2.5
0.01
10
0.1
1
10m 300m
100m
THD+N vs. Output Power
Output Power (W)
THD+N (%)
VDD=5V
RL=16Ω
AV=1
BTL
f=20Hzf=20kHz
f=1kHz
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw10
0.01
10
0.1
1
5
10m 200m50m 100m
Typical Characteristics (Cont.)
THD+N vs. Output Power
Output Power (W)
THD+N (%)
VDD=5V
RL=32Ω
AV=1
BTL
f=20Hz
f=20kHz
f=1kHz
0.01
10
0.1
1
20 20k100 1k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
VDD=5V
RL=32Ω
Po=75mW
SE
AV=1
AV=5
AV=2.5
Note:Dropout voltage definition:VIN-VOUT when VOUT is 2% below the value of VOUT for VIN= VOUT+1V
0.01
10
0.1
1
100m 3500m 12
0.01
10
0.1
1
20 20k100 1k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
THD+N vs. Output Swing
Output Swing (VRMS)
THD+N (%)
VDD=5V
RL=10Ω
Vo=1VRMS
SE
VDD=5V
RL=10Ω
AV=1
SE
f=20Hz
f=20kHz
f=1kHz
AV=1
AV=5
AV=2.5
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw11
Typical Characteristics (Cont.)
-120
+0
-100
-80
-60
-40
-20
20 20k100 1k
Crosstalk vs. Frequency
Frequency (Hz)
Crosstalk (dB)
VDD=5V
RL=32Ω
Po=75mW
AV=1
SE
R-ch to L-chL-ch to R-ch
-120
+0
-100
-80
-60
-40
-20
20 20k100 1k
Crosstalk vs. Frequency
Frequency (Hz)
Crosstalk (dB)
VDD=5V
RL=8Ω
Po=1.0W
AV=2
BTL
R-ch to L-ch
L-ch to R-ch
1u
100u
2u
5u
10u
20u
50u
20 20k100 1k
Noise Floor vs. Frequency
Frequency (Hz)
Noise Floor (µVRMS)
VDD=5V
RL=32Ω
AV=1
SE
No Filter
A-Weight
1u
100u
2u
5u
10u
20u
50u
20 20k100 1k
Noise Floor vs. Frequency
Frequency (Hz)
Noise Floor (µVRMS)
VDD=5V
RL=8Ω
AV=2
BTL
No Filter
A-Weight
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw12
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
1u
100u
2u
5u
10u
20u
50u
20 20k100 1k
Typical Characteristics (Cont.)
Noise Floor vs. Frequency
Frequency (Hz)
Power Dissipation vs. Output Power
Output Power (W)
Power Dissipation (W)
Noise Floor (µVRMS)
VDD=5V
RL=10KΩ
AV=1
SE
No Filter
A-Weight
VDD=5V
AV=1
SE
RL=32Ω
RL=16Ω
RL=8Ω
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
00.5 11.5 22.5
Power Dissipation vs. Output Power
Output Power (W)
Power Dissipation (W)
VDD=5V
AV=2
BTL
RL=3Ω
RL=4Ω
RL=8Ω
2.5
5
7.5
10
12.5
15
17.5
20
11.5 22.5 33.5 44.5 55.5
Supply Current vs. Supply Voltage
Supply Voltage (V)
Suuply Current (mA)
No Load
SE
BTL
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw13
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.5 33.5 44.5 55.5
Output Power vs. Supply Voltage
Supply Voltage (V)
Output Power (W)
RL=8Ω
AV=2
BTL
THD+N=10%
THD+N=1%
0
20
40
60
80
100
120
140
160
2.5 33.5 44.5 55.5
Typical Characteristics (Cont.)
Output Power vs. Supply Voltage
Supply Voltage (V)
Output Power (mW)
RL=32Ω
AV=1
SE
THD+N=10%
THD+N=1%
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
4 8 1216202428323640444852566064
0
0.5
1
1.5
2
2.5
3
4 8 1216202428323640444852566064
Output Power vs. Load Resistance
Load Resistance (Ω)
Output Power (W)
Output Power vs. Load Resistance
Load Resistance (Ω)
Output Power (W)
VDD=5V
AV=2
BTL
THD+N=10%
THD+N=1%
VDD=5V
AV=1
SE
THD+N=10%
THD+N=1%
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw14
-6
+6
-4
-2
+0
+2
+4
20 20k100 1k
-0
+12
+2
+4
+6
+8
+10
20 20k100 1k
Typical Characteristics (Cont.)
Close Loop Response
Frequency (Hz)
Close Loop Response
Frequency (Hz)
Loop Gain (dB)
Loop Gain (dB)
AV=2
AV=5
AV=10
VDD=5V
RL=32Ω
AV=1
SE
CO=330µF
AV=1
AV=2.5
AV=5
VDD=5V
RL=8Ω
AV=2
BTL
CO=330µF
-80
+0
-60
-40
-20
20 20k100 1k
TT
PSRR vs. Frequency
Frequency (Hz)
Ripple Rejection Ratio (dB)
VDD=5V
Vin=100mVRMS
RL=8Ω
Cbypass=2.2µF
BTL
SE
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw15
Application Descriptions
BTL Operation
The APA2065 output stage (power amplifier) has two
pairs of operational amplifiers internally, allowed for
different amplifier configurations.
Vbias
Circuit
OUT+
OUT- RL
OP1
OP2
Volume Control
amplifier output
signal
Figure 1: APA2065 internal configuration
(each channel)
The power amplifier’s OP1 gain is setting by internal
unity-gain and input audio signal is come from internal
volume control amplifier, while the second amplifier
OP2 is internally fixed in a unity-gain, inverting
configuration. Figure 1 shows that the output of OP1
is connected to the input to OP2, which results in the
output signals of with both amplifiers with identical in
magnitude, but out of phase 180°. Consequently, the
differential gain for each channel is 2 x (Gain of SE
mode).
By driving the load differentially through outputs OUT+
and OUT-, an amplifier configuration commonly referred
to as bridged mode is established. BTL mode operation
is different from the classical single-ended SE amplifier
configuration where one side of its load is connected
to ground.
A BTL amplifier design has a few distinct advantages
over the SE configuration, as it provides differential
drive to the load, thus doubling the output swing for a
specified supply voltage.
Four times the output power same conditions. A BTL
configuration, such as the one used in APA2065, also
creates a second advantage over SE amplifiers. Since
the differential outputs, ROUT+, ROUT-, LOUT+, and
LOUT-, are biased at half-supply, no need DC voltage
exists across the load. This eliminates the need for an
output coupling capacitor which is required in a single
supply, SE configuration.
Single-Ended Operation
Consider the single-supply SE configuration shown
Application Circuit. A coupling capacitor is required to
block the DC offset voltage from reaching the load.
These capacitors can be quite large (approximately
33µF to 1000µF) so they tend to be expensive, occupy
valuable PCB area, and have the additional drawback
of limiting low-frequency performance of the system
(refer to the Output Coupling Capacitor). The rules
described still hold with the addition of the following
relationship:
Output SE/BTL Operation
The ability of the APA2065 to easily switch between
BTL and SE modes is one of its most important costs
saving features. This feature eliminates the requirement
for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode
but external headphone or speakers must be
accommodated.
Internal to the APA2065, two separate amplifiers drive
OUT+ and OUT- (see Figure 1). The SE/BTL input
controls the operation of the follower amplifier that drives
LOUT- and ROUT-.
• When SE/BTL is held low, the OP2 is turn on and
the APA2065 is in the BTL mode.
1
Cbypass x 125kΩ≤1
RiCi << 1
RLCC(1)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw16
Application Descriptions (Cont.)
In Figure 2, input SE/BTL operates as follows :
When the phonejack plug is inserted, the 1kΩ resistor
is disconnected and the SE/BTL input is pulled high
and enables the SE mode. When the input goes high,
the OUT- amplifier is shutdown causing the speaker to
mute. The OUT+ amplifier then drives through the
output capacitor (CC) into the headphone jack. When
there is no headphone plugged into the system, the
contact pin of the headphone jack is connected from
the signal pin,
the voltage divider set up by resistors
100kΩ and 1kΩ.
Resistor 1kΩ then pulls low the SE/BTL pin, enabling
the BTL function.
Volume Control Function
APA2065 has an internal stereo volume control whose
setting is a function of the DC voltage applied to the
Output SE/BTL Operation (Cont.)
APA2021 volume control curve
-44
-40
-36
-32
-28
-24
-20
-16
-12
-8
-4
0
4
8
12
16
20
00.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8 22.2 2.4 2.6 2.8 33.2 3.4 3.6 3.8
(V)
Gain_BTL mode
Forward
Backward
Figure 3: Gain setting vs VOLUME pin voltage
Ring
Headphone Jack
Sleeve
Control
Pin
Tip
1kΩ
VDD
100kΩ
SE/BTL
Figure 2: SE/BTL input selection by phonejack plug
• When SE/BTL is held high, the OP2 is in a high
output impedance state, which configures the
APA2065 as SE driver from OUT+. IDD is reduced by
approximately one-half in SE mode.
Control of the SE/BTL input can be a logic-level TTL
source or a resistor divider network or the stereo head-
phone jack with switch pin as shown in Application
Circuit.
VOLUME input pin. The APA2065 volume control
consists of 32 steps that are individually selected by
a variable DC voltage level on the VOLUME control
pin. The range of the steps, controlled by the DC
voltage, are from 20dB to -80dB. Each gain step
corresponds to a specific input voltage range, as shown
in table. To minimize the effect of noise on the volume
control pin, which can affect the selected gain level,
hysteresis and clock delay are implemented. The
amount of hysteresis corresponds to half of the step
width, as shown in volume control graph.
For highest accuracy, the voltage shown in the
‘recommended voltage’ column of the table is used
to select a desired gain. This recommended voltage
is exactly halfway between the two nearest transitions.
The gain levels are 2dB/step from 20dB to -40dB in
BTL mode, and the last step at -80dB as mute mode.
Input Resistance, Ri
The gain for each audio input of the APA2065 is set by
the internal resistors (Ri and Rf) of volume control
amplifier in inverting configuration.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw17
Ri vs Gain(BTL)
0
20
40
60
80
100
120
-40 -30 -20 -10 010 20
Gain(dB)
Ri(kΩ)
Application Descriptions (Cont.)
BTL mode operation brings the factor of 2 in the gain
equation due to the inverting amplifier mirroring the
voltage swing across the load. For the varying gain
setting, APA2065 generates each input resistance
on figure 4. The input resistance will affect the low
frequency performance of audio signal. The minmum
input resistance is 10kΩ when gain setting is 20dB
and the resistance will ramp up when close loop gain
below 20dB. The input resistance has wide variation
(+/-10%) caused by process variation.
Figure 4: Input resistance vs Gain setting
RF
Ri (3)
BTL Gain=-2 x
Input Capacitor, Ci
In the typical application an input capacitor, Ci, is
required to allow the amplifier to bias the input signal to
the proper DC level for optimum operation. In this case,
Ci and the minimum input impedance Ri (10kΩ) form a
high-pass filter with the corner frequency determined in
the follow equation:
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the example where Ri is 10kΩ and the
specification calls for a flat bass response down to
100Hz. Equation is reconfigured as follow :
Consider to input resistance variation, the Ci is 0.16µF
so one would likely choose a value in the range
of 0.22µF to 1.0µF.
A further consideration for this capacitor is the leakage
path from the input source through the input network
(Ri+Rf, Ci) to the load. This leakage current creates a
DC offset voltage at the input to the amplifier that
reduces useful headroom, especially in high gain
applications. For this reason a low-leakage tantalum
or ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as
the DC level there is held at VDD/2, which is likely higher
that the source DC level. Please note that it is important
to confirm the capacitor polarity in the application.
Effective Bypass Capacitor, Cbypass
As other power amplifiers, proper supply bypassing is
critical for low noise performance and high power
supply rejection.
The capacitors located on both the bypass and power
supply pins should be as close to the device as
possible. The effect of a larger bypass capacitor will
improve PSRR due to increased supply stability.
Typical applications employ a 5V regulator with 1.0µF
and a 0.1µF bypass capacitor as supply filtering. This
does not eliminate the need for bypassing the supply
nodes of the APA2065. The selection of bypass
capacitors, especially Cbypass, is thus dependent
upon desired PSRR requirements, click and pop
performance.
Ci=1
2πx10kΩxfC(5)
SE Gain =RF
Ri (2)
AV=-
Input Resistance, Ri (Cont.)
FC(highpass)=1
2πx10kΩxCi (4)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw18
Application Descriptions (Cont.)
To avoid start-up pop noise occurred, the bypass
voltage should rise slower than the input bias voltage
and the relationship shown in equation (6) should be
maintained.
The bypass capacitor is fed thru from a 125kΩ resistor
inside the amplifier and the 100kΩ is maximum input
resistance of (Ri+ Rf). Bypass capacitor, Cb, values of
3.3µF to 10µF ceramic or tantalum low-ESR capacitors
are recommended for the best THD and noise
performance.
The bypass capacitance also effects to the start up
time. It is determined in the following equation:
1
Cbypass x 125kΩ<< 1
100kΩ x Ci (6)
Tstart up = 5 x (Cbypass x 125KΩ)(7)
Effective Bypass Capacitor, Cbypass (Cont.)
Output Coupling Capacitor, Cc
In the typical single-supply SE configuration, an output
coupling capacitor (Cc) is required to block the DC
bias at the output of the amplifier thus preventing DC
currents in the load. As with the input coupling capacitor,
the output coupling capacitor and impedance of the
load form a high-pass filter governed by equation.
FC(highpass)=2πRLCC(8)
1
For example, a 330µF capacitor with an 8Ω speaker
would attenuate low frequencies below 60.6Hz.The
main disadvantage, from a performance standpoint, is
the load impedance is typically small, which drives
the low-frequency corner higher degrading the bass
response. Large values of CC are required to pass low
frequencies into the load.
Power Supply Decoupling, Cs
The APA2065 provides two independent power inputs
for right channel and left channel used. PVDD is used
for power amplifier only and VDD is used for volume
control amplifier and internal circuit excepting power
amplifier. The APA2065 is a high-performance
CMOS audio amplifier that requires adequate power
supply decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power supply
decoupling also prevents the oscillations causing by
long lead length between the amplifier and the speaker.
The optimum decoupling is achieved by using two
different type capacitors that target on different type
of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash
on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1µF placed as
close as possible to the device VDD lead works best.
For filtering lower-frequency noise signals, a large
aluminum electrolytic capacitor of 10µF or greater
placed near the audio power amplifier is recommended.
Optimizing Depop Circuitry
Circuitry has been included in the APA2065 to minimize
the amount of popping noise at power-up and when
coming out of shutdown mode. Popping occurs
whenever a voltage step is applied to the speaker. In
order to eliminate clicks and pops, all capacitors must
be fully discharged before turn-on. Rapid on/off
switching of the device or the shutdown function will
cause the click and pop circuitry.
The value of Ci will also affect turn-on pops (Refer to
Effective Bypass Capacitance). The bypass voltage
ramp up should be slower than input bias voltage.
Although the bypass pin current source cannot be
modified, the size of Cbypass can be changed to alter
the device turn-on time and the amount of clicks and
pops. By increasing the value of Cbypass, turn-on pop
can be reduced. However, the tradeoff for using a larger
bypass capacitor is to increase the turn-on time for
this device. There is a linear relationship between the
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw19
Application Descriptions (Cont.)
size of Cbypass and the turn-on time. In a SE
configuration, the output coupling capacitor, CC, is of
particular concern.
This capacitor discharges through the internal 10kΩ
resistors. Depending on the size of CC, the time
constant can be relatively large. To reduce transients
in SE mode, an external 1kΩ resistor can be placed in
parallel with the internal 10kΩ resistor. The tradeoff
for using this resistor is an increase in quiescent current.
In the most cases, choosing a small value of Ci in the
range of 0.33µF to 1µF, Cb being equal to 4.7µF and
an external 1kΩ resistor should be placed in parallel
with the internal 10kΩ resistor should produce a
virtually clickless and popless turn-on.
A high gain amplifier intensifies the problem as the
small delta in voltage is multiplied by the gain. So it is
advantageous to use low-gain configurations.
Shutdown Function
In order to reduce power consumption while not in use,
the APA2065 contains a shutdown pin to externally
turn off the amplifier bias circuitry. This shutdown
feature turns the amplifier off when a logic low is placed
on the SHUTDOWN pin. The trigger point between a
logic high and logic low level is typically 2.0V. It is
best to switch between ground and the supply VDD
to provide maximum device performance.
By switching the SHUTDOWN pin to low, the amplifier
enters a low-current state, IDD<50µA. On normal
operating, SHUTDOWN pin pull to high level to keeping
the IC out of the shutdown mode. The SHUTDOWN
pin should be tied to a definite voltage to avoid unwanted
state changes.
Clock Generator
APA2065 integrates a clock block 130kHz to avoid
Optimizing Depop Circuitry (Cont.)volume control function abnormal when VOLUME
control signal with spike or noise. APA2065 changes
each step of volume gain after four clock cycles to
make sure control signal ready.
BTL Amplifier Efficiency
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the power
supply to the power delivered to the load.
The following equations are the basis for calculating
amplifier efficiency.
Where :
Efficiency of a BTL configuration :
Efficiency =PSUP
PO
PO = =
RL
VORMS x VORMS2RL
VPxVP
VORMS =√2
VP
PSUP = VDD x IDDAVG = VDD x2VP
πRL
( ) / (VDD x ) =
PO
PSUP=VPxVP
2RL2VP
πRLπVP
4VDD
Note that the efficiency of the amplifier is quite low for
lower power levels and rises sharply as power to the
load is increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that
the internal dissipation at full output power is less than
in the half power range. Calculating the efficiency for a
specific system is the key to proper power supply
design. For a stereo 1W audio system with 8Ω loads
and a 5V supply, the maximum draw on the power
supply is almost 3W.
A final point to remember about linear amplifiers (either
SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when
possible. Note that in equation, VDD is in the
(9)
(10)
(11)
(12)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw20
Application Descriptions (Cont.)
Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)
0.25 31.25 0.16 2.00 0.55
0.50 47.62 0.21 2.83 0.55
1.00 66.67 0.30 4.00 0.5
1.25 78.13 0.32 4.47 0.35
**High peak voltages cause the THD to increase.
Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL
Systems
BTL Amplifier Efficiency (Cont.)
Power Dissipation
Whether the power amplifier is operated in BTL or SE
modes, power dissipation is a major concern. In
equation13 states the maximum power dissipation
point for a SE mode operating at a given supply
voltage and driving a specified load.
SE mode : PD,MAX=(13)
In BTL mode operation, the output voltage swing is
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the same
given conditions is 4 times as in SE mode.
BTL mode : PD,MAX=(14)
4VDD
2π RL
2
2
Since the APA2065 is a dual channel power amplifier,
the maximum internal power dissipation is 2 times
that both of equations depending on the mode of
operation. Even with this substantial increase in power
dissipation, the APA2065 does not require extra
heatsink. The power dissipation from equation14,
For DIP-16 package with thermal pad, the thermal
resistance (θJA) is equal to 45οC/W.
Since the maximum junction temperature (TJ,MAX) of
APA2065 is 150οC and the ambient temperature (TA)
is defined by the power system design, the maximum
power dissipation which the IC package is able to
handle can be obtained from equation15.
Once the power dissipation is greater than the
maximum limit (PD,MAX), either the supply voltage
(VDD) must be decreased, the load impedance (RL)
must be increased or the ambient temperature
should be reduced.
TJ,MAX - TA
θJA
PD,MAX=(15)
VDD
2π RL
2
2
denominator. This indicates that as VDD goes down,
efficiency goes up. In other words, use the efficiency
analysis to choose the correct supply voltage and
speaker impedance for the application.
assuming a 5V-power supply and an 8Ω load, must
not be greater than the power dissipation that results
from the equation15:
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw21
Packaging Information
PDIP-16 pin ( Reference JEDEC Registration MS-001)
Millimeters Inches
Dim Min. Max. Min. Max.
A - 5.32 - 0.210
A1 0.38 - 0.015 -
A2 3.17 3.42 0.125 0.135
A3 2.92 3.80 0.115 0.150
b 0.36 0.56 0.014 0.022
b2 1.14 1.78 0.045 0.070
b3 0.76 1.14 0.030 0.045
c 0.20 0.36 0.008 0.014
D 18.632 19.646 0.735 0.775
E 7.605BSC 0.300BSC
E1 6.223 6.477 0.245 0.255
e 2.54BSC 0.100BSC
eB 8.492 9.506 0.335 0.375
Q1 1.397 1.651 0.055 0.065
s 0.58 0.84 0.023 0.033
α 3° 8° 3° 8°
D
E1
E
α
A2
A1
A3
b3
b
b2
eB
c
Q1A
e
s
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw22
Package Information
SO – 300mil ( Reference JEDEC Registration MS-013)
Millimeters Variations- D Inches Variations- D
Dim
Min. Max. Variations Min. Max. Dim Min. Max. Variations Min. Max.
A2.35 2.65 SO-16 10.10 10.50 A0.093 0.1043 SO-16 0.398 0.413
A1 0.10 0.30 SO-18 11.35 11.76 A1 0.004 0.0120 SO-18 0.447 0.463
B0.33 0.51 SO-20 12.60 13 B0.013 0.020 SO-20 0.496 0.512
DSee variations SO-24 15.20 15.60 DSee variations SO-24 0.599 0.614
E7.40 7.60 SO-28 17.70 18.11 E0.2914 0.2992 SO-28 0.697 0.713
e1.27BSC SO-14 8.80 9.20 e0.050BSC SO-14 0.347 0.362
H10 10.65 H0.394 0.419
L0.40 1.27 L0.016 0.050
NSee variations NSee variations
φ 1 0°8°φ 1 0°8°
N
1 2 3
EH
D
L
GAUGE
PLANE
1
eBA1
A
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw23
Physical Specifications
t 25 C to Peak
tp
Ramp-up
tL
Ramp-down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)
Classificatin Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classificatioon Temperature (Tp)
See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw24
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 SEC
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Reliability Test Program
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Classificatin Reflow Profiles(Cont.)
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm 3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Carrier Tape & Reel Dimensions
t
Ao
E
W
Po P
Ko
Bo
D1
D
F
P1
Copyright ANPEC Electronics Corp.
Rev. A.4 - Aug., 2005
APA2065
www.anpec.com.tw25
Application Carrier Width Cover Tape Width Devices Per Reel
SOP- 16 24 21.3 1000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Carrier Tape & Reel Dimensions(Cont.)
A
J
B
T2
T1
C
Application
A
B
C
J
T1
T2
W
P
E
330 ± 1
100 +2
13+ 0.5
2 ± 0.5
16.4 +0.3
-0.2
2.5 ± 0.5
16±
0.2
12± 0.1
1.75±0.1
F D D1 Po P1 Ao Bo Ko t
SOP- 16
7.5± 0.1
1.5 +0.1
1.5+ 0.25
4.0 ± 0.1
2.0 ± 0.1
10.9 ± 0.1
10.8±
0. 1
3.0± 0.1
0.3±0.013
(mm)
Cover Tape Dimensions
