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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J –OCTOBER 2011–REVISED APRIL 2016
AM335x Sitara™ Processors
1 Device Overview
1
1.1 Features
1
• Up to 1-GHz Sitara™ ARM®Cortex®-A8 32‑Bit
RISC Processor
– NEON™ SIMD Coprocessor
– 32KB of L1 Instruction and 32KB of Data Cache
With Single-Error Detection (Parity)
– 256KB of L2 Cache With Error Correcting Code
(ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
– Emulation and Debug - JTAG
– Interrupt Controller (up to 128 Interrupt
Requests)
• On-Chip Memory (Shared L3 RAM)
– 64KB of General-Purpose On-Chip Memory
Controller (OCMC) RAM
– Accessible to All Masters
– Supports Retention for Fast Wakeup
• External Memory Interfaces (EMIF)
– mDDR(LPDDR), DDR2, DDR3, DDR3L
Controller:
– mDDR: 200-MHz Clock (400-MHz Data Rate)
– DDR2: 266-MHz Clock (532-MHz Data Rate)
– DDR3: 400-MHz Clock (800-MHz Data Rate)
– DDR3L: 400-MHz Clock (800-MHz Data
Rate)
– 16-Bit Data Bus
– 1GB of Total Addressable Space
– Supports One x16 or Two x8 Memory Device
Configurations
– General-Purpose Memory Controller (GPMC)
– Flexible 8-Bit and 16-Bit Asynchronous
Memory Interface With up to Seven Chip
Selects (NAND, NOR, Muxed-NOR, SRAM)
– Uses BCH Code to Support 4-, 8-, or 16-Bit
ECC
– Uses Hamming Code to Support 1-Bit ECC
– Error Locator Module (ELM)
– Used in Conjunction With the GPMC to
Locate Addresses of Data Errors from
Syndrome Polynomials Generated Using a
BCH Algorithm
– Supports 4-, 8-, and 16-Bit per 512-Byte
Block Error Location Based on BCH
Algorithms
• Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRU-ICSS)
– Supports Protocols such as EtherCAT®,
PROFIBUS, PROFINET, EtherNet/IP™, and
More
– Two Programmable Real-Time Units (PRUs)
– 32-Bit Load/Store RISC Processor Capable
of Running at 200 MHz
– 8KB of Instruction RAM With Single-Error
Detection (Parity)
– 8KB of Data RAM With Single-Error Detection
(Parity)
– Single-Cycle 32-Bit Multiplier With 64-Bit
Accumulator
– Enhanced GPIO Module Provides Shift-
In/Out Support and Parallel Latch on External
Signal
– 12KB of Shared RAM With Single-Error
Detection (Parity)
– Three 120-Byte Register Banks Accessible by
Each PRU
– Interrupt Controller (INTC) for Handling System
Input Events
– Local Interconnect Bus for Connecting Internal
and External Masters to the Resources Inside
the PRU-ICSS
– Peripherals Inside the PRU-ICSS:
– One UART Port With Flow Control Pins,
Supports up to 12 Mbps
– One Enhanced Capture (eCAP) Module
– Two MII Ethernet Ports that Support Industrial
Ethernet, such as EtherCAT
– One MDIO Port
• Power, Reset, and Clock Management (PRCM)
Module
– Controls the Entry and Exit of Stand-By and
Deep-Sleep Modes
– Responsible for Sleep Sequencing, Power
Domain Switch-Off Sequencing, Wake-Up
Sequencing, and Power Domain Switch-On
Sequencing
– Clocks
– Integrated 15- to 35-MHz High-Frequency
Oscillator Used to Generate a Reference
Clock for Various System and Peripheral
Clocks
– Supports Individual Clock Enable and Disable
Control for Subsystems and Peripherals to
Facilitate Reduced Power Consumption
– Five ADPLLs to Generate System Clocks
(MPU Subsystem, DDR Interface, USB and
2
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Peripherals [MMC and SD, UART, SPI, I2C],
L3, L4, Ethernet, GFX [SGX530], LCD Pixel
Clock)
– Power
– Two Nonswitchable Power Domains (Real-
Time Clock [RTC], Wake-Up Logic
[WAKEUP])
– Three Switchable Power Domains (MPU
Subsystem [MPU], SGX530 [GFX],
Peripherals and Infrastructure [PER])
– Implements SmartReflex™ Class 2B for Core
Voltage Scaling Based On Die Temperature,
Process Variation, and Performance
(Adaptive Voltage Scaling [AVS])
– Dynamic Voltage Frequency Scaling (DVFS)
• Real-Time Clock (RTC)
– Real-Time Date (Day-Month-Year-Day of Week)
and Time (Hours-Minutes-Seconds) Information
– Internal 32.768-kHz Oscillator, RTC Logic and
1.1-V Internal LDO
– Independent Power-on-Reset
(RTC_PWRONRSTn) Input
– Dedicated Input Pin (EXT_WAKEUP) for
External Wake Events
– Programmable Alarm Can be Used to Generate
Internal Interrupts to the PRCM (for Wakeup) or
Cortex-A8 (for Event Notification)
– Programmable Alarm Can be Used With
External Output (PMIC_POWER_EN) to Enable
the Power Management IC to Restore Non-RTC
Power Domains
• Peripherals
– Up to Two USB 2.0 High-Speed OTG Ports
With Integrated PHY
– Up to Two Industrial Gigabit Ethernet MACs (10,
100, 1000 Mbps)
– Integrated Switch
– Each MAC Supports MII, RMII, RGMII, and
MDIO Interfaces
– Ethernet MACs and Switch Can Operate
Independent of Other Functions
– IEEE 1588v2 Precision Time Protocol (PTP)
– Up to Two Controller-Area Network (CAN) Ports
– Supports CAN Version 2 Parts A and B
– Up to Two Multichannel Audio Serial Ports
(McASPs)
– Transmit and Receive Clocks up to 50 MHz
– Up to Four Serial Data Pins per McASP Port
With Independent TX and RX Clocks
– Supports Time Division Multiplexing (TDM),
Inter-IC Sound (I2S), and Similar Formats
– Supports Digital Audio Interface Transmission
(SPDIF, IEC60958-1, and AES-3 Formats)
– FIFO Buffers for Transmit and Receive (256
Bytes)
– Up to Six UARTs
– All UARTs Support IrDA and CIR Modes
– All UARTs Support RTS and CTS Flow
Control
– UART1 Supports Full Modem Control
– Up to Two Master and Slave McSPI Serial
Interfaces
– Up to Two Chip Selects
– Up to 48 MHz
– Up to Three MMC, SD, SDIO Ports
– 1-, 4- and 8-Bit MMC, SD, SDIO Modes
– MMCSD0 has Dedicated Power Rail for 1.8‑V
or 3.3-V Operation
– Up to 48-MHz Data Transfer Rate
– Supports Card Detect and Write Protect
– Complies With MMC4.3, SD, SDIO 2.0
Specifications
– Up to Three I2C Master and Slave Interfaces
– Standard Mode (up to 100 kHz)
– Fast Mode (up to 400 kHz)
– Up to Four Banks of General-Purpose I/O
(GPIO) Pins
– 32 GPIO Pins per Bank (Multiplexed With
Other Functional Pins)
– GPIO Pins Can be Used as Interrupt Inputs
(up to Two Interrupt Inputs per Bank)
– Up to Three External DMA Event Inputs that can
Also be Used as Interrupt Inputs
– Eight 32-Bit General-Purpose Timers
– DMTIMER1 is a 1-ms Timer Used for
Operating System (OS) Ticks
– DMTIMER4–DMTIMER7 are Pinned Out
– One Watchdog Timer
– SGX530 3D Graphics Engine
– Tile-Based Architecture Delivering up to 20
Million Polygons per Second
– Universal Scalable Shader Engine (USSE) is
a Multithreaded Engine Incorporating Pixel
and Vertex Shader Functionality
– Advanced Shader Feature Set in Excess of
Microsoft VS3.0, PS3.0, and OGL2.0
– Industry Standard API Support of Direct3D
Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0,
and OpenMax
– Fine-Grained Task Switching, Load
Balancing, and Power Management
– Advanced Geometry DMA-Driven Operation
for Minimum CPU Interaction
3
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– Programmable High-Quality Image Anti-
Aliasing
– Fully Virtualized Memory Addressing for OS
Operation in a Unified Memory Architecture
– LCD Controller
– Up to 24-Bit Data Output; 8 Bits per Pixel
(RGB)
– Resolution up to 2048 × 2048 (With
Maximum 126-MHz Pixel Clock)
– Integrated LCD Interface Display Driver
(LIDD) Controller
– Integrated Raster Controller
– Integrated DMA Engine to Pull Data from the
External Frame Buffer Without Burdening the
Processor via Interrupts or a Firmware Timer
– 512-Word Deep Internal FIFO
– Supported Display Types:
– Character Displays - Uses LIDD Controller
to Program these Displays
– Passive Matrix LCD Displays - Uses LCD
Raster Display Controller to Provide
Timing and Data for Constant Graphics
Refresh to a Passive Display
– Active Matrix LCD Displays - Uses
External Frame Buffer Space and the
Internal DMA Engine to Drive Streaming
Data to the Panel
– 12-Bit Successive Approximation Register
(SAR) ADC
– 200K Samples per Second
– Input can be Selected from any of the Eight
Analog Inputs Multiplexed Through an 8:1
Analog Switch
– Can be Configured to Operate as a 4-Wire, 5-
Wire, or 8-Wire Resistive Touch Screen
Controller (TSC) Interface
– Up to Three 32-Bit eCAP Modules
– Configurable as Three Capture Inputs or
Three Auxiliary PWM Outputs
– Up to Three Enhanced High-Resolution PWM
Modules (eHRPWMs)
– Dedicated 16-Bit Time-Base Counter With
Time and Frequency Controls
– Configurable as Six Single-Ended, Six Dual-
Edge Symmetric, or Three Dual-Edge
Asymmetric Outputs
– Up to Three 32-Bit Enhanced Quadrature
Encoder Pulse (eQEP) Modules
• Device Identification
– Contains Electrical Fuse Farm (FuseFarm) of
Which Some Bits are Factory Programmable
– Production ID
– Device Part Number (Unique JTAG ID)
– Device Revision (Readable by Host ARM)
• Debug Interface Support
– JTAG and cJTAG for ARM (Cortex-A8 and
PRCM), PRU-ICSS Debug
– Supports Device Boundary Scan
– Supports IEEE 1500
• DMA
– On-Chip Enhanced DMA Controller (EDMA) has
Three Third-Party Transfer Controllers (TPTCs)
and One Third-Party Channel Controller
(TPCC), Which Supports up to 64
Programmable Logical Channels and Eight
QDMA Channels. EDMA is Used for:
– Transfers to and from On-Chip Memories
– Transfers to and from External Storage
(EMIF, GPMC, Slave Peripherals)
• Inter-Processor Communication (IPC)
– Integrates Hardware-Based Mailbox for IPC and
Spinlock for Process Synchronization Between
Cortex-A8, PRCM, and PRU-ICSS
– Mailbox Registers that Generate Interrupts
– Four Initiators (Cortex-A8, PRCM, PRU0,
PRU1)
– Spinlock has 128 Software-Assigned Lock
Registers
• Security
– Crypto Hardware Accelerators (AES, SHA,
RNG)
– Secure Boot
• Boot Modes
– Boot Mode is Selected Through Boot
Configuration Pins Latched on the Rising Edge
of the PWRONRSTn Reset Input Pin
• Packages:
– 298-Pin S-PBGA-N298 Via Channel Package
(ZCE Suffix), 0.65-mm Ball Pitch
– 324-Pin S-PBGA-N324 Package
(ZCZ Suffix), 0.80-mm Ball Pitch
4
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Device Overview Copyright © 2011–2016, Texas Instruments Incorporated
1.2 Applications
• Gaming Peripherals
• Home and Industrial Automation
• Consumer Medical Appliances
• Printers
• Smart Toll Systems
• Connected Vending Machines
• Weighing Scales
• Educational Consoles
• Advanced Toys
(1) For more information, see Section 9,Mechanical, Packaging, and Orderable Information.
1.3 Description
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image,
graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The
devices support high-level operating systems (HLOS). Linux®and Android™ are available free of charge
from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief
description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each
follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR
SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming
effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater
efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols
such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others.
Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all
system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized
data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor
cores of SoC.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
AM3359ZCZ NFBGA (324) 15.0 mm × 15.0 mm
AM3358ZCZ NFBGA (324) 15.0 mm × 15.0 mm
AM3357ZCZ NFBGA (324) 15.0 mm × 15.0 mm
AM3356ZCZ, AM3356ZCE NFBGA (324), NFBGA (298) 15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm
AM3354ZCZ, AM3354ZCE NFBGA (324), NFBGA (298) 15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm
AM3352ZCZ, AM3352ZCE NFBGA (324), NFBGA (298) 15.0 mm × 15.0 mm, 13.0 mm × 13.0 mm
AM3351ZCE NFBGA (298) 13.0 mm × 13.0 mm
ARM
Cortex-A8
Up to 1 GHz
32KB and 32KB L1 + SED
256KB L2 + ECC
176KB ROM 64KB RAM
Graphics
PowerVR
SGX
3D GFX
Crypto
64KB
shared
RAM
24-bit LCD controller
Touch screen controller
Display
PRU-ICSS
EtherCAT, PROFINET,
EtherNet/IP,
and more
L3 and L4 interconnect
USB 2.0 HS
OTG + PHY x2
CAN x2
(Ver. 2 A and B)
McASP x2
(4 channel)
I C x3
2
SPI x2
UART x6
Serial System Parallel
eDMA
Timers x8
WDT
RTC
eHRPWM x3
eQEP x3
PRCM
eCAP x3
ADC (8 channel)
12-bit SAR
JTAG
Crystal
Oscillator x2
MMC, SD and
SDIO x3
GPIO
EMAC (2-port) 10M, 100M, 1G
IEEE 1588v2, and switch
(MII, RMII, RGMII)
mDDR(LPDDR), DDR2,
DDR3, DDR3L
(16-bit; 200, 266, 400, 400 MHz)
NAND and NOR (16-bit ECC)
Memory interface
Copyright © 2016, Texas Instruments Incorporated
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1.4 Functional Block Diagram
Figure 1-1 shows the AM335x microprocessor functional block diagram.
Figure 1-1. AM335x Functional Block Diagram
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Table of Contents Copyright © 2011–2016, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 4
1.3 Description............................................ 4
1.4 Functional Block Diagram ........................... 5
2 Revision History ......................................... 7
3 Device Comparison ..................................... 8
3.1 Related Products ..................................... 9
4 Terminal Configuration and Functions ............ 10
4.1 Pin Diagram ......................................... 10
4.2 Pin Attributes........................................ 18
4.3 Signal Descriptions.................................. 50
5 Specifications........................................... 79
5.1 Absolute Maximum Ratings......................... 79
5.2 ESD Ratings ........................................ 80
5.3 Power-On Hours (POH)............................. 81
5.4 Operating Performance Points (OPPs) ............. 81
5.5 Recommended Operating Conditions............... 84
5.6 Power Consumption Summary...................... 86
5.7 DC Electrical Characteristics........................ 88
5.8 Thermal Resistance Characteristics for ZCE and
ZCZ Packages ...................................... 92
5.9 External Capacitors ................................. 93
5.10 Touch Screen Controller and Analog-to-Digital
Subsystem Electrical Parameters................... 96
6 Power and Clocking ................................... 98
6.1 Power Supplies...................................... 98
6.2 Clock Specifications................................ 106
7 Peripheral Information and Timings .............. 115
7.1 Parameter Information ............................. 115
7.2 Recommended Clock and Control Signal Transition
Behavior............................................ 115
7.3 OPP50 Support.................................... 115
7.4 Controller Area Network (CAN).................... 116
7.5 DMTimer ........................................... 117
7.6 Ethernet Media Access Controller (EMAC) and
Switch.............................................. 118
7.7 External Memory Interfaces........................ 126
7.8 I2C.................................................. 189
7.9 JTAG Electrical Data and Timing.................. 191
7.10 LCD Controller (LCDC) ............................ 192
7.11 Multichannel Audio Serial Port (McASP) .......... 208
7.12 Multichannel Serial Port Interface (McSPI) ........ 213
7.13 Multimedia Card (MMC) Interface ................. 219
7.14 Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRU-ICSS) 222
7.15 Universal Asynchronous Receiver Transmitter
(UART)............................................. 231
8 Device and Documentation Support.............. 234
8.1 Device Nomenclature.............................. 234
8.2 Tools and Software ................................ 235
8.3 Documentation Support............................ 239
8.4 Related Links ...................................... 242
8.5 Community Resources............................. 242
8.6 Trademarks ........................................ 243
8.7 Electrostatic Discharge Caution ................... 243
8.8 Glossary............................................ 243
9 Mechanical, Packaging, and Orderable
Information............................................. 244
9.1 Via Channel........................................ 244
9.2 Packaging Information ............................. 244
7
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Revision HistoryCopyright © 2011–2016, Texas Instruments Incorporated
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (December 2015) to Revision J Page
• Added Secure boot to Security feature list ........................................................................................ 3
• Added extended temperature range for the AM3351 device in Table 3-1 .................................................... 8
• Added Section 3.1, Related Products ............................................................................................. 9
• Reformatted and added content to Section 8, Device and Documentation Support...................................... 234
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Device Comparison Copyright © 2011–2016, Texas Instruments Incorporated
3 Device Comparison
Table 3-1 lists the features supported across different AM335x devices.
Table 3-1. Device Features Comparison
FUNCTION AM3351 AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
ARM Cortex-A8 Yes Yes Yes Yes Yes Yes Yes
Frequency(1) 300 MHz
600 MHz
300 MHz
600 MHz
800 MHz
1000 MHz
600 MHz
800 MHz
1000 MHz
300 MHz
600 MHz
800 MHz
300 MHz
600 MHz
800 MHz
600 MHz
800 MHz
1000 MHz
600 MHz
800 MHz
MIPS(2) 600
1200
600
1200
1600
2000
1200
1600
2000
600
1200
1600
600
1200
1600
1200
1600
2000
1200
1600
On-chip L1 cache 64KB 64KB 64KB 64KB 64KB 64KB 64KB
On-chip L2 cache 256KB 256KB 256KB 256KB 256KB 256KB 256KB
Graphics accelerator
(SGX530) — — 3D — — 3D 3D
Hardware acceleration Crypto
accelerator Crypto
accelerator Crypto
accelerator Crypto
accelerator Crypto
accelerator Crypto
accelerator Crypto
accelerator
Programmable real-time
unit subsystem and
industrial communication
subsystem (PRU-ICSS)
———
Features
including basic
Industrial
protocols;
ZCE: Limited
PRU I/Os pinned
out
Features
including all
Industrial
protocols
Features
including basic
Industrial
protocols
Features
including all
Industrial
protocols
On-chip memory 128KB 128KB 128KB 128KB 128KB 128KB 128KB
Display options LCD LCD LCD LCD LCD LCD LCD
General-purpose memory
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
DRAM(3) 1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
Universal serial bus (USB) ZCE: 1 port ZCE: 1 port
ZCZ: 2 ports ZCE: 1 port
ZCZ: 2 ports ZCE: 1 port
ZCZ: 2 ports
No ZCE
Available
ZCZ: 2 ports
No ZCE
Available
ZCZ: 2 ports
No ZCE
Available
ZCZ: 2 ports
Ethernet media access
controller (EMAC) with 2-
port switch
10/100/1000
ZCE: 1 port
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
10/100/1000
No ZCE
Available
ZCZ: 2 ports
10/100/1000
No ZCE
Available
ZCZ: 2 ports
10/100/1000
No ZCE
Available
ZCZ: 2 ports
Multimedia card (MMC) 3 3 3 3 3 3 3
Controller-area network
(CAN) —222222
Universal asynchronous
receiver and transmitter
(UART) 6666666
Analog-to-digital converter
(ADC) 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit 8-ch 12-bit
Enhanced high-resolution
PWM modules
(eHRPWM) 3333333
Enhanced capture
modules (eCAP) 3333333
Enhanced quadrature
encoder pulse (eQEP) 3333333
Real-time clock (RTC) 1 1 1 1 1 1 1
Inter-integrated circuit
(I2C) 3333333
9
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Table 3-1. Device Features Comparison (continued)
FUNCTION AM3351 AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
Multichannel audio serial
port (McASP) 2222222
Multichannel serial port
interface (McSPI) 2222222
Enhanced direct memory
access (EDMA) 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch 64-Ch
Input/output (I/O) supply 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V 1.8 V, 3.3 V
Operating temperature
range 0 to 90°C
–40 to 105°C
-40 to 125°C(4)
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
(1) Frequencies listed correspond to silicon revision 2.x. Earlier silicon revisions support 275 MHz, 500 MHz, 600 MHz, and 720 MHz.
(2) MIPS listed correspond to silicon revision 2.x. Earlier silicon revisions support 560, 1000, 1200, and 1440.
(3) DRAM speeds listed are data rates.
(4) Industrial extended temperature only supported for 300-MHz and 600-MHz frequencies.
3.1 Related Products
For information about other devices in this family of products, see the following links:
Sitara Processors Scalable processors based on ARM Cortex-A cores with flexible peripherals,
connectivity and unified software support – perfect for sensors to servers.
TI's ARM Cortex-A8 Advantage The ARM Cortex-A8 core is highly-optimized by ARM for performance
and power efficiency. With the ability to scale in speed from 300 MHz to 1.35 GHz, the ARM
Cortex-A8-based processor can meet the requirements for power optimized devices with a
power budget of less than the Cortex-A8 core a dual-issue superscalar, achieving twice the
instructions executed per clock cycle at 2 DMIPS/MHz.
AM335x Sitara Processors Scalable ARM Cortex-A8-based core from 300 MHz up to 1 GHz, 3D
graphics option for enhanced user interface, dual-core PRU-ICSS for industrial Ethernet
protocols and position feedback control, and premium secure boot option.
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4 Terminal Configuration and Functions
4.1 Pin Diagram
NOTE
The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An
attempt is made to use 'ball' only when referring to the physical package.
4.1.1 ZCE Package Pin Maps (Top View)
The pin maps that follow show the pin assignments on the ZCE package in three sections (left, middle,
and right).
Left
Pin map section location
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Table 4-1. ZCE Pin Map [Section Left - Top View]
A B C D E F
19 VSS I2C0_SCL UART1_TXD UART1_RTSn UART0_RXD UART0_CTSn
18 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RXD ECAP0_IN_PWM0_OUT UART0_RTSn
17 SPI0_CS0 SPI0_D1 EXTINTn XXXX UART1_CTSn UART0_TXD
16 WARMRSTn SPI0_CS1 XXXX XXXX XXXX VDDS
15 EMU0 XDMA_EVENT_INTR1 XDMA_EVENT_INTR0 XXXX PWRONRSTn XXXX
14 TDO TCK TMS EMU1 XXXX VDDSHV6
13 TRSTn TDI CAP_VBB_MPU CAP_VDD_SRAM_MPU VDDSHV6 VSS
12 AIN7 AIN5 VDDS_SRAM_MPU_BB VDDS VDDSHV6 VSS
11 AIN1 AIN3 XXXX XXXX VDDSHV6 VDD_CORE
10 AIN6 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VSS VSS XXXX
9VREFP VREFN XXXX XXXX VSS VDD_CORE
8AIN2 AIN0 AIN4 VSSA_ADC VSS VSS
7RTC_KALDO_ENn RTC_PWRONRSTn PMIC_POWER_EN VDDA_ADC VSS VSS
6RTC_XTALIN RESERVED VDDS_RTC CAP_VDD_RTC XXXX VSS
5RTC_XTALOUT EXT_WAKEUP VDDS_PLL_DDR XXXX DDR_A4 XXXX
4DDR_WEn DDR_BA2 XXXX XXXX XXXX DDR_A12
3DDR_BA0 DDR_A3 DDR_A8 XXXX DDR_A15 DDR_A0
2DDR_A5 DDR_A9 DDR_CK DDR_A7 DDR_A10 DDR_RASn
1VSS DDR_A6 DDR_CKn DDR_A2 DDR_BA1 DDR_CASn
Middle
Pin map section location
12
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ZCE Pin Map [Section Middle - Top View]
G H J K L M
19 MMC0_CLK MMC0_DAT3 MII1_COL MII1_RX_ER MII1_RX_DV MII1_RX_CLK
18 MMC0_DAT0 MMC0_DAT2 MII1_CRS RMII1_REF_CLK MII1_TXD0 MII1_TXD1
17 MMC0_CMD MMC0_DAT1 XXXX MII1_TX_EN XXXX MII1_TXD3
16 USB0_DRVVBUS VDDS_PLL_MPU XXXX VDD_CORE XXXX VDDS
15 VDDSHV4 VDDSHV4 VSS VDD_CORE VSS VDDSHV5
14 XXXX VDDSHV4 VSS XXXX VSS VDDSHV5
13 XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
12 VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
11 VDD_CORE VSS VSS VSS VSS VSS
10 XXXX VSS XXXX XXXX XXXX VSS
9VDD_CORE VSS VSS VSS VSS VSS
8VSS VDD_CORE VDD_CORE VSS VDD_CORE VDD_CORE
7XXXX VDD_CORE VDD_CORE XXXX VDD_CORE VDD_CORE
6XXXX VDDS_DDR VSS XXXX VSS VDDS_DDR
5VDDS_DDR VDDS_DDR VSS VDDS_DDR VSS VDDS_DDR
4DDR_A11 DDR_VREF XXXX VDDS_DDR XXXX DDR_D11
3DDR_CKE DDR_A14 XXXX DDR_DQM1 XXXX DDR_D10
2DDR_RESETn DDR_CSn0 DDR_A1 DDR_D8 DDR_DQSn1 DDR_D12
1DDR_ODT DDR_A13 DDR_VTP DDR_D9 DDR_DQS1 DDR_D13
Right
Pin map section location
13
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ZCE Pin Map [Section Right - Top View]
N P R T U V W
19 MII1_TX_CLK MII1_RXD1 MDC USB0_VBUS USB0_DP USB0_ID VSS
18 MII1_TXD2 MII1_RXD0 VDDA3P3V_USB0 USB0_CE USB0_DM GPMC_BEn1 GPMC_WPn
17 MII1_RXD3 MDIO VDDA1P8V_USB0 XXXX GPMC_CSn3 GPMC_AD15 GPMC_AD14
16 MII1_RXD2 VSSA_USB XXXX XXXX XXXX GPMC_CLK GPMC_AD9
15 VDDSHV5 XXXX GPMC_WAIT0 XXXX GPMC_CSn2 GPMC_AD8 GPMC_AD7
14 XXXX VSS XXXX VDDS GPMC_AD6 GPMC_CSn1 GPMC_AD5
13 XXXX VSS VDDSHV1 GPMC_AD13 GPMC_AD12 GPMC_AD4 GPMC_AD3
12 VSS VSS VDDSHV1 GPMC_AD10 GPMC_AD11 GPMC_AD2 XTALOUT
11 VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX VSS_OSC XTALIN
10 XXXX XXXX VSS VSS VDDS_OSC GPMC_ADVn_ALE GPMC_AD0
9VDD_CORE VDD_CORE VDDSHV1 XXXX XXXX GPMC_AD1 GPMC_OEn_REn
8VSS VSS VDDSHV1 VDDS_PLL_CORE_LCD GPMC_WEn GPMC_BEn0_CLE GPMC_CSn0
7XXXX VSS VDDSHV6 LCD_HSYNC LCD_VSYNC LCD_DATA15 LCD_AC_BIAS_EN
6XXXX VDDSHV6 XXXX VDDS LCD_DATA13 LCD_DATA12 LCD_DATA14
5VDDS_DDR XXXX VPP XXXX LCD_DATA10 LCD_DATA11 LCD_PCLK
4DDR_D0 DDR_D1 XXXX XXXX XXXX LCD_DATA8 LCD_DATA9
3DDR_DQM0 DDR_D4 DDR_D7 XXXX LCD_DATA7 LCD_DATA6 LCD_DATA5
2DDR_D14 DDR_D2 DDR_DQSn0 DDR_D6 LCD_DATA1 LCD_DATA3 LCD_DATA4
1DDR_D15 DDR_D3 DDR_DQS0 DDR_D5 LCD_DATA0 LCD_DATA2 VSS
14
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4.1.2 ZCZ Package Pin Maps (Top View)
The pin maps that follow show the pin assignments on the ZCZ package in three sections (left, middle,
and right).
Left
Pin map section location
15
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ZCZ Pin Map [Section Left - Top View]
A B C D E F
18 VSS EXTINTn ECAP0_IN_PWM0_OUT UART1_CTSn UART0_CTSn MMC0_DAT2
17 SPI0_SCLK SPI0_D0 I2C0_SDA UART1_RTSn UART0_RTSn MMC0_DAT3
16 SPI0_CS0 SPI0_D1 I2C0_SCL UART1_RXD UART0_TXD USB0_DRVVBUS
15 XDMA_EVENT_INTR0 PWRONRSTn SPI0_CS1 UART1_TXD UART0_RXD USB1_DRVVBUS
14 MCASP0_AHCLKX EMU1 EMU0 XDMA_EVENT_INTR1 VDDS VDDSHV6
13 MCASP0_ACLKX MCASP0_FSX MCASP0_FSR MCASP0_AXR1 VDDSHV6 VDD_MPU
12 TCK MCASP0_ACLKR MCASP0_AHCLKR MCASP0_AXR0 VDDSHV6 VDD_MPU
11 TDO TDI TMS CAP_VDD_SRAM_MPU VDDSHV6 VDD_MPU
10 WARMRSTn TRSTn CAP_VBB_MPU VDDS_SRAM_MPU_BB VDDSHV6 VDD_MPU
9VREFN VREFP AIN7 CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG VDDS
8AIN6 AIN5 AIN4 VDDA_ADC VSSA_ADC VSS
7AIN3 AIN2 AIN1 VDDS_RTC VDDS_PLL_DDR VDD_CORE
6RTC_XTALIN AIN0 PMIC_POWER_EN CAP_VDD_RTC VDDS VDD_CORE
5VSS_RTC RTC_PWRONRSTn EXT_WAKEUP DDR_A6 VDDS_DDR VDDS_DDR
4RTC_XTALOUT RTC_KALDO_ENn DDR_BA0 DDR_A8 DDR_A2 DDR_A10
3RESERVED DDR_BA2 DDR_A3 DDR_A15 DDR_A12 DDR_A0
2VDD_MPU_MON DDR_WEn DDR_A4 DDR_CK DDR_A7 DDR_A11
1VSS DDR_A5 DDR_A9 DDR_CKn DDR_BA1 DDR_CASn
Middle
Pin map section location
16
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ZCZ Pin Map [Section Middle - Top View]
G H J K L M
18 MMC0_CMD RMII1_REF_CLK MII1_TXD3 MII1_TX_CLK MII1_RX_CLK MDC
17 MMC0_CLK MII1_CRS MII1_RX_DV MII1_TXD0 MII1_RXD3 MDIO
16 MMC0_DAT0 MII1_COL MII1_TX_EN MII1_TXD1 MII1_RXD2 MII1_RXD0
15 MMC0_DAT1 VDDS_PLL_MPU MII1_RX_ER MII1_TXD2 MII1_RXD1 USB0_CE
14 VDDSHV6 VDDSHV4 VDDSHV4 VDDSHV5 VDDSHV5 VSSA_USB
13 VDD_MPU VDD_MPU VDD_MPU VDDS VSS VDD_CORE
12 VSS VSS VDD_CORE VDD_CORE VSS VSS
11 VSS VDD_CORE VSS VSS VSS VDD_CORE
10 VDD_CORE VSS VSS VSS VSS VSS
9VSS VSS VSS VSS VDD_CORE VSS
8VSS VSS VSS VDD_CORE VDD_CORE VSS
7VDD_CORE VSS VSS VSS VDD_CORE VSS
6VDD_CORE VSS VSS VDD_CORE VDD_CORE VSS
5VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VPP
4DDR_RASn DDR_A14 DDR_VREF DDR_D12 DDR_D14 DDR_D1
3DDR_CKE DDR_A13 DDR_VTP DDR_D11 DDR_D13 DDR_D0
2DDR_RESETn DDR_CSn0 DDR_DQM1 DDR_D10 DDR_DQSn1 DDR_DQM0
1DDR_ODT DDR_A1 DDR_D8 DDR_D9 DDR_DQS1 DDR_D15
Right
Pin map section location
17
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ZCZ Pin Map [Section Right - Top View]
N P R T U V
18 USB0_DM USB1_CE USB1_DM USB1_VBUS GPMC_BEn1 VSS
17 USB0_DP USB1_ID USB1_DP GPMC_WAIT0 GPMC_WPn GPMC_A11
16 VDDA1P8V_USB0 USB0_ID VDDA1P8V_USB1 GPMC_A10 GPMC_A9 GPMC_A8
15 VDDA3P3V_USB0 USB0_VBUS VDDA3P3V_USB1 GPMC_A7 GPMC_A6 GPMC_A5
14 VSSA_USB VDDS GPMC_A4 GPMC_A3 GPMC_A2 GPMC_A1
13 VDD_CORE VDDSHV3 GPMC_A0 GPMC_CSn3 GPMC_AD15 GPMC_AD14
12 VDD_CORE VDDSHV3 GPMC_AD13 GPMC_AD12 GPMC_AD11 GPMC_CLK
11 VSS VDDSHV2 VDDS_OSC GPMC_AD10 XTALOUT VSS_OSC
10 VSS VDDSHV2 VDDS_PLL_CORE_LCD GPMC_AD9 GPMC_AD8 XTALIN
9VDD_CORE VDDS GPMC_AD6 GPMC_AD7 GPMC_CSn1 GPMC_CSn2
8VDD_CORE VDDSHV1 GPMC_AD2 GPMC_AD3 GPMC_AD4 GPMC_AD5
7VSS VDDSHV1 GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD0 GPMC_AD1
6VDDS VDDSHV6 LCD_AC_BIAS_EN GPMC_BEn0_CLE GPMC_WEn GPMC_CSn0
5VDDSHV6 VDDSHV6 LCD_HSYNC LCD_DATA15 LCD_VSYNC LCD_PCLK
4DDR_D5 DDR_D7 LCD_DATA3 LCD_DATA7 LCD_DATA11 LCD_DATA14
3DDR_D4 DDR_D6 LCD_DATA2 LCD_DATA6 LCD_DATA10 LCD_DATA13
2DDR_D3 DDR_DQSn0 LCD_DATA1 LCD_DATA5 LCD_DATA9 LCD_DATA12
1DDR_D2 DDR_DQS0 LCD_DATA0 LCD_DATA4 LCD_DATA8 VSS