[AK4127]
MS0593-E-02 2010/05
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GENERAL DESCRIPTION
The AK4127 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to
216kHz. The output sample rate is from 8kHz to 216kHz. The system can take very simple configuration
because the AK4127 has an internal PLL and does not need any master clock at slave mode. The
AK4127 is suitable for the application interfacing to different sample rates such as high-end Car Audio
and DVD recorder.
FEATURES
1. SRC
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi): 8kHz ∼ 216kHz
• Output Sample Rate (fso): 8kHz ∼ 216kHz
• Input to Output Sample Rate Ratio: 1/6 to 6
• THD+N: −130dB
• Dynamic Range: 140dB (A-weighted)
• I/F format: MSB justified, LSB justified, I2S compatible and TDM
• PLL for Internal Operation Clock
• Clock for Master mode: 128/192/256/384/512/768fsi, 128/256/384/512/768fso
• SRC Bypass mode (Master/Slave)
• Soft Mute Function
2. Pow er Supply
• AVDD, DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
3. Ta = −40 ∼ 85°C
4. Package: 30pin VSOP
5. AK4124/5 Pin-compatible
PLL
PDN
SMUTE
OLRCK
OBICK
SDTO
OMCLK
Serial
Audio
I/F
SRC
Serial
Audio
I/F
ILRCK
SDTI
IBICK
PLL1
PLL2
IDIF2 IDIF1 IDIF0 ODIF1 ODIF0
OBIT1
OBIT0
UNLOCK IMCLK
AVDD AVSS DVDD DVSS
CMODE2 CMODE1 CMODE0
PLL0 DITHER
192kHz / 24Bit High Performance Asynchronous SRC
AK4127
[AK4127]
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TABLE OF CONTENTS
GENERAL DESCRIPTION............................................................................................................................................... 1
FEATURES........................................................................................................................................................................ 1
■ Ordering Guide ........................................................................................................................................................... 3
■ Pin Layout ................................................................................................................................................................... 3
■ Compatibility with AK4125........................................................................................................................................ 4
PIN/FUNCTION ................................................................................................................................................................ 5
■ Handling of Unused pins............................................................................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 6
RECOMMENDED OPERATING CONDITIONS............................................................................................................ 6
SRC CHARACTERISTICS ............................................................................................................................................... 7
FILTER CHARACTERISTICS ......................................................................................................................................... 8
DC CHARACTERISTICS ................................................................................................................................................. 9
SWITCHING CHARACTERISTICS ................................................................................................................................ 9
■ Timing Diagram ........................................................................................................................................................ 11
OPERATION OVERVIEW ............................................................................................................................................. 13
■ System Clock & Audio Interface Format for Input PORT........................................................................................ 13
■ System Clock & Audio Interface Format for Output PORT..................................................................................... 15
■ Cascade TDM Mode ................................................................................................................................................. 18
■ Soft Mute Operation.................................................................................................................................................. 19
■ Dither ........................................................................................................................................................................ 20
■ System Reset ............................................................................................................................................................. 20
■ Internal Reset Function for Clock Change................................................................................................................ 21
■ Sequence of Changing Clocks .................................................................................................................................. 21
■ UNLOCK pin............................................................................................................................................................ 21
■ PLL Loop Filter......................................................................................................................................................... 22
SYSTEM DESIGN........................................................................................................................................................... 23
PACKAGE ....................................................................................................................................................................... 27
■ Material & Lead finish .............................................................................................................................................. 27
MARKING ....................................................................................................................................................................... 28
REVISION HISTORY ..................................................................................................................................................... 28
■ Sequence of changing clocks .................................................................................................................................... 28
IMPORTANT NOTICE ................................................................................................................................................... 29
[AK4127]
MS0593-E-02 2010/05
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■ Ordering Guide
AK4127VF −40 ∼ +85°C 30pin VSOP (0.65mm pitch)
AKD4127 Evaluation Board for AK4127
■ Pin Layout
PDN
SMUTE
ILRCK
IBICK
FILT
AVSS
DITHER
PLL2
IDIF0
IDIF1
IDIF2
PLL0
PLL1
SDTI
Top View
8
7
6
5
4
3
2
1
23
24
25
26
27
28
29
30
DVDD
OMCLK
SDTO
OBICK
OLRCK
DVSS
AVDD
9
10
11
12
13
14
20
21
22 CMODE2
17
18
19
OBIT1
IMCLK
CMODE0
ODIF0
ODIF1
CMODE1
16 OBIT0
UNLOCK 15
[AK4127]
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■ Compatibility with AK4125
Item AK4125 AK4127
TDM Mode - X
Slave Mode at Bypass Mode - X
OMCLK pin OMCLK Normal Mode: OMCLK
TDM Mode: TDMIN
OMCLK=192fso for Output PORT
(at Master Mode) X -
(-: Not available, X: Available)
[AK4127]
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PIN/FUNCTION
No. Pin Name I/O Function
1 FILT O PLL Loop Filter Pin, Hi-Z when PDN pin = “L”.
2 AVSS - Analog Ground Pin
3 PDN I Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
4 SMUTE I Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
5 DITHER I Dither Enable Pin
“H” : Dither ON, “L” : Dither OFF
6 PLL2 I PLL Mode Select 2 Pin
7 ILRCK I/O Input Channel Clock Pin, Output “L” when PDN = “L” and master mode.
8 IBICK I/O Audio Serial Data Clock Pin, Output “L” when PDN = “L” and master mode.
9 SDTI I Audio Serial Data Input Pin
10 IDIF0 I Audio Interface Format 0 Pin for Input PORT
11 IDIF1 I Audio Interface Format 1 Pin for Input PORT
12 IDIF2 I Audio Interface Format 2 Pin for Input PORT
13 PLL0 I PLL Mode Select 0 Pin
14 PLL1 I PLL Mode Select 1 Pin
15 UNLOCK O Unlock Status Pin, Output “H” when PDN = “L”
16 OBIT0 I Bit Length Select 0 Pin for Output Data
17 OBIT1 I Bit Length Select 1 Pin for Output Data
18 IMCLK I Master Clock Input Pin for Input PORT
19 CMODE0 I Clock Mode Select 0 Pin
20 CMODE1 I Clock Mode Select 1 Pin
21 CMODE2 I Clock Mode Select 2 Pin
22 ODIF0 I Audio Interface Format 0 Pin for Output PORT
23 ODIF1 I Audio Interface Format 1 Pin for Output PORT
24 SDTO O Audio Serial Data Output Pin for Output PORT, Output “L” when PDN pin = “L”
25 OBICK I/O Audio Serial Data Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
26 OLRCK I/O Output Channel Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
27 OMCLK I
Master Clock/TDM Data Input Pin for Output PORT
OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”)
TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”)
28 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
29 DVSS - Digital Ground Pin
30 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V
Note: All input pins must not be left floating.
[AK4127]
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■ Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below.
Classification Pin Name Setting
Analog FILT This pin should be open.
Digital SMUTE, DITHER These pins should be connected to DVSS.
IMCLK, OMCLK These pins should be connected to DVSS in slave mode.
UNLOCK This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 1)
Parameter Symbol min max Units
Power Supplies:
Analog
Digital
|AVSS − DVSS| (Note 2)
AVDD
DVDD
ΔGND
−0.3
−0.3
-
4.6
4.6
0.3
V
V
V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage (Note 3) VIND −0.3 DVDD+0.3 V
Ambient Temperature (Power applied) Ta −40 85 °C
Storage Temperature Tstg −65 150 °C
Note 1. All voltages with respect to ground.
Note 2. AVSS, BVSS and DVSS must be connected to the same ground.
Note 3. PND, SMUTE, DITHER, PLL2, ILRCK, IBICK, SDTI, IDIF0, IDIF1, IDIF2, PLL0, PLL1, OBIT0, OBIT1,
IMCLK, CMODE0, CMODE1, CMODE2, ODIF0, ODIF1, OBICK, OLRCK and OMCLK
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies
(Note 4)
Analog
Digital
AVDD
DVDD
3.0
3.0
3.3
3.3
3.6
AVDD
V
V
Note 4. The power up sequence between AVDD and DVDD is not important.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4127]
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SRC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless
otherwise specified.)
Parameter Symbol min typ max Units
SRC Characteristics:
Resolution 24 Bits
Input Sample Rate FSI 8 216 kHz
Output Sample Rate FSO 8 216 kHz
THD+N (Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 32kHz/176.4kHz)
-
-
-
-
-
−130
−124
−133
−124
-
-
-
-
-
−91
dB
dB
dB
dB
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 48kHz/32kHz)
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5)
FSO/FSI = 44.1kHz/48kHz
-
-
-
-
132
-
136
136
136
132
-
140
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 -
Note 5. Measured by Audio Precision System Two Cascade
[AK4127]
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FILTER CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
Digital Filter
0.985 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz
0.905 ≤ FSO/FSI < 0.985 PB 0 0.4167FSI kHz
0.714 ≤ FSO/FSI < 0.905 PB 0 0.3195FSI kHz
0.656 ≤ FSO/FSI < 0.714 PB 0 0.2852FSI kHz
0.536 ≤ FSO/FSI < 0.656 PB 0 0.2182FSI kHz
0.492 ≤ FSO/FSI < 0.536 PB 0 0.2177FSI kHz
0.452 ≤ FSO/FSI < 0.492 PB 0 0.1948FSI kHz
0.357 ≤ FSO/FSI < 0.452 PB 0 0.1458FSI kHz
0.324 ≤ FSO/FSI < 0.357 PB 0 0.1302FSI kHz
0.246 ≤ FSO/FSI < 0.324 PB 0 0.0917FSI kHz
0.226 ≤ FSO/FSI < 0.246 PB 0 0.0826FSI kHz
Passband −0.01dB
0.1667 ≤ FSO/FSI < 0.226 PB 0 0.0583FSI kHz
0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz
0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz
0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz
0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz
0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz
0.492 ≤ FSO/FSI < 0.536 SB 0.2813FSI kHz
0.452 ≤ FSO/FSI < 0.492 SB 0.2604FSI kHz
0.357 ≤ FSO/FSI < 0.452 SB 0.2116FSI kHz
0.324 ≤ FSO/FSI < 0.357 SB 0.1969FSI kHz
0.246 ≤ FSO/FSI < 0.324 SB 0.1573FSI kHz
0.226 ≤ FSO/FSI < 0.246 SB 0.1471FSI kHz
Stopband
0.1667 ≤ FSO/FSI < 0.226 SB 0.1020FSI kHz
Passband Ripple PR ±0.01 dB
0.985 ≤ FSO/FSI ≤ 6.000 SA 121.2 dB
0.905 ≤ FSO/FSI < 0.985 SA 121.4 dB
0.714 ≤ FSO/FSI < 0.905 SA 115.3 dB
0.656 ≤ FSO/FSI < 0.714 SA 116.9 dB
0.536 ≤ FSO/FSI < 0.656 SA 114.6 dB
0.492 ≤ FSO/FSI < 0.536 SA 100.2 dB
0.452 ≤ FSO/FSI < 0.492 SA 103.3 dB
0.357 ≤ FSO/FSI < 0.452 SA 102.0 dB
0.324 ≤ FSO/FSI < 0.357 SA 103.6 dB
0.246 ≤ FSO/FSI < 0.324 SA 104.0 dB
0.226 ≤ FSO/FSI < 0.246 SA 103.3 dB
Stopband
Attenuation
0.1667 ≤ FSO/FSI < 0.226 SA 73.2 dB
Group Delay (Note 6) GD - 56 - 1/fs
Note 6. This delay is the a period from the rising edge of ILRCK, just after the data is input, to the rising edge of OLRCK,
just after the data is output, when there is no phase difference between ILRCK and OLRCK.
[AK4127]
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DC CHARACTERISTICS
(Ta=25°C; AVDD= DVDD=3.0 ∼ 3.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%DVDD
-
-
-
-
30%DVDD
V
V
High-Level Output Voltage (Iout=−400μA)
Low-Level Output Voltage (Iout=400μA)
VOH
VOL
DVDD−0.4
-
-
-
-
0.4
V
V
Input Leakage Current Iin - - ±10 μA
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V
FSI=FSO=192kHz at Master Mode: AVDD=DVDD=3.3V
: AVDD=DVDD=3.6V
Power down (PDN pin = “L”) (Note 7)
AVDD+DVDD
15
65
10
100
100
mA
mA
mA
μA
Note 7. All digital input pins are held DVSS.
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
1.024
0.4/fCLK
0.4/fCLK
41.472
MHz
ns
ns
LRCK for Input data (ILRCK)
Frequency
Duty Cycle Slave Mode
Master Mode
fs
Duty
Duty
8
48
50
50
216
52
kHz
%
%
LRCK for Output data (OLRCK)
Frequency
Duty Cycle Slave Mode
Master Mode
fs
Duty
Duty
8
48
50
50
216
52
kHz
%
%
LRCK for TDM Mode (OLRCK)
Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/256fs
1/256fs
48
kHz
ns
ns
Audio Interface Timing
Input PORT (Slave mode)
IBICK Period (8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
IBICK Pulse Width Low
Pulse Width High
ILRCK Edge to IBICK “↑” (Note 8)
IBICK “↑” to ILRCK Edge (Note 8)
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/256fs
1/128fs
1/64fs
27
27
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
[AK4127]
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Input PORT (Master mode)
IBICK Frequency
IBICK Duty
IBICK “↓” to ILRCK
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
fBCK
dBCK
tMBLR
tSDH
tSDS
−20
15
15
64fs
50
20
Hz
%
ns
ns
ns
Output PORT (Slave mode)
OBICK Period (8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑” (Note 8)
OBICK “↑” to OLRCK Edge (Note 8)
OLRCK to SDTO (MSB) (Except I2S mode)
OBICK “↓” to SDTO
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/256fs
1/128fs
1/64fs
27
27
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output PORT (TDM slave mode)
OBICK Period
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to BICK “↑” (Note 8)
OBICK “↑” to LRCK Edge (Note 8)
OBICK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
20
10
20
ns
ns
ns
ns
ns
ns
ns
ns
Output PORT (Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK
OBICK “↓” to SDTO
fBCK
dBCK
tMBLR
tBSD
−20
−20
64fs
50
20
20
Hz
%
ns
ns
Reset Timing
PDN Pulse Width (Note 9)
tPD
150
ns
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4127 can be reset by bringing the PDN pin = “L”.
[AK4127]
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■ Timing Diagram
1/fCLK
MCLK
tCLKH tCLKL
VIH
VIL
1/fs
LRCK VIH
VIL
tBCK
BICK
tBCKH tBCKL
VIH
VIL
Clock Timing
LRCK VIH
VIL
tBLR
BICK VIH
VIL
tLRS
SDTO 50%DVDD
tLRB
tBSD
tSDS
SDTI VIL
tSDH
VIH
Audio Interface Timing (Slave mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
[AK4127]
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LRCK
BICK 50%DVDD
SDTO 50%DVDD
tBSD
tSDS
SDTI VIL
tSDH
VIH
tMBLR dBCK
50%DVDD
Audio Interface Timing (Master mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
tPD
PDN VIL
Power Down & Reset Timing
[AK4127]
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OPERATION OVERVIEW
■ System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0 ∼ 3 of Table 2) or IBICK (Mode 4 ∼ 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And
an internal system clock is created by IMCLK (Mode 8 ∼ 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =
“L”. When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the
TDM mode at the output port.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode IDIF2 IDIF1 IDIF0 SDTI Format ILRCK IBICK IBICK Freq Master / Slave
0 L L L 16bit, LSB justified ≥ 32fsi
1 L L H 20bit, LSB justified ≥ 40fsi
2 L H L 24/20bit, MSB justified ≥ 48fsi
3 L H H 24/16bit, I2S Compatible ≥ 48fsi or 32fsi
4 H L L 24bit, LSB justified
Input Input
≥ 48fsi
Slave
5 H L H 24bit, MSB justified 64fs
6 H H L 24bit, I2S Compatible Output Output 64fs Master
7 H H H Reserved
Table 1. Input Audio Interface Format (Input PORT)
Mode Master / Slave PLL2 PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK SMUTE
(Note 14)
0 L L L
8k ∼ 96kHz
1 L L H Manual
2 L H L Semi-Auto
3 L H H
8k ∼ 216kHz
16k ∼ 216kHz
(Note 10)
Depending
on IDIF2-0
(Note 11)
Not
needed.
(Note 13) Manual
4 H L L 32fsi
(Note 12)
5 H L H 64fsi
6 H H L 128fsi
Manual
7
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
H H H
8k ∼ 216kHz
(Note 11)
64fsi
Not
needed.
(Note 13)
Semi-Auto
8 L L L
8k ∼ 216kHz 128fsi
9 L L H
8k ∼ 108kHz 256fsi
10 L H L
8k ∼ 54kHz 512fsi
Manual
11 L H H
8k ∼ 216kHz 128fsi Semi-Auto
12 H L L
8k ∼ 216kHz 192fsi
13 H L H
8k ∼ 108kHz 384fsi
14 H H L
8k ∼ 54kHz 768fsi
Manual
15
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
H H H
8k ∼ 216kHz
64fsi
192fsi Semi-Auto
Table 2. PLL Setting (Input PORT)
Note 10. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 11. The IBCIK must be continuous except when the clocks are changed.
Note 12. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
Note 13. Fixed to DVSS.
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
[AK4127]
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ILRCK
IBICK(32fs) 01102 3 9 1112131415 0 123 10109 1112131415
SDTI(i) Don't Care 1 0 15 14 13 21015 14 13 12 12Don't Care
15:MSB, 0:LSB
SDTI(i) 15 14 13 7654321015 14 13 1576543210
IBICK(64fs) 01182 3 19 20 31 0 1 2 3 1018 19 20 3117 17
Lch Data Rch Data
Figure 1. Mode 0 Timing
ILRCK
IBICK(64fs) 0 1 22431012 103124
SDTI(i) Don't Care 0 8 10
19:MSB, 0:LSB
Lch Data Rch Data
19 8 Don't Care 191
12 13 1312
Figure 2. Mode 1 Timing
ILRCK
IBICK(64fs) 0 1 220212431012 102220 21 312422 23 23
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't Ca re
432123 22 23 22 231234
Figure 3. Mode 2,5 Timing (24bit MSB)
ILRCK
IBICK(64fs) 0122521 24 0 12 1022 2521 2422 23 233
SDTI(i) Don't Care0 0
23:MSB, 0:LSB
Lch Data Rch Data
Don't C are
432123 22 23 22 1234
Figure 4. Mode 3, 6 Timing (24bit I2S)
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ILRCK
IBICK(64fs) 0 1 22431012 10312489 89
SDTI(i) Don't Care 0 8 10
23:MSB, 0:LSB
Lch Data Rch Data
23 8 Don't Care 231
Figure 5. Mode 4 Timing
■ System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins
select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = “L”.
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when the
PDN pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the TDM
mode at the output port. The OMCLK pin changes to TDMIN pin for TDM data input in TDM mode.
Mode CMODE
2
CMODE
1 CMODE0 Master / Slave OMCLK fso
0 L L L Master 256fso 8k ∼ 108kHz
1 L L H Master 384fso 8k ∼ 108kHz
2 L H L Master 512fso 8k ∼ 54kHz
3 L H H Master 768fso 8k ∼ 54kHz
4 H L L Slave
Not used. Set to DVSS.
(Note 15) 8k ∼ 216kHz
5 H L H Master 128fso 8k ∼ 216kHz
6 H H L Slave (Bypass) Not used. Set to DVSS.
(Note 15) 8k ∼ 216kHz
7 H H H Master (Bypass) Not used. Set to DVSS. 8k ∼ 216kHz
Note 15. Changed to TDMIN pin when PLL2-0 pins = “L/H/H”.
Table 3. Master/Slave Control (Output PORT)
Mode ODIF1 ODIF0 SDTO Format
0 L L LSB justified
1 L H (Reserved)
2 H L MSB justified
3 H H I2S Compatible
Table 4. Output Audio Interface Format 1 (Output PORT)
[AK4127]
MS0593-E-02 2010/05
- 16 -
OBICK Frequency
Mode Master / Slave OBIT1 OBIT
0 SDTO OLRCK OBICK MSB justified,
I2S
LSB
justified
0 L L 16bit ≥ 32fso
1 L H 18bit ≥ 36fso
2 H L 20bit ≥ 40fso
3
Slave
CMODE2-0 =
“HLL” or “HHL” H H 24bit
Input Input
≥ 48fso
64fso
4 L L 16bit
5 L H 18bit
6 H L 20bit
7
Master
Except
CMODE2-0 =
“HLL” or “HHL” H H 24bit
Output Output 64fso
Table 5. Output Audio Interface Format 2 (Output PORT)
OLRCK
OBICK(64fs) 0 1
Lch Data Rch Data
89
SDTO(O) 15:MSB, 0:LSB
SDTO(O) 17:MSB, 0:LSB
SDTO(O) 19:MSB, 0:LSB
SDTO(O) 23:MSB, 0:LSB
1
012 13 141110 16 1715 20 21 22 2923 3130
10 9 81115 14 2 1 0
10 9 81115 14 2 1 017 16
10 9 81115 14 2 1 017 1619 18
10 9 81115 14 2 1 017 1619 1821 2023 22
12 13 14118 9 10 16 1715 20 21 22 2923 3130 0 1 2
10 9 21115 14 018
2815 14 11 0117 16 10 9
2815 14 9 0117 1619 18 11 10
2815 11 10 9 0117 1619 1821 2023 22 14
Figure 6. Normal Mode LSB Timing
OLRCK
OBICK(64fs) 0 1 2
Lch Data Rch Data
34
SDTO(O)
SDTO(O)
SDTO(O)
SDTO(O) 23:MSB, 0:LSB
34
15:MSB, 0:LSB
17:MSB, 0:LSB
19:MSB, 0:LSB
32148765 010 921 2023 22
321465 017 1619 18
321415 14 017 16
15 14 13 12 2 1 0
32148765 010 921 2023 22
321465 017 1619 18
321415 14 017 16
15 14 13 12 2 1 0
031 1 2 031 1 2
191817 2413 14 1615 20 21 2322 191817 2413 14 1615 20 21 2322
23 22
19 18
17 16
15 14
Figure 7. Normal Mode MSB Timing
OLRCK
OBICK(64fs) 012
Lch Data Rch Data
34
SDTO(O)
SDTO(O)
SDTO(O)
SDTO(O) 23:MSB, 0:LSB
34
15:MSB, 0:LSB
17:MSB, 0:LSB
19:MSB, 0:LSB
012 031 1 2191817 2414 1615 20 21 2322 191817 2414 1615 20 21 2322
23
19
17
1515 14 13 12 2 1 0
321415 14 017 16
321465 017 1619 18
32148765 010 921 2023 22
15 14 13 12 2 1 0
321415 14 017 16
321465 017 1619 18
32148765 010 921 2023 22
Figure 8. Normal Mode I2S Compatible Timing
[AK4127]
MS0593-E-02 2010/05
- 17 -
23
OLRCK(I)
OBICK (I: 256fso)
SDTO(O) 22 0
L1
32 BICK
256 OBICK
22 0
R1
32 BICK
2223 23
23
TDMIN(I) 22 0
L2 22 0
R2 2223 23
23 22 0
L2
32 BICK
22 0
R2
32 BICK
23
23 22 0
L3 22 0
R3
23 23 22 0
L4 22 0
R4
23
23 22 0
L3 22 0
R3
23 23 22 0
L4 22 0
R4
23
Figure 9. TDM mode MSB Timing
OLRCK(I)
OBICK (I: 256fso)
SDTO(O) 23 0
L1
32 BICK
256 OBICK
23 0
R1
32 BICK
23
TDMIN(I) 23 0
L2 23 0
R2 23
23 0
L2
32 BICK
23 0
R2
32 BICK
23 0
L3 23 0
R3 23 0
L4 23 0
R4
23 0
L3 23 0
R3 23 0
L4 23 0
R4
Figure 10. TDM mode I2S Compatible Timing
[AK4127]
MS0593-E-02 2010/05
- 18 -
■ Cascade TDM Mode
The AK4127 supports cascading connection of up to four devices (8channels) in a daisy chain configuration at TDM
mode. In this mode, the SDTO pin of device #N is connected to TDMIN pin of device #(N+1). The device can output up
to 8ch TDM data multiplexed with TDMIN data. Figure 11shows a connection example of a daisy chain.
48kHz
256fs
(TDMIN of AK4127 #3)
OLRC
K
AK4127 #1
OBIC
K
TDMIN
SDTO
OMCL
K
256fs or 512fs
GND
OLRC
K
AK4127 #2
OBIC
K
TDMIN
SDTO
OMCL
K
Figure 11. Cascade TDM Connection Diagram
OLRCK
OBICK(256fs)
#1 SDTO(o) 33 0
L #1
32 BICK
256 BICK
22 0
R #1
32 BICK
23 23
= #2 TDMIN(i)
22 0
L #4
32 BICK
22 0
R #4
32 BICK
22 23 23 23 22 0
L #3
32 BICK
22 0
R #3
32 BICK
23 23 22 0
L #2
32 BICK
22 0
R #2
32 BICK
23 23 22 0
L #1
32 BICK
22 0
R #1
32 BICK
23 23
#2 SDTO(o)
= #3 TDMIN(i)
#3 SDTO(o)
= #4 TDMIN(i)
#4 SDTO(o)
22 0
L #3
32 BICK
22 0
R #3
32 BICK
23 23 22 0
L #2
32 BICK
22 0
R #2
32 BICK
23 23 22 0
L #1
32 BICK
22 0
R #1
32 BICK
23 23 22 23
22 0
L #2
32 BICK
22 0
R #2
32 BICK
23 23 22 0
L #1
32 BICK
22 0
R #1
32 BICK
23 23 22 23
22 23
Figure 12. Cascade TDM Timing (4devices)
[AK4127]
MS0593-E-02 2010/05
- 19 -
■ Soft Mute Operation
1. Manual mode
Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by the SMUTE pin.
When the SMUTE pin changes to “H”, the SRC output data is attenuated by −∞ within 1024 OLRCK cycles. When the
SMUTE pin changes to “L” the mute is cancelled and the output attenuation gradually changes to 0dB during 1024
OLRCK cycles. If the soft mute is cancelled before mute state after starting of the operation, the attenuation is
discontinued and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source.
SMUTE
Attenuation
0dB
-∞
(1) (2)
SDTO
1024/fso
Figure 13. Soft Mute Function (Manual Mode)
(1) The output data is attenuated by −∞ during 1024 OLRCK cycles (1024/fso).
(2) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and
returned to 0dB by the same number of clock cycles.
2. Semi-Auto mode
The soft mute is cancelled automatically by the setting of PLL2-0 pins (Table 2), after the AK4127 detects the rising edge
(PDN pin = “L” → “H”) and the mute is continued during 4410/fso=100ms@fso=44.1kHz. After PDN pin = “L” → “H”
and when SMUTE pin is “H”, the mute is not cancelled.
PD N pin
Attenuation
0dB
-∞
SDTO
4410/fso (1)
SMUTE pin Don’t care “L”
“L ”
Figure 14. Soft Mute Function (Semi-Auto Mode)
(1) The output data is returned to 0dB during 1024 OLRCK cycles (1024/fso).
[AK4127]
MS0593-E-02 2010/05
- 20 -
■ Dither
The AK4127 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the
OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode.
■ System Reset
Bringing the PDN pin = “L” sets the AK4127 power-down mode and initializes the digital filter. The AK4127 should be
reset once by bringing the PDN pin = “L” when power-up. When the PDN pin = “L”, the SDTO output is “L”. The SDTO
valid time is 100ms. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
External clocks
(Input port)
SDTI
Don’t care
SDTO
(Internal state) Power-down Normal
operation
PLL lock &
fs detection
< 100ms
Normal data
Input Clocks 1
External clocks
(Output port)
Don’t care
Don’t care
PDN
Power-down
Don’t care
Don’t care
Don’t care
“0” data
Normal
operation
PLL lock &
fs detection
< 100ms
Normal data
PD
Input Data 1
Output Clocks 1
Input Clocks 2
Input D ata 2
Output C l ocks 2
“0” data “0” data
UNLOCK
Figure 15. System Reset
Case 2
External clocks
(Input port)
SDTI
SDTO
(Internal state) Power-down Normal
operation
PLL lock &
fs detection
< 100ms
Normal data
(No Clock)
External clocks
(Output port)
PDN
Power-down
Don’t care
Don’t care
Don’t care
“0” data
PLL Unlock
Input Cl ocks
Input Data
Output Clocks
“0” data
(Don’t care)
(Don’t c are)
UNLOCK
Figure 16. System Reset 2
[AK4127]
MS0593-E-02 2010/05
- 21 -
■ Internal Reset Function for Clock Change
The AK4127 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is
output within 100ms.
■ Sequence of Changing Clocks
The change sequence of the clock supplied to AK4127 is shown in Figure 17.
PLL lock &
fs detection
Power-down
External clock
s
(Input port
or Output port )
Clocks 1
SDTO
(Int ernal st ate) Normal operation Nor m al oper at ion
Clocks 2 Don’t ca re
< 100ms
SMUTE
(recom mended) 1024/fso
Att.Level 0dB
-∞dB
Normal data Normal data
1024/fso
PDN pi n
Note1 Note2
Figure 17. Sequence of Changing Clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN
pin changes to “L”. It makes the data on SDTO remain as “0”. SMUTE can also remove this clicking noise.
Note 2. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” for 1024/fso+100ms or more
from the timing PDN pin changes to “H” while the SMUTE pin = “H”.
Note 3. When the PDN pin is not used for this clock change, a distorted signal may output for about 10ms ~ 100ms
(typ) after changing clocks.
■ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H” and the SDTO = “0”. When the PDN pin = “L”, the UNLOCK pin outputs “H”.
[AK4127]
MS0593-E-02 2010/05
- 22 -
■ PLL Loop Filter
The C1 and R should be connected in series and attached between the FILT pin and AVSS in parallel with C2. Please be
careful the noise onto the FILT pin. When using IBICK, the value of external element is not dependent on the IBICK
input frequency.
AK4127
C1
R
FILT
A
VSS
C2
Figure 18. PLL Loop Filter
[Input PORT in slave mode]
1. When using ILRCK
PLL2 PLL1 PLL0 ILRCK R [Ω] C1 [μF] C2 [nF]
L L L
8k ∼ 96kHz 1.8k ± 5% 0.68 ± 30% 0.68 ± 30%
8k ∼ 216kHz 1k ± 5% 1.0 ± 30% 2.2 ± 30%
L L H
16k ∼ 216kHz 1.5k ± 5% 0.68 ± 30% 0.68 ± 30%
8k ∼ 216kHz 1k ± 5% 1.0 ± 30% 2.2 ± 30%
L H L
16k ∼ 216kHz 1.5k ± 5% 0.68 ± 30% 0.68 ± 30%
8k ∼ 216kHz 1k ± 5% 1.0 ± 30% 2.2 ± 30%
L H H
16k ∼ 216kHz 1.5k ± 5% 0.68 ± 30% 0.68 ± 30%
Table 6. PLL Loop Filter (ILRCK Mode)
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz..
2. When using IBICK
PLL2 PLL1 PLL0 ILRCK R [Ω] C1 [μF] C2 [nF]
H * *
8k ∼ 216kHz 470 ± 5% 0.22 ± 30% 1.0 ± 30%
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in Figure 18 are not required.
2. When IMCLK is 128fs or 192fs, the external parts shown in Table 7 are required.
[AK4127]
MS0593-E-02 2010/05
- 23 -
SYSTEM DESIGN
Figure 19 and Figure 20 show the system connection diagrams. The evaluation board demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Slave mode, 24bit MSB justified
• Dither = OFF
FILT1
3
4
5
6
7
8
9
10
11
AVSS
PDN
SMUTE
DITHER
PLL2
ILRCK
IBICK
SDTI
IDIF0
IDIF1
AK4127
30
29
28
AVDD
DVSS
DVDD
12 IDIF2
13 PLL0
14 PLL1
27
26
OMCLK
OLRCK
25
24
OBICK
SDTO
ODIF1
ODIF0
21
20
CMODE2
CMODE1
19
18
CMODE0
IMCLK
17OBIT1
22
23
15 UNLOCK 16OBIT0
1.0n
2
10μ
0.1μ
0.1μ
Supply
3.0 ~ 3.6V
470
fsi
64fsi
64fso
fso
Reset
DSP
DSP, uP
0.22μ
Note:
- AVSS and DVSS of the AK4127 must be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins must not be left floating.
Figure 19. Typical Connection Diagram (Slave mode)
[AK4127]
MS0593-E-02 2010/05
- 24 -
• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Master mode, 24bit MSB justified
• Dither = OFF
FILT1
3
4
5
6
7
8
9
10
11
AVSS
PDN
SMUTE
DITHER
PLL2
ILRCK
IBICK
SDTI
IDIF0
IDIF1
AK4127
30
29
28
AVDD
DVSS
DVDD
12 IDIF2
13 PLL0
14 PLL1
27
26
OMCLK
OLRCK
25
24
OBICK
SDTO
ODIF1
ODIF0
21
20
CMODE2
CMODE1
19
18
CMODE0
IMCLK
17OBIT1
22
23
DSP
15 UNLOCK 16OBIT0
1.0n
2
DSP, uP
10μ
0.1μ
Supply
3.0 ~ 3.6V
470
fsi
64fsi
64fso
fso
128fso
Reset 0.1μ
0.22μ
Note:
- AVSS and DVSS of the AK4127 must be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins must not be left floating.
Figure 20. Typical Connection Diagram (Master mode)
1. Grounding and Power Supply Decoupling
The AK4127 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4127 as
possible, with the small value ceramic capacitor being the nearest.
[AK4127]
MS0593-E-02 2010/05
- 25 -
2. Jitter Tolerance
Figure 21 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter
amplitude shown in Figure 21. When the jitter amplitude is 0.01Uipp or less, the AK4127 operates normally regardless of
the jitter frequency.
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.)
(3) There is a possibility that the output data is lost.
Note:
- When PLL2-0 = “L/*/*” (*: Don’t care), the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one cycle of
ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8μs.
- When PLL2-0 = “H/*/*” (*: Don’t care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of
IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns.
Figure 21. Jitter Tolerance
Tracking to the Input Sampling Frequency
When the ILRCK is generated by an external PLL, it may take time to settle after changing the input sampling frequency
because the response of an external PLL to the frequency change is slow. The AK4127 operates normally up to 23%/sec
speed but outputs incorrect data at the speed of the frequency change over 23%/sec.
AK4127 Jitter Tolerance
0.00
0.01
0.10
1.00
10.00
1 10 100 1000 10000
Jitter Frequency [Hz]
Amplitude [UIpp]
(3)
(2)
(1)
[AK4127]
MS0593-E-02 2010/05
- 26 -
3. Digital Filter Response Example
Table 8 shows the examples of digital filter response performed by the AK4127.
Ratio FSO/FSI [kHz] Passband [kHz] Stopband [kHz] Stopband
Attenuation [dB] Gain [dB]
4.000 192/48.0 22.000 26.000 −121.2 −0.01@ 20k
1.000 48.0/48.0 22.000 26.000 −121.2 −0.01@ 20k
0.919 44.1/48.0 20.000 24.100 −121.4 −0.01@ 20k
0.725 32.0/44.1 14.088 17.487 −115.3 −0.01@ 14.5k
0.667 32.0/48.0 13.688 17.488 −116.9 −0.19@ 14.5k
0.544 48.0/88.2 19.250 26.232 −114.6 −0.03@ 20k
0.500 48.0/96.0 20.900 27.000 −100.2 −0.01@ 20k
0.500 44.1/88.2 19.202 24.806 −100.2 −0.08@ 20k
0.459 44.1/96.0 18.700 25.000 −103.3 −0.23@ 20k
0.363 32.0/88.2 12.863 18.665 −102.0 −0.75@ 14.5k
0.333 32.0/96.0 12.500 18.900 −103.6 −1.07@ 14.5k
0.250 48.0/192.0 17.600 30.200 −104.0 −0.18@ 20k
0.250 44.1/176.4 16.170 27.746 −104.0 −1.34@ 20k
0.230 44.1/192.0 15.860 28.240 −103.3 −1.40@ 20k
0.167 32.0/192.0 11.200 19.600 −73.2 −2.97@ 14.5k
0.181 32.0/176.4 10.278 17.987 −73.2 −7.88@ 14.5k
0.167 8/48.0 2.800 4.900 −73.2 −2.97@ 3.625k
0.181 8/44.1 2.5695 4.4968 −73.2 −7.88@ 3.625k
Table 8. Digital Filter Example
[AK4127]
MS0593-E-02 2010/05
- 27 -
PACKAGE
Det ail A
NO TE : Dimension "*" does not include mold flash.
0.22±0.1 0.65
*9.7±0.1 1.5MAX
A
115
16
30
30pin V SOP (Unit: m m )
5.6±0.1
7.6±0.2
0.45±0.2
-0.0 5
+0.10
0.3
0.15
0.12 M
0.08
1.2±0.10
0.10 +0.10
-0.05
■ Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
[AK4127]
MS0593-E-02 2010/05
- 28 -
MARKING
AKM
AK4127VF
XXXBYYYYC
XXXBYYYYC Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents
07/02/07 00 First edition
07/07/26 01
Description
Change 19 Figure 13 and Figure 14 were changed.
21
■ Internal Rest Function for Clock Change
■ Sequence of Changing Clocks
■ UNLOCK pin
10/05/17 02
Description
Addition 21 ■ Sequence of changing clocks
Description is added in notes.
[AK4127]
MS0593-E-02 2010/05
- 29 -
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
