PLL1700EG4 - Texas Instruments - Datasheet.Directory

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PLL1700

MULTI-CLOCK GENERATOR

FEATURES

●27MHz MASTER CLOCK INPUT

●GENERATED AUDIO SYSTEM CLOCK:

SCKO1: 33.8688MHz (Fixed)

SCKO2: 256fS

SCKO3: 384fS

SCKO4: 768fS

●ZERO PPM ERROR OUTPUT CLOCKS

●LOW CLOCK JITTER: 150ps at SCKO3

●MULTIPLE SAMPLING FREQUENCIES:

fS = 32kHz, 44.1kHz, 48kHz, 64kHz,

88.2kHz, 96kHz

●+3.3V CMOS LOGIC INTERFACE

●DUAL POWER SUPPLIES: +5V and +3.3V

●SMALL PACKAGE: 20-Lead SSOP

OSC

PLL2

PLL1

Counter Q Counter P

SCKO2 SCKO3 SCKO4

MCKOMCKO

XT1

XT2

Reset

Mode

Control

I/F

Power Supply

RST

MODE ML MC MD V

DDP

DDB

GNDP GNDB GND

SCKO1

PLL1700

SBOS096A – JANUARY 1998 – REVISED MAY 2007

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

DESCRIPTION

The PLL1700 is a low cost, multi-clock generator Phase

Lock Loop (PLL).

The PLL1700 can generate four systems clocks from a

27MHz reference input frequency.

The device gives customers both cost and space savings

by eliminating external components and enables custom-

ers to achieve the very low jitter performance needed for

high-performance audio digital-to-analog converters

(DACs) and/or analog-to-digital converters (ADCs).

The PLL1700 is ideal for MPEG-2 applications that use a

27MHz master clock such as DVD players, DVD add-on

cards for multimedia PCs, digital HDTV systems, and set-

top boxes.

PLL1700

2SBOS096A

www.ti.com

PIN ASSIGNMENTS

PIN CONFIGURATION

TOP VIEW SSOP

PACKAGE INFORMATION(1)

SPECIFIED

TEMPERATURE PACKAGE

PRODUCT PACKAGE RANGE DESIGNATOR

PLL1700E 20-Lead SSOP –25°C to +85°CDB

NOTE: (1) For the most current package and ordering information, see the

Package Option Addendum at the end of this data sheet, or see the TI web

site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Supply Voltage (+VDD, +VDDP, +VDDB) .............................................. +6.5V

Supply Voltage Differences (+VDD, +VDDP) ....................................... ±0.1V

GND Voltage Differences: GND, GNDP, GNDB............................... ±0.1V

Digital Input Voltage................................................. –0.3V to (VDD + 0.3V)

Digital Output Voltage ............................................ –0.3V to (VDDB + 0.3V)

Input Current (any pins except supply pins) ................................... ±10mA

Power Dissipation .......................................................................... 300mW

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature...................................................... –55°C to +125°C

Lead Temperature (soldering, 5s).................................................. +260°C

Package Temperature (IR reflow, 10s) .......................................... +235°C

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PIN NAME I/O FUNCTION

1 ML/SR0 IN Latch Enable for Software Mode/Sampling Rate

Selection for Hardware Mode. When MODE pin

is LOW, ML is selected.(1)

2 MODE IN Mode Control Select. When this pin is HIGH,

device is operated in hardware mode using SR0

(pin 1), FS0 (pin 19), and FS1 (pin 20). When

this pin is LOW, device is operated in software

mode by three-wire interface using ML (pin 1),

MD (pin 19) and MC (pin 20).(1)

DD — Digital Power Supply, +5V.

4 GND — Digital Ground.

5 XT2 — 27MHz Crystal. When an external 27MHz clock

is applied to XT1 (pin 6), this pin must be

connected to GND.

6 XT1 IN 27MHz Oscillator Input/External 27MHz Input.

7 GNDP — Ground for PLL.

DDP — Power Supply for PLL, +5V.

9 RSV — Reserved. Must be left open.

10 MCKO OUT 27MHz Output.

11 MCKO OUT Inverted 27MHz Output.

12 SCKO1 OUT Fixed 33.8688MHz Clock Output.

13 SCKO4 OUT 768fS Clock Output.

14 SCKO2 OUT 256fS Clock Output.

15 GNDB — Digital Ground for VDDB.

16 VDDB — Digital Power Supply for Clock Output Buffers,

+3.3V.

17 SCKO3 OUT 384fS Output. This output has been optimized

for the lowest jitter and should be connected to

the audio DAC(s).

18 RST IN Reset. When this pin is LOW, device is held in

reset.(1)

19 MD/FS0 IN Serial Data Input for Software Mode/Sampling

Frequency Selection for Hardware Mode. When

MODE pin is LOW, MD is selected.(1)

20 MC/FS1 IN Shift Clock Input for Software Mode/Sampling

Frequency Selection for Hardware Mode. When

MODE pin is LOW, MC is selected.(1)

NOTE: (1) Schmitt-trigger input with internal pull-down resistors.

ML/SR0

MODE

GND

XT2

XT1

GNDP

DDP

RSV

MCKO

MC/FS1

MD/FS0

RST

SCKO3

DDB

GNDB

SCKO2

SCKO4

SCKO1

MCKO

PLL1700E

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handled with appropriate precautions. Failure to ob-

serve proper handling and installation procedures can

cause damage.

ESD damage can range from subtle performance deg-

radation to complete device failure. Precision integrated

circuits may be more susceptible to damage because

very small parametric changes could cause the device

not to meet its published specifications.

PLL1700 3

SBOS096A www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, fM = 27MHz crystal oscillation, and fS = 48kHz, unless otherwise noted.

PLL1700E

PARAMETER CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUT/OUTPUT

Input Logic Level: TTL-Compatible

VIH(1) 2.0 VDC

VIL(1) 0.8 VDC

VIH(2) 1.2 VDC

VIL(2) 0.4 VDC

Input Logic Current:

IIH(1) VIN = VDD 200 µA

IIL(1) VIN = 0V –1µA

IIH(2) VIN = VDD 4mA

IIL(2) VIN = 0V –800 µA

Output Logic Level: CMOS

VOH(3) IOH = 4mA VDDB – 0.4V VDC

VOL(3) IOL = 4mA 0.4 VDC

Sampling Frequency (fS) Standard fS32 44.1 48 kHz

Double fS64 88.2 96 kHz

MASTER CLOCK (MCKO, MCKO) fM = 27MHz, CL = 20pF

Master Clock Frequency 26.73 27 27.27 MHz

Clock Jitter(4) 300 ps

Clock Duty Cycle MCKO C1 = C2 = 15pF 40 50 60 %

For Crystal Oscillation MCKO 40 50 60 %

Clock Duty Cycle MCKO 40 %

For External Clock MCKO 60 %

PHASE LOCK LOOP (PLL) fM = 27MHz, CL = 20pF

Generated System Clock Frequency

SCKO1 Fixed 33.8688 MHz

SCKO2 256fS8.192 24.576 MHz

SCKO3 384fS12.288 36.864 MHz

SCKO4 768fS24.576 36.864 MHz

Generated Clock Rise Time(3) 20% to 80% VDDB 5ns

Generated Clock Fall Time(3) 80% to 20% VDDB 5ns

Generated Clock Duty Cycle SCKO1, SCKO3, SCKO4 40 50 60 %

SCKO2 (standard) 40 50 60 %

SCKO2 (double)(5) 25 33 40 %

Generated Clock Jitter(4) SCKO1, SCKO2 (standard), SCKO4 300 ps

SCKO3 150 ps

SCKO2 (double) 450 ps

Settling Time To Programmed Frequency 20 ms

Power-Up Time To Programmed Frequency 15 30 ms

POWER SUPPLY REQUIREMENTS

Voltage Range VDD, VDDP +4.5 +5 +5.5 VDC

VDDB +2.7 +3.3 +3.6 VDC

Supply Current(6):

IDD + IDDP VDD = VDDP = 5V, fS = 48kHz 11 16 mA

IDDB VDDB = +3.3V, fS = 48kHz 6 9 mA

Power Dissipation fS = 48kHz 75 110 mW

TEMPERATURE RANGE

Operation –25 +85 °C

Storage –55 +125 °C

NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor).

(2) XT1, when an external 27MHz clock is used, the buffer ICs, such as 74HC04, are recommended to interface to XT1.

(3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.

(4) Jitter performance is specified as standard deviation of jitter under 27MHz crystal oscillation.

(5) When SCKO2 is set to double rate clock output, its duty cycle is 33%.

(6) fM = 27MHz crystal oscillation, no load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.

PLL1700

4SBOS096A

www.ti.com

TYPICAL CHARACTERISTICS

At TA = +25°C, VDD = VDDP = +5V, VDDB = +3.3V, CL = 20pF, unless otherwise noted.

JITTER vs SAMPLING FREQUENCY

Sampling Frequency, f

(kHz)

Jitter (pS rms)

400

300

200

100

044.132 48 96

SCKO1

SCKO3

MCKO

DUTY CYCLE RATIO vs SAMPLING FREQUENCY

Sampling Frequency, fS (kHz)

Duty Cycle Ratio (%)

30 44.132 48 96

SCKO3 MCKO (XTAL Operation)

MCKO (External Clock)

300

200

100

0–25 +25 +85

Temperature (°C)

SCKO Jitter (pS rms)

SCKO3 JITTER vs TEMPERATURE

48kHz

32kHz

96kHz

300

200

100

02.7 3.3 3.6

DDB

(V)

SCKO Jitter (pS rms)

SCKO3 JITTER vs V

DDB

48kHz

32kHz

96kHz

PLL1700 5

SBOS096A www.ti.com

THEORY OF OPERATION

MASTER CLOCK AND SYSTEM CLOCK OUTPUT

The PLL1700 consists of a dual PLL clock and master

clock generator which generates four system clocks and

two buffered 27MHz clocks from a 27MHz master clock.

Figure 1 shows the block diagram of the PLL1700. The

PLL is designed to accept a 27MHz master clock or

crystal oscillator. The master clock can be either a crystal

oscillator placed between XT1 (pin 6) and XT2 (pin 5), or

an external input to XT1. If an external master clock is

used, XT2 must be connected to ground. In both cases,

the signal amplitude on XT1 must satisfy the specification

described in Figure 3. Therefore, careful C1 and C2

determination is required for keeping this specification

when using a crystal oscillator.

Figure 2 illustrates possible system clock connection

options. Figure 3 illustrates the 27MHz master clock

timing requirements.

FIGURE 1. Block Diagram of PLL1700.

FIGURE 2. Master Clock Generator Connection Diagram.

FIGURE 3. External Master Clock Timing Requirement.

XT1H

XT1L

1.2V

XT1 0.4V

DESCRIPTION SYMBOL MIN TYP MAX UNITS

System Clock Pulse Width HIGH tXT1H 10 ns

System Clock Pulse Width LOW tXT1L 15 ns

OSC

Counter N

Counter M

Counter P

Counter Q

SCKO2

256f

SCKO1

33.8688MHz SCKO4

768f

SCKO3

384f

Data

ROM

Frequency Control PLL2

PLL1

Phase Detector

and

Loop Filter VCO

VCO

Counter M

Counter N

Phase Detector

and

Loop Filter

MCKO

27MHz MCKO

XT2 XT1

, C

= 10pF to 33pF

27MHz Internal

Master Clock

XTI

XT2

Crystal

OSC

Circuit

Xtal

PLL1700

MCKO

Buffer

External Clock

Crystal Resonator Connection

MCKO

Buffer

Crystal

OSC

Circuit

27MHz Internal

Master Clock

XT1

XT2

PLL1700

MCKO

Buffer

External Clock Input

MCKO

Buffer

PLL1700

6SBOS096A

www.ti.com

The PLL1700 provides a very low jitter, high accuracy

clock. SCKO1 is a fixed frequency clock which is

33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The

output frequency of the remaining clocks is determined by

the sampling frequency (fS) by software or hardware

control. SCKO2 and SCKO3 output 256fS and 384fS

systems clocks, respectively. SCKO4 output is 768fS if the

sampling frequency is 32kHz, 44.1kHz, 48kHz, or the

output is 384fS if the sampling frequency is 64kHz, 88.2kHz,

or 96kHz. Table I shows each sampling frequency. The

system clock output frequencies are generated by a

27MHz master clock and programmed sampling frequen-

cies are shown in Table II.

SAMPLING

FREQUENCY SAMPLING SKCO2 SCKO3 SCKO4

(kHz) RATE (MHz) (MHz) (MHz)

32 Standard 8.192 12.288 24.576

44.1 Standard 11.2896 16.9344 33.8688

48 Standard 12.288 18.4320 36.8640

64 Double 16.384 24.576 24.576

88.2 Double 22.5792 33.8688 33.8688

96 Double 24.576 36.8640 36.8640

TABLE II. Sampling Frequencies and Master Clock

Output Frequencies.

SAMPLING

SAMPLING RATE FREQUENCY (kHz)

Standard Sampling Frequencies 32 44.1 48

Double of Standard Sampling Frequencies 64 88.2 96

TABLE I. Sampling Frequencies.

FUNCTION CONTROL

The built-in function of the PLL1700 can be controlled in

the software mode (serial mode), which uses a three-wire

interface by ML (pin 1), MC (pin 20), and MD (pin 19), when

MODE (pin 2) = L. They can also be controlled in the

hardware mode (parallel mode) which uses SR0 (pin 1),

FS1 (pin 20) and FS0 (pin 19), when MODE (pin 2) = H.

The selectable functions are shown in Table III.

HARDWARE SOFTWARE

MODE MODE

FUNCTION (MODE = H) (MODE = L)

Sampling Frequency Select

(32kHz, 44.1kHz, 48kHz) Yes Yes

Sampling Rate Select (Standard/Double) Yes Yes

Each Clock Output Enable/Disable No Yes

TABLE III. Selectable Functions.

Response time from power-on (or applying the clock to

XT1) to SCKO settling time is typically 15ms. Delay time

from sampling frequency change to SCKO settling time is

20ms maximum. Figure 4 illustrates SCKO transient

timing.

External buffers are recommended on all output clocks in

order to avoid degrading the jitter performance of the

PLL1700.

RESET

The PLL1700 has an internal power-on reset circuit, as

well as an external forced reset (RST, pin 18). Both resets

have the same effect on the PLL1700 functions. The

mode register default settings for software mode are

initialized by reset. Throughout the reset period, all clock

outputs are enabled with the default settings. Initialization

for the internal power-on reset is done automatically

during 1024 master clocks at VDD ≥ 2.2V (1.8V to 2.6V).

When using the internal power-on reset, RST should be

HIGH. Power-on reset timing is shown in Figure 5. RST

(pin 18) accepts an external forced reset by RST = L.

Initialization (reset) is done when RST = L and 1024

master clocks after RST = H. External reset timing is

shown in Figures 6 and 7.

FUNCTION DEFAULT

Sampling Frequency Select (32kHz, 44.1kHz, 48kHz) 48kHz Group

Sampling Rate Select (Standard/Double) Standard

Each Clock Output Enable/Disable Enable

TABLE IV. Selectable Functions.

FS1 (Pin 20) FS0 (Pin 19) SAMPLING GROUP

L L 48kHz

L H 44.1kHz

H L 32kHz

H H Reserved

SR0 (Pin 1) SAMPLING RATE SELECT

L Standard

H Double

HARDWARE MODE (MODE = H)

In the hardware mode, the following functions can be

selected:

Sampling Group Select

The sampling frequency group can be selected by FS1

(pin 20) and FS0 (pin 19). This selection must be made

with an interval time greater than 20µs.

Sampling Rate Select

The sampling rate can be selected by SR0 (pin 1).

SOFTWARE MODE (MODE = L)

The PLL1700 special function in software mode is shown

in Table IV. These functions are controlled using ML, MC,

and MD serial control signal.

PLL1700 7

SBOS096A www.ti.com

FIGURE 4. System Clock Transient Timing Chart.

1024 System Clock Periods

Reset Reset Removal

2.6V

2.2V

1.8V

Internal Reset

Master Clock

FIGURE 5. Power-On Reset Timing.

FIGURE 6. External Reset Timing.

FIGURE 7. Reset Pulse Timing Requirement.

3 clocks of MCKO

SCKO2

SCKO3

SCKO4

SCKO1

Clock Transistion Region

33.8688MHz

StableStable

20ms

1024 System Clock Periods

Reset Reset Removal

Master Clock

Internal Reset

RST t

RST

System Clock Pulse Width LOW tRST 20ns (min)

tRST

1.4V

RST

PLL1700

8SBOS096A

www.ti.com

FIGURE 8. Software Mode Control Format.

FS1 FS0 SAMPLING FREQUENCY DEFAULT

0 0 48kHz O

0 1 44.1kHz

1 0 32kHz

1 1 Reserved

PROGRAM REGISTER BIT-MAPPING

The built-in functions of the PLL1700 are controlled through

a 16-bit program register. This register is loaded using

MD. After the 16 data bits are clocked in using the rising

edge of MC, ML is used to latch the data into the register.

Table V shows the bit-mapping of the registers. The

software mode control format and control data input

timing is shown in Figures 8 and 9, respectively.

Mode Register

CE [1:6]: Clock Output Control

DESCRIPTION SYMBOL MIN TYP MAX UNITS

MC Pulse Cycle Time tMCY 100 ns

MC Pulse Width LOW tMCL 40 ns

MC Pulse Width HIGH tMCH 40 ns

MD Hold Time tMDH 40 ns

MD Set-Up Time tMDS 40 ns

ML Low Level Time tMLL 16

MC Clocks

(1)

ML High Level Time tMHH 200 ns

ML Hold Time(2) tMLH 40 ns

ML Set-Up Time(3) tMLS 40 ns

NOTES: (1) MC clocks: MC clock period. (2) MC rising edge for LSB to ML rising edge. (3) ML rising edge

to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted.

FIGURE 9. Control Data Input Timing.

MODE CE6 MCKO Output Enable/Disable

CE5 MCKO Output Enable/Disable

CE4 SCKO4 Output Enable/Disable

CE3 SCKO3 Output Enable/Disable

CE2 SCKO2 Output Enable/Disable

CE1 SCKO1 Output Enable/Disable

SR [1:0] Sampling Rate Select

FS [1:0] Sampling Frequency Select

TABLE V. Register Mapping.

Mode Register

FS [1:0]: Sampling Frequency Group Select. This se-

lection must be made with an interval time

greater than 20µs.

SR [1:0]: Sample Rate Select

SR1 SR0 SAMPLING RATE DEFAULT

0 0 Standard O

0 1 Double

1 0 Reserved

1 1 Reserved

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ML (pin 1)

MC (pin 20)

MD (pin 19)

D15D14D13D12D11D0D9D8 D7D6D5D4D3D2D1D0

0 1 1 1 0 0 CE6 CE5 CE4 CE3 CE2 CE1 SR1 SR0 FS1 FS0

CE1 - CE6 CLOCK OUTPUT CONTROL DEFAULT

0 Clock Output Disable

1 Clock Output Enable O

MSB LSB

1.4V

MLS

MCH

MCL

MLL

MHH

MLH

MLS

MDS

MDH

MCY

ML (pin 1)

MC (pin 20)

MD (pin 19)

PLL1700 9

SBOS096A www.ti.com

CONNECTION DIAGRAM

Figure 10 shows the typical connection circuit for the

PLL1700. There are three grounds for digital, analog and

PLL power supply. However, the use of one common

ground connection is recommended to avoid latch-up

problems. Power supplies should be bypassed as close

as possible to the device.

MPEG-2 APPLICATIONS

Typical applications for the PLL1700 are MPEG-2 based

systems such as DVD players, DVD add-on cards for

multimedia PCs, digital HDTV systems, and set-top boxes.

The PLL1700 provides audio system clocks for a CD-DA

DSP, DVD DSP, Karaoke DSP, and DAC(s) from a

27MHz video clock.

FIGURE 11. PLL1700 System Application Block Diagram.

FIGURE 10. Typical Connection Diagram.

Clock

Output(3)

Mode

Control

0.1µF and 10µF(1)

PLL1700E

ML/SR01

MODE

VDD

GND

XT2

XT1

GNDP

VDDP

RSV

MCKO

MC/FS1

MD/FS0

RST

SCKO3

VDDB

GNDB

SCKO2

SCKO4

SCKO1

MCKO

0.1µF

and

10µF(1)

22µF to 47µF

C122µF to 47µF

0.1µF

and

10µF(1)

(2)

+5V

+3.3 V

NOTES: (1) 0.1µF ceramic and 10µF electrolytic capacitor typical, depending on quality of power supply and pattern layout.

(2) 27MHz quartz crystal and 10pF through two 33pF ceramic capacitors.

(3) To achieve best possible jitter performance, it is recommended to minimize the load capacitance on the clock output.

PCM1716

Front

Surround

Center

Subwoofer

384f

768f

256f

SCKO3

SCKO4

SCKO2

MCKO

PLL1700

27MHz

Crystal

CD-DA/

DVD DSP MPEG/AC-3

Audio Decoder

Karaoke

DSP

SCKO1

PLL1700

10 SBOS096A

www.ti.com

DATE REVISION PAGE SECTION DESCRIPTION

—Entire Document Updated format to current standard look.

Added note (1) to VIH and VIL.

Added two rows to

Input Logic Level

for VIH and VIL with note (2).

Added condition to

Clock Duty Cycle

row stating that C1 = C2 = 15pF.

Changed "X2 should be connected" to "X2 must be connected."

Added text regarding signal amplitude.

Changed voltage from 2.0V to 1.2V.

Changed voltage from 0.8V to 0.4V.

Changed tXT1H min value from 15 to 10.

6 Sampling Group Select Added text regarding interval time.

8 Mode Register Added text regarding interval time.

Deleted note (1) from C1 and C2.

Changed note text from "tantalum" to "electrolytic" capacitor.

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

5/07 A

3Electrical Characteristics

5Master Clock and

System Clock Output

5Figure 5

9 Figure 10

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

PLL1700E NRND SSOP DB 20 65 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PLL1700E-1/2K OBSOLETE SSOP DB 20 TBD Call TI Call TI

PLL1700E-1/2KG4 OBSOLETE SSOP DB 20 TBD Call TI Call TI

PLL1700E/2K NRND SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PLL1700E/2KG4 NRND SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PLL1700EG NRND SSOP DB 20 65 Pb-Free

(RoHS) CU SNBI Level-1-260C-UNLIM

PLL1700EG/2K NRND SSOP DB 20 2000 Pb-Free

(RoHS) CU SNBI Level-1-260C-UNLIM

PLL1700EG/2KE6 NRND SSOP DB 20 2000 Pb-Free

(RoHS) CU SNBI Level-1-260C-UNLIM

PLL1700EG4 NRND SSOP DB 20 65 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PLL1700EGE6 NRND SSOP DB 20 65 Pb-Free

(RoHS) CU SNBI Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 3-Jul-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

PLL1700E/2K SSOP DB 20 2000 330.0 17.4 8.5 7.6 2.4 12.0 16.0 Q1

PLL1700EG/2K SSOP DB 20 2000 330.0 17.4 8.5 7.6 2.4 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jun-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PLL1700E/2K SSOP DB 20 2000 336.6 336.6 28.6

PLL1700EG/2K SSOP DB 20 2000 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jun-2008

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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