1
®
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
HIP2101
100V/2A Peak, Low Cost, High Frequency
Half Bridge Driver
The HIP2101 is a high frequency, 100V Half Bridg e
N-Channel power MOSFET driver IC. It is equivalent to the
HIP2100 with the added advantage of full TTL/CMOS
compatible logic input pins. The low-side and high-side gate
drivers are independently control led and matched to 13ns.
This gives users total control over dead-time for specific
power circuit topologies. Undervoltage protection on both
the low-side and high-side supplies force the outputs low. An
on-chip diode eliminates the discrete diode required with
other driver ICs. A new level-shifter topology yields the low-
power benefits of pulsed operation with the safety of DC
operation. Unlike some competitors, the high-side output
returns to its correct state after a momentary undervoltage of
the high-side supply.
Features
• Drives N-Channel MOSFET Half Bridge
• SOIC, EPSOIC, QFN and DFN Package Options
• SOIC, EPSOIC and DFN Packages Compliant with 100V
Conductor Spacing Guidelines of IPC-2221
• Pb-free Product Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1Ω Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1000pF Load with Rise and Fall T imes Typ. 10ns
• TTL/CMOS Input Thresholds Increase Flexibility
• Independent Inputs for Non-Half Bridge Topologies
• No Start-Up Problems
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground, or HS Slewing at High dv/dt
• Low Power Consumption
• Wide Supply Range
• Supply Undervoltage Protection
•3Ω Output Driver Resistance
• QFN/DFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
Applications
• Telecom Half Bridge Power Supplies
• Avionics DC-DC Converters
• Two-Switch Forward Converters
• Active Clamp Forward Conve r ters
Ordering Information
PART NUMBER TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
HIP2101IB -40 to 125 8 Ld SOIC M8.15
HIP2101IBZ (Note 1) -40 to 125 8 Ld SOIC (Pb-free) M8.15
HIP2101EIB -40 to 125 8 Ld EPSOIC M8.15C
HIP2101EIBZ
(Note 1) -40 to 125 8 Ld EPSOIC
(Pb-free) M8.15C
HIP2101IR -40 to 125 16 Ld 5x5 QFN L16.5x5
HIP2101IRZ (Note 1) -40 to 125 16 Ld 5x5 QFN
(Pb-free) L16.5x5
HIP2101IR4 -40 to 125 12 Ld 4x4 DFN L12.4x4A
HIP2101IR4Z
(Note 1) -40 to 125 12 Ld 4x4 DFN
(Pb-free) L12.4x4A
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
2. Add “T” suffix for Tape and Reel packing option.
Data Sheet October 21, 2004 FN9025.8
2FN9025.8
Application Block Diagram
Pinouts
HIP2101 (SOIC, EPSOIC)
TOP VIE W HIP2101IR4 (DFN)
TOP VIEW
HIP2101 (QFN)
TOP VIEW
NOTE: EPAD = Exposed PAD.
5
6
8
7
4
3
2
1
VDD
HB
HO
HS
LO
LI
HI
VSS
EPAD
VDD
NC
NC
HB
HO
LO
VSS
NC
NC
LI
HS HI
2
3
4
1
5
11
10
9
12
8
6 7
EPAD
1
3
4
15
HB
HO
VDD
LO
16 14 13
2
12
10
9
11
6578
VSS
LI
HS
HI
NC
NC
NC
NC
NC
NC
NC
NC
EPAD
SECONDARY
CIRCUIT
+100V
CONTROL
CONTROLLER
PWM
LI
HI HO
LO
VDD
HS
HB
+12V
VSS
HIP2101 REFERENCE
AND
ISOLATION
DRIVE
LO
DRIVE
HI
HIP2101
3FN9025.8
Functional Block Diagram
UNDER
VOLTAGE
VDD
HI
LI
VSS
DRIVER
DRIVER
HB
HO
HS
LO
LEVEL SHIFT
UNDER
VOLTAGE
EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
SECONDARY
HIP
2101
ISOLATION
PWM
+48V
+12V
CIRCUIT
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
SECONDARY
CIRCUIT
HIP
2101
ISOLATION
PWM
+48V
+12V
FIGURE 2. FORWARD CONVERT ER WITH AN ACTIVE CLAMP
HIP2101
4FN9025.8
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD, VHB-VHS (Notes 3, 4). . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on HO (Note 4) . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V
Average Current in VDD to HB diode. . . . . . . . . . . . . . . . . . . 100mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . .+9V to 14.0VDC
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB. . VHS +8V to VHS +14.0V and VDD -1V to VDD +100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
SOIC (Note 5) . . . . . . . . . . . . . . . . . . . 95 N/A
EPSOIC (Note 6) . . . . . . . . . . . . . . . . . 40 3.0
QFN (Note 6) . . . . . . . . . . . . . . . . . . . . 37 6.5
DFN (Note 6) . . . . . . . . . . . . . . . . . . . . 40 3.0
Max Power Dissipatio n at 25 oC in Free Air (SOIC, Note 5) . . . . 1.3W
Max Power Dissipatio n at 25 oC in Free Air (EPSOIC, Note 6). . 3.1W
Max Power Dissipatio n at 25 oC in Free Air (QFN, Note 6). . . . . 3.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65 °C to 150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . .-55°C to 150°C
Lead Temperature (Soldering 10s - SOIC Lead Tips Only). . 300°C
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
3. The HIP2101 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this
mode of operation.
4. All voltages referenced to VSS unless otherwise spe cified.
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Te ch Brief TB379 for details.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS SYMBOL TEST CONDITIONS
TJ = 25°C TJ = -40°C TO
125°C
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS
VDD Quiescent Current IDD LI = HI = 0V - 0.3 0.45 - 0.6 mA
VDD Operating Current IDDO f = 500kHz - 1.7 3.0 - 3.4 mA
Total HB Quiescent Current IHB LI = HI = 0V - 0.1 0.15 - 0.2 mA
Total HB Operating Current IHBO f = 500kHz - 1.5 2.5 - 3 mA
HB to VSS Current, Quiescent IHBS VHS = VHB = 114V - 0.05 1.5 - 10 µA
HB to VSS Current, Operating IHBSO f = 500kHz - 0.7 - - - mA
INPUT PINS
Low Level Input Voltage Threshold VIL 0.8 1.65 - 0.8 - V
High Level Input Voltage Threshold VIH - 1.65 2.2 - 2.2 V
Input Pulldown Resistance RI- 200 - 100 500 kΩ
UNDER VOLTAGE PROTECTION
VDD Rising Threshold VDDR 7 7.3 7.8 6.5 8 V
VDD Threshold Hysteresis VDDH -0.5---V
HB Rising Threshold VHBR 6.5 6.9 7.5 6 8 V
HB Threshold Hysteresis VHBH -0.4---V
HIP2101
5FN9025.8
BOOT STRAP DIODE
Low-Current Forward Voltage VDL IVDD-HB = 100µA - 0.45 0.70 - 0.7 V
High-Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.92 - 1 V
Dynamic Resistance RDIVDD-HB = 100mA - 0.8 1 - 1.5 Ω
LO GATE DRIVER
Low Level Output Voltage VOLL ILO = 100mA - 0.25 0.3 - 0.4 V
High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD-VLO - 0.25 0.3 - 0.4 V
Peak Pullup Current IOHL VLO = 0V -2---A
Peak Pulldown Current IOLL VLO = 12V - 2 - - - A
HO GATE DRIVER
Low Level Output Voltage VOLH IHO = 100mA - 0.25 0.3 - 0.4 V
High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB-VHO - 0.25 0.3 - 0.4 V
Peak Pullup Current IOHH VHO = 0V -2---A
Peak Pulldown Current IOLH VHO = 12V - 2 - - - A
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
TJ = 25°C TJ = -40°C TO
125°C
UNITSMIN TYP MAX MIN MAX
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
PARAMETERS SYMBOL TEST
CONDITIONS
TJ = 25°C TJ = -40°C
TO 125°C
UNITSMIN TYP MAX MIN MAX
Lower Turn-Off Propagation Delay (LI Falling to LO Falling) tLPHL - 25 43 - 56 ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling) tHPHL - 25 43 - 56 ns
Lower Turn-On Propagat io n Delay (L I Rising to LO Rising) tLPLH - 25 43 - 56 ns
Upper Turn-On Propagat io n Delay (H I Risin g to HO Risin g) tHPLH - 25 43 - 56 ns
Delay Matching: Lower Turn-On and Upper Turn-Off tMON -213-16ns
Delay Matching: Lower Turn-Off and Upper Turn-On tMOFF -213-16ns
Either Output Rise/Fall Time tRC,tFC CL = 1000pF - 10 - - - ns
Either Output Rise/Fall Time (3V to 9V) tR,tFCL = 0.1µF - 0.5 0.6 - 0.8 us
Either Output Rise Time Driving DMOS tRD CL = IRFR120 - 20 - - - ns
Either Output Fall Time Driving DMOS tFD CL = IRFR120 - 10 - - - ns
Minimum Input Pulse Width that Changes the Output tPW ----50ns
Bootstrap Diode Turn-On or Turn-Off Time tBS -10- - - ns
HIP2101
6FN9025.8
Timing Diagrams
Pin Descriptions
SYMBOL DESCRIPTION
VDD Positive Supply to lower gate drivers. De-couple this pin to VSS. Bootstrap diode connected to HB.
HB High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO High-Side Output. Connect to gate of High-Side power MOSFET.
HS High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI High-Side input.
LI Low-Side input.
VSS Chip negative supply, generally will be ground.
LO Low-Side Output. Connect to gate of Low-Side power MOSFET.
EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
FIGURE 3. FIGURE 4.
tHPLH,
tLPLH tHPHL,
tLPHL
HI,
LI
HO,
LO
tMON tMOFF
LI
HI
LO
HO
Typical Performance Curves
FIGURE 5A. FIGURE 5B.
FIGURE 5. OPERATING CURRENT vs FREQUENCY
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.00010 30 50 70 200 400 600 800 1000
IDDO (mA)
90
150°C
FREQUENCY (kHz)
125°C
25°C
-40°C
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000 10 30 50 70 200 400 600 800 1000
IHBO (mA)
FREQUENCY (kHz)
90
150°C, 125°C
25°C
-40°C
HIP2101
7FN9025.8
FIGURE 6. HB TO VSS OPERATING CURRENT vs
FREQUENCY FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
Typical Performance Curves (Continued)
T = -40°C
T = 125°C
T = 25°C
T = 150°C
10
1
0.1
0.01
IHBSO (mA )
10 100 1000
FREQUENCY (kHz) TEMPERATURE (°C)
VOHL, VOHH (mV)
500
400
300
200
100
-50 0 50 100 150
VHB = VDD = 9V
VHB = VDD = 12V
VHB = VDD = 14V
TEMPERATURE (°C)
VOLL, VOLH (mV)
500
400
300
200
100
-50 0 50 100 150
VHB = VDD = 9V
VHB = VDD = 12V
VHB = VDD = 14V
TEMPERATURE (°C)
-50 0 50 100 150
7.6
7.4
7.2
7.0
6.8
6.6
VDDR
VHBR
VHBR, VDDR (V)
TEMPERATURE (°C)
-50 0 50 100 15
0
0.54
0.5
0.46
0.42
0.38
0.3
VDDH
VHBH
VHBH, VDDH (mV)
0.34
tHPHL
tHPLH
tLPHL
tLPLH
TEMPERATURE (°C)
-50 0 50 100 150
30
25
20
15
tLPLH, tLPHL, tHPLH, tHPHL (ns)
HIP2101
8FN9025.8
FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT
VOLTAGE
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
FIGURE 16. VHS VOLTAGE vs VDD VOLTAGE
Typical Performance Curves (Continued)
6
2.0
IHO, ILO (A)
12108420
2.5
1.5
1.0
0.5
0
VHO, VLO (V) 6
2.0
ILO, IHO (A)
12108420
2.5
1.5
1.0
0.5
0
VLO, VHO (V)
0.8
1
0.1
0.01
0.001
1•10-4
1•10-5
1•10-6 0.70.60.50.40.3 FORWARD VOLTAGE (V)
FORWARD CURRENT (A)
VDD, V HB (V)
0 5 10 15
60
50
40
0
IDD, IHB (µA)
30
20
10
IDD vs VDD
IHB vs VHB
120
100
80
60
40
20
014 15 1612
VHS TO VSS VOLTAGE (V)
VDD TO VSS VOLTAGE (V)
HIP2101
9FN9025.8
HIP2101
Dual Flat No-Lead Plastic Package (DFN)
Micro Lead Frame Plastic Package (MLFP)
TOP VIEW
INDEX
D1/2
D1
D/2
D
E1/2 E/2
E1 E
A
2X 0.15
B
C
A
N
BOTTOM VIEW
SEATING
PLANE
5
6
23
1
0.10
NX b A1
C
2X C
0.15
0.15
2X B
0
A1
A
C
C
B
2X AC0.15
A2
A3
AREA
//
SIDE VIEW
0.08 C
4X
9
L
5
NX b
4X P
N
eB
0.10 C A
D2
E2
1
(Nd-1)Xe
REF.
32
M
7 8
8
7
6
AREA
INDEX
N-1
D2/2
NX k
5
E2/2
e
FOR EVEN TERMINAL/SIDE
L
C
TERMINAL TIP
CC
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A - 0.85 0.90 -
A1 0.00 0.01 0.05 -
A2 - 0.65 0.70 -
A3 0.20 REF -
b 0.18 0.23 0.30 5, 8
D 4.00 BSC -
D1 3.75 BSC -
D2 2.65 2.80 2.95 7, 8
E 4.00 BSC -
E1 3.75 BSC -
E2 1.43 1.58 1.73 7, 8
e 0.50 BSC -
k 0.635 - - -
L 0.30 0.40 0.50 8
N122
Nd 6 3
P 0.24 0.42 0.60 -
θ--12-
Rev. 0 8/03
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. N is the number of terminals.
3. Nd refer to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for
the L dimension.
10 FN9025.8
HIP2101
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP) L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.28 0.33 0.40 5, 8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.55 2.70 2.85 7, 8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.55 2.70 2.85 7, 8
e 0.80 BSC -
k0.25 - - -
L 0.35 0.60 0.75 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 4 3
P- -0.609
θ--129
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull ba ck (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
11 FN9025.8
HIP2101
Small Outline Plastic Packages (SOIC)
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α0o8o0o8o-
Rev. 0 12/93
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9025.8
HIP2101
Small Outline Exposed Pad Plastic Packages (EPSOIC)
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
P1
123
P
BOTTOM VIEW
N
TOP VIEW
SIDE VIEW
M8.15C
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.056 0.066 1.43 1.68 -
A1 0.001 0.005 0.03 0.13 -
B 0.0138 0.0192 0.35 0.49 9
C 0.0075 0.0098 0.19 0.25 -
D 0.189 0.196 4.80 4.98 3
E 0.150 0.157 3.811 3.99 4
e 0.050 BSC 1.27 BSC -
H 0.230 0.244 5.84 6.20 -
h 0.010 0.016 0.25 0.41 5
L 0.016 0.035 0.41 0.89 6
N8 87
α0o8o0o8o-
P - 0.126 - 3.200 11
P1 - 0.099 - 2.514 11
Rev. 0 11/03
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
