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September 2000

Revised August 2001

74LCXZ16244 Low Voltage 16-Bit Buffer/Line Driver with 5V Tolerant Inputs and Outputs

74LCXZ16244

Low Voltage 16-Bit Buffer/Line Driver

with 5V Tolerant Inputs and Outputs

General Description

The LCXZ16244 contains sixteen non-inverting buffers

with 3-STA TE outputs designed to be employed as a mem-

ory and addre ss driver, clock driver, or bu s o riented trans-

mitter/receiver. The device is nibble controlled. Each nibble

has separate 3-STATE contro l inpu ts whi ch ca n be sh ort ed

together for full 16-bit operation.

When VCC is between 0 and 1.5V, the LCXZ12644 is in the

high impedance state during power up or power down. This

places the outputs in high impedance (Z) state pre venting

intermittent low impedance loading or glitching in bus ori-

ented appl icati o ns.

The LCXZ 16 244 i s de si gn ed for low vo ltage (2.7V o r 3 .3V )

VCC applications with capability of interfacing to a 5V signal

environment.

The LCXZ16244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Features

■5V tolerant inputs and outputs

■Guaranteed power up/down high impedance

■Supports live insertion/withdrawal

■2.7V–3.6V VCC specifications provided

■4.5 ns tPD max (VCC = 3.0V), 20 µA ICC max

■±24 mA output drive (VCC = 3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human body model > 2000V

Machine model > 200V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Ordering Code:

Note 1: BGA package available in Tape and Reel only.

Note 2: Devices also available in Tape and Reel . S pec if y by appending the suffix letter “X” to th e ordering c ode.

Logic Symbol

Order Number Package Number Package Descr iption

74LCXZ16244GX

(Note 1) BGA54A

(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74LCXZ16244MEA

(Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCXZ16244MTD

(Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2

74LCXZ16244

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FB GA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Pin Names Description

OEnOutput Enable Input (Active LOW)

I0–I15 Inputs

O0–O15 Outputs

NC No Connect

123456

AO0NC OE1OE2NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE4OE3NC I15

Inputs Outputs

OE1I0–I3O0–O3

LL L

LH H

HX Z

Inputs Outputs

OE2I4–I7O4–O7

LL L

LH H

HX Z

Inputs Outputs

OE3I8–I11 O8–O11

LL L

LH H

HX Z

Inputs Outputs

OE4I12–I15 O12–O15

LL L

LH H

HX Z

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74LCXZ16244

Functional Description

The LCXZ16244 contains sixteen non-inverting buffers

with 3-STATE standard outputs. The device is nibble

(4 bits) controlled with each nibble functioning identically,

but independent of the other. The control pins can be

shorted together to obtain full 16-bit operation. The

3-STATE outputs are controlled by an Output Enable (OEn)

input for each nibble. When OEn is LOW, the outputs are in

2-state mode. When OEn is HIGH, the outputs are in the

high impedance mode, but this does not interfere with

entering new data into the inputs.

Logic Diagram

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74LCXZ16244

Absolute Maximum Ratings(No te 3)

Recommended Operating Conditions (Note 5)

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rating s. The “Recom-

mend ed Operat ing Conditions” table will define the co nditions fo r ac t ual device operation.

Note 4: IO Absolute Maximum Rating must be observed.

Note 5: Unused inputs must be held HIGH or LO W. They may not float.

DC Electrical Characteristics

Note 6: Outputs dis abled or 3-STATE o nly.

Symbol Parameter Value Conditions Units

VCC Supply Vo lt age −0.5 to +7.0 V

VIDC Input Voltage −0.5 to +7.0 V

VODC Output Voltage −0.5 to +7. 0 Outpu t in 3-STATE or VCC = 0–1.5V V

−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4)

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

+50 VO > VCC

IODC Output Source/Sink Current ±50 mA

ICC DC Supply Current per Supply Pin ±100 mA

IGND DC Ground Current per Ground Pin ±100 mA

TSTG Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.7 3.6 V

VIInput Voltage 05.5V

VOOutput Voltage HIGH or LOW State 0 VCC V

3-STATE or VCC = OFF 0 5.5

IOH/IOL Output Current VCC = 3.0V − 3.6V ±24 mA

VCC = 2.7V − 3.0V ±12

TAFree-Air Operating Temper ature −40 85 °C

∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA = −40°C to +85°CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.7 − 3.6 2.0 V

VIL LOW Level Input Voltage 2.7 − 3.6 0.8 V

VOH HIGH Level Output Voltage IOH = −100 µA2.7 − 3.6 V CC − 0.2

IOH = −12 mA 2.7 2.2

IOH = −18 mA 3.0 2.4

IOH = −24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL = 100 µA2.7 − 3.6 0.2

IOL = 12 mA 2.7 0.4

IOL = 16 mA 3.0 0.4

IOL = 24 mA 3.0 0.55

IIInput Leakage Current 0 ≤ VI ≤ 5.5V 2.7 − 3.6 ±5.0 µA

IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 5.5V 2.7 − 3.6 ±5.0 µA

VI = VIH or VIL

IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µA

IPU/PD Power Up/Down VO = 0.5V to VCC 0 − 1.5 ±5.0 µA

3-STATE Output Current VI = GND or VCC

ICC Quiescent Supply C urrent VI = VCC or GND 2.7 − 3.6 225 µA

3.6V ≤ VI, VO ≤ 5.5V (Note 6) 2.7 − 3.6 ±225

∆ICC Increase in ICC per Input VIH = VCC −0.6V 2.7 − 3.6 500 µA

5 www.fairchildsemi.com

74LCXZ16244

AC Electrical Characteristics

Note 7: Skew is def ined as the absol ut e v alue of the difference between the actu al propaga tio n delay for any two s eparate out puts of the sam e device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Par am eter guaranteed by design.

Dynamic Switching Characteristics

Capacitance

Symbol Parameter

TA = −40°C to +85°C, RL = 500 Ω

Units

VCC = 3.3V ± 0.3V VCC = 2.7V

CL = 50 pF CL = 50 pF

MinMaxMinMax

tPHL Propagation Delay 1.0 4.5 1.0 5.2 ns

tPLH Data to Output 1.0 4.5 1.0 5.2

tPZL Output Enable Time 1.0 5.5 1.0 6.3 ns

tPZH 1.0 5.5 1.0 6.3

tPLZ Output Disable Time 1.0 5.4 1.0 5 .7 ns

tPHZ 1.0 5.4 1.0 5.7

tOSHL Output to Output Skew (Note 7) 1.0 ns

tOSLH 1.0

Symbol Parameter Conditions VCC TA = 25°CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V

VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 V

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF

www.fairchildsemi.com 6

74LCXZ16244

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig cap acitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STA TE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Characteristics; f = 1 MHz, tr = tf = 3 ns)

VICL

6V for VCC = 3.3V, 2.7V 50 pF

Symbol VCC

3.3V ± 0.3V 2.7V

Vmi 1.5V 1.5V

Vmo 1.5V 1.5V

VxVOL + 0.3V VOL + 0.3V

VyVOH − 0.3V VOH − 0.3V

7 www.fairchildsemi.com

74LCXZ16244

Schematic Diagram Generic for LCX Family

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74LCXZ16244

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Packag e Num b er BGA5 4A

Preliminary

9 www.fairchildsemi.com

74LCXZ16244

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

www.fairchildsemi.com 10

74LCXZ16244 Low Voltage 16-Bit Buffe r/Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the failu re of the life support

device or system, or to affect its safety or effectiveness.

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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