TSS901EA/883 - Atmel Corporation - Datasheet.Directory

Features

•3 identical bidirectional link channels allowing full duplex communication under

selectable transmit rate from 1.25 up to 200 Mbit/s in each direction

•A COmmunication Memory Interface (COMI) provides autonomous accesses to a

commu n ication memory whic h are controlled by an arbitration unit, allowin g two

TSS901E to share one Dual Port Ram without external arbitration

•The scalable databus width (8/16/32 bit) allows flexible integration with any CPU type

•Little or big endian mode is configurable

•AHOst Control Interface (HOCI) gives read/write accesses to the TSS901E

configuration registers and to the DS-link channels for the controlling CPU

•Device control via one of the three links allows its use in systems without a local

controller

•Link disconnect detection and parity check at token (data and control) level; possible

checksum generation for packet level check

•Power saving mode relying on automatic transmit rate reduction

•A user’s manual of the TSS901E (also called SMCS332) is available at:

http://www.spacewire.esa.int/tech/spacewire/products/index.htm

•Designed on Atmel MG1140E matrix and packaged into MQFPL196

Description and Appl ications

The TSS901E provides an interface between a Data-Strobe link - according to the

IEEE Std 1355-1995 specification carrying a simple interproces sor communication

protocol - and a data processing node consisting of a CPU and a communication and

data memory.

The TSS901E offers hardware supported execution of the major parts of the interpro-

cessor comm unication protocol: data transfer between two nodes of a multi-processor

system is performed w ith minimal host CPU intervention. The TS S901E can e xecute

simple com m ands to p rovide basic feat ures for system contr ol function s; a provisio n

of fault tolerant features exists as well.

Although the TSS 901E initial exploitation is for use in multi-processor systems wher e

the high speed links standardisation is an important issue and where reliability is a

requirement, it could be used in applications such as heterogeneous systems or mod-

ules witho ut any co mmunication f eature like special image compression chips, some

signal processors, application specific programmable logic or mass memory.

The TSS901E may also be used in single board systems where standardised high

speed inte rface s are n eede d a nd s ystems containing " non -intelligen t" modu les su ch

as A/D-converter or sensor interfaces which can be assembled with the TSS901E

thanks to the "control by link" feature.

Triple Po int to

Poi nt IEEE 1355

High Speed

Controller

TSS901E

4167E–AERO–09/06

TSS901E

Introduction The TSS901E provides an interface betw een a Data-Strobe link according to the IEEE Std

1355-1995 specification carrying the simple interprocessor communication protocol (1 ) an d a

data processing node consisting of a CPU and communication and data memory. The TSS901E

provides HW supported execution of the major par ts of the simpl e interpr ocessor communi cation

protocol, particularly:

• transfer of data between two modes of a multi-processor system with minimal host C PU

intervention,

• execution of simple commands to provide basic features for system control functions,

• provision of fault tolerant features.

How ever, with disabling of features such as the protocol handling or with reduction of the trans-

m it rate ( TSS90 1E autom atically r educes tran smit rate f or se nding null to kens) also low p ow er

usage is supported.

Figure 1. TSS901E Block Diagram

Target applications are heterogeneous multi-processor systems supported by scalable inter-

fac es incl uding the lit tle/ big endia n swa ppin g. T he TSS 901 E conne cts mod ules w ith diff eren t

processors (e.g. TSC21020F, ERC32, TSC695E and others). Any kind of network topology

could be realized through the high speed point-to-point IEEE1355-links (see chapter

Applications).

Interfaces The TSS901E consists of the follow ing blocks (See Figure 1):

1. Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIPSAPII-DAS-

31-01, Issue 3, 08.10.96, also available on the same web site as the users guide.

Receive

Transmit

macro

cell

Cha nne l 2

RX1_DS

TX1_DS

RX2_DS

TX2_DS

Channel 1

JTAG

COMI

HOCI

PRCI

Test

CADR

CCTRL

CDATA

HADR

HCTRL

HDATA

HINT

RCPU

SES

UTIL

Protocol

Cha nne l 3

RX3_DS

TX3_DS

4167E–AERO–09/06

TSS901E

•bidirectional link channels, all comprising the DS-link macro cell (DSM), receive and

transmit sections (each including FIFOs) and a protocol processing unit (PPU). Each

channel allows full duplex communication up to 200 Mbit/s in each direction. With protocol

command execution a higher level of communicati on is supported. Link disconnect detection

and parity chec k at token level are performed. A checksum generation for a check at packet

level can be enabled.

The transmit rate is selectable between 1.25 and 200 Mbit/s; an additional power saving

mod e can be en able d, where th e t ransmit rat e is automat ically reduced to 10 Mbi t/s when

only Null toke ns are being tra nsmit ted over the link. The defa ult transm it rate is 10 Mbit /s.

For special applications the data transmit rate can be programmed to values even below 10

Mbit/s; the lowest possible (to be within the IEEE-1355 specification) transmit rate is 1.25

Mbit/s (the next values are 2.5 and 5 Mbit/s).

•Communication Memory Interf ace (COM I) perform s autonomous accesses to the

communication memory of the module to store data received via the links or to read data to

be transmi tted via the links. The COMI consis ts of indivi dual memory address generator s for

the receive and transmit direction of every DS link channel. The access to the memory is

controlled vi a an arbitration unit providing a fair arbitr ation scheme. T wo TSS901E can share

one DPRAM without external arbitration.

The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type.

Operation in little or big endian mode is configurable through internal registers.

The COMI addr ess bus is 16 bit wide allowing direct access of up to 64K words of the

DPRAM. Two chip select signals are provided to allow splitting of the 64k address space in

two memory banks.

•Host Control Interface (HOCI) gives read and write access to the TSS 901E configuration

registers and to the DS-link channels for the controlling CPU. View ed from the CP U, the

interface behaves like a peripheral that generates acknowledges to synchronize the data

transfers and which is located somewhere in the CPU's address space.

Packets can be transmitted o r received directly via the HOC I. In this case the Comm unica-

tion M emory (D PRAM) is no t strictly ne eded. How ever, in this case the packet size sh ould

be limited to avoid frequent CP U interaction.

The data bu s width is scalable ( 8/16/32 bit) to allow flexible in tegration with any CPU type.

The byte alignment can be configured for little or big endian mode through an external pin.

Additionally the HOCI contains the interrupt signalling capability of the TS S901E by provid-

ing an inte rru pt out put, th e in terrup t st atu s re gister and inte rrupt mask registe r to the local

CPU.

A special pin is provided to select between control of the TSS901E by HOCI or by link. If

control by lin k is enabled, the host data bus functions as a 32-bit gener al purpose interface

(GPIO).

•Protocol Command Interface (PRCI) that collects the decoded commands from all PPUs

and forwards them to external circuitry via 5 special pins.

•JTAG Test Inter face that represents the boundary scan testing provisions specified by

IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The TSS901E' test access

port and on-chip circuitry is fully compliant with the IEEE 1149.1 specification. The test

access port enables boundary scan testing of circuitry connected to the TSS901E I/O pins.

Operation Modes According to the different protocol formats expec ted for the operati on of the TSS901E, two major

operation modes are implemented into the TSS901E. The operation modes are chosen individu-

ally for each link channel by setting the respective configuration registers via the HOCI or vi a the

link.

4167E–AERO–09/06

TSS901E

•Transparent Mod e (default after reset): This mode allows complete transparent data

transfer between two nodes without performing any interpretation of the databytes and

without generating any acknowledges. It is completely up to the host CPU to interpret the

received data and to generate acknowledges if required.

The TSS901E accepts EO P1 and EOP2 control tokens as packet delimiter s and generates

auton omous ly EOP 1/EOP2 (as con figur ed) mar kers af ter e ach end of a transm ission

packet.

This mode also includes as a special submode:

–Wormhole routing: This mode allows hardware routing of packets by the TSS901E.

• Simple Interproces sor Communication (SIC) Protocol Mode: This mode ex ecutes the simpl e

interprocessor communication protocol as described in the protocol specification (1). The

following capabilities of the protocol are implemented into the TSS901E:

– interpretation of the fir st 4 data tokens as the header bytes of the protocol

– autonomous execution of the simple control commands as described in the protocol

specification(1)

– autonomous acknowledgement of received packets if configured

In transmit direction no interpretation of the data is performed. This m eans that for transmit

packets, the four header bytes must be generated by the hos t CPU and must be available as

the first data r ead from the comm unication memory. EOP 1/EOP2 cont rol tokens are auto-

matical ly in ser ted b y t he TS S901 E w he n o ne con fig ured tr ansf er f rom the comm un icati on

memory has finished.

1. Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIPSAPII-DAS-

31-01, Issue 3, 08.10.96, also available on the same web site as the users guide.

4167E–AERO–09/06

TSS901E

TSS901E Control

by Link A feature of the TSS901E is the possibility to control the TSS901E not only via HOCI but via one

of th e three lin ks. Th is allows to use the T SS901E in systems without a local controller (µC on-

troller, FPGA etc.). Since the HOCI is no longer used in this operation mode, it is instead

available as a set of general purpose I/O (GPIO) lines.

Wormhole Routing The TS S90 1E introduces a wormho le routing function similar to the rou ting implemented in the

ST-Microelectronics C104 routing switch. Each of the three links and the TSS901E itself can be

assigned an eight bit address. When routing is enabled in the TS S901E , the first byte of a

packet will be interpreted as the address destination byte, analysed and removed from the

packet (header deletion). If this address matches one of the two other link addresses or the

TSS901E address assigned previously, the packet will be automatically forwarded to this link or

the F IFO o f the TSS90 1E. If t he he ader byte does no t mat ch a lin k addr ess, th e packet w ill be

written to the internal FIFO as well and an error interrupt (maskable) will be raised.

PPU Funct ional

Description Since the Protocol Processing Unit (PPU) determines a major part of the TSS901E functionality,

the prin cipal blocks of the PPU and their func tion are described her e. This fun ctionality is pro-

vided for every DS link channel of the TSS901E.

•Protocol Execution Unit: This unit serves as the main controller of the PPU block. It

receives the tokens from the DS macrocel l and interpret s (in protocol mode) the four header

data characters received after an EOP1/EOP2 control character. If the address field

matches the link channel address and the command field contains a valid command then

forwarding of dat a into the receive FIFO is enabled. If the command field contains a "simple

control command" then the exec ution request is forwarded to the command execution unit.

The p roto col exe cution unit also enab les fo rward ing of head er data char acters to the

ack nowledg e generat or and pro vides an er ror signa l in case of addr ess misma tch, wro ng

commands or disabled safety critical "simple control commands".

The protocol execution unit is disabled in "transparent" or “wormhole routing” operation

mode.

•Receive, Transmit, Acknowledge: The transmit and receive FIFOs decouple the DS link

related operations from the TSS901E related operations in all modes and such allows to

keep the speed of the different units even when the source or sink of data is temporarily

blocked.

In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple sending of

ack no wledge s f rom rece iving ne w d ata whe n the tran smit pat h is curren tly occu pied by a

running packet transmission.

•Command Execution Unit: This unit performs activating resp. deactivating of the CPU

reset and the specific external signals and provides the capability to reset one or all links

inside the TSS901E, all actions requested by the decoded commands from the protocol

execution unit.

The unit contains a register controlling the enable/disable state of safety critical commands

which is set into the 'enable' state upon co mmand request and which is reset after a safety

critical command has been executed.

The CPU reset and the specific external signals are forwarded to the Protocol Command

Interface (PRCI).

4167E–AERO–09/06

TSS901E

Fault Tolerance The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and parity

check at token level. The T SS901E pr ovides, through the Pr otocol Processing Unit, feat ures to

reset a link or all links inside the TS S901E, to reset the local CPU or to send special signals to

the CPU comm anded via the links.

Additio nally it is possible to enable a checksum coder/decode r to have f ault de tection capabili-

ties at packet level.

Applications The TSS901E is a very high speed, scalable link-interface chip with fault tolerance features. The

initi al exploitation is for use in multi-p ro cessor systems w here the standar disation or the high

speed of the links is an important issue and where reliabi lity is a requirement. Further application

examples are heterogeneous systems or modules without any communication featur es as spe-

cial im age co mpre ssion ch ips, ce rtain sign al processo rs ( TSC21020 F, ERC 32, ... ), application

specific programmable logic or mass memory.

The TSS901E could also be used for single board systems where standardised high speed

interfaces are needed. Even "non-intelligent" modules such as A/D-converter or sensor inter-

faces can be assembled with the TSS901E because of the "control by link" feature. The

complete control of the TSS901E can be done via link from a central controller-node.

4167E–AERO–09/06

TSS901E

This chapter d escribes the TSS90 1E registers which can be read or w ritten by the H OCI or via

the link ( in ca se the " contr ol b y link" is enabl ed) to control T S S901E operat ions. All T SS901 E

control operations are performed by writes or reads of the respective registers. Most of the con-

trol operations are obvious from the content of the registers.

General Conventions:

• bit 0 (D0) = least significant bit,

• bit 7 (D7) = most significant bit (or bit 15 resp. bit 31)

• D x:0 means data bit x until bit 0.

Access by HOCI: HOCI Data Transfer

Big/Little endian selecti on of the HOCI is done using a speci al pin (HOSTBIGE) of the TSS901E.

By co nnectin g this pin t o either Vcc or GN D t he HO CI is configu red to b e in little or big en dian

mode as follows:

When Signal HOSTBIGE = '0' (GND), the HOCI data port is in little endian mode.

When Signal HOSTBIGE = '1' (Vcc), the HOCI data port is in big endian mode.

Little endian mode selected:

• 8 bit data port (default after reset)

– register byte 0 is connected with pin HDATA0 - HD ATA7

• 16 bit data port

– register byte 0 is connected with pin HDATA0 - HD ATA7

– register byte 1 is connected with pin HDATA8 - HD ATA15

• 32 bit data port

– register byte 0 is connected with pin HDATA0 - HD ATA7

– register byte 1 is connected with pin HDATA8 - HD ATA15

– register byte 2 is connected with pin HDATA16 - HD ATA23

– register byte 3 is connected with pin HDATA24 - HD ATA31

Big endian mode selected:

• 8 bit data port (default after reset)

– register byte 0 is connected with pin HDATA24 - HD ATA31

• 16 bit data port

– register byte 0 is connected with pin HDATA24 - HD ATA31

– register byte 1 is connected with pin HDATA16 - HD ATA23

• 32 bit data port

– register byte 0 is connected with pin HDATA24 - HD ATA31

– register byte 1 is connected with pin HDATA16 - HD ATA23

– register byte 2 is connected with pin HDATA8 - HD ATA15

– register byte 3 is connected with pin HDATA0 - HD ATA7

The registers of the TSS901E are 1, 2 or 4 Bytes wide. That means, if the HOCI data port is in 8

bit mode, 4 read or write accesses are necessary to access a 4 Byte register (e. g. the interrupt

mask register). In 16/32 bit mode the data bits 31 - 8 are '0' if an 8 bit r egister is read.

4167E–AERO–09/06

TSS901E

The add resses of the TSS9 01E registers are directly mapped with pins H ADR7 - 0. The tables

below shows the addresses of all the TSS901E registers depending on the HOCI port width.

TSS901E status and control registers

TSS901E channel 1 status and control registers

Port Width / Address

(hex)

(hex) Access32 16 8

00 00 00 SICR TSS901E Interface Control Register 00 r / w

01 01 01 TRS_CTRL Transmit-Speed-Base Register 0A r / w

02 02 02 ROUTE_CTRL Routing Enable / Status Register 00 r

03 03 03 reserved 00

04 04

ISR In t er rupt St at u s Regi ster 0 4010040 ro

08 08

IMR Interrupt Mask Register 00000000 r / w

0C 0C 0C COMI_CS0R COMI Chip Select 0 upper address boundary

0D 0D 0D reserved 00

0E 0E 0E COMI_ACR COMI Arbi t rat i on Co nt rol Reg i ster 08 r / w

0F 0F 0F PRCIR PRCI Register 00 r / w

Port Width / Address

(hex)

(hex) Access32 16 8

10 10 10 CH1_DSM_MODR channel 1 DSM mode Register 03 r / w

11 11 11 CH1_DSM_CMDR channel 1 DSM command Register 00 r / w

12 12 12 CH1_DSM_STAR channel 1 DSM status Register 00 r / w

13 13 13 CH1_DSM_TSTR channel 1 DSM test Register 00 r / w

14 14 14 CH1_ADDR channel 1 address Register 00 r / w

15 15 15 CH1_RT_ADDR channel 1 Route Address Register 00 r / w

16 16 16 CH1_PR_STAR channel 1 Protocol Status Register 04 r / w

17 17 17 reserved 00 ---

18 18 18 CH1_CNTRL1 channel 1 control Register 1 00 r / w

4167E–AERO–09/06

TSS901E

TSS901E channel 2 status and control registers

19 19 19 CH1_CNTRL2 channel 1 control Register 2 00 r / w

1A 1A 1A CH1_HTID channel 1 Header Transaction ID byte 00 ro

1B 1B 1B CH1_HCNTRL channel 1 Header cont ro l byt e 00 ro

1C 1C 1C CH1_ESR1 channel 1 detailed error source register 1 00 r / w

1D 1D 1D CH1_ESR2 channel 1 detailed error source register 2 00 r / w

1E 1E 1E reserved 00 ---

1F 1F 1F CH1_COMICFG channel 1 COMI configuration register 00 r / w

20 20 20

21 CH1_TX_SAR channel 1 transmit Start Address Register 0000 r / w

22 22 22

23 CH1_TX_EAR channel 1 transmit End Address Register 0000 r / w

24 24 24

25 CH1_T X _CA R channel 1 tr an s m it Current Address Reg i st er 000 0 ro

26 26 26 CH1_TX_FIFO chan nel 1 tr ans m i t FI F O -- wo

27 27 27 CH1_TX_EOPB channel 1 transmit EOP Bit Register -- wo

28 28 28

29 CH1_RX_SAR channel 1 receive Start Address Register 0000 r / w

2A 2A 2A

2B CH1_RX_EAR channel 1 receive End Address Register 0000 r / w

2C 2C 2C

2D CH1_RX_CAR channel 1 receive Current Address Register 0000 ro

2E 2E 2 E CH1_RX_FIFO channel 1 receive FIFO xxxxxxxx ro

2F 2F 2F CH1_S TAR ch an nel 1 Status Reg i s ter 01 ro

Port Width / Address

(hex)

(hex) Access32 16 8

Port Width / Address

(hex)

(hex) Access32 16 8

30 30 30 CH2_DSM_MODR channel 2 DSM mode Register 03 r / w

31 31 31 CH2_DSM_CMDR channel 2 DSM command Register 00 r / w

32 32 32 CH2_DSM_STAR channel 2 DSM status Register 00 r / w

33 33 33 CH2_DSM_TSTR channel 2 DSM test Register 00 r / w

34 34 34 CH2_ADDR channel 2 address Register 00 r / w

35 35 35 CH2_RT_ADDR channel 2 Route Address Register 00 r / w

36 36 36 CH2_PR_STAR channel 2 Protocol Status Register 04 r / w

4167E–AERO–09/06

TSS901E

TSS901E channel 3 status and control registers

37 37 37 reserved 00

38 38 38 CH2_CNTRL1 channel 2 control Register 1 00 r / w

39 39 39 CH2_CNTRL2 channel 2 control Register 2 00 r / w

3A 3A 3A CH2_HTID channel 2 Header Transaction ID byte 00 ro

3B 3B 3B CH2_HCNTRL channel 2 Header cont ro l byt e 00 ro

3C 3C 3C CH2_ESR1 channel 2 detailed error source register 1 00 r / w

3D 3D 3D CH2_ESR2 channel 2 detailed error source register 2 00 r / w

3E 3E 3E reserved 00

3F 3F 3F CH2_COMICFG channel 2 COMI configuration register 00 r / w

40 40 40

41 CH2_TX_SAR channel 2 transmit Start Address Register 00 r / w

42 42 42

43 CH2_TX_EAR channel 2 transmit End Address Register 00 r / w

44 44 44

45 CH2_T X _CA R channel 2 tr ansmit Cur re nt Address Reg i s ter 00 ro

46 46 46 CH2_TX_FIFO chan nel 2 tr ans m i t FI F O 00 w o

47 47 47 CH2_TX_EOPB channel 2 transmit EOP Bit Register 00 wo

48 48 48

49 CH2_RX_SAR channel 2 receive Start Address Register 00 r / w

4A 4A 4A

4B CH2_RX_EAR channel 2 receive End Address Register 00 r / w

4C 4C 4C

4D CH2_RX_CAR channel 2 receive Current Address Register 00 ro

4E 4E 4 E CH2_RX_FIFO channel 2 receive FIFO xxxxxxxx ro

4F 4F 4F CH2_S TAR ch an nel 2 Status Reg i s ter 01 ro

Port Width / Address

(hex)

(hex) Access32 16 8

Port Width / Address

(hex)

(hex) Access32 16 8

50 50 50 CH3_DSM_MODR channel 3 DSM mode Register 03 r / w

51 51 51 CH3_DSM_CMDR channel 3 DSM command Register 00 r / w

52 52 52 CH3_DSM_STAR channel 3 DSM status Register 00 r / w

53 53 53 CH3_DSM_TSTR channel 3 DSM test Register 00 r / w

4167E–AERO–09/06

TSS901E

54 54 54 CH3_ADDR channel 3 address Register 00 r / w

55 55 55 CH3_RT_ADDR channel 3 Route address Register 00 r / w

56 56 56 CH3__PR_STAR channel 3 Protocol Status Register 04 r / w

57 57 57 reserved 00

58 58 58 CH3_CNTRL1 channel 3 control Register 1 00 r / w

59 59 59 CH3_CNTRL2 channel 3 control Register 2 00 r / w

5A 5A 5A CH3_HTID channel 3 Header Transaction ID byte 00 ro

5B 5B 5B CH3_HCNTRL channel 3 Header cont ro l byt e 00 ro

5C 5C 5C CH3_ESR1 channel 3 detailed error source register 1 00 r / w

5D 5D 5D CH3_ESR2 channel 3 detailed error source register 2 00 r / w

5E 5E 5E reserved 00

5F 5F 5F CH3_COMICFG channel 3 COMI configuration register 00 r / w

60 60 60

61 CH3_TX_SAR channel 3 transmit Start Address Register 00 r / w

62 62 62

63 CH3_TX_EAR channel 3 transmit End Address Register 00 r / w

64 64 64

65 CH3_T X _CA R channel 3 tr ansmit Cur re nt Address Reg i s ter 00 ro

66 66 66 CH3_TX_FIFO chan nel 3 tr ans m i t FI F O 00 w o

67 67 67 CH3_TX_EOPB channel 3 transmit EOP Bit Register 00 wo

68 68 68

69 CH3_RX_SAR channel 3 receive Start Address Register 00 r / w

6A 6A 6A

6B CH3_RX_EAR channel 3 receive End Address Register 00 r / w

6C 6C 6C

6D CH3_RX_CAR channel 3 receive Current Address Register 00 ro

6E 6E 6 E CH3_RX_FIFO channel 3 receive FIFO xxxxxxxx ro

6F 6F 6F CH3_S TAR ch an nel 3 Status Reg i s ter 01 ro

Port Width / Address

(hex)

(hex) Access32 16 8

4167E–AERO–09/06

TSS901E

TSS901E GPIO

Control Registers These registers are only enabled when the TSS901E is configured for "control by link" using the

'BOOTLIN K' pin.

Port Width / Address

(hex)

(hex) Access32 16 8

GPIO_DIR0

GPIO_DIR1

GPIO_DIR2

GPIO_DIR3

GPIO direction register 0

GPIO direction register 1

GPIO direction register 2

GPIO direction register 3

r / w

GPIO_DATA0

GPIO_DATA1

GPIO_DATA2

GPIO_DATA3

GPIO data register 0

GPIO data register 1

GPIO data register 2

GPIO data register 3

r / w

4167E–AERO–09/06

TSS901E

Signal

Description The Figu re belo w show s the TS S901 E (also ca lled SMC S3 32) e mb edded in a typ ica l m odule

environment:

This section describes the pins of the TSS901E. Groups of pins represent busses where the

highest number is the MSB.

O = Output; I = Input; Z = High Impedance; (*) = active low signalO/Z = if using a configuration

with two TSS901Es these signals can directly be connected together (WIROR)

Signal Name Type Function max. outpu t

current [mA] load [pF]

HSEL* I Select host interface

HRD* I host interface read strobe

HWR* I host interface write strobe

HADR(7:0) I TSS90 1E r eg is ter ad dress line s . This addres s lines will be

used to access (address) the TSS 901E registers.

HDATA(31:0) IO/Z TSS901E data 3 50

HACK O/Z host acknowledge. TSS901E deasserts this output to add wait

states to a TS S901E access. After TSS901E is ready this

output will be a s s erted. 350

HINTR* O/Z host interrupt request line 3 50

TSS901EADR(3:0

)ITSS901E Address. The binary value of this lines will be

compared with the value of the TSS901E ID lines.

TSS901EID(3:0) I TSS 9 01E ID line s : offers po s sibilit y to use sixt e en TS S901E

within one HSEL*

4167E–AERO–09/06

TSS901E

HOSTBIGE I 1: host I/F Big Endian

0: hos t I/ F Li ttl e E ndi an

BOOTLINK I 1: control by link

0: c o nt rol by h o st

CMCS(1:0)* O/Z Communication memory select lines. These pins are asserted

as chip selects for the correspond ing banks of the

co mmunication memory. 825

CMRD* O/Z Communication memory read strobe. This pin is asserted when

the TSS901E reads data from memory. 825

CMWR* O/Z Communication memory write strobe. This pin is asserted

when the TSS901E writes to data memory. 825

CMADR(15:0) O/Z Communication memory address. The TSS901E outputs an

address on these pins. 825

CMDATA(31:0) IOZ Com munication m emory data. The TSS901E inputs and

outputs data from and to com. mem ory on these pins. 350

COCI I Com munication interface 'occupied' input signal 3 50

COCO O/Z Communication interface 'occupied' output signal

CAM I Communication interface arbitration master input signal

1: master

0: s l ave

CPU R* O/Z CP U Rese t Signal 3 50

SES(3:0)* O/Z Specific External Signals 3 50

LDI1 I Link Data Input channel 1

LSI1 I Link Strobe Input channel 1

LDO1 O/Z Link Data Output channel 1 12 25

LSO1 O/Z Link Strobe Output channel 1 12 25

LEN1 O/Z Link Enable Out (for external drivers) 3 50

LDI2 I Link Data Input channel 2

LSI2 I Link Strobe Input channel 2

LDO2 O/Z Link Data Output channel 2 12 25

LSO2 O/Z Link Strobe Output channel 2 12 25

LEN2 O/Z Link Enable Out (for external drivers) 3 50

LDI3 I Link Data Input channel 3

LSI3 I Link Strobe Input channel 3

LDO3 O/Z Link Data Output channel 3 12 25

LSO3 O/Z Link Strobe Output channel 3 12 25

LEN3 O/Z Link Enable Out (for external drivers) 3 50

TRST* I Test Reset. Resets the test state m achine.

Signal Name Type Function max. outpu t

current [mA] load [pF]

4167E–AERO–09/06

TSS901E

TCK I Test Clock. Provides an asynchronous clock for JTAG

boundary scan.

TMS I Test Mode Select. Used to control the test state m achine.

TDI I Test Data Input. Provides serial data for the boundary scan

logic.

TDO O/Z Test Data Output. S erial scan output of the boundary scan

path. 350

RESET* I

TSS901E Reset. Sets the TSS901E to a known state. This

input m ust be asserted (low) at power-up. The minimum width

of RESET low is 5 cycles of CLK10 in parallel with CLK

running.

CLK I External clock input to TSS901E (max. 25 Mhz).

Must be derived from RAM access time.

CLK10 I External clock input to TSS901E DS-links (application specific,

nominal 10 Mhz). Used to generate to transmission speed and

link disconnect timeout.

PLLOUT O Output of internal PLL. Used to connect a network of external

RC devices.

VCC Power Supply

GND Ground

Signal Name Type Function max. outpu t

current [mA] load [pF]

4167E–AERO–09/06

TSS901E

Electrical Char acteristics

The following data is provided for information only; for the guaranteed values, refer to Atmel pro-

curement specification.

A bsolu te Ma xim um Rating s

Stresses above those listed may cause permanent damage to the device.

DC Electrical Characteristics

Specified at VCC = + 5 V ± 10% (TSS901E will only work with 5V)

Although specified for TTL outputs, all TSS901E outputs are CMO S compatible and will drive to

VCC and GND assuming no dc loads.

Max. power consumption figures (at 5.5V, 125°C) are:

Parameter Symbol Value Unit

Supp ly Volta ge VCC -0.5 to +7 V

I/O Voltage -0.5 to VCC + 0.5 V

Operating Temper at ure Ran ge (Am bi ent) TA-55 to +125 °

Junc tion Temperature T JTJ < TA +20 °

Stor age Temperature R ange Tstg -65 to +150 °

Parameter Symbol Min. Max. Unit Conditions

Operating Voltage VCC 4.5 5.5 V

Input HIGH Voltage VIH 2.0 V

Input LOW Voltage VIL 0.8 V

Output HIGH Voltage VOH 2.4 V max. output current

Output LOW Voltage VOL 0.4 V max. output current

Output Short circuit current IOS 160

130 mA

mA VOUT = VC C

VOUT = GND

Operation Mode Pow er consumption [mA]

not clocked 5

TSS901E in RESET 45

TSS9 01E i n ID LE 70

Maximum 190

4167E–AERO–09/06

TSS901E

PLL Filter The pin PLLOUT should be connected as shown below:

R1 = 249Ω ± 5%, ¼1/4W

C1 = 1nF, ± 5%, 20V

C2 = 15nF, ± 5%, 20V

TSS90E

PLLOUT

C1 R1

4167E–AERO–09/06

TSS901E

Timing

Parameters

Clock Signals

Note: 1) Max. 25 MHz

Note: 1) Typically 10 MHz

Description Symbol Min. Max. Unit

CLK per i od 1) tCLK 40 ns

CLK width high t CLKH 17 ns

CLK width low tCLKL 17 ns

Description Symbol Min. Max. Unit

CLK10 period 1) tCLK10 100 100 ns

CLK 10 w i dth high tCLK10H 40 ns

CLK10 width low tCLK10L 40 ns

4167E–AERO–09/06

TSS901E

Reset

Description Symbol Min. Max. Unit

RESET setup before CLK high tRSTS 5ns

RESET low pulse width tRSTW 2 * tCLK ns

Output disable after CLK high tOUTD 42 ns

O ut put enable af te r CLK hi gh tOUTE 2 * t CLK + 26 ns

CAM, HO STBIGE, BOOTL INK setup before RESET high tCAMS 1

4167E–AERO–09/06

TSS901E

Host Read

Note: 1) Signal HACK active when HRD* low and HSEL* low and TSS901EADR = TSS901EID

2) Signal HACK disable when HRD* high or HSEL* high or TSS901EADR ¼ TSS901EID

Description Symbol Min. Max. Unit

HSEL*, HRD* and TSS901EADR and HADR setup before CLK high tHRSU 5ns

HADR, TSS901EADR hol d af ter HSEL*, HRD* hig h tHRAH 0ns

HRD* pulse width high tHRDH 5ns

HACK low after HRD* , HSEL* active and TSS901EADR valid 1) tHRACKL 16 ns

HACK high after CLK high tHRACKH 1 * tCLK + 5 3 * tCLK + 23 ns

HACK disabl e after HRD*, HSEL* inactive or TSS901EADR invalid 2) tHRACKA 12 ns

HDATA val i d befor e HACK high t HRDV 0ns

HDATA hold after HRD*, HSEL* inactive or TSS901EADR invalid 2) tHRDH 519ns

4167E–AERO–09/06

TSS901E

Host Write

Description Symb. Min. Max. Unit

HSEL*, HWR* and TSS901EADR and HADR setup before CLK high tHWSU 5ns

HADR, TSS901EADR hol d af ter HSEL*, HWR* hig h t HWAH 0ns

HWR* pulse width high tHWWH 1 * tCLK + 5 ns

HACK low after HWR* , HSEL* active and TSS901EADR valid 1) tHWACKL 16 ns

HACK high after HSEL* and HWR* and TSS901EADR = TSS901EID tHWACKH 1 * tCLK + 5 2.5 * tCLK + 24 ns

HACK disable after HWR* or HSEL * inactive or TSS901E ADR invalid 2) tHWACKA 12 ns

HDATA setup before HSEL* or HWR* high or TSS901EADR

≠

TSS901EID

tHWDSU 5ns

HDATA hol d af ter HWR * or HSEL * ina cti v e or TSS9 01EA DR i nva l i d 2) tHWDH 0ns

4167E–AERO–09/06

TSS901E

COMI Read

Addr. Valid

CLK

CMCS0

CMCS1

CMRD

CMWR

CMADR

CMDATA

Addr. Valid Addr. Valid

CRCA

CRPW

CRCH

CRCA

CRPW

CRCH

CRCA

CRPW

CRDS

CRDH

CRDS

CRDH

Description Symbol Min. Max. Unit

CMCS0*, CMCS1* and CMRD* low and CMADR valid after CLK high tCRCA 18 ns

CMCS0*, CMCS1* or CMRD* high after CLK high tCRCH 18 ns

CMCS0*, CMCS1*, CMRD*, CM ADR pulse width tCRPW tCLK - 1 n s

CMDATA setup before CM CS0* or CMCS1* or CMRD* high or new address

on CMADR tCRDS 4ns

CMDATA hold after CMCS0* or CMCS1* or CMRD* high or new address on

CMADR tCRDH 0ns

4167E–AERO–09/06

TSS901E

COMI Write

Addr. Valid

CLK

CMCS0

CMCS1

CMRD

CMWR

CMADR

CMDATA

CWCA

CWPW

CWCH

CWCA

CWPW

CWCH

CWCA

CWDS

CWDH

Addr. Valid

CWDE

Data Valid Data Vali d

Description Symbol Min. Max. Unit

CMCS0*, CMCS1* and CMWR* low and CMADR valid after CLK high tCWCA 18 ns

CMCS0*, CMCS1* or CMWR* high after CLK high tCWCH 18 ns

CMCS0*, CMCS1*, CM WR* pulse width tCWPW tCLK - 1 ns

CMDATA valid after CLK high tCWDE 15

CMDATA valid before CMCS0* or CMCS1* or CMWR* high tCWDS 25 ns

CMDATA hold after CMCS0* or CMCS1* or CMWR* high tCWDH tCLK/2 + 18 ns

4167E–AERO–09/06

TSS901E

COMI Arbitration

Note: 3) N = content of COMI_ACR

Description Symbol Min. Max. Unit

COM Interf ace di sable af t er CLK l ow tCAID 23 ns

COM Interf ace en able aft er C LK hi gh tCAIE 22 ns

COCI setup before CLK low tCOCIS 2ns

COCO low after CLK low tCOCOL 11 ns

COCO high after CLK high tCOCOH 11 ns

COCO pulse width 3) tCOCOW N - 1 tCLK ns

4167E–AERO–09/06

TSS901E

CPUR, SES,

Interrupt

Links

CLK

OUTC

CPUR

SESx

HINTR

Description Symbol Min. Max. Unit

CPUR*, SESx*, HINTR* delay after CLK high tOUTC 22 ns

LDIx

LSIx

LOUT

LBITP

LDSI

LSOx

LDOx

LOUT

LDSI

Description Symbol Min. Max. Unit

Bit Period tLBITP 4ns

LDOx, LSOx output skew tLOUTS 0.5 ns

Data/Strobe edge separation tLDSI 1ns

4167E–AERO–09/06

TSS901E

Test Port (JTAG)

Note: The BSDL file is printed in the Annex of this document.

TCK

TMS

TIH

TIS

TCKL

TCKH

TCK

TDO

TRST

INPUTS

SYSH

SYSS

SYSO

TDI

TDO

TRST

OUTPUTS

Description Symbol Min. Max. Unit

TCK period tTCK 100 ns

TCK width high tTCKH 40 ns

TCK w idth low tTCKL 40 ns

TMS, TDI setup be fore TCK high tTIS 8ns

TMS, TDI hold after TCK high tTIH 8ns

TDO de lay after TCK low tTDO 17 ns

TR S T* pulse wi dth tTRST 2 * tTCK ns

TSS901E Inputs setup before TCK high tSYSS 8ns

TSS901E Inputs hold after TCK high tSYSM 8ns

TSS901E Outputs delay after TCK low tSYSO 27 ns

4167E–AERO–09/06

TSS901E

Package

Drawings

MQFPL 196 Code: FX Date:13/10/00

4167E–AERO–09/06

TSS901E

Pin Assignment

Pin Number Name Pin Number Name Pin Num ber Name

1 VCC 67 HDATA18 133 CMDATA8

2 GND 68 HDATA19 134 VCC

3 GND 69 HDATA20 135 GND

4 CLK 70 HDATA21 136 CMDATA9

5 RESET* 71 HDATA22 137 CMDATA10

6 CLK10 72 HDATA23 138 CMDATA11

7 HOSTBIGE 73 VCC 139 CMDATA12

8 TCK 74 GND 140 CMDATA13

9 TMS 75 HDATA24 141 CMDATA14

10 TDI 76 HDATA25 142 VCC

11 TRST* 77 HDATA26 143 GND

12 TDO 78 VCC 144 CMDATA15

13 VCC 79 GND 145 CMDATA16

14 GND 80 HDATA27 146 CMDATA17

15 HSEL* 81 HDATA28 147 CMDATA18

16 HRD* 82 HDATA29 148 CMDATA19

17 HWR* 83 VCC 149 CMDATA20

18 HACK 84 GND 150 VCC

19 HINTR* 85 HDATA30 151 GND

20 VCC 86 HDATA31 152 CMDATA21

21 GND 87 CPUR* 153 CMDATA22

22 HADR0 88 SES0* 154 CMDATA23

23 HADR1 89 SES1* 155 VCC

24 HADR2 90 SES2* 156 GND

25 HADR3 91 SES3* 157 CMDATA24

26 HADR4 92 CAM 158 CMDATA25

27 HADR5 93 COCI 159 CMDATA26

28 HADR6 94 COCO 160 VCC

29 HADR7 95 CMCS0* 161 GND

30 VCC 96 CMCS1* 162 CMDATA27

31 GND 97 VCC 163 CMDATA28

32 BOOTLINK 98 GND 164 CMDATA29

33 TSS901EADR0 99 CMRD* 165 CMDATA30

34 TSS901EADR1 100 CMWR* 166 CMDATA31

35 TSS901EADR2 101 CMADR0 167 NC

36 TSS901EADR3 102 CMADR1 168 NC

37 TSS901EID0 103 CMADR2 169 NC

38 TSS901EID1 104 CMADR3 170 NC

39 TSS901EID2 105 CMADR4 171 NC

40 TSS901EID3 106 VCC 172 VCC

41 VCC 107 GND 173 GND

42 GND 108 CMADR5 174 GND

43 HDATA0 109 CMADR6 175 LEN1

44 HDATA1 110 CMADR7 176 LDI1

4167E–AERO–09/06

TSS901E

45 HDATA2 111 CMADR8 177 LSI1

46 HDATA3 112 CMADR9 178 LDO1

47 HDATA4 113 CMADR10 179 LSO1

48 HDATA5 114 CMADR11 180 LDI2

49 HDATA6 115 VCC 181 LSI2

50 VCC 116 GND 182 LEN2

51 GND 117 CMADR12 183 VCC

52 HDATA7 118 CMADR13 184 VCC

53 HDATA8 119 CMADR14 185 VCC

54 HDATA9 120 CMADR15 186 LDO2

55 HDATA10 121 CMDATA0 187 LSO2

56 HDATA11 122 CMDATA1 188 LDI3

57 VCC 123 CMDATA2 189 LSI3

58 GND 124 VCC 190 LDO3

59 HDATA12 125 GND 191 LSO3

60 HDATA13 126 CMDATA3 192 LEN3

61 HDATA14 127 CMDATA4 193 GND

62 HDATA15 128 CMDATA5 194 GND

63 HDATA16 129 VCC 195 VCC

64 HDATA17 130 GND 196 PLLOUT

65 VCC 131 CMDATA6

66 GND 132 CMDATA7

Pin Number Name Pin Number Name Pin Num ber Name

4167E–AERO–09/06

TSS901E

Ordering

Information

(*) Contact factory

Document Revision History

Changes from

4167D to 4167E 1. Changed web address of location of TS S901E User’s Manual. Page 1.

Part-number Temp. Range Package Quality Flow

TSS901EMA-E 25°C MQFPL 196-pin Engineering sample

TSS901EAM -55°C +125°C MQF PL 196-pi n MIL

5962- 01 A1701QXC -55°C +125° C MQFPL 196-pin QML-Q

TSS901EA/883(*) -55°C +125°C MQFPL 196-pin /883S Class B

TSS901EASC -55°C +125°C MQFPL 196-pin SCC 9000 level C

5962- 01 A1701VXC -55°C +125° C MQFPL 196-pin QML-V

TSS901EASB -55°C +125°C M Q FPL 196-pin SCC 9000 level B

TSS901EAS/883(*) -55°C +125°C MQFPL 196-pin /883S Class S

TSS901EMC-E 25°C D ie Engineering sample

5962- 01 A170 1Q9A -55°C +125°C Die QML-Q

5962- 01 A170 1V9A -55°C +125° C Die QML-V

Pri nted on r ecy cled paper .

4167E–AERO–09/06

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