2013- 2018 Microchip Technology Inc. DS00001922B-page 1
General Description
The Microchip USB4640/USB4640i is a Hi-Speed
HSIC USB hub and card reader combo solution with an
upstream port that is compliant to HSIC 1.0 (supple-
ment to the USB 2.0 Specification). The two down-
stream ports are compliant with the USB 2.0
Specification.
High-Speed Inter-Chip (HSIC) is a digital interconnect
bus that enables the use of USB technology as a low -
power chip-to-chip interconnect at speeds up to
480 Mb/s. The HSIC interface is an industry standard
2-pin digital interface which uses standard USB soft-
ware. The USB4640/USB4640i provides an ultra fast
interface between an HSIC enabled host and several
popular flash media formats. The controller allows
read/write capability to flash media from the following
families:
- Secure DigitalTM (SD)
- MultiMediaCardTM (MMC)
- Memory Stick® (MS)
- xD-Picture CardTM (xD)1
The USB4640/USB4640i combo solution leverages
Microchip’s innovative technology that delivers indus-
try-leading data throughput in mixed-speed USB envi -
ronments. Average sustained transfer rates exceeding
35 MB/s are possible.2
Highlights
• Upstream HSIC port and 2 exposed Hi-Speed
USB 2.0 downstream ports for external peripheral
expansion
• Dedicated flash media reader internally attached
to a 3rd downstream port of the hub as a USB
compound device
- single or multiplexed flash media reader
interface
•PortMap - Flexible port mapping and disable
sequencing
•PortSwap - Programmable USB differential-pair
pin locations ease PCB design by aligning USB
signal lines directly to conne ctors
•PHYBoost - Programmable USB signal drive
strength for recovering signal integrity using 4-
level driving strength resolutio n
Features
• Compliance with the following flash media card
specifications SD 2.0; MMC 4.2; MS 1.43; MS-
Pro 1.02; MS-Pro-HG 1.01; MS-Duo 1.10; and
xD 1.2
• Low-power digital HSIC interface offers a replace-
ment for onboard host and device connection fo r
analog USB bus cable
• HSIC interface enables printers, mobile PCs,
ultra-mobile PCs, and cell phone products to
reduce the total power budget
• HSIC interface provides use of USB connectivity
and compatibility with existing USB drivers and
software
• External 1.2 V reference allows upstream/down-
stream HSIC li n ks to use the same voltag e refe r-
ence
• Supports a single external 3.3 V supply source;
internal regulators provide 1.8 V internal core volt-
age for additional bill of materials and power sav-
ings
• The hub transaction translator (TT) supports Full-
Speed and Low-Sp eed peripheral operati on
•9 KB RAM | 64 KB on-chip ROM
• Enhanced EMI rejection and ESD protection per-
formance
• Hub and flash media reader/writer configuration
from a single source:
- Configures internal code using an external
I2C EEPROM
- Supports external code using an SPI Flash
EEPROM
- Customizable vendor ID, product ID, and lan-
guage ID if using an external EEPROM
• The USB4640 supports the commercial tempera-
ture range of 0°C to +70°C
• The USB4640i supports the industrial tempera-
ture range of -40°C to +85°C
• 48-pin QFN (7 x 7 mm) RoHS compliant package
Applications
• 3G/4G handsets, smartphones, cell phones, and
other mobile devices
• Desktop and mobile PCs
• Printers
• GPS navigation systems
• Media players/viewers
• Consumer A/V
• Set-top boxes
• Industrial products
1. Obtain user license from the x-D-Picture Card License
Office.
2. Host and Media dependent.
USB4640/USB4640i
High-Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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USB4640/USB4640i
DS00001922B-page 2 2013- 2018 Microchip Technology Inc.
2013-2018 Microchip Technology Inc. DS00001922B-page 3
USB4640/USB4640i
Table of Contents
1.0 Overview ......................................................................................................................................................................................... 4
2.0 Block Diagram ................................................................................................................................................................................. 7
3.0 Pinning Information ......................................................................................................................................................................... 8
4.0 Configuration Options ................................................................................................................................................................... 21
5.0 AC Specifications .......................................................................................................................................................................... 41
6.0 DC Parameters ............................................................................................................................................................................. 43
7.0 Temperature Specifications .......................................................................................................................................................... 48
8.0 Package Specifications ................................................................................................................................................................. 49
Appendix A: Acronyms .................................................................... .................................................................................................... 53
Appendix B: References ..................................................................................................................................................................... 54
Appendix C: Data Sheet Revision History ................................................................................ .......................................................... 55
The Microchip Website ....................................................................................................................................................................... 57
Customer Change Notification Service ............................................................................................................................................... 57
Customer Support ............................................................................................................................................................................... 57
Product Identification System ............................................................................................................................................................. 58
USB4640/USB4640i
DS00001922B-page 4 2013-2018 Microchip Technology Inc.
1.0 OVERVIEW
The USB4640/USB4640i is a Hi-Speed HSIC USB hub and card reader combo solution with an upstream port compliant
to the High-Speed Inter-Chip USB Electrical Specification Revision 1.0 [2]. The two downstream ports are USB 2.0 com-
pliant, and the dedicated flash media reader/writer is internally attached to a 3rd downstream port as a USB compound
device.
High-Speed Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology as a low-power chip-
to-chip interconnect at speeds up to 480 Mb/s (see the High-Speed Inter-Chip USB Electrical Specification Revision
1.0). This combo solution supports several multi-format flash media cards. This multi-format flash media controller and
USB hub combo features two exposed downstream USB ports available for external peripheral expan sion.
The USB4640/USB4640i can attach to an upstream port as a Full- or Full/Hi-Speed hub. The hub supports Low-Speed,
Full-Speed, and Hi-Speed downstream devices (if operating as a Hi-Speed hub) on all of the enabled downstream ports.
All required resistors on the USB po rts are integ rated in to th e hu b, incl uding al l serie s termi nation resistors on D+ a nd
D– pins and all required pull-down and pull-up resistors. The over-current sense inputs for the downstream facing ports
have internal pull-up resistors.
The USB4640/USB4640i includes programmable features, such as:
•PortMap: provides flexible port mapping and disable sequences. The down-
stream ports of a USB4640/USB4640i hub can be reordered or disabled in any
sequence to support multiple platform designs with minimum effort. For any port
that is disabled, the USB4640/USB4640i hub controllers automatically reorder
the remaining ports to match the USB host controller’s port numbering scheme.
•PortSwap: adds per-port programmability to USB differential-pair pin locations.
PortSwap also allows direct alignment of USB signals (D+/D-) to connectors to
avoid uneven trace length or crossi ng of the USB differential signals on the PCB.
•PHYBoost: enables 4 programmable levels of USB signal drive strength in down-
stream port transceivers. PHYBoost will also attempt to restore USB signal integ-
rity.
Note: PHYBoost is only available on the two USB downstream ports.
1.1 Hardware Features
• Single-chip HSIC hub and flash media controller combo
•USB4640/USB4640i supports the commercial temperature rang e of 0°C to +70°C.
•USB4640/USB4640i supports the industrial temperature range of -40°C to +85°C.
• Transaction translator (TT) in the hub supports operation of FS and LS peripherals
• Full power management with individual or ganged power control of each downstream port
• Optional support for external firmware access via SPI interface
• Onboard 24 MHz crystal driver circuit
• Optional external 24 MHz clock input (must be a 1.8 V signal)
• Code execution via SPI ROM which must meet the following criteria:2013-2018
-30 MHz or 60 MHz operation support
- Single-bit or dual-bit mode suppo rt
- Mode 0 or Mode 3 SPI support
• Compliance with the following flash media card specifications:
- Secure Digital 2.0 and MultiMediaCard 4.2
- SD 2.0, SD-HS, SD-HC
- TransFlash™ and reduced form factor media
- 1/4/8 bit MMC 4.2
- Memory Stick 1.43
- Memory Stick Pro Format 1. 02
2013-2018 Microchip Technology Inc. DS00001922B-page 5
USB4640/USB4640i
- Memory Stick Pro-HG Duo Fo rma t 1.01
- Memory Stick, MS Duo, MS-HS, MS Pro-HG, MS Pro
- Memory Stick Duo 1.10
- xD-Picture Card 1.2
• 8051 8-bit microprocessor
-60 MHz - single-cycle execution
-64 KB ROM | 9 KB RAM
• Integrated regulator for 1.8 V core operation
1.2 Software Features
• Hub and flash media reader/writer configuration fro m a sing le source: External I2C ROM or external SPI ROM,
where the following fe atures are then av a i la ble:
- Customizable vendor ID, product ID, and device ID
- 12-hex digits maximum for the serial number string
- 28-character manufacturer ID and product strings for the flash media reader/writer
1.3 OEM Selectable Hub Features
The USB4640/USB4640i provides a default configuration that may be sufficient for most applications following a reset.
The USB4640/USB4640i can instead be configured by an external I2C EEPROM or SPI ROM.
• Compound device support on a port-by-port basis
- a port is permanently hardwired to a downstream USB peripheral device
• Select over-current sensing and port power control on an individual or ganged (all ports together) basis to match
the OEM’s choice of circuit board component selection
• Port power control and over-current detection/delay features
• Configure the delay time for filtering the over-current sense inputs
• Configure the delay time for turning on downstream port power
• Bus-powered or self-powered selection
• Hub port disable or non-removable configurati ons
• Flexible port mapping and disable sequencing supports multiple platform designs
• Programmable USB differential-pair pin location eases PCB layout by aligning USB signal lines directly to connec-
tors
• Programmable USB signal drive strength recovers USB sign al integrity using 4 levels of signal drive strength
• Indicate the maximum current that the 2-port hub consumes
• Indicate the maximum current required for the hub controller
USB4640/USB4640i
DS00001922B-page 6 2013-2018 Microchip Technology Inc.
Conventions
Within this manual, the follow ing abbreviations and symbols are used to improve readability.
Example Description
BIT Name of a single bit within a field
FIELD.BIT Name of a single bit (BIT) in FIELD
x…y Range from x to y, inclusive
BITS[m:n] Groups of bits fr om m to n, inclu s ive
PIN Pin name
zzzzb Binary number (value zzzz)
0xzzz Hexadecimal number (value zzz)
zzh Hexadecimal number (value zz)
rsvd Reserved memory location. Must write 0, read value indeterminate
code Instruction code, or API function or parameter
Multi Word Name Used for multiple words that are considered a single unit, such as:
Resource Allocate message, or Connection Label, or Decrement Stack Pointer instruction.
Section Name Section or document name.
VAL Over-bar indicates active low pin or register bit
xDon’t care
<Parameter> <> indicate a parameter is optional or is only used under some conditions.
{,Parameter} Braces indicate parameter(s) that repeat one or more times.
[Parameter] Brackets indicate a nested parameter. This parameter is not real and actually
decodes into one or more real parameters.
2013-2018 Microchip Technology Inc. DS00001922B-page 7
USB4640/USB4640i
2.0 BLOCK DIAGRAM
FIGURE 2-1: USB4640/USB4640I BLOCK DIAGRAM
1.2 V
HSIC
HSIC
Data & Strobe
Repeater Controller
Serial
Interface
Engine
Serial
Interface
Routing & Port Re-Ordering Logic
Port Controller
PHY
Port #3
OC
Sense
Switch
Driver
Transaction
Translator
PHY
Port #2
OC
Sense
Switch
Driver
USB Data
Downstream OC Sense/
Pwr Switch
8051
PROCESSOR
SFR
RAM
XDATA BRIDGE
+ BUS ARBITER
ROM
64 K
RAM
6 K ADDR
MAP
Program Memory I/O Bus
PWR_FET0 (CRD_PWR)
3 K
total RAM
EP2 TX
EP2 RX
BUS
INTFC
EP2 RX
EP0 TX
EP0 RX
SIE
CTL
BRIDGE BUS
INTFC
FMDU
CTL
AUTO_CBW
PROC
FMI
BUS
INTFC
USB Data
Downstream Flash Media Cards
(require Combo socket)
MS
xD* SD/
MMC
OC Sense/
Pwr Switch
SPI SPI (4 pins)
3.3 V
1.8 V
PLL
24 MHz
Crystal
1.8 V Reg
*For xD-P ic tu re CardTM support, please obtain a user
license from the xD-Picture Card License office.
3.3 V
1.8 V Reg
VDDCR
HSIC
Impedance
USB4640/USB4640i
DS00001922B-page 8 2013-2018 Microchip Technology Inc.
3.0 PINNING INFORMATION
This chapter outlines the pinni ng configuratio n, followed by a corresponding pin list group ed by function. The detailed
pin descriptions are listed then outlined in Section 3.3, "Pin Descriptions," on page 10.
3.1 Pin Configurations
FIGURE 3-1: USB4640/USB4640I 48-PIN QFN
Ground Pad
(must be connected to VSS)
USB4640/40i
(Top View QFN-48)
nRESET 38
39
LED/TXD 37
TEST 40
VDD12 41
HSIC_STROBE 43
XTAL2 44
XTAL1 (CLKIN) 45
RBIAS
48
VDD33
47
PLLFILT 46
HSIC_DAT 42
VDD33
1
USBDN_DM2
2
USBDN_DP2
3
USBDN_DM3
4
USBDN_DP3
5
PRTCTL2 6
PRTCTL3 7
SPI_CE_n 8
SPI_CLK 9
VDD33
10
SPI_DI 11
SPI_DO/SDA/SPI_SPD_SEL
12
21 SD_CLK/MS_BS/xD_nWP
20 SD_D6/MS_D7/xD_D0
19 SD_D7/MS_D6/xD_D1
18 SD_D0/MS_D4/xD_D2
17
CRFILT
16
SD_D1/MS_D5/xD_D3
15
VDD33
14 SD_nCD
13 SD_WP/MS_SCLK/xD_D4
23 SD_D5/MS_D1/xD_ALE
22 xD_nWE
24
35
NC
34
CRD_PWR
33
VDD33
32 SD_D3/MS_D3/xD_D6
31 MS_INS
30 SD_D4/MS_D2/xD_D7
29 xD_nCD
28 xD_nB/R
36
SD_D2/xD_D5
27 xD_nRE
26 xD_nCE
25 VDD33
SD_CMD/MS_D0/xD_CLE
HSIC_IMP
Indicates pins on the bottom of the device.
2013-2018 Microchip Technology Inc. DS00001922B-page 9
USB4640/USB4640i
3.2 48-Pin List
TABLE 3-1: USB4640/USB4640I 48-PIN LIST
UPSTREAM HSIC INTERFACE (3 PINS)
HSIC_IMP HSIC_DAT HSIC_STROBE
DOWNSTREAM USB INTERFACE (3 PINS)
XTAL1 (CLKIN) XTAL2 RBIAS
DOWNSTREAM 2-PORT USB INTERFACE (6 PINS)
USBDN_DP2 USBDN_DM2 PRTCTL2 PRTCTL3
USBDN_DP3 USBDN_DM3
SECURE DIGITAL/MEMORY STICK/xD INTERFACE (18 PINS)
SD_D7/
MS_D6/
xD_D1
SD_D6/
MS_D7/
xD_D0
SD_D5/
MS_D1/
xD_ALE
SD_D4/
MS_D2/
xD_D7
SD_D3/
MS_D3/
xD_D6
SD_D2/
xD_D5 SD_D1/
MS_D5/
xD_D3
SD_D0/
MS_D4/
xD_D2
SD_CLK/
MS_BS/
xD_nWP
SD_CMD/
MS_D0/
xD_CLE
SD_nCD MS_INS
SD_WP/
MS_SCLK/
xD_D4 xD_nCD xD_nWE xD_nB/R
xD_nRE xD_nCE
SPI INTERFACE (4 PINS)
SPI_CE_N SPI_CLK/
SCL SPI_DO/
SDA/
SPI_SPD_SEL SPI_DI
MISC (5 PINS)
nRESET TEST LED NC
(CRD_PWR)
POWER (9 PINS)
(6) VDD33 VDD12 CRFILT PLLFILT
TOTAL 48
USB4640/USB4640i
DS00001922B-page 10 2013-2018 Microchip Technology Inc.
3.3 Pin Descriptions
This section provides a detaile d description of each pin. The pins are arran ged in functional grou ps according to their
associated interface. The pin descriptions below are applied when using the internal default firmware and can be refer-
enced in Secti on 4.0, "Configuration Options," on page 21. See Appendix A:, "Acronyms," on page 53 for details.
An n in the signal name indicates that the active (asserted) state occurs when the signal is at a low-voltage level. When
the n is not present, the signal is asserted when it is at a high-voltage level. The terms assertion and negation are used
exclusively in order to avoid confusion when working with a mixture of active-low and active-high signals. The term
assert, or assertion, indicates that a signal is active, in depende nt of whether th at level is represented b y a high or l ow
voltage. The term negate, or negation indicates that a signal is inactive.
TABLE 3-2: USB4640/USB4640I PIN DESCRIPTIONS
Symbol 48-Pin
QFN Buffer Type Description
UPSTREAM HSIC INTERFACE
HSIC_IMP 39 I HSIC Impedance Control
Selects the driver impedance of HSIC_DAT and HSIC_STROBE
1 : Approximately 50 impedance
0 : Approximately 40 impedance
HSIC_DAT 42 I/O HSIC Data
Bi-directional double data rate (DDR) data signal that is synchronous
to the HSIC_STROBE signal as defined in the High-Speed Inter-Chip
USB Specification, Version 1.0.
HSIC_STROBE 43 I/O HSIC Strobe
Bi-directional data strobe signal defined in the High-Speed Inter-Chip
USB Specification, Version 1.0.
DOWNSTREAM USB INTERFACE
USBDN_DM
[3:2]
USBDN_DP
[3:2]
3
1
4
2
I/O-U USB Bus Data
Connect to the downstream USB bus data signals and can be
swapped using the PortSwap feature (See Section 4.4.4.20, "F1h: Port
Swap," on page 36).
PRTCTL[3:2] 7
6I/OD6PU USB Power Enable, when used as an:
• Output: enables power to downstream USB peripheral devices and
have weak internal pull-up resistors. (See Section 3.5, "Port Power
Control," on page 15 for diagram and usage instructions.)
• Input: monitor the Over-current condition (whe n the power is
enabled). When an Over-current condition is detected, the pins
turn the power off.
RBIAS 47 I-R USB Transceiver Bias
Sets the transceiver's internal bias currents using a 12.0 k, 1.0%
resistor attached from VSS.
XTAL1 (CLKIN) 45 ICLKx 24 MHz Crystal Input or External Clock Input
Can be connected to one terminal of the crystal or connected to an
external 24 MHz clock when a crystal is not used.
XTAL2 44 OCLKx 24 MHz Crystal Output
The other terminal of the crystal, or it is left open when an external
clock source is used to drive XTAL1(CLKIN).
2013-2018 Microchip Technology Inc. DS00001922B-page 11
USB4640/USB4640i
SECURE DIGITAL INTERFACE
SD_D[7:0] 19
20
23
30
32
33
17
18
I/O8PU Secure Digital Data 7-0
Bi-directional data signals SD_D0 - SD_D7 with weak pull-up resistor.
SD_CLK 21 O8 Secure Digital Clock
The output clock signal to the SD/MMC device
SD_CMD 24 I/O8PU Secure Digital Command
Bi-directional signal that connects to the CMD signal of the SD/MMC
device. The bi-directional signal has a weak internal pull-up resistor.
SD_nCD 14 I/O8PU Secure Digital Card Detect
Designates as the Secure Digital card detection pin and has an
internal pull-up.
SD_WP 13 I/O8 Secure Digital Write Protected
Designates as the Secure Digital card interface mechanical write
protect detect pin.
MEMORY STICK INTERFACE
MS_BS 21 O8 Memory Stick Bus State
Connected to the bus state pin of the MS device. It is used to control
the Bus States 0, 1, 2, and 3 (BS0, BS1, and BS3) of the MS device.
MS_INS 31 IPU Memory Stick Card Insertion
Designates as the Memory Stick card detection pin and has a weak
internal pull-up resistor.
MS_SCLK 13 O8 Memory Stick System Clock
Output clock signal to the MS device.
MS_D[7:0] 20
19
17
18
32
30
23
24
I/O8PD Memory Stick System Data In/Out
Bi-directional data signals for the MS devi ce. In Seria l mode, the most
significant bit (MSB) of each byte is transmitted first by either the
memory stick controller MSC or the MS device on MS_D0.
MS_D0, MS_D2, and MS_D3 have weak pull-down resistors. MS_D1
has a pull-down resistor when in Parallel mode. Otherwise, it is
disabled. In 4-bit or 8-bit Parallel modes, all MS_D7 - MS_D0 signals
have weak pull-down resistors.
xD-PICTURE CARD INTERFACE
xD_D[7:0] 30
32
33
13
17
18
19
20
I/O8PD xD-Picture Card Data 7-0
Bi-directional data signals xD_D7 - xD_D0 and have weak internal pull-
down resistors.
xD_ALE 23 O8PD xD-Picture Card Address Strobe
Active-high Address Latch Enable (ALE) signal for the xD-Picture Card
device. This pin has a weak pull-down resistor that is permanently
enabled.
TABLE 3-2: USB4640/USB4640I PIN DESCRIPTIONS (CONTINUED)
Symbol 48-Pin
QFN Buffer Type Description
USB4640/USB4640i
DS00001922B-page 12 2013-2018 Microchip Technology Inc.
xD_nB/R 28
xD_nCE 26 O8PU xD-Picture Card Chip Enable
Active-low chip enable signal for the xD-Picture Card device.
When using the internal FET, this pin has weak internal pull-up resistor
that is tied to the output of the internal power FET.
If an external FET is used (internal FET is disabled), then the internal
pull-up is not available (an external pull-up is required).
xD_CLE 24 O8PD xD-Picture Card Command Strobe
An active-high Command Latch Enable signal fo r the xD-Picture Card
device. This pin has a weak pull-down resistor that is permanently
enabled.
xD_nCD 29 I/O8 xD-Picture Card Detection
Designates as the xD-Picture Card detection pin and has an internal
pull-up.
xD_nRE 27 O8PU xD-Picture Card Read Enable
Active-low read strobe signal for the xD-Picture Card device.
When using the internal FET, this pin has a weak internal pull-up
resistor that is tied to the output of the internal power FET.
If an external FET is used (internal FET is disabled), then the internal
pull-up is not available (an external pull-up is required).
xD_nWE 22 O8PU xD-Picture Card Write Enable
Active-low write strobe signal for the xD-Picture Card device.
When using the internal FET, this pin has a weak internal pull-up
resistor that is tied to the output of the internal power FET.
If an external FET is used (internal FET is disabled), then the internal
pull-up is not available (an external pull-up is required).
xD_nWP 21 O8PD xD-Picture Card Write Protect
An active-low write-pr otect signal for the xD-Pictu re Card device. This
pin has a weak pull-down resistor that is permanently enabled.
SPI INTERFACE
SPI_CE_n 8 O12 SPI Chip Enable
An active-low chip enable output. If the SPI interface is enabled, this
pin must be driven high in power down states.
SPI_CLK/ 9 I/O12 SPI Clock Out
Clock signal out to the serial ROM. See Section 3.6, "ROM BOOT
Sequence," on page 17 for diagram and usage instructions. During
reset, this pin must be driven low.
SCL I/O6 Serial Clock
The I2C EEPROM clock pin when the device is connected to the
optional I2C EEPROM.
TABLE 3-2: USB4640/USB4640I PIN DESCRIPTIONS (CONTINUED)
Symbol 48-Pin
QFN Buffer Type Description
2013-2018 Microchip Technology Inc. DS00001922B-page 13
USB4640/USB4640i
SPI_DO/ 10 I/O12 SPI Serial Data Out
The output for the SPI port. See Section 3.6, "ROM BOOT Sequence"
for diagram and usage instructions.
SDA/ I/O6 Serial Data Line
The I2C EEPROM data pin when the device is connected to the
optional I2C EEPROM.
SPI_SPD_SEL I/O12 SPI Speed Select
Selects the speed of the SPI interface. Durin g nRESET assertion, this
pin will be tri-stated with the weak pull-down resistor enabled. When
nRESET is negated, the value on the pin will be internally latched, and
the pin will revert to SPI_DO functionality, where the internal pull-down
will be disabled.
0 : 30 MHz (no external resistor should be applied)
1 : 60 MHz (a 10 k external pull-up resistor must be applied)
If the latched value is 1, then the pin is tri-stated when the chip is in
the suspend state.
If the latched value is 0, then the pin is driven low during a suspend
state.
SPI_DI 11 I/O12PD SPI Serial Data In
The SPI data in to the controller from the ROM. This pin has a weak
internal pull-down applied at all times to prevent floating.
MISC
LED 37 I/O6 Can be used as an LED output.
NC 36
CRD_PWR 35 I/O200 Card Power Drive: 3.3 V (100 mA or 200 mA)
This must be the only FET used to power devices. Failure to do this
will violate voltage specifications on device pins.
Please see Section 4.4.2.3, "A4h-A5h: Smart Media Device Power
Configuration," on page 28 for more information.
nRESET 38 IS Reset Input
The system uses this active low signal to reset the chip. The active
low pulse should be at least 1 s wide.
TEST 40 I Test Input
Tie to ground for normal operation.
DIGITAL/POWER/GROUND
CRFILT 15 VDD Core Regulator Filter Capacitor
Requires a 1.0 F (or greater) 20% (ESR <0.1) capacitor to VSS.
PLLFILT 46 Phase-Locked Loop Regulator Filter Capacitor
Requires a 1.0 F (or greater) 20% (ESR < 0.1 ) capacitor to VSS.
VDD12 41 1.2 V Power
For HSIC pads and buffers
TABLE 3-2: USB4640/USB4640I PIN DESCRIPTIONS (CONTINUED)
Symbol 48-Pin
QFN Buffer Type Description
USB4640/USB4640i
DS00001922B-page 14 2013-2018 Microchip Technology Inc.
3.4
TABLE 3-3: USB4640/USB4640I BUFFER TYPE DESCRIPTIONS
Buffer Description
Buffer Type Descriptions
VDD33 5
12
16
25
34
48
3.3 V Power and Regulator Input
See Section 6.0, "DC Parameters," on page 43 for more information.
Pins 16 and 48 each require an external bypass capacitor of 4.7 F
minimum.
VSS ePad Ground Pad/ePad
The package slug is the only VSS for the device and must be tied to
ground with multiple vias.
IPU xD-Picture Card Busy or Data Ready
Connected to the BSY/RDY pin of the xD-Picture Card device.
When using the internal FET, this pin has a weak internal pull-up resistor that is tied to the output
of the internal power FET.
If an external FET is used (the internal FET is disabled), then the internal pull-up is not available
(an external pull-up is required).
I Input
I/O Input/output
IPU Input with weak internal pull-up
IS Input with Schmitt trigger
I/O6 Input/output buffer with 6 mA sink and 6 mA source
I/OD6PU Input/open drain output buffer with a 6 mA sink
O8 Output buffer with an 8 mA sink and an 8 mA source
O8PD Output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-down resistor
O8PU Output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-up resistor
I/O8 Input/output buffer with an 8 mA sink and an 8 mA source
I/O8PD Input/output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-down resistor
I/O8PU Input/output buffer with an 8 mA sink and an 8 mA source with a weak internal pull-up resistor
O12 Output buffer with a 12 mA sink and a 12 mA source
I/O12 Input/output buffer with 12 mA sink and 12 mA source
I/O12PD Input/output buffer with 12 mA sink and 12 mA source with a weak internal pull-down resistor
I/O200 Input/output buffer 12 mA with FET disabled, 100/200 mA source only when the FET is enabled
ICLKx XTAL clock input
OCLKx XTAL clock output
I/O-U Analog input/output as defined in the USB 2.0 Specification
I-R RBIAS
TABLE 3-2: USB4640/USB4640I PIN DESCRIPTIONS (CONTINUED)
Symbol 48-Pin
QFN Buffer Type Description
2013-2018 Microchip Technology Inc. DS00001922B-page 15
USB4640/USB4640i
3.5 Port Power Control
3.5.1 PORT POWER CONTROL USING A USB POWER SWITCH
The USB4640/USB4640i has a single port power control and over-current sense signal for each downstream port.
When disabling port power, the d river will actively d rive a 0. To avoid unnecessary power dissipation, the internal pu ll-
up resistor will be disabled at that time. When port power is enabled, the output driver is disabled, and the pull-up resistor
is enabled creating an open drain output.
If there is an over-current situation, the USB Powe r Switch will assert the open drain OCS signal. The Schmitt trigger
input will detect this event as a low . The open drain output does not interfere. The internal over-current sense filter han-
dles the transient conditions, such as low voltage, while the device is powering up.
FIGURE 3-2: PORT POWER CONTROL WITH USB POWER SWITCH
USB Power
Switch
5 V
USB
Device
PRTCTL3
EN
OCS
USB Power
Switch
5 V
USB
Device
PRTCTL2
EN
OCS
USB4640/40i
3.5.2 PORT POWER CONTROL USING A POLY FUSE
When using the USB4640/USB4640i with a poly fuse, an external diode must be used (see Figure 3-3). When disabling
port power , the USB4640/USB4640i will drive a 0. This procedure will have no effect since the external diode will isolate
the pin from the load. Wh en port power is enable d, the USB4640/USB4640i outp ut driver is disabled, and the pull-up
resistor is enabled which creates an open drain output. This open drain output condition means that the pull-up resistor
is providing 3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will
cause the cathode of the diode to go to zero volts. The anode of the diode will be at 0.7 volts, and th e Schmitt trigger
input will register this as a low resulting in an over-current detection. The open drain output does not interfere.
FIGURE 3-3: PORT POWER CONTROL WITH A SINGLE POLY FUSE AND MULTIPLE LOADS
USB4640/40i
USB
Device
5 V
PRTCTL3
USB
Device
5V
PRTCTL2
USB4640/USB4640i
DS00001922B-page 16 2013-2018 Microchip Technology Inc.
When using a single po ly fuse to power all devices, note that for the ganged situation, all power con trol pins must be
tied together.
FIGURE 3-4: PORT POWER WITH GANGED CONTROL WITH POLY FUSE
USB
Device
Poly Fuse
5 V
USB
Device
PRTCTL2
PRTCTL3
USB4640/40i
2013-2018 Microchip Technology Inc. DS00001922B-page 17
USB4640/USB4640i
3.6 ROM BOOT Sequence
After power-on reset, the internal firmware checks for an external SPI flash device that contains a valid signature of
2DFU (device firmware upg rade) b eginnin g at address 0xFF FA. If a valid signature i s fou nd, then the exte rnal R OM is
enabled and code execution begins at address 0x0000 in the external SPI device. Otherwise, code execution continues
from the internal ROM.
If there is no SPI ROM detected, the internal firmware then checks for the presence of an I2C ROM. The firmware looks
for the signature ATA2 at the offset of FCh-FFh and ecf1 at the of fset of 17Ch-17Fh in the I2C ROM. The firmware reads
in the I2C ROM to configure the hardware and software internally. Please refer to Section 4.3.2, "EEPROM Data
Descriptor," on page 21 fo r the details of the configuration options.
The SPI ROM required for the USB4640/USB4640i is a recommended minimum of 1 Mb and support either 30 MHz or
60 MHz. The frequency used is set using the SPI_SPD_SEL. For 30 MHz operation, thi s pin must be pulle d to ground
through a 100 k resistor. For 60 MHz operation, this pin must pulled up through a 100 k resistor.
The SPI_SPD_SEL pin is used to choose the spe ed of the SPI interface. During nRESET assertion, thi s pin will be tri-
stated with the weak pull-down resistor enabled. When nRESET is negated, the value on the pin will be internally
latched, and the pin will revert to SPI_DO functionality. The internal pull-down will be disabled.
The firmware can determine th e speed of op eration on th e SPI port by checking th e SPI_CTL.SPI_SPEED b it (0x2400 -
RESET = 0x02). Both 1-bit and 2-bit SPI operation is supported. For optimum throughp ut, a 2-bit SPI ROM is recom-
mended. Both mode 0 and mode 3 SPI ROMS are also supported.
FIGURE 3-5: SPI ROM CONNECTION
SPI ROM
SPI_CE_N
SPI_CLK/SCL
SPI_DI
SPI_DO/SDA/SPI_SPD_SEL
CE#
CLK
SI
SO
USB4640/40i
FIGURE 3-6: I2C CONNECTION
I2C ROM
SCL
SDA
3.3 V
3.3 V
10 K
10 K
USB4640/40i
USB4640/USB4640i
DS00001922B-page 18 2013-2018 Microchip Technology Inc.
3.7 Pin Reset States
FIGURE 3-7: PIN RESET STATES
Voltage
Signal
(v)
Time
(t)
RESET
RESET
Hardware
Initialization Firmware
Operational
VDD33
VSS
TABLE 3-4: LEGEND FOR PIN RESET STATES TABLE
Symbol Description
0 Output driven low
1 Output driven high
IP Input enabled
PU Hardware enables pull-up.
PD Hardware enables pull-down.
none Hardware disables pad.
-- Hardware disables function.
Z Hardware disables pad. Both output driver and input buffers are disabled.
TABLE 3-5: USB4640/USB4640I RESET STATES TABLE
Reset State
Pin Pin Name Function Input/
Output PU/
PD
1 USBDN_DM2 USBDN_DM2 IP PD
2 USBDN_DP2 USBDN_DP2 IP PD
3 USBDN_DM3 USBDN_DM3 IP PD
4 USBDN_DP3 USBDN_DP3 IP PD
6 PRTCTL2 PRTCTL 0 --
7 PRTCTL3 PRTCTL 0 --
2013-2018 Microchip Technology Inc. DS00001922B-page 19
USB4640/USB4640i
8 SPI_CE_n SPI_CE_n 1 --
9 SPI_CLK/SCL none 0 --
10 SPI_DO/SDA/SPI_SPD_SEL none 0 --
11 SPI_DI SPI_DI IP PD
13 SD_WP/MS_SCLK/xD_D4 none 0 --
14 SD_nCD none IP PU
17 SD_D1/MS_D5/xD_D3 none Z --
18 SD_D0/MS_D4/xD_D2 none Z --
19 SD_D7/MS_D6/xD_D1 none Z --
20 SD_D6/MS_D7/xD_D0 none Z --
21 SD_CLK/MS_BS/xD_nWP none Z --
22 xD_nWE xD_nWE Z --
23 SD_D5/MS_D1/xD_ALE none Z --
24 SD_CMD/MS_D0/xD_CLE none Z --
26 xD_nCE xD_nCE Z --
27 xD_nRE xD_nRE Z --
28 xD_nB/R xD_nB/R Z --
29 xD_nCD none IP PU
30 SD_D4/MS_D2/xD_D7 none Z --
31 MS_INS none IP PU
32 SD_D3/MS_D3/xD_D6 none Z --
33 SD_D2/xD_D5 none Z --
35 CRD_PWR none Z --
36 NC none 0 --
37 LED none 0 --
38 nRESET nRESET IP --
39 HSIC_IMP HSIC_IMP Z --
TABLE 3-5: USB4640/USB4640I RESET STATES TABLE (C ONTINUED)
Reset State
Pin Pin Name Function Input/
Output PU/
PD
USB4640/USB4640i
DS00001922B-page 20 2013-2018 Microchip Technology Inc.
40 TEST TEST IP PD
42 HSIC_DAT HSIC_DAT IP --
43 HSIC_STROBE HSIC_STROBE IP --
TABLE 3-5: USB4640/USB4640I RESET STATES TABLE (CONTINUED)
Reset State
Pin Pin Name Function Input/
Output PU/
PD
2013-2018 Microchip Technology Inc. DS00001922AB-page 21
USB4640/USB4640i
4.0 CONFIGURATION OPTIONS
4.1 Hub
Microchip’s USB 2.0 hub is fully compliant to the Universal Serial Bus Specification [1].
The hub provides 1 transacti on translator (TT) that is shared by both dow nstream ports defin ed as a single-TT config-
uration. The TT contains 4 non-periodic buffers. The hub supports a large number of features (some are mutually exclu-
sive), and must be configured in order to correctly function when attached to a USB host controller. There are two
principal ways t o configure the hub:
• Internal default settings
• External EEPROM or SPI Flash device
Note: See Chapter 11 (Hub Specification) of the USB specification for ge neral details regarding hub operation
and functionality.
4.2 Card Reader
The Microc hip USB4640/USB4640i is fully compliant with the following flash media card reader specifications:
• Secure Digital 2.0/MultiMediaCard 4.2
- SD 2.0, HS-SD, HC-SD
- T ransFlash™ and reduced form factor media
- 1/4/8 bit MMC 4.2
• Memory Stick 1.43
• Memory Stick Pro Format 1.02
• Memory Stick Pro-HG Duo Format 1.01
- Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro
• Memory Stick Duo 1.10
• xD-Picture Card 1.2
4.3 System Configurations
4.3.1 EEPROM/SPI INTERFACE
The USB4640/USB4640i can be configured via a 2-wire I2C EEPROM (5 12x8) or an e xternal SPI f lash device co ntain-
ing the USB4640/USB4640i fi rmware. If an external configuration device does not exist, the internal default values will
be used. If one of the external devices is used for configuration, the USB4640/USB4640i values can be updated through
the USB interface. The hub will then attach to the upstream USB host.
The USBDM tool set is available in the USB264x Hub Card reader combo software release package. To download the
software package from Microchip’s website, visit:
•http://www.microchip.com/search/searchapp/searchhome.aspx?id=2&q=mkt/CW_SFT_PUB.nsf/Agree-
ments/OBJ+Hub+Card+Reader
Review the license and select the I agree checkbox, followed by the Confirm button. Download the USB264x Hub Card
reader combo Release Package zip file with the USBDM tool set will then be available for download.
4.3.2 EEPROM DATA DESCRIPTOR
TABLE 4-1: INTERNAL FLASH MEDIA CONTROLLER CONFIGURATIONS
Address Register Name Description Internal Default Value
00h USB_SER_LEN USB Serial String
Descriptor Length 1Ah
01h USB_SER_TYP USB Serial String
Descriptor Type 03h
02h-19h USB_SER_NUM USB Serial Number 000008264001
(Note 4-1)
1Ah-1Bh USB_VID USB Vendor Identifier 0424
USB4640/USB4640i
DS00001922AB-page 22 2013-2018 Microchip Technology Inc.
1Ch-1Dh USB_PID USB Product Identifier 4040
1Eh USB_LANG_LEN USB Language String Descriptor
Length 04h
1Fh USB_LANG_TYP USB Lan guage String Descriptor
Type 03h
20h USB_LANG_ID_LSB USB Language Identifier
Least Significant Byte 09h
(Note 4-3)
21h USB_LANG_ID_MSB USB Language Identifier
Most Significant Byte 04h
(Note 4-3)
22h USB_MFR_STR_LEN USB Manufacturer String
Descriptor Length 10h
23h USB_MFR_STR_TYP USB Manufacturer String
Descriptor Type 03h
24h-31h USB_MFR_STR USB Manufacturer String Generic
(Note 4-1)
32h-5Dh rsvd 00h
5Eh USB_PRD_STR_LEN USB Product String
Descriptor Length 30h
5Fh USB_PRD_STR_TYP USB Product String
Descriptor Type 03h
60h-99h USB_PRD_STR USB Product String Ultra Fast Media Reader
—(Note 4-1)
9Ah USB_BM_ATT USB BmAttribute 80h
9Bh USB_MAX_PWR USB Max Power 30h (96 mA)
9Ch ATT_LB Attribute Lo byte 40h (reverse SD_WP only)
9Dh ATT_HLB Attribute Hi Lo byte 80h (reverse SD2_WP only)
9Eh ATT_LHB Attribute Lo Hi byte 00h
9Fh ATT_HB Attribute Hi byte 00h
A0h MS_PWR_LB Memory Stick Device
Power Lo byte 00h
A1h MS_PWR_HB Memory Stick Device
Power Hi byte 0Ah
A2h-A3h N/A 00h
A4h SM_PWR_LB Smart Media Device
Power Lo byte 00h
(Note 4-2)
A5h SM_PWR_HB Smart Media Device
Power Hi byte 0Ah
(Note 4-2)
A6h SD_PWR_LB Secure Digital Device
Power Lo byte 00h
A7h SD_PWR_HB Secure Digital Device
Power Hi byte 0Ah
A8h LED_BLK_INT LED Blink Interval 02h
A9h LED_BLK_DUR LED Blink After Access 28h
AAh - B0h DEV0_ID_STR Device 0 Identifier String N/A
B1h - B7h DEV1_ID_STR Device 1 Identifier String MS
B8h - BEh DEV2_ID_STR Device 2 Identifier String SM
(Note 4-2)
BFh - C5h DEV3_ID_STR Device 3 Identifier String SD/MMC
C6h - CDh INQ_VEN_STR Inquiry Vendor String Generic
CEh - D2h INQ_PRD_STR Inquiry Product String 82640
TABLE 4-1: INTERNAL FLASH MEDIA CONTROLLER CONFIGURATIONS (CONTINUED)
Address Register Name Description Internal Default V alue
2013-2018 Microchip Technology Inc. DS00001922AB-page 23
USB4640/USB4640i
Note 4-1 This value is a UNICODE UTF-16LE encoded string value that meets the USB 2.0 Specification [1].
Note 4-2 A value of SM will be overridden with xD once an xD-Picture Card has been identified.
Note 4-3 Current 16-bit language IDs are defined by the USB-IF, see The Unicode Standard, Worldwide
Character Encoding [4].
TABLE 4-2: HUB CONTROLLER CONFIGURATIONS
Address Register Name Description Internal Default Value
TABLE 4-3: OTHER INTERNAL CONFIGURATIONS
Address Register Name Description Internal Default Value
D3h DYN_NUM_LUN Dynamic Number of LUNs 01h
D4h - D7h DEV_LUN_MAP Device to LUN Mapping FFh, 00h, 00h, 00h
D8h - DAh 00h, 06h, 0Dh
DBh - DDh 59h, 56h, 97h
DEh VID_LSB Vendor ID Least Significant Byte 24h
DFh VID_MSB Vendor ID Most Significant Byte 04h
E0h PID_LSB Product ID Least Significant Byte 40h
E1h PID_MSB Product ID Most Significant Byte 26h
E2h DID_LSB Device ID Least Significant Byte A1h
E3h DID_MSB Device ID Most Significant Byte 08h
E4h CFG_DAT_BYT1 Configuration Data Byte 1 8Bh
E5h CFG_DAT_BYT2 Configuration Data Byte 2 28h
E6h CFG_DAT_BYT3 Configuration Data Byte 3 00h
E7h NR_DEVICE Non-Removable Devices 02h
E8h PORT_DIS_SP Port Disable (Self) 00h
E9h PORT_DIS_BP Port Disable (Bus) 00h
EAh MAX_PWR_SP Max Power (Self) 01h
EBh MAX_PWR_BP Max Power (Bus) 32h
ECh HC_MAX_C_SP Hub Controller Max Current (Self) 01h
EDh HC_MAX_C_BP Hub Controller Max Current (Bus) 32h
EEh PWR_ON_TIME Power-on Time 32h
EFh BOOST_UP Boost_Up 00h
F0h BOOST_3:0 Boost_3:0 00h
F1h PRT_SWP Port Swap 00h
F2h PRTM12 Port Map 12 00h
F3h PRTM3 Port Map 3 00h
F4h 00h
F5h 66h
F6h 00h
F7-FAh N/A N/A
FBh N/A 00h
FCh-FFh NVSTORE_SIG Non-Volatile Storage Signature ata2
TABLE 4-1: INTERNAL FLASH MEDIA CONTROLLER CONFIGURATIONS (CONTINUED)
Address Register Name Description Internal Default Value
USB4640/USB4640i
DS00001922AB-page 24 2013-2018 Microchip Technology Inc.
4.4 Internal Flash Media Controller Extended Configurations
Set bit 7 of bmAttribute to enable these extended configuration regist ers.
TABLE 4-4: INTERNAL FLASH MEDIA CONTROLLER EXTENDED CONFIGURATIONS
Address Register Name Description Internal Default Value
4.4.1 EEPROM DATA DESCRIPTOR REGISTER DESCRIPTIONS
4.4.1.1 00h: USB Serial Stri ng Descriptor Length
4.4.1.2 01h: USB Serial String Descriptor Type
4.4.1.3 02 h -19h : USB S eri al Num b er Opt ion
4.4.1.4 1Ah-1Bh: USB Vendor ID Option
4.4.1.5 1Ch-1Dh: USB Product ID Option
100h - 106h CLUN0_ID_STR Combo LUN 0 Identifier String COMBO
107h- 129h N/A N/A
12Ah-145h N/A 00h
146h N/A 01h
147h - 14Bh N/A 01h, FFh, FFh, FFh, FFh
14Ch N/A 0Ah
14Dh-17Bh N/A 00h
17Ch-17Fh NVSTORE_SIG2 Non-Volatile Storage Signature ecf1
Byte Name Description
0 USB_SER_LEN USB serial string descriptor length as defined by Section 9.6.7: String of the
USB 2.0 Specification [1]. This field is the bLength, which describes the size
of the string descriptor (in bytes).
Byte Name Description
1 USB_SER_TYP USB serial string descriptor type as defined by Section 9.6.7: String of the
USB 2.0 Specification [1]. This field is the bDescriptorType, a constant value
associated with a string descriptor type.
Byte Name Description
25:2 USB_SER_NUM Maximum string length is 12 hex digits. Must be unique to each device.
Byte Name Description
1:0 USB_VID This ID is unique for every vendor. The vendor ID is assigned by the USB
Implementer’s Forum.
Byte Name Description
1:0 USB_PID The product ID: assigned by the vendor; unique for every product.
2013-2018 Microchip Technology Inc. DS00001922AB-page 25
USB4640/USB4640i
4.4.1.6 1Eh: USB Language Identifier Descriptor Length
4.4.1.7 1Fh: USB Language Identifier Descriptor Type
4.4.1.8 20h: USB Language Identifier Least Significant Byte
4.4.1.9 21h: USB Language Identifier Most Significant Byte
4.4.1.10 22h: USB Manufacturer String Descriptor Length
4.4.1.11 23h: USB Manufacturer String Descriptor Type
4.4.1.12 24h-31h: USB Manufacturer String Option
4.4.1.13 32h-5Dh: Reserved
Byte Name Description
0 USB_LANG_LEN USB language I D string descrip tor length as d efined by Sectio n 9.6.7: String of
the USB 2.0 Specification [1]. This field is the bLength, which describes the size
of the string descriptor (in bytes).
Byte Name Description
1 USB_LANG_TYP USB language ID string descriptor type as defined by Section 9.6.7: String of
the USB 2.0 Specification [1]. This field is the bDescriptorType, a constant
value associated with a string descriptor type.
Byte Name Description
2 USB_LANG_ID
_LSB English language code = 0409. See Note 4-3 for additional language IDs
defined by the USB-IF.
Byte Name Description
3 USB_LANG_ID
_MSB English language code = 0409. See Note 4-3 for additional language IDs
defined by the USB-IF.
Byte Name Description
0 USB_MFR_STR
_LEN USB manufacturer string descriptor length as defined by Section 9.6.7 String
of the USB 2.0 Specification [1]. This field is the bLength which describes the
size of the string descriptor (in bytes).
Byte Name Description
1 USB_MFR_STR
_TYP USB manufacturer string descriptor type as defined by Section 9.6.7 String of
the USB 2.0 Specification [1]. This field is the bDescriptorType, a constant
value associated with a string descriptor type.
Byte Name Description
15:2 USB_MFR_STR The maximum string length is 28 characters.
Byte Name Description
59:16 rsvd
USB4640/USB4640i
DS00001922AB-page 26 2013-2018 Microchip Technology Inc.
4.4.1.14 5Eh: USB Product String D es crip to r Le ng th
4.4.1.15 5Fh: USB Product String Descriptor Type
4.4.1.16 60h-99h: USB Product Str i ng Opt ion
4.4.1.17 9Ah: USB BmAttribute (1 Byte )
4.4.1.18 9Bh: USB MaxPower (1 Byte)
Byte Name Description
0 USB_PRD_STR
_LEN USB product string descriptor length as defined by Section 9.6.7 String of the
USB 2.0 Specification [1]. This field is the bLength, which describ es the size of
the string descriptor (in bytes).
Byte Name Description
1 USB_PRD_STR
_TYP USB product string descriptor type as defined by Section 9.6.7 String of the
USB 2.0 Specification [1]. This field is the bDescriptorType, a constant value
associated with a string descriptor type.
Byte Name Description
59:2 USB_PRD_ STR This string will be use d during the USB enumeration process in the Windows ®
operating system. Maximum string length is 28 characters.
Bit Name Description
7:0 USB_BM_ATT Self-Power or Bus-Power: selects between self-powered and bus-powered
operation.
The hub is either self-pow ered (draws less than 2 mAor bu s-powered (limited
to 100 mA maximum power prior to being configured by the host controller).
When configured as a bus-powered device, the hub consumes less than
100 mA of current prior to being configured. After configuration, the bus-
powered Microchip hub (along with all associated hub circuitry, any embedded
devices if part of a compound device, and 100 mA per externally available
downstream port) must consume no more than 500 mA of current. The current
consumption is system dependent and must follow the USB 2.0 Specification
requirements.
When configured as a self-powered device, <1 mA of current is consumed and
all ports are available, with each port being capable of sourcing 500 mA of
current.
80 : (default) Bus-powered operation
C0 : Self-powered operation
A0 : Bus-powered operation with remote wake-up
E0 : Self-powered operation with remote wake-up
Bit Name Description
7:0 USB_MAX_PWR USB Max Power per the USB 2.0 Specification [1]. Do NOT set this value
greater than 100 mA.
2013-2018 Microchip Technology Inc. DS00001922AB-page 27
USB4640/USB4640i
4.4.1.19 9Ch-9Fh: Attribute Byte Descriptions
Byte Byte Name Bit Description
0 ATT_LB 3:0 Always read as 0
4 Inquire Manufacturer and Product ID Strings
1 : use the Inquiry Manufacturer and Product ID Strings
0 : (default) use the USB Descriptor Manufacturer and Product ID Strings
5 Always read as 0
6 Reverse SD Card Write Protect Sense
1 : (default) SD cards will be write protected when SW_nWP is high, and
writable when SW_nWP is low.
0 : SD cards will be write protected when SW_nWP is low, and writable when
SW_nWP is high.
7 Extended Configuration Enable
1 : enables editing, updating, and reading from registers 100h-17Fh.
0 : internal config uration is loade d, where it will not rea d from registers 100h-
17Fh.
1 ATT_HLB 3:0 Always read as 0
4 Activity LED True Polarity
1 : activity LED to low true
0 : (default) - activity LED polarity to high true
5 Common Media Insert/Media Activity LED
1 : activity LED will function as a common media inserted/media access
LED.
0 : (default) - activity LED will remain in its idl e state until media is accessed.
6 Always read as 0
7 Reverse SD2 Card Write Protect Sense
1 : (default) - SD cards in LUN 1 will be write protected when SW_nWP is
high, and writable when SW_nWP is low.
0 : SD cards in LUN 1 will be write protected when SW_nWP is low, and
writable when SW_nWP is high.
2 ATT_LHB 0 Attach on Card Insert/Detach on Card Removal
1 : attach on insert is enabled
0 : (default) - attach on insert is disabled
1 Always read as 0
2 Enable Device Power Configuration
1 : Custom Device Power Configuration stored in the NVSTORE is used
0 : (default) - Default Device Power Configuration is used
7:3 Always read as 0
3 ATT_HB 6:0 Always read as 0
7 xD Player Mode
USB4640/USB4640i
DS00001922AB-page 28 2013-2018 Microchip Technology Inc.
4.4.2 A0H-A7H: DEVICE POWER CONFIGURATION
The USB4640/USB4640i has one internal FET which can be utilized for card power. This section describes the default
internal configuration. The settings are stored in NVSTORE and provide the following features:
1. A card can be powered by an external FET or by an internal FET.
2. The power limit can be set to 100 mA or 200 mA (default) for the internal FET.
Each media uses two bytes to store its device power configuration. Bit 3 selects between internal or external card power
FET options. For internal FET card power control, b its 0 through 2 a re used to set the power limit. The Device Power
Configuration bits are ignored unless the Enable Device Power Configuration bit is set. See Section 4.4.1.19 on
page 27.
4.4.2.1 A 0 h-A 1h : Me m or y S tick Device Power Configuration
FET Name Bits Bit Type Description
4.4.2.2 A2 h- A3h : No t Applic ab le
4.4.2.3 A4h-A5h: Smart Media Device Power Configuration
FET Name Bits Bit Type Description
4.4.2.4 A6 h- A 7h : Sec ur e Dig ital Device Power Configuration
FET Name Bits Bit Type Description
0 MS_PWR_LB 3:0 Low Nibble FET Lo Byte
0000 : disabled
1 7:4 High Nibble
2 MS_PWR_HB 3:0 Low Nibble FET Hi Byte
0000 : disabled
0001 : external FET enabled
1000 : internal FET - 100 mA power limit
1010 : (default) internal FET - 200 mA power limit
3 7:4 High Nibble 0000 : disabled
Byte Name Description
1:0 N/A
0SM_PWR_LB 3:0 Low Nibble FET Lo Byte:
0000 : disabled
1 7:4 High Nibble
2 SM_PWR_HB 3:0 Low Nibble FET Hi Byte
0000 : disabled
0001 : external FET enabled
1000 : internal FET - 100 mA power limit
1010 : (default) internal FET - 200 mA power limit
3 7:4 High Nibble 0000 : disabled
0 SD_PWR_LB 3:0 Low Nibble FET Lo Byte:
0000 : disabled
1 7:4 High Nibble
2 SD_PWR_HB 3:0 Low Nibble FET Hi Byte
0000 : disabled
0001 : external FET enabled
1000 : internal FET - 100 mA power limit
1010 : (default) internal FET - 200 mA power limit
3 7:4 High Nibble 0000b : disabled
2013-2018 Microchip Technology Inc. DS00001922AB-page 29
USB4640/USB4640i
4.4.2.5 A8h: LED Blink Interval
4.4.2.6 A9h: LED Blink Duration
4.4.3 DEVICE ID STRINGS
These bytes are use d to specify t he LU N de scri ptor ret urn ed by the devi ce. These bytes are used in combination with
the device to LUN mapping bytes in applications where the LUNs need to be reordered and renamed. If multiple devices
are mapped to the same LUN (a COMBO LUN), then the CLUN#_ID_STR will be used to name the COMBO LUN instead
of the individual devic e strings. When applicable, the SM value will be overridden with xD once an xD-Picture Card has
been identified.
4.4.3.1 AAh-B0h: Device 0 Identifier String
4.4.3.2 B1h-B7h: Device 1 Identifier String
4.4.3.3 B8h-BEh: Device 2 Identifier String
4.4.3.4 BFh-C5h: Device 3 Identifier String
4.4.3.5 C6h-CDh: Inquiry Vendor String
Byte Name Description
0 LED_BLK_INT The blink rate is programmable in 50 ms intervals. The high bit (7) indicates
an idle state:
0 : off
1 : on
The remaining bits (6:0) are used to determine the blink interval up to a max
of 128 x 50 ms.
Byte Name Description
1 LED_BLK_DUR LED Blink After Access: designates the number of seconds that the LED will
continue to blink after a drive access. Setting this byte to 05 will cause the
LED to blink for 5 seconds after a drive access.
Byte Name Description
6:0 DEV0_ID_STR N/A
Byte Name Description
6:0 DEV1_ID_STR ID string is associated with the Memory Stick device.
Byte Name Description
6:0 DEV2_ID_STR ID string is associated with the Smart Media (Note 4-2) device.
Byte Name Description
6:0 DEV3_ID_STR ID string is associated with the Secure Digital/MultiMediaCard device.
Byte Name Description
7:0 INQ_VEN_STR If bit 4 of the first attribute byte is set, the device will use these strings in
response to a USB inquiry command instead of the USB descriptor
manufacturer and product ID strings.
USB4640/USB4640i
DS00001922AB-page 30 2013-2018 Microchip Technology Inc.
4.4.3.6 CEh-D2h: Inquiry Product String
4.4.3.7 D3h: Dynamic Number of LUNs
4.4.3.8 D4h-D7h: Device to LUN Mapping
4.4.3.9 D8 h- DDh : Res er ve d
4.4.4 HUB CONTROLLER CONFIGURATIONS
4.4.4.1 DEh : Ven do r ID (L SB)
4.4.4.2 DFh: Vendor ID (MSB)
Byte Name Description
4:0 INQ_PRD_STR If bit 4 of the first attribute byte is set, the device will use these strings in
response to a USB inquiry command instead of the USB descriptor
manufacturer and product ID strings.
Bit Name Description
7:0 DYN_NUM_LUN These bytes are used to specify the number of LUNs the device exposes to
the host. These bytes are also used for icon sharing by assigning more than
one LUN to a single icon. This is used in applications where the device utilizes
a combo socket with only a single icon displayed for one or more interfaces.
If this field is set to FF, the program assumes that you are using the default
value and icons will be configured per the default configuration.
Byte Name Description
3:0 DEV_LUN_MAP These registers map a device controller (SD/MMC, SM (Note 4-2), and MS)
to a Logical Un it Number (LUN). The device reports the mapped LUNs to th e
USB host in the USB descriptor during enumeration. The icon installer
associates custom icons with the LUNs specified in these fields.
Setting a register to FF in dicates that the device is not mappe d. Setting all of
the DEV_LUN_MAP registers for all devices to FF forces the use of the
default mapping configuration. Not all configurations are valid. Valid
configurations depend on the hardware, packaging, and the board layout. The
number of unique L UNs mapped must match th e value in the Section 4.4.3.7
on page 30.
Byte Name Description
2:0 rsvd
Bit Name Description
7:0 VID_LSB Least Significant Byte of the Vendor ID: a unique 16-bit value that identifies
the vendor of the user device (assigned by USB Implementer ’s Forum).
Bit Name Description
7:0 VID_MSB Most Significant Byte of the Vend or ID: a uniq ue 16-bit value that identif ies the
vendor of the user device (assigned by USB Implementer ’s Forum).
2013-2018 Microchip Technology Inc. DS00001922AB-page 31
USB4640/USB4640i
4.4.4.3 E0h: Product ID (LSB)
4.4.4.4 E1h: Product ID (MSB)
4.4.4.5 E2h: Device ID (LSB)
4.4.4.6 E3h: Device ID (MSB)
4.4.4.7 E4h: Configuration Data Byte 1 (CFG_DAT_BYT1)
Bit Name Description
7:0 PID_LSB Least Signi ficant Byte of the Product ID: a unique 16-bi t value that id entifies a
particular product (vendor assigned).
Bit Name Description
7:0 PID_MSB Most Significant Byte of the Product ID. a unique 16-bit val ue that iden tifies a
particular product (vendor assigned).
Bit Name Description
7:0 DID_LSB Least Significant Byte of the Device ID: a 16-bit device release number in
BCD (binary coded decimal) format.
Bit Name Description
7:0 DID_MSB Most Significant Byte of the Device ID: a 16-bit device release number in BCD
format.
Bit Name Description
7 SELF_BUS_PWR Self-Powered or Bus-Powered: Selects between self-powered and bus-
powered operation.
The hub is either self-pow ered (draws less than 2 mAor bu s-powered (limited
to 100 mA maximum power prior to being configured by the host controller).
When configured as a bu s-powere d device , the Micro chip hub con sumes less
than 100 mA of current prior to being configured. After configuration, the bus-
powered hub (along with all associated hub circuitry, any embedded devices
if part of a compound device, and 100 mA per externally available downstream
port) must consume no more than 500 mA of current. The current
consumption is system dependent, and the USB 2.0 specifications must not
be violated.
When configured as a self-powered device, <1 m A of current is consumed
and all ports are available, with each port being capable of sourcing 500 mA
of current.
0 : Bus-powered operation
1 : Self-powered operation
6 rsvd
2:1 CURRENT_SNS Over-Current Sense
Selects current sensing on a port-by-port basis, all ports ganged, or none (only
for bus-powered hubs). The ability to sup port current sensing on a pe r port or
ganged basis is dependent upon the hardware implementation.
00 : Ganged sensing (all ports together)
01 : individual (port-by-port)
1x : over-current sensing not suppo rted (must only be used with bus-powered
configurations)
USB4640/USB4640i
DS00001922AB-page 32 2013-2018 Microchip Technology Inc.
4.4.4.8 E5 h: Co nf igu ra tio n Da ta Byte 2 (CFG_DAT_BYT2)
4.4.4.9 E6 h: Co nf igu ra tio n Da ta Byte 3 (CFG_DAT_BYT3)
0 PORT_PWR Port Power Switching
Enables power switching on all ports simultaneously (ganged), or port power
is individually switched on and off on a port-by-port basis (individual). The
ability to support power ena bling on a port or ganged basis is dependent upon
the hardware implementation.
0 : ganged switching (all ports together)
1 : individual port-by-port switching
Bit Name Description
7:6 rsvd
5:4 OC_TIMER OverCurrent Timer: over-current timer delay
00 : 50 ns
01 : 100 ns
10 : 200 ns
11 : 400 ns
3 COMPOUND Compound Device: allows OEM to indicate that the hub is part of a compound
device (per the USB 2.0 Specification). The applicable port(s) must also be
defined as having a “non-removable device”.
When configured via strapping options, declaring a port as non-removable
automatically causes th e hub controller to report that it is part of a compound
device.
0 : no
1 : yes, the hub is part of a compound device
2:0 rsvd
Bit Name Description
7:4 rsvd
3 PRTMAP_EN Port Mapping Enable: selects the method used by the hub to assign port
numbers and disable ports.
0 : Standard Mode. Strap opt ions or the following registers ar e used to define
which ports are enabled, and the ports are mapped as port ‘n’ on the hub is
reported as port ‘n’ to the host, unless one of the ports is disabled, then the
higher numbered ports are remapped in order to report contiguous port
numbers to the host.
Register 300Ah: Port disable for self-powered operation (Reset = 0x00)
Register 300Bh: Port disable for bus-powered operation (Reset = 0x00)
1 : Port Map mode. The mode enables remapping via the registers defined
below.
Register 30FBh: Port Map 12 (Reset = 0x00)
Register 30FCh: Port Map 3 (Reset = 0x00)
2:0 rsvd
Bit Name Description
2013-2018 Microchip Technology Inc. DS00001922AB-page 33
USB4640/USB4640i
4.4.4.10 E7h: Non-Removable Device
4.4.4.11 E8h: Port Disable For Self -Po w ere d Op er ation
Bit Byte Name Description
7:0 NR_DEVICE Indicates which port(s) include non-removable devices.
0 : Port is removable
1 : Port is non-removable
Informs the host if one of the active ports has a permanent device that is
undetachable from the hub. The device must provide its own descriptor data.
When using the internal default option, NON_REM[1:0] designates the
appropriate ports as being non-removable.
Bit 7 : rsvd
Bit 6 : rsvd
Bit 5 : rsvd
Bit 4 : rsvd
Bit 3 : controls physical port 3
Bit 2 : controls physical port 2
Bit 1 : controls physical port 1
Bit 0 : rsvd
Note: Bit 1 must be set to a 1 by the firmware for proper identification of
the card reader as a non-removable device.
Bit Byte Name Description
7:0 PORT_DIS_SP Disables 1 or more ports.
0 : port is available
1 : port is disabled
During self-powered operation this register selects the ports which will be
permanently disabled. The ports are unavailable to be enabled or enumerated
by a host controller. The ports can be disabled in any order sin ce the internal
logic will automatically report the correct number of enabled ports to the USB
host and will reorder the active ports in order to ensure proper function.
Bit 7 : rsvd
Bit 6 : rsvd
Bit 5 : rsvd
Bit 4 : rsvd
Bit 3 : controls physical port 3
Bit 2 : controls physical port 2
Bit 1 : controls physical port 1
Bit 0 : rsvd
USB4640/USB4640i
DS00001922AB-page 34 2013-2018 Microchip Technology Inc.
4.4.4.12 E9h: Port Disable For Bus-Powe re d Op er a tion
4.4.4.13 EAh: Max Power For Self-Powered Operation
4.4.4.14 EBh: Max Power For Bus-Powered Operation
4.4.4.15 ECh: Hub Controller Max Current For Self-Powered Operation
Bit Byte Name Description
7:0 PORT_DIS_BP Disables 1 or more ports.
0 : port is available
1 : port is disabled
During self-powered operation, this register selects the ports which will be
permanently disabled. The ports are unavailable to be enabled or enumerated
by a host controller. The ports can be disabled in any order, the internal logic
will automa tically report the correct numb er of enabled ports to the USB host
and will reorder the active ports in order to ensure proper function.
When using the interna l default opt ion, PRT_DIS[1:0] disable th e appropriate
ports.
Bit 7 : rsvd
Bit 6 : rsvd
Bit 5 : rsvd
Bit 4 : rsvd
Bit 3 : controls physical port 3
Bit 2 : controls physical port 2
Bit 1 : controls physical port 1
Bit 0 : rsvd
Bit Byte Name Description
7:0 MAX_PWR_SP Value in 2 mA increments that the hub consumes when operating as a self-
powered hub. This value includes the hub silicon along with the combined
power consumption of all associated circuitry on the board. This value also
includes the power consumption of a permanently attached peripheral if the
hub is configured as a compound device, and the embedded peripheral
reports 0 mA in its descriptors.
Note: Per USB 2.0 Specification: this value cannot exceed 100 mA.
Bit Byte Name Description
7:0 MAX_PWR_BP Value in 2 mA increments that the hub consumes when operating as a bus-
powered hub. This value includes the hub silicon along with the combined
power consumption of all associated circuitry on the board. This value also
includes the power consumption of a permanently attached peripheral if the
hub is configured as a compound device, and the embedded peripheral
reports 0 mA in its descriptors.
Bit Byte Name Description
7:0 HC_MAX_C_SP Value in 2 mA increments that the hub consumes when operating as a self-
powered hub. This value includes the hub silicon along with the combined
power consumption of all associated circuitry on the board. This value does
NOT include the power consumption of a permanently attached peripheral if
the hub is configured as a compound device.
Note: Per USB 2.0 Specification: this value cannot exceed 100 mA.
A value of 50 (decimal) indicates 100 mA, which is the default value.
2013-2018 Microchip Technology Inc. DS00001922AB-page 35
USB4640/USB4640i
4.4.4.16 EDh: Hub Controller Max Current For Bus-Powered Operation
4.4.4.17 EEh: Power-On Time
4.4.4.18 EFh: Boost_Up
4.4.4.19 F0h: Boost_3:0
Bit Byte Name Description
7:0 HC_MAX_C_BP Value in 2 mA increments that the hub consumes when operating as a bus-
powered hub. This value will i nclude the hub silicon alon g with the combined
power consumption of all associated circuitry on the board. This value will
NOT include the power consumption of a permanently attached peripheral if
the hub is configured as a compound device.
A value of 50 (decimal) would indicate 100 mA, which is the default value.
Bit Byte Name Description
7:0 PWR_ON_TIME The length of time that it takes (in 2 ms intervals) from the time the host
initiated power-on sequ ence begins on a port until power is adequat e on that
port. If the host requests the power-on time, the system software uses this
value to determine how long to wait before accessing a powered-on port.
Bit Name Description
7:2 rsvd
1:0 BOOST_IOUT USB electrical signaling drive strength boost bit for the upstream port A.
00 : Normal electrical drive strength - no boost
01 : Elevated electrical drive strength - low (approximately 4% boost)
10 : Elevated electrical drive strength - medium (approximately 8% boost)
11 : Elevated electrical drive strength - high (approximately 12% boost)
Note: Boost could result in non-USB compliant parameters. Therefore, a
value of 00 should be implemented unless specific implementation
issues require additional signal boosting to correct for degraded USB
signaling levels.
Bit Name Description
7:6 rsvd
5:4 BOOST_IOUT_3 Upstream USB electrical signaling drive strength boost bit for downstream
port 3.
00 : normal electrical drive strength - no boost
01 : elevated electrical drive strength - low (approximately 4% boost)
10 : elevated electrical drive strength - medium (approximately 8% boost)
11 : elevated electrical drive strength - high (approximately 12% boost)
3:2 BOOST_IOUT_2 Upstream USB electrical signaling drive strength boost bit for downstream
port 2.
00 : normal electrical drive strength - no boost
01 : elevated electrical drive strength - low (approximately 4% boost)
10 : elevated electrical drive strength - medium (approximately 8% boost)
11 : elevated electrical drive strength - high (approximately 12% boost)
Note: Boost could result in non-USB compliant parameters. Therefore, a
value of 00 should be implemented unless specific implementation
issues require additional signal boosting to correct for degraded USB
signaling levels.
1:0 rsvd Always read as 0
USB4640/USB4640i
DS00001922AB-page 36 2013-2018 Microchip Technology Inc.
4.4.4.20 F1h: Port Swap
4.4.4.21 F2h: Port Map 12
Bit Byte Name Description
7:0 PRT_SWP Port Swap: swaps the upstream and downstream USB DP and DM pins for
ease of board routing to devices and connectors.
0 : USB D+ functionality is associated with t he DP pin, and D- functionality is
associated with the DM pin.
1 : USB D+ functionality is associat ed with the DM pin, and D- fun ctionalit y is
associated with the DP pin.
Bit 7 : rsvd
Bit 6 : rsvd
Bit 5 : rsvd
Bit 4 : rsvd
Bit 3 : controls physical port 3
Bit 2 : controls physical port 2
Bit 1 : rsvd
Bit 0 : controls physical port 0
Bit Byte Name Description
7:0 PRTM12 PortMap Register for Ports 1 and 2: when a hub is enumerated by a USB host
controller, the hub is only permitted to report how many ports it has; the hub
is not permitted to select a numerical range or assignment. The host controller
will number the downstream ports of the hub starting with the number 1, up
to the number of ports that the hub reports having.
The host's port number is called the Logical Port Number and the physical
port on the hub is the Physical Port Number. When mapping mode is enabled
(see PORTMAP12.PRTMAP_EN) the hub's downstream port numbers can be
mapped to different logical port numbers (assigned by the host).
Note: Contiguous logical port numbers must be implemented, starting from
number 1 up to the maximum number of enabled ports. This ensures
that the hub's ports are numbered in accordance with the way a host
will communicate with the ports.
TABLE 4-5: PORT MAP REGISTER FOR PORTS 1 AND 2
Bit [7:4] 0000 Physical port 2 is disabled
0001 Physical port 2 is mapped to logical port 1
0010 Physical port 2 is mapped to logical port 2
0011 Physical port 2 is mapped to logical port 3
0100
to
1111
Illegal; do not use
Bit [3:0] 0000 Physical port 1 is disabled
0001 Physical port 1 is mapped to logical port 1
0010 Physical port 1 is mapped to logical port 2
0011 Physical port 1 is mapped to logical port 3
0100
to
1111
Illegal; do not use
2013-2018 Microchip Technology Inc. DS00001922AB-page 37
USB4640/USB4640i
4.4.4.22 F3h: Port Map 3
4.4.4.23 F4h-: Reserved
4.4.4.24 F7h-FBh: Not Applicable
Bit Byte Name Description
Bit Byte Name Description
7:0 PRTM3 PortMap Register for Ports 1 and 2: when a hub is enumerated by a USB host
controller, the hub is only permitted to report how many ports it has; the hub
is not permitted to select a numerical range or assignment. The host controller
will number the downstream ports of the hub starting with the number 1, up
to the number of ports that the hub reports having.
The host's port number is called the Logical Port Number and the physical
port on the hub is the Physical Port Number. When mapping mode is enabled
(see PORTMAP12.PRTMAP_EN: Configuration Data Byte 3) the hub's
downstream port numbers ca n be remapped to different logical port numbers
(assigned by the host).
Note: Contiguous logical port numbers must be implemented, starting from
number 1 up to the maximum number of enabled ports. This ensures
that the hub's ports are numbered in accordance with the way a host
will communicate with the ports.
Byte Byte Name Description
6:0 rsvd
7:0 N/A
TABLE 4-6: PORT MAP REGISTER FOR PORT 3
Bit [7:4] 0000 rsvd
0001 rsvd
0010 rsvd
0011 rsvd
0100
to
1111
Illegal; do not use
Bit [3:0] 0000 Physical port 3 is disabled
0001 Physical port 3 is mapped to logical port 1
0010 Physical port 3 is mapped to logical port 2
0011 Physical port 3 is mapped to logical port 3
0100
to
1111
Illegal; do not use
USB4640/USB4640i
DS00001922AB-page 38 2013-2018 Microchip Technology Inc.
4.4.4.25 FCh-FFh: Non-Volatile Storage Signature
4.4.5 INTERNAL FLASH MEDIA CONTROLLER EXTENDED CONFIGURATIONS
Enable registers 100h-17Fh by setting bit 7 of bmAttribute.
4.4.5.1 100h-106h: Combo LUN 0 Identifier String
4.4.5.2 107h-17Bh: Not Applicable
4.4.5.3 17Ch -17Fh: Non-Volatile Storage Signature for Extended Configuration
4.4.6 I2C EEPROM
The I2C EEPROM interface implements a subset of the I2C Master Specification (refe r to I2C-Bus Specification [6] for
I2C bus protocols). The device’s I2C EEPROM interface is designed to attach to a single dedicated I 2C EEPROM, and
it conforms to the Standard-mode I2C Specification (100 kbps transfer rate and 7-bit addressing) for protocol and elec-
trical compatibility.
Note: Extensions to the I2C Specification are not supported. The device acts as the master and generate s the
serial clock SCL, controls the bus access (determines which device acts as the transmitter and which
device acts as the receiver), and generates the START and STOP conditions.
4.4.6.1 Protocol Implementation
The hub will only access an EEPROM using the sequential read protocol as outlined in Chapter 8 of the Microchip
24AA02/24LC02B Data Sheet [8].
4.4.6.2 Pull-Up Resistor
The circuit board designer is required to place external pull-up resistors (10 k recommended) on the
SPI_DO/SDA/SPI_SPD_SEL and SPI_CLK/SCL lines (per SMBus 1.0 Specification [7] and EEPROM manufacturer
guidelines) to VDD33 in order to assure prop er operation.
4.5 Default Configuration Option
The Microchip device can be configured via its in ternal default configuration . Please see Section 4.3. 2 on page 21 for
specific details on how t o enable def au lt co nfi guratio n. Pl ease re fer t o Table 4-1 for the internal default values that are
loaded when this option is selected.
Byte Name Description
3:0 NVSTORE_SIG This signature is used to verify the validity of the data in the first 256 bytes of
the configuration area. The signature must be set to ATA2 for
USB4640/USB4640i.
Byte Name Description
6:0 CLUN0_ID_STR If the device to LUN mapping bytes have configured this LUN to be a combo
LUN, then these strings will be used to identify the LUN rather than the device
identifier strings.
Byte Name Description
116:0 N/A
Byte Name Description
3:0 NVSTORE_SIG2 This signature is used to verify the validity of the data in the upper 256 bytes if
a 512 byte EEPROM is used, otherwise this bank is a read-only configuration
area. The signature must be set to ecf1.
2013-2018 Microchip Technology Inc. DS00001922AB-page 39
USB4640/USB4640i
4.5.1 EXTERNAL HARDWARE NRESET
A valid hardware reset is defined as assertion of nRESET for a minimum of 1 s after all power supplies are within oper-
ating range. While reset is asserted, the device (and its associated external circuitry) consumes less than 500 A o f
current.
Assertion of nRESET (external pin) causes the fo llo w i ng :
1. All downstream ports are disabled and PRTCTL power to downstream devices is removed
2. The PHYs are disabled and the differential pairs will be in a high-impedance state
3. All transactions immediately terminate; no states are saved
4. All internal registers return to the default state (in most cases, 00h)
5. The external crystal oscillator is halted
6. The PLL is halted
4.5.1.1 nRESET for EEPROM Configuration
FIGURE 4-1: NRESET TIMING FOR EEPROM MODE
t1 t2 t4 t5 t6 t7
nRESET
VSS
Hardware
reset asserted
Device
Recovery/
Stabilization
8051 S ets
Configuration
Registers Attach USB
Upstream USB Reset
recovery Idle Sta rt co m p letion
request response
t3
Note: All power supplies must have reac hed the operating levels mandated in Sect ion 6.0 on pa ge 43, prior to
(or coincident with) the assertion of nRESET.
4.5.2 USB BUS RESET
In response to the upstream port signaling a reset to the device, the device does the following:
1. Sets default address to 0
2. Sets configuration to: Unconfigured
TABLE 4-7: NRESET TIMING FOR EEPROM MODE
Name Description MIN TYP MAX Units
t1 nRESET asserted 1 sec
t2 Device recovery/stabilization 500 sec
t3 8051 programs device configuration 20 50 msec
t4 USB attach (Note) 100 msec
t5 Host acknowledges attach and signals USB reset 100 msec
t6 USB idle Undefined msec
t7 Completion time for requests (with or without data
stage) 5msec
USB4640/USB4640i
DS00001922AB-page 40 2013-2018 Microchip Technology Inc.
3. Negates PRTCTL[3:2] to all downstream ports
4. Clears all TT buffers
5. Moves device from suspended to active (if suspended)
6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence
Note: The device does not propagate the upstream USB reset to downstream devices.
The host then configures the device and the device’s downstream port devices in accordance with the USB 2.0 Speci-
fication.
2013-2018 Microchip Technology Inc. DS00001922B-page 41
USB4640/USB4640i
5.0 AC SPECIFICATIONS
5.1 Oscillator/Crystal
Parallel Resonant, Fund amental Mode, 24 MHz 350 ppm.
FIGURE 5-1: TYPICAL CRYSTAL CIRCUIT
TABLE 5-1: CRYSTAL CIRCUIT LEGEND
Symbol Description In Accordance With
FIGURE 5-2: CAPACITANCE FORMULAS
C1 = 2 x (CL – C0) – CS1
C2 = 2 x (CL – C0) – CS2
Note 5-1 C0 is usually included (subtracted by the crystal manufacturer) in the specification for CL and should
be set to ‘0’ for use in the calculation of the capacitance formulas in Figure 5-2, "Capacitance
Formulas". Howeve r, the PCB may present a parasitic capacitance between XTAL1 and XTAL2. For
an accurate calculation of C1and C2, take the parasitic capacitance between traces XTAL1 and
XTAL2 into account.
Note 5-2 Each of these capacitance values is typically approximately 18 pF.
C0Crystal shunt capacitance Crystal manufacturer’s specification (See Note 5-1)
CLCrystal load capacitance
CBTotal board or trace capacitance OEM board design
CSStray capacitance Microchip IC and OEM board design
CXTAL XTAL pin input capacitance Microchip IC
C1Load capacitors installed on OEM
board Calculated values based on Figure 5-2, "Capacitance
Formulas" (See Note 5-2)
C2
USB4640/USB4640i
DS00001922B-page 42 2013-2018 Microchip Technology Inc.
5.2 Ceramic Resonator
24 MHz 350 ppm
FIGURE 5-3: CERAMIC RESONATOR USAGE WITH MICROCHIP IC
5.3 External Clock
50% Duty cycle 10%, 24 MHz 350 ppm, Jitter < 100 ps rms.
The external clock is recommended to conform to the signaling level designated in the JESD76-2 Specification on 1.8 V
CMOS Logic. XTAL2 should be treated as a no connect.
5.3.1 I2C EEPROM
Frequency is fixed at 58.6 kHz 20%
5.3.2 USB 2. 0
The Microchip device conforms to all voltage, power, and timing characteristics and specifications as set forth in the
USB 2.0 Specification. Please refer to the USB 2.0 Specification fo r more information.
2013-2018 Microchip Technology Inc. DS00001922B-page 43
USB4640/USB4640i
6.0 DC PARAMETERS
6.1 Maximum Ratings
Parameter Symbol MIN MAX Units Comments
Note 1: Stresses above the specified parameters could cause permanent damage to the device. This is a stress rat-
ing only . Therefore, functional operation of the device at any condition above those indicated in the operation
sections of this specification are not implied.
2: When powering this device from laboratory or system power supplies, it is important that the absolute max-
imum ratings not be exceeded or de vice fa ilure can result. Some power supplies exhib it volta ge spikes on
their outputs when the AC power is switched on or off. In addition, voltage tr ansient s on the AC powe r line
may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
Storage
Temperature TSTOR -55 150 °C
Lead
Temperature °C Refer to JEDEC Specification
J-STD-020D [5]
1.2 V supply
voltage VDD12 -0.5 1.5 V
3.3 V supply
voltage VDD33 -0.5 4.0 V
Voltage on
USB+ and
USB- pins
-0.5 (3.3 V supply voltage + 2) 6V
Voltage on
CRD_PWR -0.5 VDD33 + 0.3 V When internal power FET
operation of these pins are
enabled, these pins may be
simultaneously shorted to
ground or any voltage up to
3.63 V indefinitely, without
damage to the device as long
as VDD33 is less than 3.63 V
and TA is less than 70oC.
Voltage on any
signal pin -0.5 VDD33 + 0.3 V
Voltage on
XTAL1 -0.5 3.6 V
Voltage on
XTAL2 -0.5 2.0 V
USB4640/USB4640i
DS00001922B-page 44 2013-2018 Microchip Technology Inc.
6.2 Operating Conditions
Parameter Symbol MIN MAX Units Comments
FIGURE 6-1: SUPPLY RISE TIME MODEL
t10%
10%
90%
Voltage tRTxx
t90% Time
100%
3.3 V
VSS
VDD33
90%
100%
1.2 V
VDD12
Commercial
USB4640
Operating Temperature
TA0 70 °C Ambient temperature in still air.
Industrial
USB4640i
Operating Temperature
TA-40 85 °C Ambient temperature in still air.
1.2 V suppl y voltage VDD12 1.1 1. 3 V The ripple on VDD12 must be less
than 50 mV peak to peak.
1.2 V supply rise time tRT12 0400s Under all conditions the voltage on
the 1.2 V supply must be below the
3.3 V supply. (Figure 6-1)
3.3 V supply voltage VDD33 3.0 3.6 V A 3.3 V regulator with an output
tolerance of 1% must be used if
the output of the internal power
FET’s must support a 5%
tolerance.
3.3 V supply rise time tRT 0400s(Figure 6-1)
Voltage on
USB+ and USB- pins -0.3 5.5 V If any 3.3 V supply voltage drops
below 3.0 V, then the MAX
becomes:
(3.3 V supply voltage) + 0.5 5.5
Voltage on any signal
pin -0.3 VDD33 V
Voltage on XTAL1 -0.3 2.0 V
Voltage on XTAL2 -0.3 2.0 V
2013-2018 Microchip Technology Inc. DS00001922B-page 45
USB4640/USB4640i
6.3 DC Electrical Characteristics
Parameter Symbol MIN TYP MAX Units Comments
I, IPU, IPD Type Input Buffer
Low Input Level VILI 0.8 V TLL Levels
High Input Level VIHI 2.0 V
Pull Down PD 72 A
Pull Up PU 58 A
IS Type Input Buffer
Low Input Level VILI 0.8 V TTL Levels
High Input Level VIHI 2.0 V
Hysteresis VHYSI 420 mV
ICLK Input Buffer
Low Input Level VILCK 0.5 V
High Input Level VIHCK 1.4 V
Input Leakage IIL -10 +10 AV
IN = 0 to VDD33
Input Leakage
(All I and IS buffers)
Low Input Leakage IIL -10 +10 AV
IN = 0
High Input Leakage IIH -10 +10 AV
IN = VDD33
I/O6, I/OD6PU Type Buffers
Low Output Level VOL 0.4 V IOL = 6 mA @
VDD33 = 3.3 V
High Output Level VOH VDD33
-0.4 VI
OH = -6 mA @
VDD33 = 3.3 V
Output Leakage IOL -10 +10 AV
IN = 0 to VDD33
(Note 6-1)
Pull Down PD 72 A
Pull Up PU 58 A
O8, O8PD, 08PU, I/O8, I/O8PD, and
I/O8PU Type Buffers
Low Output Level VOL VI
OL = 8 mA @
VDD33 = 3.3 V
High Output Level VOH VDD33
- 0.4 VI
OH = -8 mA @
VDD33 = 3.3 V
Output Leakage IOL -10 +10 AV
IN = 0 to VDD33
(Note 6-1)
Pull Down PD 72 A
Pull Up PU 58 A
O12, I/O12, and I/O12PD
Type Buffers
Low Output Level VOL 0.4 V IOL = 12 mA @
VDD33 = 3.3 V
High Output Level VOH VDD33
- 0.4 VI
OH = -12 mA @
VDD33 = 3.3 V
Output Leakage IOL -10 +10 AV
IN = 0 to VDD33
(Note 6-1)
Pull Down PD 72 A
Pull Up PU 58 A
USB4640/USB4640i
DS00001922B-page 46 2013-2018 Microchip Technology Inc.
Note 6-1 Output leakage is measured with the current pins in high impedance.
Note 6-2 See the USB 2.0 Specification, Chapter 7, for USB DC electrical characteristics
Note 6-3 RBIAS is a 3.3 V tolerant analog pin.
Note 6-4 Output current range is controlled by program software. The software disables the FET during short
circuit condition.
Note 6-5 Refer to the High-Speed Inter-Chip USB Electrical Specification Revision 1.0 [2].
Note 6-6 Typical and maximum values were characterized using the following temperature ranges: The
USB4640 supports the commercial temperature range of 0°C to +70°C.
The USB4640i supports the industrial temperature range of -40°C to +85°C.
IO-U (Note 6-2)
I-R (Note 6-3)
I/O200 Integrated Power FET for
CRD_PWR
High Output Current IOUT 200 mA VdropFET = 0.46 V
Low Output Current (Note 6-4)I
OUT 100 mA VdropFET = 0.23 V
On Resistance (Note 6-4)R
DSON 2.1 IFET = 70 mA
Output Voltage Rise Time tDSON 800 sC
LOAD = 10 F
Integrated Power FET Set to 100 mA
Output Current (Note 6-4)I
OUT 100 mA VdropFET = 0.22 V
Short Circuit Current Limit ISC 140 mA VoutFET = 0 V
On Resistance (Note 6-4)R
DSON 2.1 IFET = 70 mA
Output Voltage Rise Time tDSON 800 sC
LOAD = 10 F
Integrated Power FET Set to 200 mA
Output Current (Note 6-4)I
OUT 200 mA VdropFET = 0.46 V
Short Circuit Current Limit ISC 181 mA VoutFET = 0 V
On Resistance (Note 6-4)R
DSON 2.1 IFET = 70 mA
Output Voltage Rise Time tDSON 800 sC
LOAD = 10 F
Supply Current Unconfigured (Note 6-6)
USB4640 ICCINTHS 58 60 mA
USB4640i ICCINTHS 58 62 mA
Supply Current Configured
1 downstream port (Note 6-6)
USB4640 IHCH1 155 160 mA
USB4640i IHCH1 155 165 mA
Supply Current Configured
Each additional downstream port (Note 6-6)
USB4640 30 35 mA
USB4640i 30 40 mA
HSIC_DAT, HSIC_STROBE
Driver Impedance ID40 46 60 (Note 6-5)
Supply Current Suspend (Note 6-6)
USB4640 ICSBY 210 375 µA
USB4640i ICSBY 210 450 µA
Supply Current Reset (Note 6-6)
USB4640 IRST 220 400 µA
USB4640i IRST 220 500 µA
Parameter Symbol MIN TYP MAX Units Comments
2013-2018 Microchip Technology Inc. DS00001922B-page 47
USB4640/USB4640i
6.4 Capacitance
TA = 25°C; fc = 1 MHz; VDD33 = 3.3 V
TABLE 6-1: PIN CAPACITANCE
Parameter Symbol Limits Unit Test Condition
MIN TYP MAX
Clock Input Capacitance CXTAL 2 pF All pins (except USB pins and
pins under test) a re tied to AC
ground.
Input Capacitance CIN 10 pF
Output Capacitance COUT 20 pF
USB4640/USB4640i
DS00001922B-page 48 2013-2018 Microchip Technology Inc.
7.0 TEMPERATURE SPECIFICATIONS
TABLE 7-1: TEMPERATURE SPECIFICATIONS
Parameter Symbol Limitations Unit Test Conditions
MIN TYP MAX
TEMPERATURE SPECIFICATIONS
Operating Junct ion Temperature TJ0 — +125 °C
Ambient Temperature Commercial TA0 — +70 °C Ambient temperature in still air
Industrial TA–40 —+85 °C Ambient temperature in still air
Storage Temperature TS–55 —+150 °C
PACKAGE THERMAL RESISTANCE
48-pin QFN (7 X 7) 0 m/s
JA
—27 —°C/W
1 m/s —24 —°C/W
2.5 m/s —21 —°C/W
48-pin QFN (7 X 7) (Junction to Case) JC —2.1 —°C/W
48-pin QFN (7 X 7) (Junction to Board) JB —15 —°C/W
2013-2018 Microchip Technology Inc. DS00001922B-page 49
USB4640/USB4640i
8.0 PACKAGE SPECIFICATIONS
FIGURE 8-1: USB4640/USB4640i 48-Pin QFN, 7 x 7mm Body, 0.4mm Lead Length
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
USB4640/USB4640i
DS00001922B-page 50 2013-2018 Microchip Technology Inc.
FIGURE 8-1: USB4640/USB4640i 48-Pin QFN, 7 x 7mm Body, 0.4mm Lead Length (CONTINUED)
2013-2018 Microchip Technology Inc. DS00001922B-page 51
USB4640/USB4640i
8.1 Tape and Reel Specifications
FIGURE 8-2: 48-PIN PACKAGE TAPE SPECIFICATIONS
10 mm
DIRECTION OF UNREELING
A
A
SECTION A — A
7.25
1.10
B0
K0
A0
B0
K0
7.25
1.00
7.35
1.20
MIN NOM MAX
COVER TAPE
A0
W1
13.30
-
W1
T1
13.20
-
13.40
0.10
0.30
T1
4.00
7.50
12.00
1.75
16.00±0.3
2.00 Ø1.50
Ø1.50
7.257.25 7.35
FIGURE 8-3: 48-PIN PACKAGE REEL SPECIFICATIONS
USB4640/USB4640i
DS00001922B-page 52 2013-2018 Microchip Technology Inc.
2013- 2018 Microchip Technology Inc. DS00001922B-page 53
USB4640/USB4640i
APPENDIX A: ACRONYMS
ACK: Handshake packet (positive acknowledgment)
EOF: End of (micro) Frame
FM: Flash Media
FMC: Flash Media Controller
FS: Full-Speed Device
LS: Low-Speed Device
HS: Hi-Speed Device
I2C: Inter-Integrated Circuit1
MMC: MultiMediaCard
MS: Memory Stick
MSC: Memory Stick Controller
OCS: Over-current Sense
PHY: Physical Layer
PLL: Phase-Locked Loop
SD: Secure Digital
SDC: Secure Digital Controller
TXD: Transmit eXchange Data
UART: Universal Asynchronous Receiver-Transmitter
UCHAR: Unsigned Character
UINT: Unsigned Integer
1. I2C is a registered trademark of Philips Corporation.
USB4640/USB4640i
DS00001922B-page 54 2013-2018 Microchip Technology Inc.
APPENDIX B: REFERENCES
1. Universal Serial Bus Specification, Version 2.0, April 27, 2000 (12/7/2000 and 5/28/2002 Errata)
USB Implemente rs Fo ru m, In c. http://www.usb.org
2. USB 2.0 Supplement High-Speed Inter-Chip USB Electrical Specification Revision 1.0. 09/23/07.
USB Implemente rs Fo ru m, In c. http://www.usb.org/developers/docs/
3. HSIC ECN. May 25, 20 1 0
USB Implemente rs Fo ru m, In c. http://www.usb.org/developers/docs/
4. The Unicode Standard, Worldwide Character Encoding Version 4.0
The Unicode Consortium. http://www.unicode.org
5. JEDEC Specification J-STD-020D
JEDEC Global Standards for the Microelectronics Industry.http://www.jedec.org/standards-documents
6. I2C-Bus Specification Version 1.1
NXP (formerly a division of Philips). http://www.nxp.com/products/interface_control/i2c/
7. System Management Bus Specification, version 1.0
SMBus. http://smbus.org/specs/
8. Microchip 24AA02/24LC02B
Microchip Technology Inc. http://www.microchip.com/
2013-2018 Microchip Technology Inc. DS00001922B-page 55
USB4640/USB4640i
APPENDIX C: DATA SHEET REVISION HISTORY
TABLE C-1: REVISION HISTORY
Revision Section/Figure/Entry Correction
DS00001922B (11-14-18) Table 4-3 Changed “ATA2” to “ata2”
Section 4.4 “Internal Flash
Media Controller Extended
Configurations”
Removed subsection,“4.4.7 IN-CIRCUIT EEPROM
PROGRAMMING”
DS00001922A (05-01-15) Th roughout document GPIOs and SDIO support removed
REV A replaces previous SMSC version Rev. 1.3 (03-13-13)
USB4640/USB4640i
DS00001922B-page 56 2013-2018 Microchip Technology Inc.
NOTES:
2013-2018 Microchip Technology Inc. DS00001922B-page 57
USB4640/USB4640i
THE MICROCHIP WEBSITE
Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the website con-
tains the followi ng information:
•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
•General Technical Support – Frequently Asked Que stions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
•Business of M icr oc hi p – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip we bsite at www.microchip.com. Under “Support”, click on “Customer Cha nge Notifi -
cation” and follow the registration instructio ns.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance thro ugh several channels:
• Distributor or Representative
• Local Sales Of fice
• Field Application Engineer (F AE)
• Technical Support
Customers should contact their distributor, represent ative or field application engineer (FAE) for support. Loca l sales
offices are also available to help customers. A listi ng of sales offices and locati ons is inclu ded in the back of th is docu-
ment.
Techn ical support is available through the website at: http://www.microchip.com/support
USB4640/USB4640i
DS00001922B-page 58 2013-2018 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: USB4640, USB4640i
Temperature
Range: Blank = 0C to +70C (Extende d Commercial)
i= -40C to +85C (Industrial)
Package: HZH = 48-pin QFN
Tape and Reel
Option: Blank = Standard packaging (tray)
TR = T ape and Reel(1)
Examples:
a) USB4640-HZH-03
48-pin QFN, 7 x 7mm
RoHS Compliant Package, Tray
b) USB4640-HZH-03-TR
48-pin QFN, 7 x 7mm
RoHS Compliant Package, Tape & Reel
c) USB4640i-HZH-03
48-pin QFN, 7 x 7mm
RoHS Compliant Package, Tray
d) USB4640i-HZH-03-TR
48-pin QFN, 7 x 7mm
RoHS Compliant Package, Tape & Reel
PART NO. [X] XXX
PackageTemperature
Range
Device
[X](1)
Tape and Reel
Option
-
-
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not printed
on the device package. Check with your
Microchip Sales Of f ice fo r pa ckage availab ili ty
with the Tape & Reel option.
Reel size is 2,500.
2013-2018 Microchip Technology Inc. DS00001922B-page 59
Note the following deta ils of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code pro tection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-169 49:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, mi cr operi pherals, nonvola tile memory and
analog products. In additi on, Microchip ’ s qua lity syste m for t he design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELA TED TO THE INFORMA TION, INCLUDING BUT NOT LIMITED TO ITS COND ITION, QUALITY, PERFORMANCE,
MERCHANT ABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual propert y rig hts un le ss o therwise sta ted.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kle er, LANCheck, LINK MD, maXStylu s, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication,
CryptoAutomoti ve, Cr ypto Companio n, Cryp toCont rolle r, dsPICDEM, dsPICDEM.net, Dyna mic Average Matc hing , DAM, EC AN, Ethe rGREEN,
In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certif ied logo, MPLIB, MPLINK, MultiTRAK, NetDet ach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitch er, SuperSwitcher II, Total En durance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Sto rage Technology is a regi stered trademar k of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2018, Microchip Technology Incorp orated, All Rights Reserved.
ISBN: 978-1- 5224-3860-1
DS00001922B-page 60 2013-2018 Microchip Technology Inc.
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