MM74C373N_NL - Fairchild Semiconductor

October 1987

Revised January 2004

MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop

MM74C373 • MM74C374

3-STATE Octal D-Type Latch •

3-STATE Octal D-Type Flip-Flop

General Description

The MM74C373 and MM74C374 are integrated, comple-

mentary MOS (CMOS), 8-bit storage elements with 3-

STATE outputs. These outputs have been specially

designed to drive high capacitive loads, such as one might

find when driving a bus, and to have a fan out of 1 when

driving standard T TL. When a h igh logic le vel is applied to

the OUTPUT DISABLE input, all outputs go to a high

impeda nce stat e, r eg ard less o f wh at s i gna ls are pres ent at

the other inputs and the state of the storage elements.

The MM74C 373 is an 8-bit latch. When LATCH ENABLE is

high, the Q outputs will follow the D inputs. When LATCH

ENABLE goes low, data at the D inputs, which meets the

set-up and hold time requirements, will be retained at the

outputs until LATCH ENABLE returns high again.

The MM74C 3 74 is an 8-b i t, D-typ e, positive- edg e tri gg er ed

flip-flop. Data at the D inputs, meeting the set-up and hold

time req uirements, is transferre d to the Q outp uts on posi -

tive-going transitions of the CLOCK input.

Bot h the M M7 4C 373 a n d t h e MM74 C 37 4 ar e be i n g ass e m-

bled in 20-pin dual-in-line packages with 0.300” pin cen-

ters.

Features

■Wide supply voltage range: 3V to 15V

■High noise immunity: 0.45 VCC (typ.)

■Low power consu mp ti on

■TTL compatibility:

Fan out of 1driving standard TTL

■Bus driving capability

■3-STATE outputs

■Eight storage elements in one package

■Single CLOCK/LATCH ENABLE and OUTPUT DIS-

ABLE control inputs

■20-pin dual-in-line package with 0.300” centers takes

half the board space of a 24-pin package

Ordering Code:

Note 1: Devices also availab le in Tape and Reel. Specif y by append ing the suffix let t er “X” to th e ordering c ode.

Order Number Package Number Package Description

MM74C373M

(Note 1) M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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MM74C373 • MM74C374

Connection Diagrams

MM74C373

Top View

MM74C374

Top View

Truth Tables

MM74C373

L = LOW logic lev el

H = HIGH logic level

X = Irrel ev a nt

MM74C374



= LOW-to-HIGH logic level transition

Q = Preexisting output level

Hi-Z = High impedance output state

Output LATCH DQ

Disable ENABLE

LHHH

LHLL

LLXQ

H X X Hi-Z

Output Clock D Q

Disable



LLXQ

LHXQ

H X X Hi-Z

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MM74C373 • MM74C374

Block Diagrams

MM74C 3 73 (1 of 8 Latch es)

MM74C3 74 (1 of 8 Flip-Flo ps)

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MM74C373 • MM74C374

Absolute Maximum Ratings(Note 2)

Note 2: “Absolute Maximum Ratings” are those values beyond which the

safety of t he device ca nnot be guara nt eed. Ex cept f or “Operating Tempera-

ture Range” they a re not mean t to imply that the devices s hould be oper-

ated at these limits. The table of “Electrical Characteristics” provides

conditions for act ual devi c e operation.

DC Electrical Characteristi cs

Min/Max limits apply across temperature range unless otherwise noted

Note 3: These are peak output current capabilities. Continuous output current is rated at 12 mA max.

Voltage at Any Pin −0.3V to VCC + 0.3V

Operati ng Tem per atu re Rang e (TA)

MM74C373 −55°C to +125°C

Storage Temperature Range (TS)−65°C to +150°C

Power Dissipation

Dual-In-Line 700 mW

Small Out lin e 500 mW

Operati ng VCC Range 3V to 15V

Absolute Maximum VCC 18V

Lead Temperature (TL)

(Solder ing, 10 seco nds) 260°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

VIN(1) Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 8.0

VIN(0) Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0

VOUT(1) Logical “1” Output V ol tag e VCC = 5V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0

VOUT(0) Logical “0” Output V ol tag e VCC = 5V, IO = 10 µA0.5

VCC = 10V, IO = 10 µA1.0

IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA

IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

IOZ 3-STATE Leakage Current VCC = 15V, VO = 15V 0.005 1.0 µA

VCC = 15V, VO = 0V −1.0 −0.005

ICC Supply Current VCC = 15V 0.05 300 µA

CMOS/LPTTL INTERFACE

VIN(1) Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V

VIN(0) Logical “0” Input Voltage VCC = 4.75V 0.8 V

VOUT(1) Logical “1” Output V ol tag e VCC = 4.75V, IO = −360 µAV

CC − 0.4 V

VCC = 4.75V, IO = −1.6 mA 2.4

VOUT(0) Logical “0” Output V ol tag e VCC = 4.75V, IO = 1.6 mA 0.4 V

OUTPUT DRIVE (Short Circuit Current)

ISOURCE Output Source Current VCC = 5V, VOUT = 0V −12 −24 mA

TA = 25°C (Note 3)

ISOURCE Output Source Current VCC = 10V, VOUT = 0V −24 −48 mA

TA = 25°C (Note 3)

ISINK Output Sink Current VCC = 5V, VOUT = VCC 612 mA

(N-Channel) TA = 25°C (Note 3)

ISINK Output Sink Current VCC = 10V, VOUT = VCC 24 48 mA

(N-Channel) TA = 25°C (Note 3)

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MM74C373 • MM74C374

AC Electrical Characteristics (Note 4)

MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless other wise noted

Note 4: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Note 5: Capacitance is guaranteed by periodic testing.

Note 6: CPD determines the no load AC power co ns um ption of any C M OS devic e. For com plete expla nation se e F am ily Characterist ic s Applicat ion Note

AN-90.

Symbol Parameter Conditions Min Typ Max Units

tpd0, tpd1 Propagation Delay, VCC = 5V, CL = 50 pF 165 330

LATCH ENABLE to Output VCC = 10V, CL = 50 pF 70 140

VCC = 5V, CL = 150 pF 195 390

VCC = 10V, CL = 150 pF 85 170

tpd0, tpd1 Propagation Delay Data LATCH ENABLE = VCC

In to Output VCC = 5V, CL = 50 pF 155 310

VCC = 10V, CL = 50 pF 70 140

VCC = 5V, CL = 150 pF 185 370

VCC = 10V, CL = 150 pF 85 170

tSET-UP Minimum Set-Up Time Data In tHOLD = 0 ns

to CLOCK/LATCH ENABL E VCC = 5V 70 140 ns

VCC = 10V 35 70

fMAX Maximum LATCH ENABLE VCC = 5V 3.5 6.7 MHz

Frequency VCC = 10V 4.5 9.0

tPWH Minimum LATCH ENABLE VCC 5V 75 150 ns

Pulse W idth VCC = 10V 55 110

tr, tfMaximum LATCH ENABLE VCC = 5V NA µs

Rise and Fall Time VCC = 10V NA

t1H, t0H Propagation Delay OUTPUT RL = 10k, CL = 5 pF

DISABLE to High Impedance VCC = 5V 105 210 ns

State (from a Logic Level) VCC = 10V 60 120

tH1, tH0 P ropagation Delay OUTPUT RL = 10k, CL = 50 pF

DISABLE to Logic Level VCC = 5V 105 210 ns

(from High Impedance State) VCC = 10V 45 90

tTHL, tTLH Transition Time VCC = 5V, CL = 50 pF 65 130

VCC = 10V, CL = 50 pF 35 70

VCC = 5V, CL = 150 pF 110 220

VCC = 10V, CL = 150 pF 70 140

CLE Input Capacitance LE Input (Note 5) 7.5 10 pF

COD Input Capacitance OUTPUT DISABLE 7.5 10 pF

Input (Note 5)

CIN Input Capacitance Any Other Input (Note 5) 5 7.5 pF

COUT Output Capacitance High Impedance 10 15 pF

State (Note 5)

CPD Power Dissipation Capacitance Per Package (Note 6) 200 pF

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MM74C373 • MM74C374

AC Electrical Characteristics (Note 7)

MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted

Note 7: AC Parameters are guara nt eed by DC c orrelat ed testing.

Note 8: Capacita nce is guaranteed by periodic tes ti ng.

Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note

AN-90.

Symbol Parameter Conditions Min Typ Max Units

tpd0, tpd1 Propagation Delay, VCC = 5V, CL = 50 pF 150 300

CLOCK to Output VCC = 10V, CL = 50 pF 65 13 0

VCC = 5V, CL = 150 pF 180 360

VCC = 10V, CL = 150 pF 80 160

tSET-UP Minimum Set-Up Time Data In tHOLD = 0 ns

to CLOCK/LATCH ENABL E VCC = 5V 70 140 ns

VCC = 10V 35 70

tPWH, tPWL Minimum CLOCK Pulse Width VCC = 5V 70 140 ns

VCC = 10V 50 100

fMAX Maximum CLOCK Frequency VCC = 5V 3.5 7.0 MHz

VCC = 10V 5 10

t1H, t0H Propagation Delay OUTPUT RL = 10k, CL = 50 pF

DISABLE to High Impedance VCC = 5V 105 210 ns

State (from a Logic Level) VCC = 10V 60 120

tH1, tH0 Propagation Delay OUTPUT RL = 10k, CL = 50 pF

DISABLE to Logic Level VCC = 5V 105 210 ns

(from High Impedance State) VCC = 10V 45 90

tTHL, tTLH Transition Time VCC = 5V, CL = 50 pF 65 130

VCC = 10V, CL = 50 pF 35 70

VCC = 5V, CL = 150 pF 110 220

VCC = 10V, CL = 150 pF 70 140

tr, tfMaximum CLOCK Rise VCC = 5V 15 >2000 µs

and Fall Time VCC = 10V 5 >2000

CCLK Input Capacitance CLOCK Input (Note 8) 7.5 10 pF

COD Input Capacitance OUTPUT DISABLE 7.5 10 pF

Input (Note 8)

CIN Input Capacitance Any Other Input (Note 8) 5 7.5 pF

COUT Output Capacitance High Impedance 10 15 pF

State (Note 8)

CPD Power Dissipation Capacitance Per Package (Note 9) 250 pF

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MM74C373 • MM74C374

Typical Performance Characteristics

MM74C373

Propagation Delay, LATCH ENABLE to Output

vs Load Capacitance

MM74C373

Propagation Delay, Data In to Output

vs Load Capacitance

MM74C373

Propagation Delay, CLOCK to Output

vs Load Capacitance

MM74C373, MM74C374

Change in Propagation Delay

per pF of Load Capacitance

(∆tPD/pF) vs Power Supply Voltage

MM74C373, MM74C374

Output Sink Current vs VOUT

MM74C373, MM74C374

Source Current vs VCC − VOUT

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MM74C373 • MM74C374

Typical Applications

Data Bus Interfacing Element

Simple, Latching, Octal, LED Indicator

Driver with Blanking for Use as Data Display,

Bus Mo ni to r, µP Front Panel Display, Etc.

3-STATE Test Circui ts and Switching T ime Waveforms

t1H, tH1

t1H, CL = 5 pF

tH1, CL = 50 pF

t0H, tH0

t0H, CL = 5 pF

tH0, CL = 50 pF

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MM74C373 • MM74C374

Switching Time Waveforms

MM74C373

Output D is able = GND

MM74C374

Output D is able = GND

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MM74C373 • MM74C374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

11 www.fairchildsemi.com

MM74C373 • MM74C374 3-STATE Octal D-Type Lat ch • 3-STATE Octal D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does not assume an y responsibility for u se of any circuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

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to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.