TCA9617B
I C slave devices
2
SCLA SCLB
EN
VCCA
GND
I C or SMBus
Master
2
(e.g. Processor)
VCCB
SDAA SDAB
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TCA9617B
SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
TCA9617B Level-Translating FM+ I
2
C Bus Repeater
1 Features 2 Applications
1• Two-Channel Bidirectional I2C Buffer • Servers
• Support for Standard Mode, Fast Mode (400 kHz), • Routers (Telecom Switching Equipment)
and Fast Mode+ (1 MHz) I2C Operation • Industrial Equipment
• Operating Supply Voltage Range of 0.8 V to 5.5 V • Products With Many I2C Slaves and/or Long PCB
on A-Side Traces
• Operating Supply Voltage Range of 2.2 V to 5.5 V 3 Description
on B-Side The TCA9617B is a BiCMOS dual bidirectional buffer
• Voltage-Level Translation From 0.8 V to 5.5 V and intended for I2C bus and SMBus systems. It can
2.2 V to 5.5 V provide bidirectional voltage-level translation (up-
• Footprint and Function Replacement for TCA9517 translation and down-translation) between low
• Active-High Repeater-Enable Input voltages (down to 0.8 V) and higher voltages (2.2 V
to 5.5 V) in mixed-mode applications. This device
• Open-Drain I2C I/O enables I2C and similar bus systems to be extended,
• 5.5-V Tolerant I2C and Enable Input Support without degradation of performance even during level
• Lockup-Free Operation shifting.
• Powered-Off High-Impedance I2C Bus Pins The TCA9617B buffers both the serial data (SDA)
• Support for Clock Stretching and Multiple Master and the serial clock (SCL) signals on the I2C bus,
Arbitration Across The Device allowing two buses of 550 pF to be connected in an
I2C application. This device can also be used to
• Latch-Up Performance Exceeds 100 mA Per isolate two halves of a bus for voltage and
JESD 78, Class II capacitance.
• ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A) Device Information(1)
– 1500-V Charged-Device Model (C101) PART NUMBER PACKAGE BODY SIZE (NOM)
TCA9617B VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA9617B
SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
www.ti.com
Table of Contents
9.1 Overview................................................................... 9
1 Features.................................................................. 19.2 Functional Block Diagram....................................... 10
2 Applications ........................................................... 19.3 Feature Description................................................. 10
3 Description............................................................. 19.4 Device Functional Modes........................................ 11
4 Simplified Schematic............................................. 110 Application and Implementation........................ 12
5 Revision History..................................................... 210.1 Application Information.......................................... 12
6 Pin Configuration and Functions......................... 310.2 Typical Application................................................ 12
7 Specifications......................................................... 311 Power Supply Recommendations ..................... 15
7.1 Absolute Maximum Ratings ..................................... 312 Layout................................................................... 16
7.2 ESD Ratings.............................................................. 312.1 Layout Guidelines ................................................. 16
7.3 Recommended Operating Conditions....................... 412.2 Layout Example .................................................... 16
7.4 Thermal Information.................................................. 413 Device and Documentation Support................. 17
7.5 Electrical Characteristics........................................... 513.1 Trademarks........................................................... 17
7.6 Timing Requirements................................................ 613.2 Electrostatic Discharge Caution............................ 17
7.7 Typical Characteristics.............................................. 613.3 Glossary................................................................ 17
8 Parameter Measurement Information .................. 714 Mechanical, Packaging, and Orderable
9 Detailed Description.............................................. 9Information........................................................... 17
5 Revision History
Changes from Original (December 2014) to Revision A Page
• Initial release of full version. .................................................................................................................................................. 1
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DGK PACKAGE
(TOP VIEW)
18
VCCA VCCB
45
GND EN
3 6
SDAA SDAB
27
SCLA SCLB
TCA9617B
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SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
6 Pin Configuration and Functions
Pin Functions
PIN DESCRIPTION
NAME NO.
EN 5 Active-high repeater enable input
GND 4 Supply ground
SCLA 2 I2C SCL line, A side. Connect to VCCA through a pull-up resistor.
SCLB 7 I2C SCL line, B side. Connect to VCCB through a pull-up resistor.
SDAA 3 I2C SDA line, A side. Connect to VCCA through a pull-up resistor.
SDAB 6 I2C SDA line, B side. Connect to VCCB through a pull-up resistor.
VCCA 1 A-side supply voltage (0.8 V to 5.5 V)
VCCB 8 B-side and device supply voltage (2.2 V to 5.5 V)
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCCB Supply voltage range –0.5 7 V
VCCA Supply voltage range –0.5 7 V
VIEnable input voltage range(2) –0.5 7 V
VI/O I2C bus voltage range(2) –0.5 7 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50
Continuous output current ±50 mA
IOContinuous current through VCC or GND ±100 mA
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCCA Supply voltage, A-side bus 0.8 VCCB V
VCCB Supply voltage, B-side bus 2.2 5.5 V
IOLA Low-level output current 30 mA
IOLB Low-level output current 0.1 30 mA
TAOperating free-air temperature –40 85 °C
7.4 Thermal Information TCA9617B
THERMAL METRIC(1) DGK UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 171.8
RθJC(top) Junction-to-case (top) thermal resistance 61.2
RθJB Junction-to-board thermal resistance 93.6 °C/W
ψJT Junction-to-top characterization parameter 7.9
ψJB Junction-to-board characterization parameter 91.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, .
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7.5 Electrical Characteristics
VCCB = 2.2 V to 5.5 V, GND = 0 V, TA= –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS VCCB MIN TYP MAX UNIT
VIK Input clamp voltage II= –18 mA 2.2 V to 5.5 V –1.2 V
IOL = 100 µA or 30 mA,
SDAB, SCLB 0.48 0.53 0.58
VILA = 0 V
VOL Low-level output voltage 2.2 V to 5.5 V V
SDAA, SCLA IOL = 30 mA 0.1 0.23
SDAA, SCLA 0.7 × VCCA 5.5
VIH High-level input voltage SDAB, SCLB 2.2 V to 5.5 V 0.7 × VCCB 5.5 V
EN 0.7 × VCCB 5.5
0.3 ×
SDAA, SCLA VCCA
VIL Low-level input voltage SDAB, SCLB 2.2 V to 5.5 V 0.4 V
0.3 ×
EN VCCB
Both channels low,
SDAA = SCLA = GND and
ICCA Quiescent supply current for VCCA IOLB =100 µA, or 2.2 V to 5.5 V 13 µA
SDAA = SCLA = open and
SDAB = SCLB = GND
Both Channels high,
SDAA = SCLA = VCCA +4.5 +7
B-side pulled up to VCCB with
pull-up resistors
ICCB Quiescent supply current 5.5 V mA
Both channels low,
SDAA = SCLA = GND, +5.7 +8.1
IOLB = 100 µA
VI= VCCB –1 +1
VI= 0.2 V, EN = 0 2.2 V to 5.5 V –10 +10
SDAB, SCLB VI= VCCB – 0.2 V –1 +1
VI= 5.5 V,VCCA = 0 V 0 V –10 +10
VI= VCCA –1 +1
IIInput leakage current μA
VI= 0.2 V, EN = 0 2.2 V to 5.5 V –10 +10
SDAA, SCLA VI= VCCA – 0.2 V –1 +1
VI= 5.5 V, VCCA = 0 V 0 V –10 +10
VI= VCCB –1 +1
EN VI= 0.2 V –25
CIInput capacitance EN VI= 3 V or 0 V 3.3 V 7
3.3 V 9
SCLA, SDAA VI= 3 V or 0 V 0 V 9 pF
CI/O Input/output capacitance 3.3 V 14
SCLB, SDAB VI= 3 V or 0 V 0 V 14
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TA= -40 C
TA= 25 C
TA= 85 C
Port B IOL (mA)
Port B VOL (V)
Port A IOL (mA)
Port A VOL (V)
TA= -40 C
TA= 25 C
TA= 85 C
TCA9617B
SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
www.ti.com
7.6 Timing Requirements
VCCA = 0.8 V to 5.5 V, VCCB = 2.2 V to 5.5 V, GND = 0 V, TA= –40°C to 85°C (unless otherwise noted)(1)(2)(3)
FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
SDAB, SCLB SDAA, SCLA 42 55 90
tPLH Propagation delay VCCB ≤3 V 61 88 137 ns
SDAA, SCLA SDAB, SCLB VCCB > 3 V 61 94 250
SDAB, SCLB SDAA, SCLA 69 93 144
tPHL Propagation delay ns
SDAA, SCLA SDAB, SCLB 68 90 140
B side 88
Transition
tTLH(4) 30% 70% ns
time A side 37
B side 5.40 6.41 13.8
Transition
tTHL 70% 30% ns
time A side 1.40 4.71 11.3
tsu,en Setup time, EN high before Start condition(5) 100 ns
(1) Times are specified with loads of 240 Ω±1% and 400 pF ±10% on B-side and 240 Ω±1% and 200 pF ±10% on A-side. Different load
resistance and capacitance alter the rise time, thereby changing the propagation delay and transition times.
(2) Times are specified with A-side signals pulled up to VCCA and B-side signals pulled up to VCCB.
(3) Typical values were measured with VCCA = 0.9 V and VCCB = 2.5 V at TA= 25°C, unless otherwise noted.
(4) TTLH is determined by the pull-up resistance and load capacitance.
(5) EN should change state only when the global bus and the repeater port are in an idle state.
7.7 Typical Characteristics
VCCA = 0.9 V VCCB = 2.2 V VCCA = 0.9 V VCCB = 2.2 V
Figure 1. Port A VOL vs IOL Figure 2. Port B VOL vs IOL
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DUT
Open Drain
Driver
VCCA VCCB
RPUB
VCCB
VCCA
RPUA
1M
CLA CLB
VOUT
VIN
TCA9617B
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SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
8 Parameter Measurement Information
Figure 3. Test Circuit for Open-Drain Output from A to B
A. VCCA = 0.9 V
B. VCCB = 2.5 V
C. RPUA = RPUB = 240 Ωon the A-side and the B-side
D. CLA = 200 pF on A-side and CLB = 400 pF on B-side (includes probe and jig capacitance)
E. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω, slew rate
≥1 V/ns
F. The outputs are measured one at a time, with one transition per measurement.
Figure 4. Test Circuit for Open-Drain Output from B to A
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tPHL,BA tTHL,A
0.7 * VCC
0.3 * VCC
0.3 * VCC
A-side
B-side
0.4 V
tPLH,BA
0.7 * VCC
tTLH,A
tPHL,AB tTHL,B
0.7 * VCC
0.3 * VCC
tPLH,AB
VOLB
VOLB
0.3 * VCC
A-side
B-side
0.7 * VCC
tTLH,B
VILA
VILA
TCA9617B
SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
www.ti.com
Parameter Measurement Information (continued)
Figure 5. Propagation Delay And Transition Times (A to B)
Figure 6. Propagation Delay And Transition Times (B to A)
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9 Detailed Description
9.1 Overview
The TCA9617B is a BiCMOS dual bidirectional buffer intended for I2C bus and SMBus systems. As with the
standard I2C system, pull-up resistors are required to provide the logic high levels on the buffered bus. The
TCA9617B has standard open-drain configuration of the I2C bus. The size of these pull-up resistors depends on
the system, but each side of the repeater must have a pull-up resistor. The device is designed to work with
Standard mode, Fast mode and Fast Mode+ I2C devices. The SCL and SDA lines shall be at high-impedance
when either one of the supplies is powered off.
The TCA9617B B-side drivers operate from 2.2 V to 5.5 V. The output low level for this internal buffer is
approximately 0.5 V, but the input voltage must be below VIL when the output is externally driven low. The
higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not
recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low
condition is released. This type of design on the B side prevents it from being used in series with another
TCA9617B B-side or other buffers that incorporate a static or dynamic offset voltage. This is because these
devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.
The TCA9617B A-side drivers operate from 0.8 V to 5.5 V and do not have the buffered low feature (or the static
offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on the A side, which
accommodates smaller voltage swings of low-voltage logic. The output pull-down on the A side drives a hard low,
and the input level is set to 0.3 VCCA to accommodate the need for a lower low level in systems where the low-
voltage-side supply voltage is as low as 0.8 V.
The A side of two or more TCA9617Bs can be connected together to allow a star topology, with the A side on the
common bus. Also, the A side can be connected directly to any other buffer with static or dynamic offset voltage.
Multiple TCA9617Bs can be connected in series, A side to B side, with no buildup in offset voltage with only
time-of-flight delays to consider.
The TCA9617B includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.0 V and
VCCA is above 0.7 V. VCCA is only used to provide references for the A-side input comparators and the power-
good-detect circuit. The TCA9617B internal circuitry and all I/Os are powered by the VCCB pin.
After power up and with the EN high, the A side falling below 0.7 VCCA turns on the corresponding B-side driver
(either SDA or SCL) and drives the B-side down momentarily to 0 V before settling to approximately 0.5 V. When
the A-side rises above 0.3 VCCA, the B-side pull-down driver is turned off and the external pull-up resistor pulls
the pin high. If the B side falls first and goes below 0.7 VCCB, the A-side driver is turned on and drives the A-side
to 0 V. When the B-side rises above 0.45 V, the A-side pull-down driver is turned off and the external pull-up
resistor pulls the pin high.
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SDAB
SCLBSCLA
SDAA
EN
VCCB
Pullup
Resistor
GND
1 8
VCCA VCCB
4
3
2
5
6
7
TCA9617B
SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
www.ti.com
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Bidirectional Level Translation
The TCA9617B can provide bidirectional voltage level translation (up-translation and down-translation) between
low voltages (down to 0.8 V) and higher voltages (2.2 V to 5.5 V) in mixed-mode applications.
9.3.2 Low to High Transition Characteristics
Figure 8 depicts the offset voltage on the B side of the device. As shown in Figure 8 the slave releases and the
B-side rises, and it will rise to 0.5 V and stay there until the A-side rises above 0.3 VCCA. This effect can cause
the low level signal to have a "pedestal." Once the voltage on the A-side crosses 0.3 VCCA, the B-side will
continue to rise to VCCB.
Due to nature of the B-side pedestal and the static offset voltage, there will be a slight overshoot as the B-side
rises from being externally driven low to the 0.5 V offset. The TCA9617B is designed to control this behavior
provided the system is designed with rise times greater than 20 ns. Therefore, care should be taken to limit the
pull-up strength when devices with rise time accelerators are present on the B side. Excessive overshoot on the
B-side pedestal may cause devices with rise time accelerators to trip prematurely if the overshoot is more than
accelerator thresholds. Since the A-side does not have a static offset low voltage, no pedestal is seen on the A-
side as shown in Figure 7.
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9th Clock Pulse – Acknowledge
SCL
SDA
GND
VOL of SlaveVOL of TCA9617B
Inverted Pedestal
Pedestal
9th Clock Pulse – Acknowledge
SCL
SDA
TCA9617B
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SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
Feature Description (continued)
9.3.3 High to Low Transition Characteristics
When the A side of the bus is driven to 0.7 VCCA, the B side driver will turn on. This will drive the B-side to 0 V for
a short period (see Figure 8) and then the B-side will rise to the static offset voltage of 0.5 V (VOL of TCA9617B).
This effect, called an inverted pedestal, allows the B-side to drive to logic low much faster than driving to the
static offset. Driving to the static offset voltage requires that the fall time be slowed to prevent ringing.
Figure 7. Bus A (0.8 V to 5.5 V Bus) Waveform
Figure 8. Bus B (2.2 V to 5.5 V Bus) Waveform
9.4 Device Functional Modes
The TCA9617B has an active-high enable (EN) input with an internal pull-up to VCCB, which allows the user to
select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It
should never change state during an I2C operation, because disabling during a bus operation may hang the bus,
and enabling part way through the bus cycles could confuse the I2C parts being enabled. The EN input should
change state only when the global bus and repeater port are in the idle state to prevent system failures.
Table 1. Function Table
INPUT FUNCTION
EN
L Outputs disabled
SDAA = SDAB
HSCLA = SCLB
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TCA9617B Slave
1 MHz
Master
1 MHz
VCCA VCCB
240 820
2 .5 V0 .9 V
SDAA
SCLA
EN
SCLB
SDAB
240 820
BUS A BUS B
TCA9617B
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10 Application and Implementation
10.1 Application Information
A typical application is shown in Figure 9. In this example, the system master is running on a 0.9-V I2C bus, and
the slave is connected to a 2.5-V bus. Both buses are running at 400 kHz. Decoupling capacitors are required
but are not shown in Figure 14 for simplicity.
The TCA9617B is 5-V tolerant so no additional circuits are required to translate between 0.8-V to 5.5-V bus
voltages and 2.7-V to 5.5-V bus voltages.
When the A side of the TCA9617B is pulled low by a driver on the I2C bus, a comparator detects the falling edge
when it goes below 0.7 VCCA and cause the internal driver on the B side to turn on. The B-side will first pull down
to 0 V and then settle to 0.5 V. When the B side of the TCA9617B falls below 0.45 V, the TCA9617B will detect
the falling edge, turn on the internal driver on the A side and pull the A-side pin down to ground.
On the B-side bus of the TCA9617B, the clock and data lines will have a positive offset from ground equal to the
VOL of the TCA9617B. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is
close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by the
driver of the TCA9617B for a short delay (approximately 0.5 V), while the A-side bus rises above 0.3 VCCA and
then continues high.
Although the TCA9617 has a single application, the device can exist in multiple configurations. Figure 9 shows
the standard configuration for the TCA9617. Multiple TCA9617s can be connected either in star configuration
(Figure 12) or in series configuration (Figure 13). The design requirements , detailed design procedure, and
application curves in Standard Application are valid for all three configurations.
10.2 Typical Application
10.2.1 Standard Application
Figure 9. Bidirectional Voltage Level Translator
10.2.1.1 Design Requirements
For the level-translating application, the following should be true:
• VCCA = 0.8 V to 5.5 V
• VCCB = 2.2 V to 5.5 V
• VCCA < VCCB
• IOL > IO
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2
1
2
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Typical Application (continued)
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Pullup Resistor Sizing
For the TCA9617B to function correctly, all devices on the B-side must be able to pull the B-side below the
voltage input low contention level (0.45 V). This means that the VOL of any device on the B-side must be below
0.4 V to ensure proper operation.
The VOL of a device can be adjusted by changing the IOL through the device which is set by the pull-up resistor
value. The pull-up resistor on the B-side must be carefully selected to ensure that logic levels will be transferred
correctly to the A-side.
The B-side pull-up resistor sizing must also ensure that the rise time is greater than 20 ns. Shorter rise times will
increase the pedestal overshoot shown in point 2 of Figure 10.
10.2.1.3 Application Curves
Figure 10. B-side Pedestal Figure 11. B-side Inverted Pedestal
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TCA9617B Slave
1 MHz
Master
1 MHz
VCCA VCCB
240 820
VCCB
VCCA
SDAA
SCLA
EN
SCLB
SDAB
240 820
TCA9617B Slave
1 MHz
VCCA VCCB
SDAA
SCLA
EN
SCLB
SDAB
BUS B
TCA9617B Slave
1 MHz
VCCA VCCB
SDAA
SCLA
EN
SCLB
SDAB
820 820
820 820
TCA9617B
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Typical Application (continued)
10.2.2 Star Application
Multiple TCA9617B A sides can be connected in a star configuration, allowing all nodes to communicate with
each other.
Figure 12. Typical Star Application
10.2.2.1 Design Requirements
Refer to Design Requirements.
10.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
10.2.2.3 Application Curves
Refer to Application Curves.
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TCA9617B
Master
1 MHz
VCCA VCCB
240 820
VCCA
SDAA
SCLA
EN
SCLB
SDAB
240 820
TCA9617B
VCCA VCCB
SDAA
SCLA
EN
SCLB
SDAB
VCCB
820 820
TCA9617B
VCCA VCCB
SDAA
SCLA
EN
SCLB
SDAB
820 820
Slave
1 MHz
SDA
SCL
TCA9617B
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SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
Typical Application (continued)
10.2.3 Series Application
Multiple TCA9617Bs can be connected in series as long as the A side is connected to the B side. I2C bus slave
devices can be connected to any of the bus segments. The number of devices that can be connected in series is
limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements.
Figure 13. Typical Series Application
10.2.3.1 Design Requirements
Refer to Design Requirements.
10.2.3.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
10.2.3.3 Application Curves
Refer to Application Curves.
11 Power Supply Recommendations
For VCCA, an 0.8-V to 5.5-V power supply is required. For VCCB, a 2.2-V to 5.5-V power supply is required.
Standard decoupling capacitors are recommended. These capacitors typically range from 0.1 µF to 1 µF, but the
ideal capacitance depends on the amount of noise from the power supply.
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TCA9617B
1
2
3
4
8
7
6
5
VCCA
SCLA
SDAA
GND
VCCB
SCLB
SDAB
EN
VIA to GND Plane
Polygonal Copper Pour
Decoupling capacitors
TCA9617B
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www.ti.com
12 Layout
12.1 Layout Guidelines
The recommended decoupling capacitors should be placed as close to the VCCA and VCCB pins of the
TCA9617B as possible.
12.2 Layout Example
Figure 14. Layout Schematic
16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TCA9617B
TCA9617B
www.ti.com
SCPS259A –DECEMBER 2014–REVISED DECEMBER 2014
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TCA9617B
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TCA9617BDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 ZBOK
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Dec-2014
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TCA9617BDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA9617BDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2014
Pack Materials-Page 2
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