LTC6994-1/LTC6994-2 TimerBlox: Delay Block/ Debouncer Features n n n n n n n n n n Description Delay Range: 1s to 33.6 Seconds Configured with 1 to 3 Resistors Delay Max Error: - <2.3% for Delay > 512s - <3.4% for Delay of 8s to 512s - <5.1% for Delay of 1s to 8s Delay One or Both Rising/Falling Edges 2.25V to 5.5V Single Supply Operation 70A Supply Current at 10s Delay 500s Start-Up Time CMOS Output Driver Sources/Sinks 20mA -55C to 125C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOTTM) and 2mm x 3mm DFN Applications n n n n n Noise Discriminators/Pulse Qualifiers Delay Matching Switch Debouncing High Vibration, High Acceleration Environments Portable and Battery-Powered Equipment L, LT, LTC, LTM, Linear Technology, TimerBlox and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. The LTC(R)6994 is a programmable delay block with a range of 1s to 33.6 seconds. The LTC6994 is part of the TimerBlox(R) family of versatile silicon timing devices. A single resistor, RSET , programs an internal master oscillator frequency, setting the LTC6994's time base. The input-to-output delay is determined by this master oscillator and an internal clock divider, NDIV , programmable to eight settings from 1 to 221: tDELAY = NDIV * RSET * 1s, NDIV = 1, 8, 64,...,221 50k The output (OUT) follows the input (IN) after delaying the rising and/or falling transitions. The LTC6994-1 will delay the rising or falling edge. The LTC6994-2 will delay both transitions, and adds the option to invert the output. DEVICE DELAY FUNCTION LTC6994-1 or LTC6994-2 or The LTC6994 also offers the ability to dynamically adjust the delay time via a separate control voltage. For easy configuration of the LTC6994, download the TimerBlox Designer tool at www.linear.com/timerblox. Typical Application Noise Discriminator NOISY INPUT OUT IN LTC6994-2 GND QUALIFIED OUTPUT 3.3V V+ IN 2V/DIV 1.5s 0.1F RSET 75k SET DIV 1.5s OUT 2V/DIV 699412 TA01a 20s/DIV 699412 TA01b 699412fb 1 LTC6994-1/LTC6994-2 Absolute Maximum Ratings (Note 1) Supply Voltage (V+) to GND.........................................6V Maximum Voltage on Any Pin .................................. (GND - 0.3V) VPIN (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6994C.............................................-40C to 85C LTC6994I..............................................-40C to 85C LTC6994H........................................... -40C to 125C LTC6994MP........................................ -55C to 125C Specified Temperature Range (Note 3) LTC6994C................................................. 0C to 70C LTC6994I..............................................-40C to 85C LTC6994H........................................... -40C to 125C LTC6994MP........................................ -55C to 125C Junction Temperature............................................ 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) S6 Package........................................................ 300C Pin Configuration TOP VIEW V+ 1 DIV 2 TOP VIEW 6 OUT 7 IN 1 5 GND 4 IN SET 3 DCB PACKAGE 6-LEAD (2mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 64C/W, JC = 10.6C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL 6 OUT GND 2 5 V+ SET 3 4 DIV S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 192C/W, JC = 51C/W Order Information Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6994CDCB-1#TRMPBF LTC6994IDCB-1#TRMPBF LTC6994HDCB-1#TRMPBF LTC6994CDCB-2#TRMPBF LTC6994IDCB-2#TRMPBF LTC6994HDCB-2#TRMPBF LTC6994CS6-1#TRMPBF LTC6994IS6-1#TRMPBF LTC6994HS6-1#TRMPBF LTC6994MPS6-1#TRMPBF LTC6994CS6-2#TRMPBF LTC6994IS6-2#TRMPBF LTC6994HS6-2#TRMPBF LTC6994MPS6-2#TRMPBF LTC6994CDCB-1#TRPBF LTC6994IDCB-1#TRPBF LTC6994HDCB-1#TRPBF LTC6994CDCB-2#TRPBF LTC6994IDCB-2#TRPBF LTC6994HDCB-2#TRPBF LTC6994CS6-1#TRPBF LTC6994IS6-1#TRPBF LTC6994HS6-1#TRPBF LTC6994MPS6-1#TRPBF LTC6994CS6-2#TRPBF LTC6994IS6-2#TRPBF LTC6994HS6-2#TRPBF LTC6994MPS6-2#TRPBF LFCT LFCT LFCT LFCW LFCW LFCW LTFCV LTFCV LTFCV LTFCV LTFCX LTFCX LTFCX LTFCX 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C -55C to 125C 0C to 70C -40C to 85C -40C to 125C -55C to 125C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 699412fb 2 LTC6994-1/LTC6994-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER tDELAY Delay Time tDELAY Delay Accuracy (Note 4) CONDITIONS MIN TYP MAX UNITS 33.55 sec 1.7 2.3 3.0 % % 2.4 3.4 4.4 % % 3.8 5.1 6.2 % % 1 NDIV 512 l 8 NDIV 64 l NDIV = 1 l tDELAY/T Delay Drift Over Temperature NDIV 512 NDIV 64 Delay Change With Supply NDIV 512 V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V l l -0.6 -0.4 -0.2 -0.1 8 NDIV 64 V+ = 4.5V to 5.5V V+ = 2.7V to 4.5V V+ = 2.25V to 2.7V l l l -0.9 -0.7 -1.1 -0.2 -0.2 -0.1 NDIV = 1 V+ = 5.5V V+ = 2.25V Delay Jitter (Note 10) tS Delay Change Settling Time (Note 9) 0.006 0.008 l l %/C %/C % % 0.4 0.9 % % % 1.0 0.5 %P-P %P-P NDIV = 8 0.20 %P-P NDIV = 64 0.05 %P-P NDIV = 512 0.20 %P-P NDIV = 4096 0.03 %P-P tMASTER = tDELAY/NDIV 6 * tMASTER s Power Supply V+ IS(IDLE) Operating Supply Voltage Range l Power-On Reset Voltage l Supply Current (Idle) 2.25 5.5 V 1.95 V RL = , RSET = 50k, NDIV 64 V+ = 5.5V V+ = 2.25V l l 165 125 200 160 A A RL = , RSET = 50k, NDIV 512 V+ = 5.5V V+ = 2.25V l l 135 105 175 140 A A RL = , RSET = 800k, NDIV 64 V+ = 5.5V V+ = 2.25V l l 70 60 110 95 A A RL = , RSET = 800k, NDIV 512 V+ = 5.5V V+ = 2.25V l l 65 55 100 90 A A 1.00 1.03 V Analog Inputs Voltage at SET Pin l VSET/T VSET Drift Over Temperature l RSET Frequency-Setting Resistor l VSET VDIV DIV Pin Voltage VDIV/V+ DIV Pin Valid Code Range (Note 5) DIV Pin Input Current 75 V/C 50 800 k 0 V+ V l 1.5 % l 10 nA l Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 0.97 699412fb 3 LTC6994-1/LTC6994-2 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = , CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O IN Pin Input Capacitance VIH 2.5 IN Pin Input Current IN = 0V to V+ High Level IN Pin Input Voltage (Note 6) 10 l VIL Low Level IN Pin Input Voltage (Note 6) IOUT(MAX) Output Current V+ = 2.7V to 5.5V VOH High Level Output Voltage (Note 7) V+ = 5.5V IOUT = -1mA IOUT = -16mA l l V+ = 3.3V IOUT = -1mA IOUT = -10mA V+ = 2.25V VOL Low Level Output Voltage (Note 7) pF 0.7 * V+ nA V 0.3 * V+ l V 20 mA 5.45 4.84 5.48 5.15 V V l l 3.24 2.75 3.27 2.99 V V IOUT = -1mA IOUT = -8mA l l 2.17 1.58 2.21 1.88 V V V+ = 5.5V IOUT = 1mA IOUT = 16mA l l 0.02 0.26 0.04 0.54 V V V+ = 3.3V IOUT = 1mA IOUT = 10mA l l 0.03 0.22 0.05 0.46 V V V+ = 2.25V IOUT = 1mA IOUT = 8mA l l 0.03 0.26 0.07 0.54 V V tPD Propagation Delay V+ = 5.5V V+ = 3.3V V+ = 2.25V 10 14 24 ns ns ns tWIDTH Minimum Recognized Input Pulse Width V+ = 3.3V 5 ns tr Output Rise Time (Note 8) V+ = 5.5V V+ = 3.3V V+ = 2.25V 1.1 1.7 2.7 ns ns ns tf Output Fall Time (Note 8) V+ = 5.5V V+ = 3.3V V+ = 2.25V 1.0 1.6 2.4 ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6994C is guaranteed functional over the operating temperature range of -40C to 85C. Note 3: The LTC6994C is guaranteed to meet specified performance from 0C to 70C. The LTC6994C is designed, characterized and expected to meet specified performance from -40C to 85C but it is not tested or QA sampled at these temperatures. The LTC6994I is guaranteed to meet specified performance from -40C to 85C. The LTC6994H is guaranteed to meet specified performance from -40C to 125C. The LTC6994MP is guaranteed to meet specified performance from -55C to 125C. Note 4: Delay accuracy is defined as the deviation from the tDELAY equation, assuming RSET is used to program the delay. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. Note 6: The IN pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VIN(RISING) 0.55 * V+ + 185mV and VIN(FALLING) 0.48 * V+ - 155mV Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within 1% of the final delay after a 0.5x or 2x change in ISET . Note 10: Jitter is the ratio of the deviation of the programmed delay to the mean of the delay. This specification is based on characterization and is not 100% tested. 699412fb 4 LTC6994-1/LTC6994-2 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Delay Drift vs Temperature (NDIV 64) Delay Drift vs Temperature (NDIV 64) 1.5 1.5 RSET = 50k 3 PARTS 1.0 0.5 DRIFT (%) 0 0 -0.5 -0.5 -1.0 -1.0 -1.0 50 25 75 0 TEMPERATURE (C) 100 -1.5 -50 -25 125 50 25 75 0 TEMPERATURE (C) 100 699412 G01 1.5 1.5 0.5 0 0 -0.5 -0.5 -0.5 -1.0 -1.0 -1.0 50 25 75 0 TEMPERATURE (C) 100 -1.5 -50 -25 125 50 25 75 0 TEMPERATURE (C) 100 1.0 1.0 1.0 0.4 0.2 0.2 0.2 0 -0.2 -0.4 -0.6 2 3 4 SUPPLY (V) 6 699412 G07 -1.0 -0.6 RSET = 50k RSET = 200k RSET = 800k -0.8 5 0 -0.2 -0.4 -0.6 RSET = 50k RSET = 200k RSET = 800k -0.8 -1.0 DRIFT (%) 0.6 0.4 DRIFT (%) 0.6 0.4 -0.4 125 REFERENCED TO V+ = 4V 0.8 0.6 -0.2 100 Delay Drift vs Supply Voltage (NDIV > 1) FALLING EDGE DELAY REFERENCED TO V+ = 4V 0.8 0 50 25 75 0 TEMPERATURE (C) 699412 G06 Delay Drift vs Supply Voltage (NDIV = 1) RISING EDGE DELAY REFERENCED TO V+ = 4V 0.8 -1.5 -50 -25 125 699412 G05 699412 G04 Delay Drift vs Supply Voltage (NDIV = 1) 125 RSET = 800k 3 PARTS 1.0 DRIFT (%) DRIFT (%) DRIFT (%) 1.5 0.5 0.5 -1.5 -50 -25 100 Delay Drift vs Temperature (NDIV 512) RSET = 200k 3 PARTS 1.0 0 50 25 75 0 TEMPERATURE (C) 699412 G03 Delay Drift vs Temperature (NDIV 512) RSET = 50k 3 PARTS 1.0 -1.5 -50 -25 125 699412 G02 Delay Drift vs Temperature (NDIV 512) DRIFT (%) 0 -0.5 -1.5 -50 -25 RSET = 800k 3 PARTS 1.0 0.5 DRIFT (%) DRIFT (%) 1.5 RSET = 200k 3 PARTS 1.0 0.5 Delay Drift vs Temperature (NDIV 64) 2 3 4 SUPPLY (V) RSET = 50k, NDIV = 8 RSET = 50k TO 800k, NDIV 512 RSET = 800k, NDIV = 8 -0.8 5 6 699412 G08 -1.0 2 3 4 SUPPLY (V) 5 6 699412 G09 699412fb 5 LTC6994-1/LTC6994-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Delay Error vs RSET (8 NDIV 64) Delay Error vs RSET (NDIV = 1) 5 RISING EDGE DELAY 3 PARTS 4 Delay Error vs RSET (NDIV 512) 5 3 PARTS 4 3 3 2 2 1 1 1 0 -2 ERROR (%) 3 -1 0 -1 -2 -2 -3 -3 -4 -4 -4 -5 -5 100 200 RSET (k) 400 800 100 50 200 RSET (k) 400 2 2 1 1 1 0 -1 -2 -2 -3 -3 -4 -4 -5 -5 100 200 RSET (k) 400 800 3 ERROR (%) ERROR (%) ERROR (%) 3 2 50 RISING EDGE DELAY 0 -1 -2 FALLING EDGE DELAY 0 2 4 6 8 10 DIVCODE 12 -5 14 VSET Drift vs Supply Voltage 1.020 0.8 1.015 0.6 0.6 0.4 0.4 0.2 0.2 0 -0.4 -0.6 -0.6 5 10 ISET (A) 15 20 699412 G16 6 8 10 DIVCODE 3 PARTS 1.000 0.995 0.990 -0.8 -1.0 14 12 1.005 -0.2 -0.4 0 4 1.010 VSET (V) DRIFT (mV) 1.0 -1.0 2 VSET vs Temperature 1.0 REFERENCED TO ISET = 10A 0 699412 G15 0.8 -0.8 FALLING EDGE DELAY 699412 G14 VSET Drift vs ISET 0 RISING EDGE DELAY -3 -4 699412 G13 -0.2 800 LTC6994-1 RSET = 800k 3 PARTS 4 3 0 400 Delay Error vs DIVCODE 5 LTC6994-1 RSET = 50k 3 PARTS 4 -1 200 RSET (k) 699412 G12 Delay Error vs DIVCODE 5 FALLING EDGE DELAY 3 PARTS 4 100 50 699412 G11 Delay Error vs RSET (NDIV =1) 5 -5 800 699412 G10 VSET (mV) 0 -1 -3 50 3 PARTS 4 2 ERROR (%) ERROR (%) 5 0.985 REFERENCED TO V+ = 4V 2 3 4 SUPPLY (V) 6 5 699412 G17 0.980 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125 699412 G18 699412fb 6 LTC6994-1/LTC6994-2 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Typical VSET Distribution 100 50 0 0.98 0.996 1.004 VSET (V) 0.988 1.012 250 RSET = 50k, /1, IDLE 200 150 RSET = 100k, /8, ACTIVE 100 RSET = 100k, /8, IDLE 50 0 1.02 RSET = 50k, /1, ACTIVE RSET = 800k, /512 CLOAD = 5pF RLOAD = 2 3 Supply Current vs IN Pin Voltage 250 POWER SUPPLY CURRENT (A) POWER SUPPLY CURRENT (A) 150 5V IN RISING 3.3V IN RISING 3.3V IN FALLING 100 50 0 CLOAD = 5pF RLOAD = 0 0.2 0.6 0.4 VIN/V+ (V/V) 0.8 200 /1 /8 100 50 3.5 V+ = 5V CLOAD = 5pF RLOAD = 0.01 ACTIVE IDLE 0.1 1 tDELAY (ms) 3.0 0.6 6 699412 G25 125 ACTIVE CURRENT MEASURED USING LTC6994-1 WITH fIN = 1/(2 * tDELAY) 200 150 /1 /8 100 50 V+ = 2.5V CLOAD = 5pF RLOAD = 0.01 ACTIVE IDLE 0.1 1 tDELAY (ms) 100 10 Typical ISET Current Limit vs V+ /1, 2.25V 1000 SET PIN SHORTED TO GND 800 600 400 0.4 /8, 5.5V 4 5 SUPPLY VOLTAGE (V) 100 0.8 /512 0.2 3 0 25 50 75 TEMPERATURE (C) 699412 G24 ISET (A) JITTER (%P-P) IN PIN VOLTAGE (V) 2.5 2 -25 RSET = 800k, /512 Supply Current vs tDELAY (2.5V) 0 0.001 100 10 PEAK-TO-PEAK tDELAY VARIATION MEASURED OVER 30s INTERVALS 1.0 POSITIVE GOING 0 50 Peak-to-Peak Jitter vs tDELAY /1, 5.5V 0.5 RSET = 100k, /8, IDLE 699412 G23 1.2 1.0 RSET = 100k, /8, ACTIVE 100 250 ACTIVE CURRENT MEASURED USING LTC6994-1 WITH fIN = 1/(2 * tDELAY) 150 IN Threshold Voltage vs Supply Voltage 1.5 RSET = 50k, /1, IDLE 699412 G21 Supply Current vs tDELAY (5V) 0 0.001 1.0 NEGATIVE GOING RSET = 50k, /1, ACTIVE 150 0 -50 6 699412 G22 2.0 200 699412 G20 250 5V IN FALLING LTC6994-1 IS(ACTIVE) MEASURED WITH fIN = 1/(2 * tDELAY) CLOAD = 5pF RLOAD = 4 5 SUPPLY VOLTAGE (V) 699412 G19 200 POWER SUPPLY CURRENT (A) 150 LTC6994-1 IS(ACTIVE) MEASURED WITH fIN = 1/(2 * tDELAY) Supply Current vs Temperature 250 POWER SUPPLY CURRENT (A) 2 LOTS DFN AND SOT-23 1274 UNITS 200 NUMBER OF UNITS Supply Current vs Supply Voltage 300 POWER SUPPLY CURRENT (A) 250 0 0.001 /8, 2.25V 0.01 /64 0.1 1 tDELAY (ms) 200 /4096 10 100 699412 G26 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 699412 G27 699412fb 7 LTC6994-1/LTC6994-2 Typical Performance Characteristics + V = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Input Propagation Delay (tPD) vs Supply Voltage 3.0 CLOAD = 5pF 50 CLOAD = 5pF 45 20 15 10 5 OUTPUT RESISTANCE () 2.5 RISE/FALL TIME (ns) PROPAGATION DELAY (ns) 25 Output Resistance vs Supply Voltage Rise and Fall Time vs Supply Voltage 2.0 tRISE 1.5 tFALL 1.0 0.5 40 35 OUTPUT SOURCING CURRENT 30 25 20 OUTPUT SINKING CURRENT 15 10 5 0 2 4 3 5 6 0 2 SUPPLY VOLTAGE (V) 3 4 5 SUPPLY VOLTAGE (V) 0 6 2 3 4 5 SUPPLY VOLTAGE (V) 699412 G29 6 699412 G30 699412 G28 Start-Up, RSET = 800k (LTC6994-1) V+ 2V/DIV Start-Up, RSET = 50k (LTC6994-2, POL = 1) 7.2ms IN 2V/DIV IN 2V/DIV OUT 2V/DIV OUT 2V/DIV V+ = 2.5V 1ms/DIV 500s V+ 2V/DIV 699412 G31 V+ = 2.5V 100s/DIV 699412 G32 699412fb 8 LTC6994-1/LTC6994-2 Pin Functions (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1F capacitor. A resistor connected between SET and GND is the most accurate way to set the delay. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. The DIV pin voltage (VDIV) is internally converted into a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) selects the delay functionality. For the LTC6994-1, POL = 0 will delay the rising transition and POL = 1 will delay the falling transition. For the LTC69942, both transitions are delayed so POL = 1 can be used to invert the output. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. IN (Pin 4/Pin 1): Logic Input. Depending on the version and POL bit setting, rising or falling edges on IN will propagate to OUT after a programmable delay. The LTC6994-1 will delay only the rising or falling edge. The LTC6994-2 will delay both edges. GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25A to 20A. The delayed output transition will be not occur if ISET drops below approximately 500nA. Once ISET increases above 500nA the delayed edge will transition. OUT (Pin 6/Pin 6): Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30. When driving an LED or other low impedance load a series output resistor should be used to limit source/ sink current to 20mA. V+ IN OUT LTC6994 RSET V+ GND V+ SET DIV 699412 PF C1 0.1F R1 R2 699412fb 9 LTC6994-1/LTC6994-2 Block Diagram (S6 package pin numbers shown) 5 V+ R1 4 DIV 4-BIT A/D CONVERTER POL DIGITAL FILTER R2 1 IN INPUT BUFFER MASTER OSCILLATOR V 1s tMASTER = * SET 50k ISET MCLK PROGRAMMABLE DIVIDER EDGECONTROLLED DELAY LOGIC OUTPUT OUT 6 POLARITY (LTC6994-2) /1, 8, 64, 512, 4096, 215, 218, 221 POR HALT OSCILLATOR IF ISET < 500nA ISET + - VSET = 1V 1V + - GND SET 3 ISET 2 699412 BD RSET 699412fb 10 LTC6994-1/LTC6994-2 Operation The LTC6994 is built around a master oscillator with a 1s minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1s/50k conversion factor that is accurate to 1.7% under typical conditions. 1s VSET tMASTER = * 50k ISET A feedback loop maintains VSET at 1V 30mV, leaving ISET as the primary means of controlling the input-to-output delay. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: R tMASTER = 1s * SET 50k From this equation, it is clear that VSET drift will not affect the input-to-output delay when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent accuracy tDELAY of the LTC6994. RSET may range from 50k to 800k (equivalent to ISET between 1.25A and 20A). When the input makes a transition that will be delayed (as determined by the part version and POL bit setting), the master oscillator is enabled to time the delay. When the desired duration is reached, the output is allowed to transition. The LTC6994 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. This extends the delay duration by those same factors. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. tDELAY = NDIV VSET * * 1s 50k ISET DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6994: 1. DIVCODE determines the frequency divider setting, NDIV . 2. The DIVCODE MSB is the POL bit, and configures a different polarity setting on the two versions. a. LTC6994-1: POL selects rising or falling-edge delays. POL = 0 will delay rising-edge transitions. POL = 1 will delay falling-edge transitions. b. LTC6994-2: POL selects the output inversion. POL = 1 inverts the output signal. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1. 2.25V TO 5.5V V+ R1 LTC6994 DIV R2 GND 699412 F01 Figure 1. Simple Technique for Setting DIVCODE Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to 1.5% (including resistor tolerances and temperature effects) 2. The driving impedance (R1||R2) does not exceed 500k. With RSET in place of VSET/ISET the equation reduces to: tDELAY = NDIV *RSET * 1s 50k 699412fb 11 LTC6994-1/LTC6994-2 Operation If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V + = For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 * 3.3V = 928mV 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. DIVCODE + 0.5 1.5% 16 Table 1. DIVCODE Programming DIVCODE POL NDIV Recommended tDELAY R1 (k) R2 (k) VDIV /V+ 0 0 1 1s to 16s Open Short 0.03125 0.015 1 0 8 8s to 128s 976 102 0.09375 0.015 2 0 64 64s to 1.024ms 976 182 0.15625 0.015 3 0 512 512s to 8.192ms 1000 280 0.21875 0.015 4 0 4,096 4.096ms to 65.54ms 1000 392 0.28125 0.015 5 0 32,768 32.77ms to 524.3ms 1000 523 0.34375 0.015 6 0 262,144 262.1ms to 4.194sec 1000 681 0.40625 0.015 7 0 2,097,152 2.097sec to 33.55sec 1000 887 0.46875 0.015 8 1 2,097,152 2.097sec to 33.55sec 887 1000 0.53125 0.015 9 1 262,144 262.1ms to 4.194sec 681 1000 0.59375 0.015 10 1 32,768 32.77ms to 524.3ms 523 1000 0.65625 0.015 11 1 4,096 4.096ms to 65.54ms 392 1000 0.71875 0.015 12 1 512 512s to 8.192ms 280 1000 0.78125 0.015 13 1 64 64s to 1.024ms 182 976 0.84375 0.015 14 1 8 8s to 128s 102 976 0.90625 0.015 15 1 1 1s to 16s Short Open 0.96875 0.015 POL BIT = 0 POL BIT = 1 10000 7 6 1000 9 10 5 100 tDELAY (ms) 8 11 4 10 12 3 1 13 2 0.1 1 0.01 0.001 14 0 0V 15 0.5*V+ INCREASING VDIV V+ 699412 F02 Figure 2. Delay Range and POL Bit vs DIVCODE 699412fb 12 LTC6994-1/LTC6994-2 Operation Edge-Controlled Delay The LTC6994 is a programmable delay or pulse qualifier. It can perform noise filtering, which distinguishes it from a delay line (which simply delays all input transitions). When the voltage on the LTC6994 input pin (IN) transitions low or high, the LTC6994 can delay the corresponding output transition by any time from 1s to 33.6 seconds. LTC6994-1 Functionality Figures 3 details the basic operation of the LTC6994-1 when configured to delay rising edge transitions (POL = 0). A rising edge on the IN pin initiates the timing. OUT remains low for the duration of tDELAY . If IN stays high then OUT will transition high after this time. If the input doesn't remain high long enough for OUT to transition high then the timing will restart on each successive rising edge. In this way, the LTC6994-1 can serve as a pulse qualifier, filtering out noisy or short signals. On a falling edge at the input, the output will follow immediately (after a short propagation delay tPD).Note that the output pulse width may be extremely short if IN falls immediately after OUT rises. Figure 4 details the operation of the LTC6994-1 when configured to delay falling edges (POL = 1). tWIDTH IN tPD tPD tPD tPD tPD tPD OUT 699412 F03 tDELAY tDELAY tDELAY Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0) tWIDTH IN tPD tPD tPD tPD tPD tPD OUT 699412 F04 tDELAY tDELAY tDELAY Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1) 699412fb 13 LTC6994-1/LTC6994-2 Operation LTC6994-2 Functionality Figures 5 details the basic operation of the LTC6994-2 when configured for noninverting operation (POL = 0). As before, a rising edge on the IN pin initiates the timing and, if IN remains high, OUT will transition high after tDELAY . Unlike the LTC6994-1, falling edges are delayed in the same way. When IN transitions low, OUT will follow after tDELAY . If the input doesn't remain high or low long enough for OUT to follow, the timing will restart on the next transition. Also unlike the LTC6994-1, the output pulse width can never be less than tDELAY . Therefore, the LTC6994-2 can generate pulses with a defined minimum width. Figure 6 details the operation of the LTC6994-2 when the output is inverted (POL = 1). tWIDTH IN tPD tPD tPD tPD tPD OUT tDELAY tDELAY tDELAY tDELAY 699412 F05 Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0) tWIDTH IN tPD tPD tPD tPD tPD 699412 F06 OUT tDELAY tDELAY tDELAY tDELAY Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1) 699412fb 14 LTC6994-1/LTC6994-2 Operation Changing DIVCODE After Start-Up Start-Up Time Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6994 places a priority on eliminating any "wandering" in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . The OUT pin is held low during this time and the IN pin has no control over the output. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tDIVCODE = 16 * (DIVCODE + 6) * tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. However, if the delay timing is active during the transition, the actual delay can take on a value between the two settings. DIV 500mV/DIV 512s 256s OUT 2V/DIV 699412 F07a 500s/DIV LTC6994-1 V+ = 3.3V RSET = 200k During start-up, the DIV pin A/D converter must determine the correct DIVCODE before the LTC6994 can respond to an input. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not extend the start-up time. At the end of tSTART the DIVCODE and IN pin settings are recognized, and the state of the IN pin is transferred to the output (without additional delay). If IN is high at the end of tSTART, OUT will go high. Otherwise OUT will remain low. The LTC6994-2 with POL = 1 is the exception because it inverts the signal. At this point, the LTC6994 is ready to respond to rising/falling edges on the input. IN 2V/DIV 4s tSTART(TYP) = 500 * tMASTER V+ Figure 7a. DIVCODE Change from 0 to 2 IN DIV 500mV/DIV tSTART (IN IGNORED) 512s OUT IN 2V/DIV 256s tPD IF IN = 1 AT END OF tSTART* IF IN = 0 AT END OF tSTART* *LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT 4s OUT 2V/DIV 699412 F08 Figure 8. Start-Up Timing Diagram LTC6994-1 V+ = 3.3V RSET = 200k 500s/DIV 699412 F07b Figure 7b. DIVCODE Change from 2 to 0 699412fb 15 LTC6994-1/LTC6994-2 Applications Information Basic Operation The simplest and most accurate method to program the LTC6994 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a 3-step process. Alternatively, Linear Technology offers the easy-to-use TimerBlox Designer tool to quickly design any LTC6994 based circuit. Download the free TimerBlox Designer software at www.linear.com/timerblox. Step 1: Select the LTC6994 Version and POL Bit Setting. Choose LTC6994-1 to delay one (rising or falling) input transition. The POL bit then defines which edge is to be delayed. POL = 0 delays rising edges. POL = 1 delays falling edges. Choose LTC6994-2 to delay rising and falling edges. Set POL = 0 for normal operation, or POL = 1 to invert the output. Step 2: Select the NDIV Frequency Divider Value. As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given delay time (tDELAY), NDIV should be selected to be within the following range: t tDELAY NDIV DELAY 16s 1s (1) To minimize supply current, choose the lowest NDIV value. However, in some cases a higher value for NDIV will provide better accuracy (see Electrical Characteristics). Table 1 can also be used to select the appropriate NDIV values for the desired tDELAY . Select the standard resistor value closest to the calculated value. Example: Design a circuit to delay falling edges by tDELAY = 100s with minimum power consumption. Step 1: Select the LTC6994 Version and POL Bit Setting. To delay negative transitions, choose the LTC6994-1 with POL = 1. Step 2: Select the NDIV Frequency Divider Value. Choose an NDIV value that meets the requirements of Equation (1), using tDELAY = 100s: 6.25 NDIV 100 Potential settings for NDIV include 8 and 64. NDIV = 8 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 1 and NDIV = 8 requires DIVCODE = 14. Using Table 1, choose R1 = 102k and R2 = 976k values to program DIVCODE = 14. Step 3: Select RSET . Calculate the correct value for RSET using Equation (2). RSET = 50k 100s * = 625k 1s 8 Since 625k is not available as a standard 1% resistor, substitute 619k if a -0.97% shift in tDELAY is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. The completed design is shown in Figure 9. With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. Step 3: Calculate and Select RSET . 16 50k tDELAY * 1s NDIV OUT LTC6994-1 GND (2) 2.25V TO 5.5V V+ 0.1F SET The final step is to calculate the correct value for RSET using the following equation: RSET = IN RSET 625k DIV R1 102k DIVCODE = 14 R2 976k 699412 F09 Figure 9. 100s Negative-Edge Delay 699412fb LTC6994-1/LTC6994-2 Applications Information Voltage-Controlled Delay Digital Delay Control With one additional resistor, the LTC6994 output delay can be manipulated by an external voltage. As shown in Figure 10, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the delay as described in Equation (3): The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled delay. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC's reference voltage, as shown in Figure 11. The DAC's output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC's REF input would affect the delay. tDELAY = NDIV *RMOD * 50k 1s IN GND VCTRL ISET Extremes (Master Oscillator Frequency Extremes) OUT V+ LTC6994 RMOD (3) R V 1+ MOD - CTRL RSET VSET SET V+ C1 0.1F When operating with ISET outside of the recommended 1.25A to 20A range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. R1 DIV RSET R2 The oscillator will still function with reduced accuracy for ISET < 1.25A. At approximately 500nA, the oscillator will stop. Under this condition, the delay timing can still be initiated, but will not terminate until ISET increases and the master oscillator starts again. 699412 F10 Figure 10. Voltage-Controlled Delay At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. IN OUT V+ LTC6994 0.1F V+ GND + SET 1/2 LTC6078 0.1F DIN P CLK CS/LD GND 699412 F11 N *R tDELAY = DIV MOD * 50k VOUT R1 R2 REF LTC1659 C1 0.1F DIV - V+ VCC V+ RMOD DIN = 0 TO 4095 1s RMOD DIN 1+ - RSET 4096 RSET Figure 11. Digitally Controlled Delay 699412fb 17 LTC6994-1/LTC6994-2 Applications Information Settling Time Following a 2x or 0.5x step change in ISET , the output delay takes approximately six master clock cycles (6 * tMASTER) to settle to within 1% of the final value. An example is shown in Figure 12, using the circuit in Figure 10. VCTRL 2V/DIV Even an excellent layout will allow some coupling between IN and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this. Figure 13 shows that /1 supply variation is dependent on coupling from rising or falling inputs. A very poor layout can actually degrade performance further. The PCB layout should avoid routing SET next to IN (or any other fast-edge, wide-swing signal). IN 5V/DIV OUT 5V/DIV 1.0 DELAY 2s/DIV 0.6 0.8 20s/DIV Figure 12. Typical Settling Time Coupling Error The current sourced by the SET pin is used to bias the internal master oscillator. The LTC6994 responds to changes in ISET almost immediately, which provides excellent settling time. However, this fast response also makes the SET pin sensitive to coupling from digital signals, such as the IN input. FALLING EDGE DELAY 0.4 699412 F12 DRIFT (%) LTC6994-1 V+ = 3.3V DIVCODE = 0 RSET = 200k RMOD = 464k tOUT = 3s AND 6s 0.2 0 RISING EDGE DELAY -0.2 -0.4 -0.6 RSET = 50k NDIV = 1 -0.8 -1.0 2 3 4 SUPPLY (V) 6 5 699412 F13 Figure 13. Delay Drift vs Supply Voltage 699412fb 18 LTC6994-1/LTC6994-2 Applications Information Power Supply Current The Electrical Characteristics table specifies the supply current while the part is idle (waiting for an input transition). IS(IDLE) varies with the programmed tDELAY and the supply voltage, as described by the equations in Table 2, valid for both the LTC6994-1 and LTC6994-2. Table 2. Approximate Idle Supply Current Equations CONDITION TYPICAL IS(IDLE) V + * (NDIV * 7pF + 4pF ) NDIV 64 tDELAY Table 3. Active Increase in Supply Current CONDITION DEVICE LTC6994-1 NDIV 64 V+ + + 2.2 *ISET + 50A 500k V + *NDIV * 7pF V+ + + 1.8 *ISET + 50A 500k tDELAY NDIV 512 IS(ACTIVE) can be estimated using the equations in Table 3, assuming a periodic input with frequency fIN. The equations assume the input pulse width is greater than tDELAY; otherwise, the output will not transition (and the increase in supply current will be less). When an input transition starts the delay timing circuity, the instantaneous supply current increases to IS(ACTIVE). LTC6994-2 NDIV 512 Either Version TYPICAL IS(ACTIVE)* + fIN * V * (NDIV * 5pF + 18pF + CLOAD) fIN * V+ * (NDIV * 10pF + 22pF + CLOAD) fIN * V+ * CLOAD *Ignoring resistive loads (assumes RLOAD = ) Figures 14 and 15 show how the supply current increases from IS(IDLE) as the input frequency increases. At higher NDIV settings, the increase in active current is smaller. IS(ACTIVE) = IS(IDLE) + IS(ACTIVE) 250 V+ = 3.3V INPUT PULSE WIDTH = 1.1 * tDELAY POWER SUPPLY CURRENT (A) POWER SUPPLY CURRENT (A) 250 200 /1, RSET = 50k 150 /8, RSET = 50k /1, RSET = 100k 100 /1, RSET = 800k 50 0.2 /1, RSET = 50k /8, RSET = 50k 150 /1, RSET = 100k 100 /1, RSET = 800k 50 CLOAD = 5pF RLOAD = CLOAD = 5pF RLOAD = 0 "IDLE" 200 V+ = 3.3V fIN < 1/(2 * tDELAY) TO ALLOW RISING AND FALLING DELAYS TO REACH THE OUTPUT 0.6 0.4 fIN * tDELAY 0.8 1.0 699412 F14 Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1 0 "IDLE" 0.1 0.3 0.2 fIN * tDELAY 0.4 0.5 699412 F15 Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2 699412fb 19 LTC6994-1/LTC6994-2 Applications Information Supply Bypassing and PCB Layout Guidelines The LTC6994 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 16 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6994. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1's connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1's GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1F ceramic capacitor. IN 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the output delay. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. OUT LTC6994 GND SET V+ V+ C1 0.1F R1 DIV RSET R2 V+ R1 R2 V+ C1 C1 V+ OUT IN OUT DIV GND GND V+ SET IN SET DIV R1 RSET RSET R2 699412 F16 DCB PACKAGE TSOT-23 PACKAGE Figure 16. Supply Bypassing and PCB Layout 20 699412fb LTC6994-1/LTC6994-2 Typical Applications Delayed One-Shot IN OUT IN TRIG LTC6994-1 GND DELAYED PULSE OUT OUT LTC6993-1 5V V+ GND 5V V + 0.1F SET DIV SET 604k 0.1F 1M DIV 121k tRISE_DELAY = 50ms 392k tONESHOT = 10ms IN DELAY 50ms OUT SHOT 10ms DELAY SHOT 699412 TA02 Pulse Stretcher IN OUT OUT IN LTC6994-1 V+ GND V+ 0.1F SET 787k 182k DIV 976k tMIN = 1ms OUTPUT PULSE DURATION = tPULSE_IN + 1ms IN OUT tMIN tMIN 699412 TA03 V+ OR Switch/Relay Debouncer OUT IN V+ OUT CHATTER LTC6994-2 GND V+ V+ 0.1F SET 154k 1M STABLE OR CHATTER STABLE DIV t = 100ms 523k 699412 TA04 OUTPUT GOES TO SAME FINAL LEVEL OF INPUT AFTER STABLE FOR 100ms 699412fb 21 LTC6994-1/LTC6994-2 Typical Applications Edge Chatter Filter IN OUT OUT IN LTC6994-2 GND V+ SET DIV 499k V+ 0.1F 10s INPUT MUST BE STABLE FOR AT LEAST 10s IN OUT 10s NORMAL 10s 10s NOISY EDGES 10s 699412 TA05 Crossover Gate--Break-Before-Make Interval Timer V+ LOAD LOW IN OUT IN 100k FALLING DELAYED P TP0610 LTC6994-1 LOAD HIGH GND V+ V+ 0.1F SET 787k DIV 100k VLOAD IN LOAD 442k tDELAY = 1ms OUT IN V+ V+/2 VLOAD OFF OFF OFF GND 1ms OFF INTERVAL AT EACH TRANSITION 100k RISING DELAYED V+ N 2N7000 LTC6994-1 GND V+ V+ 0.1F SET 787k 100k 699412 TA06 DIV tDELAY = 1ms 699412fb 22 LTC6994-1/LTC6994-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DCB Package 6-Lead Plastic DFN (2mm x 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 0.70 0.05 3.55 0.05 1.65 0.05 (2 SIDES) 2.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 1.35 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 2.00 0.10 (2 SIDES) R = 0.05 TYP 3.00 0.10 (2 SIDES) 0.40 0.10 4 6 1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 x 45 CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 0.05 1 (DCB6) DFN 0405 0.25 0.05 0.50 BSC 1.35 0.10 (2 SIDES) 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 699412fb 23 LTC6994-1/LTC6994-2 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 - 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 - 0.90 0.20 BSC 0.01 - 0.10 1.00 MAX DATUM `A' 0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.90 BSC S6 TSOT-23 0302 REV B 699412fb 24 LTC6994-1/LTC6994-2 Revision History REV DATE DESCRIPTION A 7/11 Revised the Description section. PAGE NUMBER B 1/12 Added text to Basic Operation paragraph in the Applications Information section. Added MP-Grade. 1 16 1, 2, 4 Corrected sizing of the Typical Performance Characteristics curves G31 and G32. 8 699412fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 25 LTC6994-1/LTC6994-2 Typical Application Press-and-Hold (0.3s to 4s) Delay Timer V+ V+ ACTIVE HIGH OUT IN 100k 100k OUT LTC6994-1 GND SET V V+ V+ V+ GND 0.1F 0.1F 681k DIV RSET 576k 681k SET DIV 1M tDELAY 3s BOUNCE BOUNCE HOLD OUT OUT LTC6994-1 tDELAY 3s IN OUT IN + 1M RSET 576k ACTIVE LOW DELAY IN HOLD OUT DELAY 699412 TA07 RSET (k) = 190 * tDELAY (SECONDS) Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35A at 400kHz LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110s Start-Up Time, 105A at 32kHz LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation LTC6991 TimerBlox: Resettable Low Frequency Oscillator Clock Periods up to 9.5 hours LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range LTC6993 TimerBlox: Monostable Pulse Generator (One-Shot) Resistor-Programmable Pulse Width of 1s to 34s 699412fb 26 Linear Technology Corporation LT 0112 REV B * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2010