TSS461CR - Atmel Corporation - Datasheet.Directory

4193G–AUTO–12/04

Features

•Fully Compliant to VAN Specification ISO/11519-3

•Handles All Specified Module Types

•Handles All Specified Message Types

•Handles Retransmission of Frames on Contention and Errors

•3 Separate Line Inputs with Automatic Diagnosis and Selection

•1 Mbit/s Maximum Transfer Rate

•Normal or Pulsed (Optical and Radio Mode) Coding

•Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor

Interface

•Multiplexed Address and Data Bus

•Idle and Sleep Modes

•128 Bytes of General-purpose RAM

•DMA Capabilities for Message Handling

•14 Identifier Registers with All Bits Individually Maskable

•6-source Maskable Interrupt, Including an Interrupt-on-reset to Detect Glitches on the

Reset Pin

•Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and

Buffered Clock Output

•Single +5V Power Supply

•0.8 µm CMOS Technology

•SO24 Package

Description

Cost optimiz ation in c ar manufacturi ng is of extre me importance today. Solution s to

this problem often implies the use of more advanced and intelligent electronic circuits.

The TSS461C is a circuit which allows the transfer of all the status information needed

in a car or truck over a single low-cost wire pair, that minimizes the electrical wir e

usage.

It can be used to interconnect powerful functions (ABS, dashboard, power train con-

trol) and to control and interface car body el ectronics (lights, wipers, power window,

etc.).

The TSS461 C is fully compliant wi th the ISO Standard 115 19-3. This standard sup-

ports a wide range of applications such as low-cost remote-control switches. Typically

it is used for lamp control; complex, highly-autonomous, distributed systems like

engine controls, which require fast and secure data transfers.

The TSS461C is a microprocessor-interfaced line controller for mid-to-high complexity

bus-masters and listeners like injection/ignition control calculators, dashboard control-

lers and car stereo or mobile telephone CPUs.

The micropr ocessor interface consists of a 256-b ytes of RAM and a register area

divi ded into 11 con trol regis ters, 14 c hannel re gister s ets a nd 128 bytes of gener al

purpose RAM, used as a message storage area, and a 6-source maskable interrupt.

The circuit operates in RAM using DMA techniques, controlled by the channel and

control registers. This allows virtually any microprocessor to interface with ease to the

TSS461C, and to use the free RAM as a scratch pad.

Messages are encoded in enhanced Manchester code, and an optional pulsed code

for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461C

analyzes the messages received or transmitted according to 6 different criteria includ-

ing some higher level checks.

In additi on, the bus i nte rface ha s t hr ee se parate in puts with auto mati c s ourc e di ag no-

sis and selec tion, that allows for multibus list ening or the automatic selection of the

most reliable s ource at any time if sev eral line receivers ar e connected to the sam e

bus.

VAN Data Link

Controller

TSS461C

2TSS461C 4193G–AUTO–12/04

Block Diagram

Message ID registers

RAM

128 bytes

buffer

Protocol controller

state machine and

Data serializer and

deserializer

Clock generator and

line synchronization

logic

Multiplexing logic Status and

control

registers

Reception logic

CRC generator

and checker

Transmission logic

Source diagnosis

and selection logi

AD[7:0] ALE

control bus

data bus

address bus

INT

XTAL1 XTAL2 CKOUT TxD

status bus

RxD0 RxD1 RxD2

RESET TEST VCC GND

Address and Data Bus

TSS461C

4193G–AUTO–12/04

Pin Configuration

Note: 1. The names in parenthesis refer to the functionalities in Motorola mode.

1 24

2 23

3 22

4 21

5 20

6 19

7 18

8 17

AD4

AD5

AD6

AD7

VCC

INT

(E) C S

XTAL1

TOP VI EW

9 16

10 15

11 14

12 13

ALE

XTAL2

Test/VSS

CKOUT

AD3

AD2

AD1

AD0

VSS

RESET

RXD0

RXD2

TXD

RXD1

WR (R/W)

RD (VSS)

24 Pin SOP

I/O Type Pin Name Pin Number Pin Function

I/O TTL AD0 21 Multiplexed address and

data bus. The address is

latched on the falling

address of ALE.

AD1 22

AD2 23

AD3 24

AD4 1

AD5 2

AD6 3

AD7 4

I Trigger TTL ALE 7 Addr ess Latch Enable

RD (VSS) 13 Read Com man d

WR (R/W) 14 Write Command

CS(E) 8 Chip Select (active high)

Open-drain INT 6 Interrupt

I Trigger CMOS Pull-down RESET 19 Asynchronous general

reset glitch filtered

(12 ns)

4TSS461C 4193G–AUTO–12/04

I CMOS Pull-down RXD0 17 VAN bus Inputs

RXD1 15

RXD2 16

3-state TXD 18 VAN bus Output

IXTAL1 9 Crys tal oscil lator or clo ck

input pins

0XTAL2 10

0CKOUT 12 Buffered clockout output

enabled if no reset

Ground TEST/VSS 11 Oscillator Gro und

Power VCC 5 +5V Power Supply

Ground VSS 20

I/O Type Pin Name Pin Number Pin Function

TSS461C

4193G–AUTO–12/04

Operation The TSS461C is a microprocessor-controlled line controller for the VAN bus. It can inter-

face to virtually any microprocessor, but the I/O signals of the circuit have been

optimized to use with the TSC51/TSC251 series of microcontrollers.

It features a multiplexed address and data bus, controlled by an address strobe pin ALE

and se par at ed re ad RD and write WR command pins. The address is latched on the fall-

ing edge of ALE.

The circuit also features one single interrupt pin. This pin can be treated as level or edge

sensitive, For example, if there is a pending interrupt inside the circuit when another

interrupt is reset, the INT pin will emit a high pulse with the same pulse width as the

internal write strobe (typically 20 ns).

Figure 1. Typical Application

Remaining Pins

TSS461C

Microcontroller

Series

P3.6/WR

P3.7/RD

ALE

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

ALE

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

XTAL1 XTAL2

TXD

RXD0

RXD1

RXD2

VAN

DLC

INT CKOUT RESETRESET XTAL1 INT VCC

33 pF

GND GND

VREF

DATA

Differential

DATA

VAN Bus

VAN Line Driver

& Receivers

General I/O

6TSS461C 4193G–AUTO–12/04

Microprocessor

Interface The proces s or controls the TS S4 61C b y read ing and writing the i nter na l regi st er s of th e

circuit. These registers appear to the processor as regular memory locations.

Interface Modes The TSS461C must be plugged in an Intel or Motorola environment with an 8-bit

addres s/data bus multi plex ed.

Table 1. Access M ode Logic

In Intel environment, ac cess operations need CS ac tive, a read one with RD active , a

write one with WR active. If TSS461C is the single per ipheral in the processor space,

CS can be wired to VCC.

In Motorola environment, the RD pin is wired to VSS and the access operations are

dri ve n by CS (E). C o ntrary to I nte l mo d e, C S (E) must never be wi r e d t o V CC even if t he

TSS461C is alone.

To switch on-the-fly from one mode to the other, CS must be inactive.

Intel Mode The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and

data bus, and the rest are the address strobe, the read and write commands, the chip

select and the interrupt request pins.

To access the memory locations in Intel mode, the proces sor must first assert a valid

address on the multiplexed address and data bus and drive the address strobe pin high.

When the r eq ui red s etup ti me h as pas s ed, t he p roce ss or mu st drive th e ad dr es s strob e

low, and keep the address valid for the required hold time.

The processor must then either assert the data to be written on the addr ess and data

bus, if a write is intended, or float the data bus for a read. The next step is to drive either

the write or read command pins low, according to the function required, and at the same

time drive the chip select pin high.

The TSS46 1C access cy cle is then termi nated by driv ing the chip sele ct and comman d

pins low.

Note: that the chip select pin may be driven high for the entire access cycle, and may also

remain high during and after the termination of the cycle.

CS (E) RD WR (R/W)Operation Mode

0No operation

10 0

Write Operation in Motorola mode

10 1

Read operation in both modes

11 0

Wr ite operati on in Inte l mod e

11 1

No operation

TSS461C

4193G–AUTO–12/04

Figure 2. Intel Read and Write Cycles

Motorola Mo de In Motorola mode, the WR pin becomes the R/W command, the RD pin mu st be con-

nected to ground and the CS pin becomes the E strobe. There is no separate chip select

input. F or example , if some exter nal decode r is used, thi s decoder should not dr ive the

E input high unless the processors E output is high as well.

See F igure 3 for the M otor ola rea d and wri te cyc les. The ma in d iffer ence bet ween I ntel

and Motorola mode is that the timing in Intel mode is referenced to the command signals

(RD and WR), but in Motorola mode the reference is the E signal.

Figure 3. Motorola Read and Write Cycles

Interrupts If an ev ent o ccur s in the T SS461C that nee ds the at tent ion of the pr oces so r, t his will b e

signalled on th e a ctiv e l ow, ope n- drai n i nte rrup t req ues t pin . T h e e ve nts th at c r eat e t his

reques t are contro ll ed by the int er nal regi ste r s.

Every time the microprocessor accesses any of the interrupt registers (addresses 0x08

to 0x0 B), the IN T pin will be released mo mentarily. This enables the TSS461C to work

with processors that either have edge or level sensitive interrupt inputs.

ALE

AD[7:0]

ADDRESS DATA TO BE

WRITTEN ADDRESS DATA

READ

WRITE CYCLE READ CYCLE

ALE

AD[7:0]

VSS (RD)

R/W (WR)

E (CS)

ADDRESS DATA TO BE

WRITTEN ADDRESS DATA

READ

WRITE CYCLE READ CYCLE

8TSS461C 4193G–AUTO–12/04

Reset T he reset is appli ed async hrono usly reg ardin g XTAL cl ock . It can be don e either by the

RESET pin or by software. The RESET pin is a CMOS trigger input with a pull-down

resistor (110 kΩ). An external 1 µF capacitor to VCC provides to RESET pin an efficient

behavior.

The software reset is made through the GRES command bit of the Command Regist er

(0x03).

The two resets are ored, filtered and gauged. Then the internal reset, always asserted

asynchronously, enables the internal oscillator. Then it waits for eight clock periods for

the oscillator stability.

The different blo cks of the TSS461C need to be turned on synchronously. So the

release of the internal reset is synchr onous and a loose clock can let the TSS461C in

permanent reset after applying Reset.

TSS461C

4193G–AUTO–12/04

Oscillator An oscillator is integrated in the TSS461C, and consists of an inverting amplifier which

the input is XTAL1 and the output XTAL2.

A par allel re sonan ce quar tz cry stal o r ceram ic reso nator m ust be connect ed to these

pins. As shown in Figure 1, two capacitors have to be connected from the crystal pins to

ground. The values of C1 depend on the frequency chosen and can be selected using

the graphic given in Figure 33.

If the osc illator is not use d, then a cl ock sign al must be fed to the ci rcuit vi a the XTAL 1

input.

Note, t hat this pin will beh ave as a CMOS l evel c ompati ble S chmitt trigger inpu t. In t his

case, the X TAL2 output sho uld b e le ft unc onnec ted. The os cill ator also featu res a buff-

ered clock output pin CKOUT. The signal on this pin is directly buffered from the XTAL1

input, without inversion.

There is on e more pin u sed for the osc illator. The TE ST/VSS pin i s in fact its g round,

and unless this pin is firmly connected to ground, with decoupling capacitors, the oscilla-

tor will not operate correctly.

The tes t mode itse lf, i.e., when the TEST/V SS pin is he ld high, is only intend ed for fac-

tory use, and the functionality of this mode is not specified in any way.

Furthermor e, it is s ubject to c hange witho ut notice, the only exc eption is for incoming

inspection tests using the test program.

The clock signal is then fed to the clock generator generate all the necessary timing sig-

nals for the operation of the circuit. The clock generator is controlled by a 4-bit code

called the cl oc k div id er .

FTSCLK FXTAL1

n16×

------------------

10 TSS461C 4193G–AUTO–12/04

Table 2. Clock Divider

Clock

Divider Divide by

8 MHz 6 MHz 4 MHz 2 MHz

KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s KTS/s Kbits/s

0000 1 500 400 375 300 250 200 125 100

0001 2 250 200 187.50 150 125 100 62.50 50

0010 4 125 100 93.75 75 62.50 50 31.25 25

0011 8 62.5 50 46.875+ 37.5 31.25 25 15.625 12.5

0100 16 31.25 25 23.438 18.75 15.625 12.5 7.813 6.25

0101 32 15.625 12.5 11.718 9.375 7.813 6.25 3.906 3.125

0110 64 7.813 6.25 5.859 4.688 3.906 3.125 1.953 1.562

0111 128 3.906 3.125 500 400 1.953 1.562 166.666 133.333

1000 1.5 333.333 266.666 250 200 166.666 133.333 83.333 66.666

1001 3 166.666 133.333 125 100 83.333 66.666 41.666 33.333

1010 6 83.333 66.666 62.50 50 41.666 33.333 20.833 16.666

1011 12 41.666 33.333 31.25 25 20.833 16.666 10.416 8.333

1100 24 20.833 16.666 15.625 12.50 10.416 8.333 5.208 4.166

1101 48 10.416 8.333 7.813 6.25 5.208 4.166 2.604 2.083

1110 96 5.208 4.166 3.906 3.125 2.604 2.083 1.302 1.042

1111 192 2.604 2.083 1.953 1.5625 1.302 1.042 0.651 0.521

TSS461C

4193G–AUTO–12/04

VAN Protocol

Line Interface There are three line inputs and one line output available on the TSS461C. The three

inputs are either programmed by software or automatically selected by a diagnosis

system.

The diagnosis system continuously monitors the data received through the three inputs,

and compares them and the selected bitrate. It then chooses the most reliable input

according to the results.

The data on the line is encoded according to the VAN standard ISO/11519-3. This

means that the TSS4 61C is usin g a two- level si gnal hav ing a re cess ive (1) and a domi-

nant (0) state . Further more, due to the simp le medi um used , all data tran smitt ed on the

bus is also rece iv ed simul taneously.

Consequen tly, the VAN protocol is a CSMA/CD (Ca rrier Sense Multip le Access/Colli-

sion Dete ction) pr otoc ol, allowi ng for con tin uous bi twise ar bitratio n of the bu s, and non-

destructive (for the higher priority message) collision detection.

Figure 4. CSMA/CD Arbitration

In addition to the VAN specific ation there is also a pulsed c oding of the dominant and

recessive states. This mode is intended to be used with an optical or radio link. In this

mode, the dominant state for the transmitter is a low pu lse, (2x prescaled clocks at the

beginning of the bit) and the r ecessive state is just a high level. When receiving in this

mode, it is not the state of the signal which is decoded, but the edges. Also, reception is

imposed on the RxD0 input, and the diagnosis system does not operate correctly.

In addition, in this mode there is an internal loopback in the c ircuit since optical trans-

ceivers are not able to receive the signal that they transmit.

Node a: TxD

Node a loses the arbitration

Node a releases the bus

Node b wins the arbitration

Node c loses the arbitration

Node c releases the bus

Node b: TxD

Node c: TxD

On Bus: DATA

Arbitration field

R: Recessive Level D: Dominant Level

12 TSS461C 4193G–AUTO–12/04

In Figure 5 the pulsed waveforms are shown. In Figure 8 through Figure 14 the low

"timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominan t

waveform showed in Figure 5, to obtain the correct representations for pulsed coding.

Figure 5. State Encoding

VAN Frame Figure 6. VAN Bus Frame

The VAN bus supports three different module (unit) types:

1. The Autonomous module, which is a bus master. It can transmit Start Of Frame

(SOF) sequences, it can initiate data transfers and can receive messages.

2. The Synchronous access module. It cannot transmit SOF sequences, but it can

initiate data transfers and can receive messages.

3. The Slave module, which can only transmit using an in-frame mechanism and

can receive messages.

Figure 7. Hierarchical Access Methods

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

NORMAL OR PULSED RECESSIVE STATE

NORMAL DOMINANT STATE

PUSED DOMINANT STATE

0481216

2 6 10 14

SOF Identifier

Field

Command Data

Field

Frame

Check

Sum EOD ACK EOF

EXT RAK R/W RTR

SOF ID COM DATA ACK EOF

EOD

Autonomous

ank 0

ID COM DATA FCS ACK EOF

EOD

Synchronous

ank 1

DATA FCS ACK EOFEOD

Slave

ank 16

RTR

FCS

TSS461C

4193G–AUTO–12/04

Figure 6 s hows a normal VA N bus frame. It is initi ated with a Start of Frame (SOF)

sequence shown in Figure 8. The SOF can only be transmitted by an autonomous mod-

ule. During the preamble, the TSS461C will synchronize its bit rate clock to the data

received.

Figure 8. Framing Sequences

When the complete SOF sequence has been transmitted or received, the circuit will

start the transmission or reception of the identifier field.

All data on the VAN bus, including the identifier and Frame Check Sum (FCS), are

transmitted using enhanced Manchester code.

In enhanc ed Manchester c ode, three NRZ bits are tran smitted first foll owed by one

Manchester bit, then three more NRZ bits followed by one Manchester bit and so on.

Since the high state is recessive and the low state is dominant, the bus arbitration can

be done. If a module wants access to the bus, it must first listen to the bus during one

full End of Frame (EOF) and one full Inter Frame Spacing (IFS) period, to determine

whether the bus is free or not (i.e., no dominant states received).

Figure 9. Data Encoding

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

PREAMBLE

START OF FRAME

START

SYNC

END OF

DATA ACK END OF FRAME

0 16 32 48 64 80 96 112 128 144 160 176 192

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

NRZ 0  NRZ 1

MANCHESTER 0

MANCHESTER 1

0 8 16 24 32

14 TSS461C 4193G–AUTO–12/04

The IFS is defined to be a minimum of 64 prescaled clocks periods. The TSS 461C,

accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence.

Once the bu s is free, the modul e must now , if it is an auton omo us module em its a SO F

sequence or, if it is a synchronous access module, wait until it detects a preamble

sequence.

Until this point there can be several modules transmitting on the bus, and there is no

poss ibility of knowing if this is the case or not. Th erefor e, the fi rst fiel d in which a rbitra-

tion can be performed is the identifi er field. Sinc e the logical zeroes on the b us are

domina nt, and all dat a is transmi tted with the mo st signific ant bit (MSB) fi rst, the firs t

module to tr a nsm it a logical ze ro on th e bu s wi ll be th e pr io riti ze d mo dul e, i .e., th e me s-

sage that is tagged with the lowest identifier will have priority over the other messages.

However it is possible that two messages transmitted on the bus will have the same

identifier. The T SS461C therefore, continues the arbitration of the bus throughout the

whole frame. In addition, if the identifier in transmission has been programmed for

recep tion as well, it tran smits an d rece ives messag es simultan eously, righ t up til l the

Frame Check Sequence (FCS) . Only then, i f the TSS461C has transmitted the whole

message. It discards the message received. Arbitration loss in the FCS field is consid-

ered as a CRC error during transmission.

This feature is called full data field arbitration, and it enables the user to extend the iden-

tifier. For instance, it can be used to transmit the emitting modules address in the first

bytes of the data field, thus enabling the identifier to specify the contents of the fr ame

and the data field to specify the source of the information.

The identifier field of the VAN bus frame is always 12 bits long, and it is always followed

by the 4-bit command field:

• The first bit of the command is the extension bit (EXT). This bit is defined by the

user on transmission and is received and retained by the TSS461C. To conform with

the standard, it should be set to 1 (recessive) by the user, else the frame is ignored

without any IT generation.

• The second bit is the request ACKnowledge bit (RAK). If this bit is a logical one, the

receiving module must acknowledge the transfer with an in-frame

acknowledgement in the ACK field. If it is set to logical zero, then the ACK field must

contain an acknowledge absent sequence.

• The third bit is the Read/Write bit (R/W). This bit indicates the direction of the data in

a frame.

– If set to zero it is a "write" message, i.e. data transmitted by one module to

be received by another module.

– If it is set to one it implies a "read" message, i.e., a request that another

module should transmit data to be received by the one that requested the

data (reply request message).

• Last in the command field is the Remote Transmission Request bit (RTR). This bit is

a logical zero if the frame contains data and a logical one if the frame does not

contain data. In order to conform with the standard a received frame included the

combination R/W. RTR = 01 is ignored without any IT generation.

All the bits in the command field are automatically handled by the TSS461C, so the user

doesn’t need to b e c oncer ne d for e ncodi ng a nd d e codi ng t hes e b its. T he co mma nd b its

transmitted on the VAN bus are calculated from the current status of the active

message.

TSS461C

4193G–AUTO–12/04

After the co mma nd field com es the data field. T his is jus t a sequen ce of byt es tran smit-

ted, MSB first. In the VAN standard, the maximum message l ength is set to 28 bytes,

but the TSS461C handles messages up to 30 bytes.

The next field is the FCS field. This field is a 15-bit CRC checksum defined by the follow-

ing generator polynomial g(x) of order 15:

g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1

The division is done with a rest initialized to 0x7FFF, and an inversion of the CRC bits is

performed befo re transmi s sion.

However, since the CRC is calculated automatically from the identifier, command and

data fields by the TSS461C, the user should not be concerned with the circuit. When the

frame c heck sequ ence has been trans mitted, the transmi tting mod ule must t ransmit an

End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of

Frame sequence (EOF) to terminate the transfer.

Figure 10. Acknowledge Sequences

Frame Examples The frames transmitted on the VAN bus are generated by several modules, each sup-

plying different parts of the message. Figure 11 through Figure 14 show the four frame

types specified in the VAN standard, and what module is generating the different fields.

• The most straightforward frame is the normal data frame in Figure 11. Like all other

frames it is initiated with a SOF sequence. This sequence is generated by a bus

master (not shown in the figure).

• During this frame, there is basically only one module transmitting with the exception

of the acknowledgement, generated by the receiving module if requested in the

RAK bit.

• The reply request frame with immediate reply in Figure 12 is the only frame in which

a slave module can transmit data by filling it into the appropriate field.

• The difference for the frame on the bus is that the R/W bit has changed state

compared to the normal frame.

• This is a highly interactive frame where a bus master generates the SOF and the

initiator generates the identifier, the three first bits of the command, and the

acknowledge. The RTR bit, the data field, the frame check, the EOD and the EOF

are all generated by the replying module.

• The reply request frame with deferred reply in Figure 13 is the same frame as the

reply request frame with immediate reply. But since the requested module does not

VAN BUS

SEQUENCE

VAN BUS

SEQUENCE

NUMBER OF

PRESCALED

CLOCKS

POSITIVE ACKNOWLEDGE

ABSENT ACKNOWLEDGE

0 8 16 24 32

16 TSS461C 4193G–AUTO–12/04

generate the RTR bit, the requesting module will continue with the frame check, the

EOD and the EOF.

• During this frame, the requested module will only generate the acknowledge, and

only if this was requested by the initiator through the RAK bit.

• Finally, the deferred reply frame in Figure 14, which is sent when a module has

prepared a reply for a reply request that has been received earlier.

This frame is similar to the normal data frame with the exception being the R/W bit

that has chan ged state.

Figure 11. Normal Data Frame

FRAME

on Bus

TRANSMITTING

FRAME

on Bus

TRANSMITTING

Module

CRC

SOF

IDENTIFIER

DATA

EOF

Module

RECEIVING

Module

RECEIVING

Module

: Positive from Receiver because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Transmitter

: Recessive from Transmitter

: Dominant from Transmitter

: Dominant from T ransmitter – (*) Manchester bit

With Acknowlegment

Without Acknowlegment

: Absent from Transmitter and from Receiver because RAK is Dominant

RAK

EXT

R/W

RTR

ACK

: Dominant for no acknowledge from Transmitter

: Recessive from Transmitter

: Dominant from Transmitter

: Dominant from Transmitter– (*) Manchester bit

EXT

RAK

R/W

RTR

(*)

EXT

RAK

R/W

RTR

(*)

EXT

RAK

R/W

RTR

(*)

EXT

RAK

R/W

RTR

(*)

EOD

ACKACK

EOD

ACK

EOD

ACK

EOD

ACK

TSS461C

4193G–AUTO–12/04

Figure 12. Reply Request Frame with Immediate Reply

Figure 13. Reply Request Frame with Deferred Reply

(*)

SOF IDENTIFIER

RTR

FRAME

Module

REQUESTED

Module

REQUESTING

(*)

CRC

SOF IDENTIFIER DATA

DATA EOF

EOF

on Bus

: Absent from Requestee and Positive from Requestor because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Requestor

: Recessive from Requestor

: Recessive from Requestor and Dominant from Requestee (*) Manchester bit

EXT

RAK

R/W

RTR

(*)

EOD

ACK ACK

EXT

RAK

R/W

RTR

EOD

ACK

SOF

RTR

IDENTIFIER

FRAME

on Bus

REQUESTING

(*)

CRC

SOF IDENTIFIER

EOF

Module

REQUESTED

Module

: Absent from Requestor and Positive from Requestee because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Requestor

: Recessive from Requestor

: Recessive from Requestor – (*) Manchester bit

EXT

RAK

R/W

EOD

ACK

EOD

ACK ACK

RTR

EXT

RAK

R/W

(*)

18 TSS461C 4193G–AUTO–12/04

Figure 14. Deferred Reply Frame

FRAME

on bus

module

REPLYING

CRC

CRCSOF

SOF

IDENTIFIER

IDENTIFIER DATA

DATA EOF

EOF

RECEIVING

module

: Absent from Replyer and Positive from Receiver because RAK is Recessive

RAK

EXT

R/W

RTR

ACK

: Recessive for acknowledge from Replyer

: Recessive from Replyer

: Dominant from Replyer - (*) Manchester bit

EXT

RAK

R/W

EOD

ACK

EOD

ACK ACK

EXT

RAK

R/W

(*) (*)

RTRRTR

TSS461C

4193G–AUTO–12/04

Diagnosis System The purpose of the diagnosis system is to detect any short or open circuits on either the

DATA or DATA l ines an d to per mit, if i t is pos sible, to carr y the co mmuni cation s on th e

non-defective line.

The diagnosis system is based on the assumption that three separate line receivers are

connected to the VAN bus (see Figure 3):

• One of the line receivers is connected in differential mode, sensing both DATA and

DATA signals, and is connected to the RxD0 input.

• The other two line receivers are operating in single wire mode and are sensing only

one of the two VAN bus signals:

– The line receiver sensing DATA is connected to RxD1

– The line receiver sensing DATA is connected to RxD2

The diagnosis system analyzes and compares the data sent over both VAN lines. So,

the diag nos is sy ste m ex ecutes a d igi tal fi lt er ing an d tra nsiti on an aly s es. In or de r to pe r-

form its inv estigation, three internal signa ls are generated, RI (Return to Idle), SDC

(Synchronous Diagnosis Clock) and TIP (Transmission In Progress).

One of four operating modes c an be chosen to manage the results of the diagnosis

system.

Diagnosis States If the diagnosis system finds a fail ure on any of the VAN bus signals , it changes from

nominal to degraded mode, and connects the line receiver not coupled to the failing sig-

nal to the reception logic.

When the diagnosis system finds that the failing signal is working again, it returns to

nominal mode and re-connects the differential line receiver to the reception logic.

A major error occurs when both the VAN bus signals fail.

Figure 15. Diagnosis States

Nominal

Major

Error Degraded

Data

Degraded

Data

- Failure during the frame.

- Default of transitions on the valid input between 2 consecutive SDC rising edges.

- Protocol fault

- In specified selection mode, every RI pulse when an EOF is detected or through an active SDC.

- In automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges.

- General reset.

20 TSS461C 4193G–AUTO–12/04

Status bits give permanent information on the diagnosis performed, whatever the pro-

grammed operating mode. This is encoded over three bits: Sa, Sb and Sc. Sa and Sb

bits indicate the four possible states of the VAN bus.

Table 3. Status Bits Sa and Sb

Notes: 1. Sc bit sets to 1 as soon as one of the three inputs (RXD2, RXD1, RXD0) differs from

the others in the input comparison analysis performed by the diagnosis system, S2 is

set.

2. The only way to reset this status bit is through the RI signal or a general reset.

Internal Operations

Digital Filtering If seve ral spurious pulses occur during one bit, the diagnosis for defective conductor

may occur. To avoid such errors, digital filters are implemented.

Filtering operation is based on sampling of the comparator output signals. A transition is

taken into account only if it is observed over five samples (1/16th of timeslot).

Transition Analyses These analyses are continuously done on the effective edges on comparators after digi-

tal filtering.

•Asynchronous diagnosis:

The asynchronous diagnosis is done by comparing the number of edges on DATA

and DATA.

If four edges are detected on one input and no edges on the other during the same

period, the second input is considered faulty and the diagnosis mode will change to

one of the degraded modes.

•Synchronous diagnosis :

The synchronous diagnosis counts the number of edges on the data input

connected to the reception logic during one SDC period.

Sa Sb Communication

0 0 Mode Nominal

Fault No fault on VAN bus

Status Differential communication DATA and DATA

0 1 Mode Degraded on DATA

Fault Fault on DATA

Status Communication on DATA

1 0 Mode Degraded on DATA

Fault Fault on DATA

Status Communication on DATA

1 1 Mode Major error

Fault Fault on DATA and DATA

Status No communication on DATA and DATA (attempt to

commu nicate alternati ve ly on DATA then DATA every

SDC period.

TSS461C

4193G–AUTO–12/04

If there are less than four edges during one SDC period, the diagnosis mode will

change to the major error mode.

•Transmission diagnosis:

The transmission compares RxD1 and RxD2 inputs (through the input comparators

and the filters) with the data transmi tted on TxD output.

At a time when the transmission logic generates a dominant (recessive transition),

the inputs can give different values. Taking into account the filtering delay, the bus

line seen as dominant is assumed to be correct, the other one, recessive, is

considered faulty. The diagnosis mode is changed to reflect that.

•Protocol fault:

The protocol fault is detected by counting the number of consecutive dominant

timeslots.

If eight consecutive timeslots are dominant, the diagnosis mode will change to the

major error mode.

Generation of Internal

Signals

RI Signal (Return to Idle) This signal is used to return to nominal mode in the three specified selection modes (see

Sect ion “Diag nosis St ates” and S ection “P rogramm ing Mode s”). Th e RI signal is dis-

abled in automatic selection mode.

The RI signal is a pulse generated when an EOF is detected. So, at the end of each

frame, regarding the diagnosis status bit Sa, Sb & Sc, the user can select its own

choice.

SDC Signal (Synchronous

Diagnosis Clock) This time base is used by diagnosis system in automatic selection mode (see

Section “Programming Modes”) when no event is recorded on the bus.

The S DC is gene rated eithe r by a spec ial SD C divide r conne cted t o the tim eslot c lock,

or manually. The SDC clock period must be longer compared to the timeslot duration.

A typical SDC period should be greater than the maximum frame length appearing on

the VAN network.

TIP Signal (Transmission in

Progress) This signal must be enabled to allow the transmission diagnosis (see Section “Transition

Analyses”).

The TIP turns on synchronously at the beginning of the transmission:

• For asynchronous bus access, the beginning of SOF;

• For synchronous bus access, the beginning of the identifier field; and

• For a request of in frame reply, the RTR bit of the command field.

The TIP turns off synchronously at the end of the transmission:

•after EOF;

• after a losing of arbitration or a code violation detection; and

• for a requester of in frame reply, when the arbitration is lost on RTR the bit.

This signal is not generated when the transmission logic only sends an ACK.

22 TSS461C 4193G–AUTO–12/04

Programming Modes Four progr amming mod es deter mine how to use the three diffe rent inputs and the diag-

nosis system.

• 3 specified selection modes

• 1 automatic se lection mode

Table 4. Programming Modes

Ma Mb Operati n g Mod e

0 0 Differential communication

0 1 Degraded communication on RxD2 (DATA)

1 0 Degraded communication on RxD1 (DATA)

1 1 Automatic selection according to the diagnosis status

TSS461C

4193G–AUTO–12/04

Registers The TSS461C memory map consists of three different areas, the Control & Status regis-

ters, the Channel Registers and the Message Data (or Mailbox).

Mapping

Figure 16. Memory Map

Notes: 1. All the non-specified addresses between 0x00 and 0x7F are considered as absent.

2. (r) means read-only register.

(w) means write-only register.

(r/w) means read/write register.

3. Value after RESET is found after register name. If no value is given, the register is not initialized at RESET.

0x70 to 0x77 (r/w)

Reserved

0x7C & 0x7D Reserved

Channe l 90x58 to 0x5F (r/w)

Channe l 100x60 to 0x67 (r/w)

0x17 (r/w )

Channe l 20x20 to 0x27 (r/w) 0x10 (r/w )

0x28 to 0x2F (r/w)

Channe l 5

0x78 (r/w )

0x79 (r/w )

0x7A (r/w)

0x7B (r/w )

Channel 13

0x78 to 0x7F (r/w)

0x38 to 0x3F (r/w) ID_Mas k [11..4]

ID_TA G [11..4]

ID_Mask [3..0]

0x11 (r /w)

0x12 (r/w )

0x13 (r/w )

0x14 & 0x15

0x16 (r/w )

Line Con trol (0x00)

0x01 (r/w) Transmit Control (0x0 2) 0x81 Data Byte 1

Diagnosis Control (0x00)

Command (0x00)

Line Status (0bx01xxx00 )

Transmit Status (0x00)

Last Message Status (0x00)

Last Error Status (0x00)

Reserved

Interrup t Status (0x80)

Interrup t En able (0x80)

0x00 (r/w)

0x02 (r/w)

0x03 (w)

0x04 (r)

0x05 (r)

0x06 (r)

0x07 (r)

0x08

0x09 (r)

0x0B (w) Interrupt Reset

0x0A (r/w )

0xFF Data Byte 127

0x80

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

Data Byte 0

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Data Byte 8

Data Byte 9

Data Byte 10

Data Byte 11

Data Byte 12

Channe l 4

Channe l 8

Channe l 6

Channe l 12

Channe l 1

Channe l 11

Channe l 7

Reserved

0x10 to 0x17 (r/w)

0x30 to 0x37 (r/w)

0x50 to 0x57 (r/w)

0x40 to 0x47 (r/ w )

0x18 to 0x1F (r/w)

0x68 to 0x6F (r/w)

0x48 to 0x4F (r/w)

0x0C to 0x0F

ID_TAG [3..0] + COM

DRAK + Message Address

Message Length + Status

Reserved

Channel 0 Registers

Channel 0

ID_TAG (lsb) + COM

ID_TAG (msb)

DRAK + Message Address

Message Length + Status

0x7E (r/w )

Channel 13 Registers

ID_Mask [11..4]

0x7F (r/w) ID_Mask [3..0 ]

ID_Mask [11..4]

Channe l 3

Channel 13

Chann el 2

0x17 (r/w)

24 TSS461C 4193G–AUTO–12/04

Control and Status

Registers

Line Control Register (0x00)

• Read/write register.

• Default value after reset: 0y00

• reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this

bit.

CD[3:0] Clock Divider They control the VAN Bus rate through a Baud Rate generator according to the follow-

ing formula:

PC Pulsed CodeOne The TSS461C will transmit and receive data using the pulsed coding mode (i.e optical

or radio link mode). The use of this mode implies communication via the RXD0 input

and the non-functionality of the diagnosis system.

Zero: (Default at Reset). The TSS461C will transmit and receive data using the

Enhanced Manchester code (RXD0, RXD1, RXD2).

IVTX Invert TXD output.

IVRX Invert RXD inputs.The user can invert the logical levels used on either the TXD output or

the RXD inputs in order to adapt to different line drivers and receivers.

One: A one on either of these bits will invert the respective signals.

Zero: (Default at Reset). Th e TSS461 C w ill set TXD to r ec essi ve sta te in Id le mo de an d

consider the bus free (recessive states on RXD inputs).

Transmit Control Register

(0x01)

• Read/Write register

• Default value after reset: 0x02

76543210

MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT

FTSCLK FXTAL1

n16×

------------------

76543210

MR3 MR2 MR1 MR0 VER2 VER1 VER0 MT

TSS461C

4193G–AUTO–12/04

MR[3:0]: Maximum Retries These bits allow the user to control the amount of retries the circuit will perform if any

errors occurred during transmission.

Table 5. Retries

Note: Bus contention is not regarded as an error and an infinite number of transmission

attempts will be performed if bus contention occurs continuously.

VER[2:0]: DLC Version After

Reset • 000: TSS461A & B

• 001: TSS461C and TSS461C

These bits cannot be set by user; 001 must always be written to these bits.

MT: Module Type The three different module types are supported (see Section “VAN Frame”):

One: The TSS461C is an autonomous module (Rank 0), an synchronous access mod-

ule (Rank 1) or a slave module (Rank 16).

Zero: The TSS4 61C is an synchrono us access module ( Rank 1) or a slav e module

(Rank 16).

Diagnosis Control Register

(0x02)

• Read/Write register

• Default value after reset: 0x00

MR [3:0] Max Number of Retries M ax Number of Tran smits

0000 0 1

0001 1 2

0010 2 3

0011 3 4

0100 4 5

0101 5 6

0110 6 7

0111 7 8

1000 8 9

1001 9 10

1010 10 11

1011 11 12

1100 12 13

1101 13 14

1110 14 15

1111 15 16+

76543210

SDC3 SDC2 SDC1 SDC0 Ma Mb ETIP ESDC

26 TSS461C 4193G–AUTO–12/04

The diagnosis is discussed in detail in Section “Diagnosis States”.

• In its four high order bits the user can program the SDC rate SDC [3:0]

• In its two medium order bits the diagnosis system mode is controlled: M1, M0

• In the two low order bits, the user controls if the SDC and TIP are to be generated

automati c all y ETIP, ESD C

SDC [3:0]: SDC Divider The input clock is the times lot clock.

Table 6. System Diagnosis Clock Divider

Ma, Mb: Operating Mode

Command Bits Table 7. Diagnosis System Command Bits

ETIP: Enable Transmission In

Progress One: Enable TIP generation

Zero: Disable TIP generation.

SDC Divider SDC [3:0] Divide By

0000 64

0001 128

0010 256

0011 512

0100 1024

0101 2048

0110 4096

0111 8192

1000 16384

1001 32768

1010 65536

1011 131072

1100 262144

1101 524288

1110 1048576

1111 2097152

Ma Mb

0 0 Forces the Communication on RxD0 (differential)

0 1 Forces the Communication on RxD2 (DATA)

1 0 Forces the Communication on RxD1 (DATA)

1 1 Automatic selection

TSS461C

4193G–AUTO–12/04

• The Transmission In Progress (TIP) tells the diagnostic system to enable

transmission diagnosis.

ESDC: Enable System

Diagno si s C lo ck One: Enable SDC divider.

Zero: Disable SDC divider.

• The Synchronous Diagnosis Clock (SDC) controls the cycle time of the

synchronous diagnosis.

Command Register (0x03)

• Write only register.

• Reserved: Bit 1, 2. These bits cannot be set by the user; a zero must always be

written to these bit.

• If the circuit is operating at low bit rates, there might be a considerable delay

between the writing of this register and the performing of the actual command (worst

case 6 timeslots). The user must verify, by reading the Line Status Register (0x04),

that the commands have been performed.

GRES: General Reset The Reset circuit command bit performs, if set, exactly as if the external reset pin was

asserted. This command bit has its own auto-reset circuitry.

One: Reset active

Zero: Reset inactive

SLEEP: Sleep Command If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit is in

sleep mode, all non-user registers are setup to minimize power consumption and the

oscill ato r is s topp ed. To ex it fr om this mod e, the us er mus t s et eit her the id le or acti va te

commands.

One: Sleep active

Zero: Sleep inactive

76543210

GRES SLEEP IDLE ACTI REAR 0 0 MSDC

28 TSS461C 4193G–AUTO–12/04

IDLE: Idle Command If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will

operate, but the TSS461C will not transmit or receive anything on the bus, and the TXD

output will be in three-state

One: Idle active

Zero: Idle inactive

ACTI: Activate Command The Activate command will put the circuit in the active mode, i.e it will transmit and

receive no rmally on the bus. When the circuit is in activa te mode the TXD thre e-state

output is enabl ed.

One: Activ at e active

Zero: Activate inactive

REAR: Re-Arbitrate Command This com man d wi ll , aft er the cu rrent attemp t, r eset th e r etry c ount er and re- arbit ra te th e

messages to be transmitted in order to find the highest priority message to transmit.

One: Re-arbitrate active

Zero: Re-arbitrate inactive

MSDC: Manual System

Diagno si s C lo ck Rather than using the SDC divider described in Section “Diagnosis Control Register

(0x02)”, the user can use the manual SDC command to generate a SDC pulse for the

diagnosis system.

This MSDC pulse should be high at least two timeslot clock.

Line Status Register (0x04)

Read only register.

• Default value after reset: 0bx01xxx00.

• This register reports the operation mode of the TSS461C in the Sleep an Idle bits

(Command Register located at address 0y03) as well as the diagnosis system

status bits S2 to S0 discussed in Section “Diagnosis System”.

SPG: Sleeping

IDG: Idling Default mode at reset

Sa, Sb and Sc Diagnosis system status bits

• Sa and Sb

76543210

xSPGIDGScSbSaTXGRXG

TSS461C

4193G–AUTO–12/04

Table 8. Diagnosis System Status Bits

• Sc: As soon as one of the three inputs (RXD2, RXD1, RXD0) differs from the others

in the input comparison analysis perform by the diagnosis system, S2 is set.

The only way to reset this status bit is through the RI signal or a general reset.

TXG: Transmitting If this status bit is active, it indicates that the TSS461C has chosen an identifier to trans-

mit, and it will continue to make transmission attempts for this message until it succeeds

or the retry count is exceeded.

RXG: Receiving The receiving indicates that there is activity on the bus.

Note: For safe modification of active channel registers both bits should be inactive (except

"abort" command).

Transmission Status Register

(0x05)

• Read only register.

• Default value after reset: 0x00.

• The transmission Status register contains the number of retries made up-to-date,

according to Table 3, and the channel currently in transmission.

NRT [3:0]: Number of Retries

Done in Transmission

IDT [3:0]: Channel Number

Currently in Transmission

Last Message Status Register

(0x06)

• Read only register.

• Default value after reset: 0x00.

• This register is the same as the transmission status register. It contains the last

identifier number that was successfully transmitted, received or exceeded its retry

count.

If it was a successful transmission, the number of retries performed can be seen in

this register as well.

Sb Sa Communication Indication

0 0 No minal mode, differential communication

0 1 Degraded over DATA, fault on DATA

1 0 De graded over DATA, fault on DATA

1 1 Major error, fault on DATA and DATA

76543210

NRT3 NRT2 NRT1 NRT0 IDT3 IDT2 IDT1 IDT0

76543210

NRTR3 NRTR2 NRTR1 NRTR0 IDTR3 IDTR2 IDTR1 IDTR0

30 TSS461C 4193G–AUTO–12/04

NRTR [3:0]: Number of retries done successfully in transmission. In case of reception NRTR[3:0] is

undefined.

IDTR [3:0]: Channel number that was successfully transmitted, received or exceeded its retry count.

Last Error Status Register

(0x07)

• Read only register.

• Default value after reset: 0×00.

• The Last Error Status Register contains the error code for the last transmission or

reception attempt. It is updated after each attempt, i.e. several error codes can be

reported during one single transmission (with several retries).

BOC: Buf fer Occ up ie d • When one channel configured in “Reply request” mode has its “received” bit set

when it attempts to transmit its request.

• BOC with the link capability between two channels sharing the same received buffer

is set when one channel has already set its “received” bit in its “Message length and

status Channel register” and a receive is attempted on the other one.

BOV: Buffer Overflow BOV indicates that the buffer length setup in the Channel Status Register was shorter

than the number of bytes received plus 1, therefore, some data got lost.

One: BOV active

Zero: BOV inactive

FCSE: Framing Check

Sequence Error FCSE indicates a mismatch between the FCS received and the FCS calculated

One: FCSE active

Zero: FCSE inactive

ACKE: Acknowledge Error ACKE in dicates a p hysical violati on or collis ion on ACK fi eld of the fr ame when the

TSS463 is produced.

One: ACKE active

Zero: ACKE inactive

76543210

x BOC BOV x FCSE ACKE CV FV

TSS461C

4193G–AUTO–12/04

Figure 17. AC K E Sta tus Bit

CV: Code Violation CV indicates:

• either a Manchester code violation (2 identical TS on Manchester bit), or a physical

violation (transmitted bit “dominant”, received bit “recessive”), on fields ID, COM,

DATA and CRC, or

• a physical violation or collision on field “preamble” and the “recessive” bit of the “S tar

Sync ” field.

One: CV active

Zero: CV inactive

RAK* = 1

*RAK: bit of the frame COMMAND field

ACKE = 0

ACKE = 1

ACKE = 0

ACKE = 1

EOD fi e l d ACK field

EOD field ACK field

Expected

Received

Expected

Received

DLC: Producer

RAK = 0

32 TSS461C 4193G–AUTO–12/04

FV: Frame Violation FV indicates a physical violation or collision on ACK field of the frame when the TSS463

is consumed.

One: FV active

Zero: FV inactive

Figure 18. FV Status Bit

Interrupt Status Register

(0x09)

• Read only register.

• Default value after reset: 0×80

RST: Reset inte rrupt RE indicates that th e circuit has detected a valid reset command via the RESET pin or

the reset command bit GRES. This interrupt cannot be disabled, since its enable bit is

set when a reset is detected.

TE: Transmit Error Status Flag

(or Exceeded Retry) This flag is set only when the Max number of transmission (1 + MR [3:0]) is reached with

error o f transmission.

Figure 19. Exceeded Retry with MR[3.0] = 3

FV = 0

FV = 1

FV = 0

FV = 1

EOD Field ACK Field

Expected

Received

Expected

Received

DLC: Consumer

76543210

RST 0 0 TE TOK RE ROK RNOK

1st TX 2nd TX 3rd TX set TE

set CHER

set CHTx

TSS461C

4193G–AUTO–12/04

TOK: Transmit OK Status Flag One: Status flag activated

Zero: No status flag.

RE: Receive Error Status Flag One: Status flag activated

Zero: No status flag.

ROK: Receive “with RAK

(RAK=1)” OK Status Flag One: Status flag activated

Zero: No status flag.

RNOK: Receive “with no RAK

(RAK=0)” OK Status Flag One: Status flag activated

Zero: No status flag.

Interrupt Enable Register

(0x0A)

• Read/write register

• Default value reset: 0x80

Note: On reset the Reset Interrupt Enable bit is set to 1 instead of 0, as the general rule.

TEE: Transmit Error Enable One: IT enabled.

Zero: IT disabled.

TOKE: Transmission OK Enable One: IT enabled.

Zero: IT disabled.

REE: Reception Error Enable One: IT enabled.

Zero: IT disabled.

ROKE: Reception “with RAK”

OK Enable One: IT enabled.

Zero: IT disabled.

RNOKE: Reception “with no

RAK” OK Enable One: IT enabled.

Zero: IT disabled.

Interrupt Reset Register

(0x0B)

• Write only register.

• Reserved bit: 5 and 6. This bit cannot be set by user; a zero must always be written

to this bit.

76543210

1 0 0 TEE TOKE REE ROKE RNOKE

76543210

RSTR 0 0 TER TOKR RER ROKR RNOKR

34 TSS461C 4193G–AUTO–12/04

RSTR: Reset Interrupt Reset One: Status flag reset

Zero: Status flag unchanged

TER: Transmit Error S t atus Flag

Reset One: Status flag reset

Zero: Status flag unchanged

TOKR: Transmit OK Status Flag

Reset One: Status flag reset

Zero: Status flag unchanged

RER: Receive Error Status Flag

Reset One: Status flag reset

Zero: Status flag unchanged

ROKR: Receive “with RAK” OK

Status Flag Reset One: Status flag reset

Zero: Status flag unchanged

RNOKR: Receive “with no RAK”

OK Status Flag Reset One: Status flag reset

Zero: Status flag unchanged

Figure 20. Update of the Status Register

Channel Registers There is a total of 1 4 chann el reg ister s ets, each o ccup ying 8 byt es for address ing si m-

plicity, integrated into the circuit. Each set contains two 2 x 8-bit registers for the

inden tifier tag, inde nti fie r m ask and com ma nd fi eld s plus two 1 x 8-bit regi st er s for DMA

pointers and message status.

The base_address of each set is: (0x10 + [0x08 * channel_number]).

When the TSS461C is reset either via the external reset pin or the general reset com-

mand, the channel registers are not affected. For example, on power-up of the circuit, all

the channel registers start with random values.

Due to this fact, the us er should take care to initialize al l the chan nel register s before

exiting from idle mode. The easiest way to disable a channel register is to set the

received and transmitted bits to 1 in the Message Length & Status Register.

Reset RXG, TXG

Line Status Register (0x04)

4 TS

Set RXG

Set TXG

4 TS 1 to 2 TS 6 TS

SOF ID+COM+DATA+CRC

BUS

INT

Write “IT Status Register”

Write “Last Error Register”

Write “Last Message Register”

Write “Message Length & Status Register”Write “Message Status”

TSS461C

4193G–AUTO–12/04

Table 9. Chann el Regi st er Sets Map

Table 10. Channel Register Set Structure

Identifier Tag and Command

Registers The identifier tag and command registers are located at the base_address and

base_address + 1. It allows the user to specify the full 12-bit identifie r field of the ISO

standard and the 4-bit command.

• Read/Write registers.

Channel Numbe r From To Channel Number From To

6 0x40 0x47 13 0x78 0x7F

5 0x38 0x3F 12 0x70 0x77

4 0x30 0x37 11 0x68 0x6F

3 0x28 0x2F 10 0x60 0x67

2 0x20 0x27 9 0x58 0x5F

1 0x18 0x1F 8 0x50 0x57

0 0x10 0x17 7 0x48 0x4F

Re g. Name Offs e t Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ID_MASK0x07 ID_M [3:0] xxxx

ID_ MASK 0x06 ID_M [11 :4]

(no register)0x05x xxxxxxx

(no register)0x04x xxxxxxx

MESS_L/

STA 0x03 M_L [4:0] CHER CHTx CHRx

MESS_PTR 0x02 DRACK M_P [6:0]

ID_TAG/

CMD 0x01 ID_T [3: 0] EXT RAK RNW RTR

ID_TAG 0x00 ID_T [11:4]

76543210

ID_T 3 ID_T 2 ID_T 1 ID_T 0 EXT RAK RNW RTR base_address

+ 0x01

76543210

ID_T 11ID_T 10ID_T 9ID_T 8ID_T 7ID_T 6ID_T 5ID_T 4base_address

+ 0x00

36 TSS461C 4193G–AUTO–12/04

ID_T [11:0]: Identifier Tag Upon a reception hit (i.e, a good comparison between the identifier received and an

identifi er specifi ed, taki ng the c omparison mask i nto acco unt, as w ell as a s tatus an d

command indicating a message to be received, the identifier tag bits value will be rewrit-

ten with the identifier bits actually received.

EXT, RAK, RNW & RTR: (See

Section “Retrie s, Rear bi trate

and Abort”)

No comparison will be done on the command bits, except on EXT bit. The RAK, RNW

and RTR bits will be written into the first byte of the Message upon a reception hit.

The RNW and RTR bits, as well as the status bits in the length and status register, must

be in a valid position for reception or transmission. If not, the message corresponding to

this identifier is considered as inactive or invalid.

The way of knowing if an acknowledge sequence was requested or not is to check the

first byte of the Message.

Message Pointer Register The message pointer register at address (base_address + 0x02) is 8 bits wide. It indi-

cates where, in the Message DATA RAM area, the message buffer is located.

• Read/Write register

DRAK: Disable RAK (Used in

'Spy Mode') In reception: whatever is the RAK bit of the incoming valid frame, no ACK answer will be

set. If the message was successfully received, an IT is set (ROK or RNOK).

In transmission: no action.

One: disable ac tive, 'spy ' mode.

Zero: disable inactive, normal operation.

M_P [6:0]: Message Pointer Since the Message DATA RAM area base address is 0x80, the value in this register is

the offs et fr om t hat ad dress . If t he me ssag e buf fer length val ue i s illega l (i.e. z ero), this

channel tha t c onta in s t he a ct ual me ss ag e po in ter , m ess ag e l eng th a nd re ce iv ed sta tus .

Howev er, the ide ntifier , mask, er ror and tran smitte d status used will be the orig inally

matched channel. I n any case, if a link is intended , the three high bits of M_P [6:0]

should be set to 0.

This allo ws s ev eral cha nne ls to us e the sam e ac tual re ce ption buffer in Me ssag e DA TA

RAM, thus diminishing the memory usage.

Note that only 1 level of link is supported.

76543210

DRAK M_P 6 M_P 5 M_P 4 M_P 3 M_P 2 M_P 1 M_P 0 base_address

+ 0x02

TSS461C

4193G–AUTO–12/04

Message Length And Status

wide. It indicates the length reserved for the message in the Message DATA RAM area.

• Read/Write register.

M_L [4:0]: Message Length The 5 high bits of this reg ister all ow the user to s pecify either the leng th of the me ss ag e

to be transmitted, or the maximum length of a message receivable in the pointed recep-

tion buffer.

Note tha t the fir st byte in this reg ister do es not c ontain da ta, but th e lengt h of the me s-

sage received. This implies that the length value has to be equal to or greater than the

maximum le ngth of a mess age to be rece ived in this b uffer (or the len gth of a mess age

to be tra nsmit ted) plus 1. Thus al lowing a maximum length of 30 bytes and a min imum

length of 0 byte.

If the value of this fiel d i s ill ega l (i.e 0x0 0) then thi s mess ag e poi nte r is defi ned as b ein g

a link (see section “Message Pointer Register” and Section “Linked Channels”).

CHER: Channel Error Status

and Abort Command As status , this bit is set b y the TSS46 1C when error occurs in transmissi on or on a

received frame. The user must reset it.

To abort the transmission defined in the channel, this bit can be set to1 by the user (see

Section “Retries, Rearbitrate and Abort” and Section “Abort”).

CHTx: Channel Transmitted and

Transmit Enable Command

76543210

M_L 4 M _L 3 M _L 2 M_L 1 M_L 0 CHER CHTx CHRx base_address

+ 0x03

M_L [4:0] = 0x00 Linked channel

M_L [4:0] = 0x01 Frame with no DATA field (*)

M_L [4:0] = 0x02 Frame with 1 DATA byte

- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

M_L [4:0] = 0x1D Frame with 28 DATA bytes

M_L [4:0] = 0x1E Frame with 29 DATA bytes

M_L [4:0] = 0x1F Frame with 30 DATA bytes

(*) Different of a reply request frame with no in-frame reply (deferred reply).

38 TSS461C 4193G–AUTO–12/04

CHRx: Channel Received and

Receive Enable Command The two low order bits of this register contain the message status. Together with the

RNW and RTR bits of the command register (base_address + 0x01), they define the

message type of this channel (seeSection “Messages Types”). As a general rule (see

Section “Abort”), the status bits are only set by the TSS461C, so the user must reset

them to perform a transmission (CHTx) or/and a reception (CHRx). The received and

transmitted bits are onl y set if the correspo nding frame is without er rors or if the retry

count has been exceeded.

Identifier Mask Registers T he Identifie r Mask r egisters ( base_addres s + 0x0 6 and base _address + 0x07) allow

bitwise masking of the comparison between the identifier received and the identifier

specified.

• Read/Write registers

ID_M [11:0]: Identifier Mask A value of 1 indicates comparison enabled.

A value of 0 indicates comparison disabled.

76543210

ID_M 3ID_M 2ID_M 1ID_M 0xxxx

76543210

ID_M 11 ID_M 10 ID_M 9 I D_M 8 ID_M 7 ID_M 6 ID_M 5 ID_M 4

TSS461C

4193G–AUTO–12/04

Mailbox The mailbox contains all the messages received or to be transmitted. Each messages is

link to a ch annel. The Ma ilbox RAM area has 12 8 bytes and is map ped from 0x80 to

0xFF (see Section “Mapping”).

The message (o r mess age buff er) is compo se d of:

• 1 byte of message status (only used in receiving)

• Bytes of data. These data are the bytes of the DAT A field of the frame with the same

organization.

The message is pointed by the Message Pointer Register of the channel, the length of

the message is given by the Message Length & Status Register of the channel

(Section “Message Pointer Register” and Section “Message Length And Status Regis-

ter”). This area is a pure RAM, it contains a random value after reset.

Figure 21. Message Buffer Structure for Reception

Note: Received DATA Frame, immediate or deffered reply

CHER CHTx CHRx Message Pointer Register

DRAK M_P [6..0]

Message Length & Status Register

M_L [4..0]

RTRRNWRAK M_L [4..0] = n+1

receivedreceivedreceived received

DATA 0

Message

RTR

RNW

ID [11..0 ]

EXT

SOF DATA 0 DATA n FCS

EOD

ACK

EOF

received

DATA nReceived M_P + 0x80 + n + 2

( M_L >= n + 2 )

M_P + 0x80

RAK

40 TSS461C 4193G–AUTO–12/04

Figure 22. Message Buffer Structure for Transmission

Message Status (Pointed

by: Message Pointer

(no significant value in case of message to be transmitted)

RRAK: Received RAK Bit This bit is the RAK bit coming from the COM field of the received frame.

RRNW: Received RNW Bit This bit is the RNW bit coming from the COM field of the received frame.

RRTR: Received RTR Bit This bit is the RTR bit coming from the COM field of the received frame.

RM_L[4:0]: Message Length of

the Received Fra me If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1,

even if the reserved length (Message Length & Status Register) is larger.

CHER CHTx CHRx Message Pointer Register

DRAK M_P [6..0]

essage Length & Status Register

M_L [4..0]

DATA 0

Message

RTR

RNW

RAK

ID [11..0]

EXT

SOF DATA 0 DATA n FCS

EOD

ACK

EOF

Transmitted DATA Frame

transmitted

DATA n

transmitted M_P + 0x80 + n + 2

( M_L >= n + 2 )

M_P + 0x80

(nothing)

76543210

RRAK RRNW RRTR RM_L4 RM_L3 RM_L2 RM_L1 RM_L0

TSS461C

4193G–AUTO–12/04

Figure 23. Message Status Updating

Message Data (String

Pointed by: Message

Pointer Register + 1)

DATA0 is the first received (or transmitted) byte, DATAn is the last one.

Notes: 1. If the leng th res erved (in the mes s age leng th & st a tus regi st er) for an incoming fr ame

is 2 bytes greater or more, the TSS461C will write the 2 bytes of the CRC field in the

message string just after DATAn.

Because the VAN frame does not contain a message length, the only way for the

component to know the length of the DATA field is either the message length register

value, or the EOD field detection. When the reserved length is too large, at the

moment w hen i t detec ts the EOD , the T SS461C has al ready written th e 2 b ytes of the

CRC field, considerin g these bytes as normal DATA.

2. The Mailbox RAM area is a circular buffer. The next location after 0xFF is 0x80.

Data Frame

Immediate

I, P C

Fram e Type

Node x Message Status on Node A after IT(*)

Commu- Node A

RAK RNW RTR Length

Value

I, C P

RAK

RNW RTR

Deferred

Reply Previous

Value

I, C P

RAK RNW RTR

Data Frame

I, PC

Immediate

I, CP

RAK RNW RTR Length

Deferred

I, CP

RAK RNW RTR Length

previous values

P: Producer I: Initiator C: Consumer

(*) After IT ROK or RNOK. In case of IT RE, the values can be erroneous.

nication

76543210

DATAn

- - - - - - - - - - - - - - - - - - -- - - - - -

DATA0

42 TSS461C 4193G–AUTO–12/04

Messages Types There are 5 basic message types defined in the TSS461C. Two of them (transmit and

receive message types) correspond to the normal frame, and the rest correspond to the

different versions of reply frames.

To transmit a normal data frame on the VAN bus, the user must program an identifier as

a Transmit Message. The TSS461C will then transmit this me ssage on the bus until it

has succeeded or the retry count is exceeded.

The opposite of the transmit message type is the Receive Message type. This message

type will not gener ate any frames on the bus. Instead, it wi ll listen to the bus until a

frame passes that matches its identifier, with the mask taken into account, and then

receive the data in that frame.

The data received will be stored in the message buffer and the length of the message

received is stored in the first byte of the message buffer.

The act ual identif ier rece ived is sto red in the ide ntifier r egister its elf. This i dentifier may

differ from the identifier specified in the register due to the effect of the mask register.

Normall y, this sho uld no t inte rfere with th e nex t iden tifier co mparis on sinc e the bits that

may differ are masked via the mask register.

The Reply Request Message type is a demand to transmit on the VAN bus a reply

request. When this message type is programmed, three things can happen.

First, no other modul es on the bus r esponde d with a n in-f rame rep ly, in this ca se the

TSS461C will set th e m es sa ge typ e to the afte r trans mi s sion st ate. W hen thi s me ss ag e

type is programmed, the TSS461C will listen on the bus for a deferred reply frame

matching this identifier, without transmitting the reply request.

Transmit Message

RNW RTR CHTx CHRx

Initial Setup 0 0 0 Don’t Care

After Transm ission 0 0 1 Unchanged

Receive Message

RNW RTR CHTx CHRx

Initial Setup 0 1 Don’t Care 0

After Transmission 0 1 Unchanged 1

Reply Request Message

RNW RTR CHTx CHRx

Initial Setup 1 1 0 0

After Transmission

(Waiting for reply) 11 1 0

After Reception

(of reply) 11 1 1

TSS461C

4193G–AUTO–12/04

Seco nd, ano the r mod ule on the bus r eplies with an in-f ra me re ply. In thi s cas e the mes-

sage type will pass immediately into the after reception state, without passing the after

transmission state.

Third, the TSS46 1C has not yet started to transm it the reply request, when another

module ei ther req uests a reply , and get s it, or transm its a d eferred repl y. Warni ng! T his

should be avoided as it may result in an illegal message type (Illegal reply Request).

The imme diate Re ply Mes s age will atte mpt to tra ns mit an in -f ra me repl y , usi ng the da ta

in the message buffer. A deferred Reply Message is shown below.

This message type will immediately transmit a deferred reply frame.

Finally, there is the Reply Request Detector Message type. Its purpose is to receive a

reply request frame and notify the processor, without transmitting an in-frame reply.

The table above shows all inactive messages types. The last combination will transmit a

reply request, but will not receive the reply since its buffer is tagged as occupied.

Reply Request Message Without Transmission

RNW RTR CHTx CHRx

Initial Setup 1 1 Don’t Care 0

After Reception 1 1 Unchanged 1

Immediate Reply Message

RNW RTR CHTx CHRx

Initial Setup 1 0 0 0

After Transmission 1 0 1 1

Deferred Reply Message

RNW RTR CHTx CHRx

Initial Setup 1 0 0 1

After Reception

(of Reply Request) 10 1 1

Reply Request Detection Message

RNW RTR CHTx CHRx

Initial Setup 1 0 1 0

After Reception 1 0 1 1

Inactive Message

RNW RTR CHTx CHRx

Recommended Don’t Care Don’t Care 1 1

After Trans miss ion 0 0 1 Don’t care

After Reception 0 1 Don’t Care 1

Illegal Reply Request 1 1 0 1

44 TSS461C 4193G–AUTO–12/04

Priority Among the

Different Channels The p riority han dling o n the VA N bus is alre ady explai ned i n th e Li ne In terfa ce sec tion.

The priorities for the messages in the TSS461C is, however, slightly different.

For instance, it's possible that an identifier matches two or more of the identi fiers pro-

grammed into the registers. In this case, it is the lowest identifier number that has

priority. i.e., if both identifier 5 and 10 match the identifier received, it is the identifier 5

that will receive the message.

However, since the identifier 5 will become an inac tive message when it has received

the frame, the next time the same identifier is seen on the bus, the corresponding data

will be received by identifier 10.

The same is valid for messages to be transmitted, i.e., if two or more messages are

ready to be transmitted, it is the one with the lowest identifier number that will get

priority.

TSS461C

4193G–AUTO–12/04

Retries, Rearbitrate

and Abort Retries and rearbitrate commands are located, in the Transmit Control Register and in

the Command Register, respectively. An abort command is located in each channel reg-

ister se t, in the Mes sage Length & Statu s Regis ter (base _ad dr es s + 0x03). The se thre e

commands are available only when the TSS461C is producer.

Figure 24. Transmit Function

Retries The purpo se o f re trie s fe atur e is to provid e, th e ca pa bility of r etr ying a t ransmi t r eques t

in case of failure, when a node tries to reach another n ode, either on normal DA TA

frame or on REPLY REQUEST frame.

The maximum number of retries is programmable through MR[3:0] of the Transmit Con-

trol Register (0x01). When a channel is enable – bit CHTx = 0 of Message Length &

Status Register, a 4-bit counter is loaded with MR[3:0]. At each attempt, this counter will

be countdown. To 0, an IT TE is set in the Interrupt Status Register (0x09), and the

transmission is stopped.

MR[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see

Table 4). The number of retries performed, as well as the current channel number asso-

ciated, can be read in the Transmission Status Register (0x05).

Activate

Ch. Enabled in

Xmit Mode? no

Select the low est

Ch. number and

load”Max - retries”

yes

Abort activated

on current Ch.?

yes

Disable of

current Ch.

Wait for bus free

(EOF+IFS= 12 Timeslots)

Retry needed?

abort

Abort required

rearbitrate?

on current Ch. rearbitrate

yes

Tran smit fra m e

and wait for the end

Decrement

retry counter

46 TSS461C 4193G–AUTO–12/04

The Last Error Status Register (0x07) informs about the trouble encountered:

• Failure cases:

– Code viol (CV error bit)

– Acknowledge error (ACKE error bit)

– CRC error (FCSE erro r bit)

• It should be noticed that contention is considered as normal CSMA/CD pr otocol

and, therefore, is not taken into account in failure cases. So, an “infinite” number of

attempts can be performed if bus contention occurs continuously.

There is only one retr y counte r for al l channe ls. Whe n the us er writ es the Max _Retri es

value, all channels start their transmission with this parameter.

Rearbitrate The purpose of rearbitrate feature is to postpone a channel already in transmis sion in

order to au thorize an hig her priority (see Se ction “Prio rity Amon g the Differen t Chan-

nels”) message to be transmit.

Typical Example • Max_retries = 1 (2 transmissions attempts).

• If Ch8 is in a the retry loop and the user wants to transmit the Ch5 without waiting

the end of the loop, the user can use the rearbitrate command.

• Then, the TSS461C will wait the end of the current transmission, reload the retries

counte r and enab le the Ch5 to transm it.

• At the end of this transmission Ch5, either when the attempt is successful or either

when the exceeded retry count is reached, the retries counter is reloaded and the

transmission is activated for the Ch8 again.

Figure 25. Rearbitrate Example

First attempt

Xmit Ch5

Ex: FCS Error

Rearbitrate

VCC

EOF+IFS

(Activate Ch5)

Delay

Set CHTx/Ch5 & IT ROK

Xmit Ch8 (Load Max-Retries)

(Load Max-retries)

* (not seen by applicatio

(Load Max-retries)

Ex: FCS Error

(not seen by application

)

stand-b

First attempt

Xmit Ch8

econd attempt

Xmit Ch8

(Retries - 1)

Delay

Set CHER & CHTx /Ch8

Ex: set FSCE status bi

and set IT TE

Delay

Viol Viol Viol

EOF+IFS: 8 + 4 Timeslots

Delay Viol: 12 Timeslots

* (not seen by application means no IT generation)

TSS461C

4193G–AUTO–12/04

Figure 26. Idle and Rearbitrate Example

If the us er sets the idle bi t any where (aft er rea rbit rate), the i dle m ode i s en tered on ly at

the e nd of all th e transm it attempts (for mor e inform ation abou t idle co mmand, se e

Sect ion “ Ac tivate, Idle and Sleep Modes ”).

Disable Channel After

Rearbitrate

Figure 27. Disable Channel After Rearbitrate Example

Note: 1. In this case, the TSS461C completes the current attempt (Ch8) and lets the transmission go to the new channel (Ch5 if val-

idated); otherwise, it stops all attempts on the current channel.

First Attempt

Xmit Ch5

Ex: FCS Error

Rearbitrate

EOF+IFS

(Activate Ch5)

Set CHTx/Ch5 & IT ROK

Xmit Ch8 (Load Max-retries)

(Load Max-retries)

Ex: FCS Error

(not seen by application)

First Attempt

Xmit Ch8

econd Attempt

Xmit Ch8

(Retries - 1)

Idle command

Idle

Set CHER & CHTx /Ch

Ex: set FSCE status b

and set IT TE

Delay Delay

Delay

iol Viol Viol

EOF+IFS: 8 + 4 Timeslots

Delay Viol: 12 Timeslots

* (not seen by application)

* (not seen by application means no IT generation)

First attempt

Ex: FCS Error

Rearbitrate

(Activate Ch5)

Set CHTx/Ch5 & IT TO K

Set CHER & CHTx /Ch5,

Xmit Ch8 (Load Max-retrie

(Load Max-retrie

(not seen by application)

Ex: set ACKE status bit

stand-by

First attempt

Xmit Ch5

Second attempt Xmit Ch5

Ex: ACK Error

(not seen by application)

(Retries - 1)

EOF+IFS stand-by

Disable Ch8(*

)

(1) The disable is applied setting the CHTx/Ch8 bit to 1.

and set IT TE

Delay Delay

Delay

Viol

Viol Viol

EOF+IFS: 8 + 4 Timeslots

Delay Viol: 12 Timeslots

48 TSS461C 4193G–AUTO–12/04

Abort An abort command is dedicated to channels already enabled in transmission or in-frame

response. For example, this command can be used to break the retry procedure on one

channel.

Abort channel is done by setting the Error bit (CHER) in the Message Length & Status

aborted is not transmitted. When this abort command is really done, the TSS461C set to

1 the Transmitted bit (CHTx) of the Message Length & Status Register.

The abort mechanism is integrated into the transmit function. This means, abort, priority

and retries live together in the transmit function.

Figure 28. Abort Example

Reset

Chs Initialization

Activate

Abort Ch0 (before Xmit)

Set CHTx/Ch0

Abort Ch13 (before Xmit)

Abort Ch4 (during Xmit)

Set CHTx/Ch4 &IT ROK

Set CHTx/Ch6 & IT ROK

if Successful

Set CHTx/Ch6 & IT ROK

if Successful

/Ch6 &

Set CHTx/Ch13

Xmit Ch6

Xmit Ch4

12 Timeslots

f Previously Fail

Xmit Ch6

f Previously Fail

IT ROK

or IT RE

Set CHTx

or CHER

TSS461C

4193G–AUTO–12/04

Activate, Idle and

Sleep Modes Sleep, idle and activate commands are located in the Command Register (0x03). These

three commands are general commands for the TSS461C.

Idle and Activate

Commands After reset, the TSS461C starts in idle mode. In this mode, the oscillator operates

(CKOUT pin active) but the c ircui t ca nnot t ransmi t or receive any thing on th e VA N bus .

The TxD output (pi n 18) is i n three-state mode, a pull-up re sistor mus t be provide d

externally or by the line driver to avoid floating state on the VAN bus.

To activate t he TSS 461 C, the us er mus t se t the ac ti va te bit (AC TI) an d reset the idle bi t

(IDLE).

Figure 29. Idle and Activate Timings

In both cases, the idle state can be verified by reading the Line Status register (0x04).

Sleep Command If the user sets the sleep bit (SLEEP), the TSS461C enters in sleep mode, whatever are

the va lue s o f activ ate and idle b its. Al l n on- us er r egi s ters a re se tup t o redu ce t he power

consump tio n a nd the internal os c illat or is i mm edi ate ly s topp ed. Howeve r, al l u se r r egi s-

ters (accessible by µP bus) are always available by the user

To exit from this mode, the user must set either the idle bit or the activate bit.

In a typical applicat ion (Figure 1) using the CKOUT feature (pin 12), if the TSS461C is

put in sleep mode, the clock provided to the microcontroller is stopped. So, the system

does not run and the only way to awake this application is an external reset.

(max)

RxD

TxD

fter Reset

Idle Mode Activate Mode

Activate Command

3 TS 8 TS

12 TS TS: Timeslot Period

SOF

Idle Command

FCS

EOD

ACK

5 TS4 TS

RxD

INT

Idle ModeActivate Mode

50 TSS461C 4193G–AUTO–12/04

Linked Channels The linkage feature allows two channels to share the same Message area, the message

pointer and the message length assumes the following property:

• Zero value as message length (M_L [4:0] - base_address + 0x03) declares the

channel linked to another channel.

• The number of this other channel is defined in the message pointer field (M_P [6:0]

- base_address + 0x02).

• The pointer and the length values for the Message area are defined only once time,

in the register set of this other Channel.

Only one level of linkage can be created. For example, (see Figure 29) a Channel k can

be linked to the Channel i but not to Channel j, already defined as linked to Channel i.

All the others can be different between the two channels, for example the ID_Tag.

Figure 30. Linkage Mechanism

This Message Area sharing permits either optimizing the allocation of the 128 bytes of

DATA, performing some special communications between the different nodes of the

network.

ID_Tag j (msb)

ID_Tag j (lsb) EXT RAK RNW RTR

DRAK i

0x00 CHRx

Message Status

DATA 0

--- Channel i ---

ID_Tag i (msb)

ID_Tag i (lsb) EXT RAK RNW

DRAK Mess_Ptr

Mess_Len = n+2CHERCHTx CHRx

ID_Mask i (lsb)

--- Channel j ---

DATA n

The Channel j linked

to the Channel i

. . . .

Length = n+2

--- Message for Channels i & j ---

Channel i and j

share the same

Message area

ID_Mask i (msb)

RTR

CHERCHTx

ID_Mask j (msb)

ID_Mask j (lsb)

TSS461C

4193G–AUTO–12/04

Electrical Characteristics

Absolute Maximum Ratings

DC Characteristic s TA = -40°C to 125°C; VCC = 5V ± 10%; VSS = 0V

Ambient temperature under Bias:

A = Automotive.................................................-40°C to 125°C

Storage Temperature........................................-65°C to 150°C

Volta ge on VCC to VSS..........................................-0.5 to +7.0V

Voltage on any Pin to VSS........................-0.5V to VCC + 0.5V

Note: Stresses at or above those listed under "Absolute

Maximum Ratings" may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions exceeding those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

Symbol Parameter Min Max Type Test Conditions

VIL Input Low Voltage (except RESET and

XTAL1) -0.5 0.8 V

VIH Input High Voltage (except RESET and

XTAL1) 2.0 VCC+0.5 V

VIL1 Input Low Voltage (RESET and XTAL1) -0.5 0.3·VCC V See Figure 2

VIH1 Input High Voltage (RESET and XTAL1) 0.7 VCC VCC+0.5 V

VOL Output Low V oltage 0.4 V IOL = 3.2 mA, VCC min

VOH Output High V oltage 2.4 IOH = -3.2 mA, VCC min

IL Input Leakage Current +5µA0 < V

IN < VCC

RPD Input Pull-down Resistor 110 kΩ0 < VIN < VCC

CIO I/O Buffer Capacitance 10 pF Not tested

ICCSB Power Supply Current

Sleep Mode 50 µA(Note 1)

ICCOP Power Supply Current

Idle or Active Mode 4

15 mA

mA (Notes 2, 4)

(Notes 3, 4)

Notes : 1. Sleep Mode I CCSB is measured according to Figure 31 with a VSS Clock Signal.

2. Active mode ICCOP is measured at: XTAL = 1 MHz clock, VAN speed rate = 62.5 KTS/s.

3. Active mode ICCOP is measured at: XTAL = 16 MHz clock, VAN speed rate = 250 KTS/s.

4. ICC is a function of the Clock Frequency. Figure 32 displays a graph showing ICC versus Clock frequency.

5. RESET, RxD0, RxD1, RxD2 inputs.

52 TSS461C 4193G–AUTO–12/04

Figure 31. ICC

Figure 32. ICC versus Clock Frequency at 250 KTimeslot/s

LOCK SIGNAL

N.C.

Icc

TXD

11.5

10.5

TSS461C

4193G–AUTO–12/04

AC Characteristic s

Microprocessor Interface

TA = -40°C to 125°C; VCC = 5V ± 10%; VSS = 0V

Symbol Characteristic Min Max Unit

TRESET RESET High Pulse Width (For Power-up Reset) 15 ns

LHLL ALE High Pulse Width 10 ns

AVLL Address V alid to ALE Low Setup Time 10 ns

LLAX ALE Low to Address Invalid Hold Time 10 ns

AVWL A ddress Valid to Command Active Time 20 ns

DVWH Data Valid to Write Inactive Setup T ime 10 ns

6TWHDX Write Inactive to Data Invalid Hold Time 12 ns

WHLH Write Inactive to ALE High Recovery Time 20 ns

RLDV Read Active to Data Valid Access Time 110 ns

RHDZ Read Inactive to Data Float Time 20 ns

10 TWHRLIZ Write Inactive or Read Active to IRQ Float Tim e 90 ns

11 TIZIL IRQ Float Pulse Width 2 20 ns

54 TSS461C 4193G–AUTO–12/04

Oscillato r Charac terist ic s Figure 33. C2 versus Frequency

Note: C1 (no cap ac itance needed) see Figure 1.

External Clock Dr ive

Characteristics (XTAL1)

200

100

12 48

MHz

Symbol Parameter Min Max Unit

TCHCH Oscillator Period 120 ns

TCHCX High Time 20 ns

TCLCX Low Time 20 ns

TCLCH Rise Time 20 ns

TCHCL Fall Time 20 ns

tCHCX tCLCX

tCHCH

TAL1 VIH

VIL

tCLCH

tCHCL

VIH VIH

VIL

TSS461C

4193G–AUTO–12/04

Packaging Information

SO24

SO MM INCH

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.35 0.49 0.014 0.019

C 0.23 0.32 0.009 0.013

D 15.20 15.60 0.599 0.614

E 7.40 7.60 0.291 0.299

e 1.27 BSC 0.050 BSC

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.029

L 0.40 1.27 0.016 0.050

N24 24

a0° 0°

56 TSS461C 4193G–AUTO–12/04

Ordering Information

Note: 1. These products are available in ROHS version.

Part Number Supply Voltage Temperature

Range Package Packing

TSS461C 5V +10% -40°C - +125°C SO24 Tube

TSS461C:R 5V +10% -40°C - +125°C SO 24 Tape & Reel

TSS461C-TDRZ(1) 5V +10% -40°C - +125°C SO24 Tube

Printed on recycled paper.

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warranty which is detailed in Atmel’s Ter ms and Conditions locate d on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifica tions detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

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