LTC2946CDE-1#PBF - LINEAR TECHNOLOGY

LTC2946

2946fa

For more information www.linear.com/LTC2946

TYPICAL APPLICATION

FEATURES DESCRIPTION

Wide Range I2C Power,

Charge and Energy Monitor

The LT C

2946 is a rail-to-rail system monitor that measures

current, voltage, power, charge and energy. It features an

operating range of 2.7V to 100V and includes a shunt regu-

lator for supplies above 100V. The current measurement

common mode range of 0V to 100V is independent of the

input supply. A 12-bit ADC measures load current, input

voltage and an auxiliary external voltage. Load current and

internally calculated power are integrated over an external

clock or crystal or internal oscillator time base for charge

and energy. An accurate time base allows the LTC2946

to provide measurement accuracy of better than ±0.6%

for charge and ±1% for power and energy. Minimum and

maximum values are stored and an overrange alert with

programmable thresholds minimizes the need for software

polling. Data is reported via a standard I2C interface.

The LTC2946 I2C interface includes separate data input

and output pins for use with standard or opto-isolated I2C

connections. The LTC2946-1 has an inverted data output

for use with inverting opto-isolator configurations.

Wide Range Power, Charge and Energy

Monitor with Onboard ADC and I2C ADC Total Unadjusted Error (ADIN)

APPLICATIONS

n Rail-to-Rail Input Range: 0V to 100V

n Wide Input Supply Range: 2.7V to 100V

n Shunt Regulator for Supplies >100V

n Δ∑ ADC with Less Than ±0.4% Total

Unadjusted Error

n 12-Bit Resolution for Current and Voltages

n ±1% Accurate Power and Energy Measurements

n ±0.6% Accurate Current and Charge Measurements

n Additional ADC Input Monitors an External Voltage

n Internal ±5% or External Time Bases

n Continuous Scan and Snapshot Modes

n Stores Minimum and Maximum Values

n Alerts When Limits Exceeded

n Split SDA Pin Eases Opto-Isolation

n Shutdown Mode with IQ < 40µA

n Available in 4mm × 3mm DFN and 16-Lead

MSOP Packages

n Telecom Infrastructure

n Industrial Equipment

n General Purpose Energy Measurement

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

I2C

INTERFACE

NINE I2C

ADDRESSES

ACCUMULATION

ENABLE

OPTIONAL

CRYSTAL

TIMEBASE

SENSE+SENSE–

GPIO3 ALERT

SCL

SDAI

SDAO

ADIN

CLKOUT

GPIO1

VDD

INTVCC

ADR1

ADR0

GND

GPIO2

CLKIN

LTC2946

MEASURED

VOLTAGE

GENERAL

PURPOSE

OUTPUT

LOAD

0.1µF

0.02Ω

VIN

4V TO 100V

2946 TA01a

CODE

–0.10

ADC TUE (%)

–0.05

0.05

0.10

1024 2048 3072 4096

2946 TA01b

LTC2946

2946fa

For more information www.linear.com/LTC2946

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

VDD Voltage .............................................. –0.3V to 100V

SENSE+ Voltage ...........................................–1V to 100V

SENSE– Voltage .....–1V or SENSE+ – 1V to SENSE+ + 1V

INTVCC Voltage

(Note 3) ................... –0.3V to Lesser of 5.8V, VDD + 0.3V

ADR1, ADR0, ADIN, SDAO, SDAO, GPIO1 TO GPIO3

Voltages ....................................................... –0.3V to 7V

CLKOUT Voltage ........................–0.3V to INTVCC + 0.3V

CLKIN Voltage ........................................... –0.3V to 5.5V

INTVCC Clamp Current ...........................................35mA

(Notes 1, 2)

LTC2946

GND

SENSE+

SENSE–

ADR1

ADIN

ADR0

GND

CLKOUT

CLKIN

VDD

INTVCC

GPIO1

GPIO2

GPIO3

SDAO

SDAI

SCL

TOP VIEW

DE PACKAGE

16-LEAD (4mm × 3mm) PLASTIC DFN

TJMAX = 125°C, θJA = 43°C/W, E PAD GND SOLDERED DOWN

EXPOSED PAD (PIN 17) IS GND, PCB GND CONNECTION IS OPTIONAL

VDD

INTVCC

GPIO1

GPIO2

GPIO3

SDAO

SDAI

SCL

SENSE+

SENSE–

ADR1

ADIN

ADR0

GND

CLKOUT

CLKIN

TOP VIEW

MS PACKAGE

16-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 120°C/W

LTC2946-1

SENSE+

SENSE–

ADR1

ADIN

ADR0

GND

CLKOUT

CLKIN

VDD

INTVCC

GPIO1

GPIO2

GPIO3

SDAO

SDAI

SCL

TOP VIEW

DE PACKAGE

16-LEAD (4mm × 3mm) PLASTIC DFN

GND

TJMAX = 125°C, θJA = 43°C/W, E PAD GND SOLDERED DOWN

EXPOSED PAD (PIN 17) IS GND, PCB GND CONNECTION IS OPTIONAL

VDD

INTVCC

GPIO1

GPIO2

GPIO3

SDAO

SDAI

SCL

SENSE+

SENSE–

ADR1

ADIN

ADR0

GND

CLKOUT

CLKIN

TOP VIEW

MS PACKAGE

16-LEAD PLASTIC MSOP

TJMAX = 125°C, θJA = 120°C/W

SCL, SDAI Voltages (Note 4) ..................... –0.3V to 5.9V

SCL, SDAI Clamp Current ........................................5mA

Operating Temperature Range

LTC2946C ................................................ 0°C to 70°C

LTC2946I .............................................–40°C to 85°C

LTC2946H .......................................... –40°C to 125°C

LTC2946MP ...................................... –55°C TO 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MS Package Only ..............................................300°C

LTC2946

2946fa

For more information www.linear.com/LTC2946

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VDD VDD Input Supply Voltage l4 100 V

VCC INTVCC Input Supply Voltage l2.7 5.8 V

IDD VDD Supply Current VDD = 48V, INTVCC Open

Shutdown

0.9

1.3

μA

ICC INTVCC Supply Current INTVCC = VDD = 5V

Shutdown

0.7

1.0

μA

VCC(LDO) INTVCC Linear Regulator Voltage 8V < VDD < 100V, ILOAD = 0mA l4.4 5 5.4 V

ΔVCC(LDO) INTVCC Linear Regulator Load Regulation 8V < VDD < 100V, ILOAD = 0mA to 10mA l100 200 mV

VCCZ Shunt Regulator Voltage at INTVCC VDD = 48V, ICC = 1mA l5.8 6.3 6.7 V

ΔVCCZ Shunt Regulator Load Regulation VDD = 48V, ICC = 1mA to 35mA l250 mV

VCC(UVL) INTVCC Supply Undervoltage Lockout INTVCC Rising, VDD = INTVCC l2.3 2.6 2.69 V

VDD(UVL) VDD Supply Undervoltage Lockout VDD Rising, INTVCC Open l2.4 2.8 3 V

VDDI2C(RST) VDD I2C Logic Reset VDD Falling, INTVCC Open l1.7 2.1 V

VCCI2C(RST) INTVCC I2C Logic Reset INTVCC Falling, VDD = INTVCC l1.7 2.1 V

SENSE Inputs

ISENSE+(HI) 48V SENSE+ Input Current SENSE+, SENSE–, VDD = 48V

Shutdown

100 150

µA

ISENSE–(HI) 48V SENSE– Input Current SENSE+, SENSE–, VDD = 48V

Shutdown

µA

ISENSE+(LO) 0V SENSE+ Source Current SENSE+, SENSE– = 0V, VDD = 48V

Shutdown

–10

–1

µA

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 100V, unless otherwise noted. (Note 2)

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2946CDE#PBF LTC2946CDE#TRPBF 2946 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C

LTC2946IDE#PBF LTC2946IDE#TRPBF 2946 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C

LTC2946HDE#PBF LTC2946HDE#TRPBF 2946 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C

LTC2946CDE-1#PBF LTC2946CDE-1#TRPBF 29461 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C

LTC2946IDE-1#PBF LTC2946IDE-1#TRPBF 29461 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C

LTC2946HDE-1#PBF LTC2946HDE-1#TRPBF 29461 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C

LTC2946CMS#PBF LTC2946CMS#TRPBF 2946 16-Lead Plastic MSOP 0°C to 70°C

LTC2946IMS#PBF LTC2946IMS#TRPBF 2946 16-Lead Plastic MSOP –40°C to 85°C

LTC2946HMS#PBF LTC2946HMS#TRPBF 2946 16-Lead Plastic MSOP –40°C to 125°C

LTC2946MPMS#PBF LTC2946MPMS#TRPBF 2946 16-Lead Plastic MSOP –55°C to 125°C

LTC2946CMS-1#PBF LTC2946CMS-1#TRPBF 29461 16-Lead Plastic MSOP 0°C to 70°C

LTC2946IMS-1#PBF LTC2946IMS-1#TRPBF 29461 16-Lead Plastic MSOP –40°C to 85°C

LTC2946HMS-1#PBF LTC2946HMS-1#TRPBF 29461 16-Lead Plastic MSOP –40°C to 125°C

LTC2946MPMS-1#PBF LTC2946MPMS-1#TRPBF 29461 16-Lead Plastic MSOP –55°C to 125°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

Consult LT C Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2946

2946fa

For more information www.linear.com/LTC2946

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 100V, unless otherwise noted. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISENSE(LO)–0V SENSE– Source Current SENSE+, SENSE– = 0V, VDD = 48V

Shutdown

–5

–1

µA

ADC (SENSE+, SENSE– = 0V, 100V) (Note 5)

RES Resolution (No missing codes) (Note 7) l12 Bits

TUE Total Unadjusted Error (Note 6) ΔSENSE (C-, I-Grade)

ΔSENSE (H-, MP-Grade)

SENSE+, VDD (C-, I-Grade)

SENSE+, VDD (H-, MP-Grade)

ADIN (C-, I-Grade)

ADIN (H-, MP-Grade)

±0.6

±0.7

±0.4

±0.5

±0.3

±0.4

VFS Full-Scale Voltage ΔSENSE (C-, I-Grade)

ΔSENSE (H-, MP-Grade)

SENSE+, VDD (C-, I-Grade)

SENSE+, VDD (H-, MP-Grade)

ADIN (C-, I-Grade)

ADIN (H-, MP-Grade)

101.8

101.7

102

101.9

2.042

2.04

102.4

2.048

103

103.1

102.8

102.9

2.054

2.056

LSB LSB Step Size ΔSENSE

SENSE+, VDD

ADIN

0.5

µV

VOS Offset Error ΔSENSE (C-, I-Grade)

ΔSENSE (H-, MP-Grade)

SENSE+, VDD

ADIN

±2.1

±3.1

±1.5

±1.1

LSB

INL Integral Nonlinearity ΔSENSE

SENSE+, VDD

ADIN

±2.5

±2

LSB

στTransition Noise (Note 7) ΔSENSE

SENSE+, VDD

ADIN

1.2

0.3

µVRMS

mVRMS

µVRMS

tCONV Conversion Time (Snapshot Mode) ΔSENSE

SENSE+, VDD, ADIN

62.4

31.2

65.6

32.8

68.8

34.4

RADIN ADIN Input Resistance VDD = 48V, ADIN = 3V l3 10 MΩ

CLKIN, CLKOUT, GPIO

VCLKIN(TH) CLKIN Input Threshold l0.7 1 1.3 V

fCLKIN(MAX) Maximum CLKIN Frequency l25 MHz

ICLKIN(IN) CLKIN Input Current VCLKIN = 5V l5 10 μA

ICLKOUT CLKOUT Output Current VCLKIN = 0V, VCLKOUT = 0V l–70 –100 –130 μA

VGPIO(TH) GPIO Input Threshold VGPIO Rising l1.06 1.22 1.32 V

VGPIO(HYST) GPIO Input Hysteresis 36 mV

VGPIO(OL) GPIO Output Low Voltage IGPIO = 8mA l0.15 0.4 V

IGPIO(IN) GPIO Input Leakage Current VGPIO = 5V l0 ±1 μA

I2C Interface (VDD = 48V)

VADR(H) ADR0, ADR1 Input High Threshold l1.9 2.4 2.7 V

VADR(L) ADR0, ADR1 Input Low Threshold l0.3 0.6 0.9 V

IADR(IN) ADR0, ADR1 Input Current ADR0, ADR1 = 0V, 3V l±13 μA

IADR(IN,Z) Allowable Leakage When Open l±7 μA

VOD(OL) SDAO, SDAO, Output Low Voltage ISDAO, ISDAO = 8mA l0.15 0.4 V

ISDA,SCL(IN) SDAI, SDAO, SDAO, SCL Input Current SDAI, SDAO, SDAO, SCL = 5V l0 ±1 μA

LTC2946

2946fa

For more information www.linear.com/LTC2946

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive. All voltages are referenced to

ground, unless otherwise noted.

Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of

5.8V. Driving this pin to voltages beyond 5.8V may damage the part. This

pin can be safely tied to higher voltages through a resistor that limits the

current below 35mA.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 100V, unless otherwise noted. (Note 2)

Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of

5.9V. Driving these pins to voltages beyond the clamp may damage the

part. The pins can be safely tied to higher voltages through resistors that

limit the current below 5mA.

Note 5: ΔSENSE is defined as VSENSE+ – VSENSE–

Note 6: TUE = (ACTUAL CODE – IDEAL CODE)/4096 • 100% where IDEAL

CODE is derived from a straight line passing through Code 0 at 0V and

theoretical code of 4096 at VFS.

Note 7: Guaranteed by design and not subject to test.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VSDA,SCL(TH) SDAI, SCL Input Threshold l1.5 1.8 2.1 V

VSDA,SCL(CL) SDAI, SCL Clamp Voltage ISDAI, ISCL = 3mA l5.9 6.4 6.9 V

I2C Interface Timing

fSCL(MAX) Maximum SCL Clock Frequency l400 kHz

tLOW SCL LOW Period l0.65 1.3 μs

tHIGH SCL HIGH Period l50 600 ns

tBUF(MIN) Bus Free Time Between

STOP/START Condition

l0.12 1.3 μs

tHD,STA(MIN) Hold Time After (Repeated) START

Condition

l140 600 ns

tSU,STA(MIN) Repeated START Condition

Setup Time

l30 600 ns

tSU,STO(MIN) STOP Condition Setup Time l30 600 ns

tHD,DATI(MIN) Data Hold Time Input l–100 0 ns

tHD,DATO(MIN) Data Hold Time Output l300 600 900 ns

tSU,DAT(MIN) Data Setup Time l30 100 ns

tSP(MAX) Maximum Suppressed Spike Pulse Width l50 110 250 ns

tRST Stuck Bus Reset Time SCL or SDAI Held Low l25 33 ms

CXSCL, SDAI Input Capacitance (Note 7) 5 10 pF

TYPICAL PERFORMANCE CHARACTERISTICS

VDD Supply Current INTVCC Supply Current INTVCC Load Regulation

VDD SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

20 40 8060

1000

800

700

900

100

2946 G01

SHUTDOWN

NORMAL

INTVCC SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

3 4 5

900

700

600

800

2946 G02

SHUTDOWN

NORMAL

LOAD CURRENT (mA)

4.8

INTVCC VOLTAGE (V)

5.0

2 4 86

5.2

4.9

5.1

2946 G03

LTC2946

2946fa

For more information www.linear.com/LTC2946

TYPICAL PERFORMANCE CHARACTERISTICS

INTVCC Shunt Regulator

Load Regulation SENSE Input Current

ADR Voltage with Current

Source or Sink

SCL/SDAI Loaded Clamp Voltage

vs Load Current

GPIO, SDAO, SDAO Loaded Output

Low Voltage vs Load Current

ADC Integral Nonlinearity (ADIN)ADC Total Unadjusted Error (ADIN)

INTVCC Line Regulation

ADC Differential Nonlinearity

(ADIN)

VDD SUPPLY VOLTAGE (V)

3.5

INTVCC OUTPUT VOLTAGE (V)

4.5

20 40 8060

5.5

4.0

5.0

100

2946 G04 INTVCC SHUNT CURRENT (mA)

6.20

INTVCC VOLTAGE (V)

6.30

10 20 30

6.40

6.25

6.35

2946 G05 SENSE VOLTAGE (V)

–20

SENSE CURRENT (µA)

100

20 40 60 80 100

SENSE+

2946 G06

SENSE–

IADR (µA)

–10

2.0

2.5

1.5

1.0

–5 5 10

0.5

3.0

VADR (V)

2946 G07 ILOAD (mA)

0.01

6.4

VSDA,SCL(CL) (V)

6.5

0.10 1.00 10.00

6.3

6.2

6.1

6.0

6.6

2946 G08 IOD (mA)

VOD(OL) (V)

0.2

2 4 86

0.4

0.1

0.3

2946 G09

CODE

–0.10

ADC TUE (%)

–0.05

0.05

0.10

1024 2048 3072 4096

2946 G10

CODE

0.1

0.2

–0.1

2048

1024 3072 4096

–0.2

–0.3

0.3

ADC INL (LSB)

2946 G11 CODE

0.1

0.2

–0.1

2048

1024 3072 4096

–0.2

–0.3

0.3

ADC DNL (LSB)

2946 G12

LTC2946

2946fa

For more information www.linear.com/LTC2946

ADC Total Unadjusted Error

(ΔSENSE)

TYPICAL PERFORMANCE CHARACTERISTICS

Internal Clock Frequency

Over Temperature

VDD Supply Current

over CLKIN Frequency

Current Sense Amplifier Offset

Drift Over Temperature

ADC Conversion Time over

Internal Clock Frequency

Current Sense Amplifier Offset

Drift Over Input Common Mode

ADC Integral Nonlinearity

(ΔSENSE)

ADC Differential Nonlinearity

(ΔSENSE)

CODE

–0.2

ADC TUE (%)

–0.1

0.1

0.2

1024 2048 3072 4096

2946 G13

CODE

0.1

0.2

–0.1

2048

1024 3072 4096

–0.2

–0.3

0.3

ADC INL (LSB)

2946 G14 CODE

0.1

0.2

–0.1

2048

1024 3072 4096

–0.2

–0.3

0.3

ADC DNL (LSB)

2946 G15

TEMPERATURE (°C)

–50

INTERNAL CLOCK FREQUENCY (kHz)

254.4

254.3

254.2

0 50

–25 25 75 100 125

254.1

254.0

254.5

2946 G16 TEMPERATURE (°C)

–50

OFFSET DRIFT (LSB)

0 50

–25 25 75 100 125

–2

2946 G17

CALIBRATION

OFF

CALIBRATION

COMMON MODE VOLTAGE (V)

OFFSET DRIFT (LSB)

25 75 100

–2

2946 G18

INITIAL CALIBRATION DONE AT VCM = 48V

NO CALIBRATION THEREAFTER

CALIBRATION

OFF

CALIBRATION

fCLKIN (MHz)

850

SUPPLY CURRENT (µA)

950

5 10 2015

1050

900

1000

2946 G19 INTERNAL CLOCK FREQUENCY (kHz)

100

CONVERSION TIME (ms)

150 200 250 350300

100

400

2946 G20

SNAPSHOT MEASUREMENT OF ADIN

LTC2946

2946fa

For more information www.linear.com/LTC2946

PIN FUNCTIONS

ADIN: ADC Input. The onboard ADC measures voltages

between 0V and 2.048V with respect to GND or INTVCC.

Tie to ground if unused. See Table 3 in the Applications

Information section for details.

ADR1, ADR0: I2C Device Address Inputs. Connecting these

pins to INTVCC, GND, or leaving the pins open configures

one of nine possible addresses. See Table 1 in the Ap-

plications Information section for details.

CLKIN: Clock Input. Connect to ground to use the internal

±5% clock. For improved accuracy, connect to an external

crystal oscillator circuit or drive with an external clock.

CLKOUT: Clock Output. Connect to an external crystal

oscillator circuit. Leave open if unused.

EXPOSED PAD: Exposed Pad may be left open or con-

nected to device ground. For best thermal performance,

connect to a large PCB area.

GND: Device Ground.

GPIO1: General Purpose Input/Output (Open Drain). Con-

figurable to general purpose output or input. Tie to ground

if unused. See Table 9 in the Applications Information

section for details.

GPIO2: General Purpose Input/Output (Open Drain). Con-

figurable to general purpose output, input or accumulation

enable (ACC) to gate internal accumulators. Tie to ground

if unused. See Table 9 in the Applications Information

section for details.

GPIO3: General Purpose Input/Output (Open Drain).

Configurable to general purpose output, input or ALERT.

As ALERT, it is pulled to ground when a fault occurs to

alert the host controller. A fault alert is enabled by setting

the corresponding bit in the ALERT registers, as shown

in Tables 5 and 8. Tie to ground if unused. See Table 9 in

the Applications Information section for details.

INTVCC: Internal Low Voltage Supply Input/Output. This pin

is used to power internal circuitry. It can be configured as

a direct input for a low voltage supply, as a linear regula-

tor from a higher voltage supply connected to VDD, or as

a shunt regulator. Connect this pin directly to a 2.7V to

5.8V supply if available. When INTVCC is powered from

an external supply, short the VDD pin to INTVCC. If VDD is

connected to a 4V to 100V supply, INTVCC becomes the

5V output of an internal series regulator that can supply

up to 10mA to external circuitry. For even higher supply

voltages, or if a floating topology is desired, INTVCC can

be used as a 6.3V shunt regulator. Connect the supply to

INTVCC through a resistor or current source that limits the

shunt regulator current to less than 35mA. An undervolt-

age lockout circuit disables the ADC when the voltage at

this pin drops below 2.5V. Connect a bypass capacitor of

0.1μF or greater from this pin to ground. If an external

load is present, for loop stability use a bypass capacitor

of 0.22μF or greater.

SCL: I2C Bus Clock Input. Data at the SDAI pin is shifted

in or out on rising edges of SCL. This pin is driven by an

open-collector output from a master controller. An external

pull-up resistor or current source is required and can be

placed between SCL and VDD or INTVCC. The voltage at

SCL is internally clamped to 6.4V typically.

LTC2946

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For more information www.linear.com/LTC2946

SDAI: I2C Bus Data Input. Used for shifting in address,

command or data bits. This pin is driven by an open-

collector output from a master controller. An external

pull-up resistor or current source is required and can be

placed between SDAI and VDD or INTVCC. The voltage at

SDAI is internally clamped to 6.4V typically. Tie to SDAO

for normal I2C operation.

SDAO: LTC2946 Only. I2C Bus Data Output. Open-drain

output used for sending data back to the master control-

ler or acknowledging a write operation. An external

pull-up resistor or current source is required. Tie to SDAI

for normal I2C operation.

SDAO: LTC2946-1 Only. Inverted I2C Bus Data Output.

Open-drain output used for sending data back to the

master controller or acknowledging a write operation.

Data is inverted for convenience of opto-isolation. An

external pull-up resistor or current source is required. The

LTC2946-1 cannot be used in nonisolated I2C applications

without additional components.

SENSE+: Supply Voltage and Current Sense Input. Used

as a supply and current sense input for internal current

sense amplifier. The voltage at this pin is monitored by

the onboard ADC with a full-scale input range of 102.4V.

See Figure 20 for recommended Kelvin connection.

SENSE–: Current Sense Input. Connect an external sense

resistor between SENSE+ and SENSE–. The differential

voltage between SENSE+ and SENSE– is monitored by the

onboard ADC with a full-scale sense voltage of 102.4mV.

VDD: High Voltage Supply Input. This pin powers an in-

ternal series regulator with input voltages ranging from

4V to 100V and produces 5V at INTVCC when VDD is above

8V. Connect a bypass capacitor of 0.1μF or greater from

this pin to ground if an external load is present on the

INTVCC pin. The onboard 12-bit ADC can be configured

to monitor the voltage at VDD with a full-scale input range

of 102.4V.

PIN FUNCTIONS

LTC2946

2946fa

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BLOCK DIAGRAM

TIMING DIAGRAM

tSP

tBUF

tSU,STO

tSP

tHD,STA

START

CONDITION

STOP

CONDITION

tSU,STA

tHD,DATI

tHD,DATO

REPEATED START

CONDITION

REPEATED START

CONDITION

tSU,DAT

SDA

SCL

tHD,STA

2946 TD

–

2946BD

SDAO/SDAO

LTC2946/

LTC2946-1

SDAI

CLKOUT

SENSE–

SENSE+

VDD

VREF

2.048V

INTVCC

ADIN

CLKIN

GND

ADR0

VOLTAGE

CURRENT

POWER

TIME COUNTER

CHARGE

ENERGY

I2C

DECODER

ADR1

GPIO3

1.22V

GPIO2

SCL

20X

6.3V

735k

15k

735k

15k

6.4V 6.4V

1.22V

GPIO1

1.22V

OSC

5V LDO

∆∑ ADC

11 9 10

1412876

LTC2946

2946fa

For more information www.linear.com/LTC2946

0.1µF

33pF

VIN

4V TO

100V

RSNS

0.02Ω

VOUT

VADIN

GP OUTPUT

X1: ABLS-4.000MHZ-B2-T

3.3V

VDD

SCL

SDA

INT

GND

ADR0

SCL

VDD

INTVCC

SDAI

SDAO

GPIO1

ALERT

ADR1

SENSE+

ACCUMULATE

SENSE–

LTC2946

µP

GPIO3

CLKOUT

GND

GPIO2

3.3V

CLKIN

2946 F01

ADIN

33pF

OPERATION

The LTC2946 accurately monitors current, voltage and

power of any supply rail from 0V to 100V. An internal linear

regulator allows the LTC2946 to operate directly from a 4V

to 100V rail, or from an external supply voltage between

2.7V and 5.8V. Quiescent current is less than 1.3mA in

normal operation. Enabling shutdown mode via the I2C

interface reduces the quiescent current to below 40µA.

The onboard 12-bit analog-to-digital converter (ADC)

runs either continuously or on demand using snapshot

mode. There are seven continuous scan modes that can

be selected via I2C. These modes configure the ADC to re-

peatedly measure the differential voltage between SENSE+

and SENSE– (full-scale 102.4mV), the voltage at SENSE+

or VDD pin (full-scale 102.4V) and the voltage applied to

ADIN pin (full-scale 2.048V) at internally set duty cycles.

See the Applications Information section for more details.

The conversion results are stored in onboard registers.

In snapshot mode, the LTC2946 performs a single mea-

surement of one selected voltage or current. A status bit

in the STATUS2 register monitors the ADC’s conversion

progress; when complete, the conversion result is stored

in the corresponding data registers.

The GPIO1 to GPIO3 pins are general purpose inputs or

general purpose open-drain outputs. GPIO2 may also be

configured as an enabling input for the accumulators.

Similarly, GPIO3 may be configured as an ALERT output.

Onboard logic stores the minimum and maximum values

for each ADC measurement, calculates power data by

digitally multiplying the stored current and voltage data,

and optionally triggers an alert by pulling the GPIO3

pin low when the ADC measured value falls outside the

programmed window thresholds. The LTC2946 includes

accumulators that integrate the measured current and

power over time to produce charge and energy values.

The accumulators integrate at a rate determined either

with an internal trimmed ±5% clock, a precision clock

generated from an external crystal, or an external clock.

The accumulators can be preset with a value and optionally

generate an alert when they overflow.

The LTC2946 includes an I2C interface to access the

onboard data registers and to program the alert thresh-

old, configuration and control registers. Tw o three-state

pins, ADR1 and ADR0, are decoded to allow nine device

addresses (see Table 1). The SDA pin is split into SDAI

(input) and SDAO (output, LTC2946) or SDAO (output,

LTC2946-1) to facilitate opto-isolation. Tie SDAI and

SDAO together for normal, nonisolated I2C operation.

Figure 1. High Side Power, Energy and Charge

Monitor Using the LTC2946

APPLICATIONS INFORMATION

The LTC2946 offers a compact and complete solution for

high and low side power monitoring with integrated energy

and charge accumulators. With an input common mode

range of 0V to 100V and a wide input supply operating

voltage range from 2.7V to 100V, this device is ideal for a

wide variety of power management applications including

automotive, industrial and telecom infrastructure. The basic

application circuit shown in Figure 1 provides monitoring of

high side current with a 0.02Ω resistor (5.12A full-scale),

input voltage (102.4V full-scale) and an external voltage

(2.048V full-scale), all using an internal 12-bit ADC.

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APPLICATIONS INFORMATION

is shown where the ADC periodically calibrates the cur-

rent sense amplifier with other voltages sequenced for

conversions in between.

Tw o factors need to be considered when selecting between

these configurations:

1. Presence of load current harmonics in sync with the

windows when the ADC is not sampling the current.

The user can improve measurement accuracy of the

load current signal with such harmonics by selecting

a higher duty cycle for ΔSENSE. For most complete

coverage, the ADC can be configured to continuously

measure the current by setting CA[2:0] to 110.

2. Increasing the duty cycle for current measurement

will result in less frequent updates of the current

sense amplifier’s offset and the supply voltage values,

hence the amount they drift with respect to time and

temperature determines the best configuration to use.

An on-demand update can also be done with a single

I2C write transaction to the CTRLA register, which will

command new measurements of the current sense

amplifier’s offset and the supply voltage. The results

will be used for offset calibration and for providing the

voltage value for the multiplier. For example, if CA[6:5]

is set to code 11, and CA[2:0] is set to 110, a new

offset and voltage values will be produced two ADC

conversions after the I2C write transaction. The ADC

will continuously measure the current thereafter.

The timing diagram shown in Figure 2d illustrates the

sequence in which the power and accumulator data are

generated following conversions in the default configura-

tion. At t1, the ADC has just finished a conversion of the

current (ΔSENSE) signal. The time counter is incremented

by one count while the new current data at t1 is added to

the charge accumulator. A new power value is generated

by multiplying I(t1) with the previous voltage (VIN) data

that is then added to the energy accumulator. From t1 to

t3, the systematic offset of the current sense amplifier is

measured and stored. The ADC then performs a conversion

on VIN. A calibration is done again at t4 before the ADC

converts ΔSENSE. The charge and energy accumulators

are incremented at t2, t3, t4, t5, t6 and t7, with current and

power data from time t1. The timer counter will keep track

Data Converter, Multiplier and Accumulator

The LTC2946 features an onboard, 12-bit Δ∑ ADC that

inherently averages input signal and noise over the con-

version time window. The differential voltage between

SENSE+ and SENSE– (ΔSENSE) is monitored with 25μV/

LSB resolution (102.4mV full-scale) to allow accurate

measurement of the load current across very low value

shunt resistors. The supply voltage at VDD or SENSE+ is

directly measured with 25mV/LSB resolution (102.4V

full-scale). The voltage at the uncommitted ADIN pin can

also be measured with 0.5mV/LSB resolution (2.048V full-

scale) to allow monitoring of an arbitrary external voltage.

The supply voltage data is derived from VDD, SENSE+ or

ADIN depending on the external application circuit. SENSE+

is selected by default as it is normally connected to the

supply voltage as shown in Figure 4 (4a to 4c) and Figure

5b. In negative supply voltage systems, such as shown in

Figure 5d, VDD is used to measure the supply voltage at

GND with respect to the device ground. For positive and

negative supply voltages of more than 100V, as shown in

Figure 5a and Figure 5c, external resistors can be used to

divide down the voltage for ADIN to measure the supply

voltage. CA[4:3] in the CTRLA register select between VDD,

SENSE+ and ADIN for supply voltage data. More details

can be found in Table 3. A 24-bit power value is generated

by digitally multiplying the 12-bit load current data with

the 12-bit supply voltage data. 1LSB of power is 1LSB of

voltage multiplied by 1LSB of ΔSENSE (current). The result

is held in the three adjacent POWER registers (Table 2).

During conversions, the data converter’s input is mul-

tiplexed to measure four voltages: ΔSENSE, the current

sense amplifier’s offset, VDD or VSENSE+, and VADIN at

various duty cycle by configuring CA[6:5] and CA[2:0]

in the CTRLA register (Table 3). Some configurations

are shown in Figure 2 (2a to 2c) to illustrate the various

conversion timing sequences. In Figure 2a, it is shown

that upon power-up or after an I2C write transaction to

the CTRLA register the ADC will first measure the current

sense amplifier’s offset (calibration) and again after every

other conversion which can be either VADIN, the supply

voltage (VDD or VSENSE+) or the load current (ΔSENSE).

Figure 2b shows periodic calibration performed every 16

conversions. In Figure 2c a more specific configuration

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MEAS ADIN

N = 1

MEAS ADIN

N = 1

CAL CALCAL

MEAS V

N = 2

MEAS I

N = 3

POWER-UP OR

CTRLA WRITTEN

MEAS I

N = 128

MEAS I

N = 129

MEAS I

N = 256

2946 F02

MEAS

N = 1

CAL CAL

MEAS

N = 2

MEAS

N = 3

POWER-UP OR

CTRLA WRITTEN

MEAS

N = 16

MEAS

N = 1

MEAS

N = 2

MEASCAL CAL MEAS

MEAS VMEAS I CAL CAL CALMEAS I

POWER-UP OR

CTRLA WRITTEN

16.4ms

NEW POWER = P(t8)

NEW CURRENT= I(t8)

16.4ms

POWER = P(t1)

CURRENT= I(t1)

16.4ms

POWER = P(t1)

CURRENT= I(t1)

16.4ms

POWER = P(t1)

CURRENT= I(t1)

16.4ms

POWER = P(t1)

CURRENT= I(t1)

16.4ms

POWER = P(t1)

CURRENT= I(t1)

16.4ms

POWER = P(t1)

CURRENT= I(t1)

NEW POWER = P(t1)

NEW CURRENT= I(t1)

(2b) Current Sense Amplifier Calibrated Every 16 Conversions, CA[6:5] = 01

(2c) The ADC Conversion Sequence for CA[6:5] = 10 and CA[2:0] = 101

(2d) Default ADC Conversion Sequence

Figure 2

(2a) Current Sense Amplifier Calibrated Every Conversion, CA[6:5] = 00

APPLICATIONS INFORMATION

of the number of accumulations that have occurred. At t8,

new current and power data becomes available and these

values are added to the charge and energy accumulators.

For other CA configurations, the charge and energy ac-

cumulators behave similarly; during calibration and when

not measuring current the last current value will be used

for accumulation and calculation of power.

A 12-bit digital word corresponding to each measured

voltage is stored in two adjacent registers out of the six

total ADC data registers (ΔSENSE MSB/LSB, VIN MSB/

LSB, and ADIN MSB/LSB), with the eight MSBs in the first

The lowest 4 bits in the LSB registers are set to 0. These

data registers are updated immediately following the cor-

responding ADC conversion.

The 4-byte time counter keeps track of the elapsed time

during which current and power measurements have been

added to the charge and energy accumulators, respectively.

At 16.395ms per count it will keep counts up to 2.23 years

(see Table 15). Dividing the energy/charge by the time in

the timer will yield the average power/current over the

time interval in the timer. The charge accumulator is a

36-bit register with the most significant 32-bits accessible,

hence one charge bit is equivalent to one timer tick of 16

(24) counts of current. Similarly, the energy accumulator

is a 48-bit register with the most significant 32-bits ac-

cessible, hence one energy bit is equivalent to one timer

tick of 65536 (216) counts of power. With current and

power at full-scale the charge and energy accumulators

are capable of storing 3.2 days of data which translates

to several months at nominal current and power levels.

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Since the accumulators contain multiple bytes of data,

a single page read transaction of the accumulators is

required to ensure the data is coherent. All the accumula-

tors are writable, allowing them to be preloaded with given

values. The LTC2946 can then be configured to generate

an overflow alert after a specified amount of energy or

charge has been delivered or when a preset amount of

time has elapsed.

A snapshot mode is also included which makes a measure-

ment of a single selected voltage (either ΔSENSE, VDD or

VSENSE+, or VADIN). To make a snapshot measurement,

write the 2-bit code of the desired ADC channel to CA[4:3]

and code 111 to CA[2:0] using a write byte command to

the CTRLA register. When the write byte command is

completed, the ADC converts the selected voltage and

the busy bit S2[3] in the STATUS2 register (see Table 10)

will be set to indicate that the conversion is in progress.

After completing the conversion, the ADC will halt and the

busy bit will reset to indicate that the data is ready. An

alert may be generated at the end of a snapshot conver-

sion by setting bit AL2[7] in the ALERT2 register (Table

8). To make another snapshot measurement, rewrite the

CTRLA register. In snapshot mode, the POWER registers,

time counters, charge and energy accumulators are not

refreshed.

Crystal Oscillator/External Clock

Accurately measuring energy/charge by integrating power/

current requires a precise integration period. The on-chip

clock of the LTC2946 is trimmed to within ±5%. To enable

timekeeping with the on-chip clock, tie CLKIN to GND and

leave CLKOUT open. For better accuracy, a crystal oscillator

or resonator may be connected to the CLKIN and CLKOUT

pins, as shown in Figure 1. Alternately, an external clock

between 1MHz and 25MHz may be applied to CLKIN with

CLKOUT left unconnected. The clock frequency at CLKIN is

divided by 4× the value in the CLK_DIV register (see Table

13) to generate an internal clock with targeted frequency

of 250kHz for the data converter’s delta-sigma modulator.

With an external clock or crystal, the sampling frequency

of the ADC can be adjusted by configuring the CLK_DIV

100kHz and 400kHz and at least 20kHz above or below fIN.

The delta-sigma ADC provides inherent averaging of the

input signal such that an anti-aliasing filter is not required

in most applications. However, noise ripple (fIN) occurring

at integer multiples of the modulator sampling frequency

(fS) can still pose problems. Figure 3 shows how the

sampling frequency as a function of the input frequency

affects the amount of error. When fS = fIN, in the worst

case the input signal may be sampled entirely at its peak

APPLICATIONS INFORMATION

Figure 3. Waveforms Showing the Effect of Aliasing

0µs 10µs 20µs 30µs 40µs 50µs 60µs 70µs 80µs 100µs90µs 2946 F03

fS = 0.9 • fIN

tIN

fS = 1.1 • fIN

fS = fIN

tIN

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(or trough) resulting in an average output value of VPEAK

(or VTROUGH). The actual average value of the input is

½ • (VPEAK – VTROUGH). Slightly adjusting the sampling

frequency will remove the error as samples representative

of the entire waveform are averaged over the conversion

period. This is illustrated in the waveforms corresponding

to fS = 0.9fIN and fS = 1.1fIN. The input can be seen to

get sampled at multiple instances between the peak and

trough. Averaging sufficient number of samples will then

yield the correct result.

Flexible Power Supply to LTC2946

The LTC2946 can be externally configured to derive power

from a wide range of supplies. The LTC2946 includes an

onboard linear regulator to power the low voltage inter-

nal circuitry connected to the INTVCC pin from high VDD

voltages. The linear regulator operates with VDD voltages

from 4V to 100V, and a shunt regulator is available for

voltages above 100V. The linear regulator produces a 5V

output capable of supplying 10mA at the INTVCC pin when

VDD is greater than 8V. The regulator is disabled when the

junction temperature rises above 150°C, and the output

is protected against accidental shorts. Bypass capacitors

of 0.1μF, or greater, at both the VDD and INTVCC pins are

recommended for optimal transient performance. Note that

operation with high VDD voltages can result in significant

power dissipation, and care is required to ensure that the

maximum operating junction temperature stays below

125°C. For improved thermal resistance, use the DFN

package and solder the exposed pad to a large copper

region on the PCB.

Figure 4a shows the LTC2946 being used to monitor an

input supply that ranges from 4V to 100V. No secondary

supply is needed since VDD can be connected directly to

the input supply. If the LTC2946 is used to monitor an

input supply of 0V to 100V, it can derive power from a

wide range secondary supply connected to the VDD pin

as shown in Figure 4b. The SENSE+/– pins can be biased

independently of the part’s supply voltage. Alternatively,

if a low voltage supply is present it can be connected to

the INTVCC pin, as shown in Figure 4c, to minimize on-

chip power dissipation. When INTVCC is powered from a

secondary supply, connect VDD to INTVCC.

For supply voltages above 100V, the shunt regulator at

INTVCC can be used in both high and low side configura-

tions to provide power to the LTC2946 through an external

shunt resistor, RSHUNT. Figure 5a shows a high side power

APPLICATIONS INFORMATION

Figure 4

(4c) LTC2946 Derives Power from a

Low Voltage Secondary Supply

(4a) LTC2946 Derives Power from the

Supply Being Monitored

(4b) LTC2946 Derives Power from a

Wide Range Secondary Supply

SENSE+SENSE–

VDD

INTVCC

LTC2946

GND

VOUT

RSNS

VIN

4V TO 100V

2946 F04a

SENSE+SENSE–

VDD

INTVCC

LTC2946

GND

VOUT

RSNS

VIN

0V TO 100V

4V TO 100V

2946 F04b

SENSE+SENSE–

VDD

INTVCC

LTC2946

GND

VOUT

RSNS

VIN

0V TO 100V

2.7V TO 5.9V

2946 F04c

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Figure 5

monitor with an input monitoring range beyond 100V in a

high side shunt regulator configuration. The device ground

is separated from ground through RSHUNT and clamped at

6.3V below the input supply. Note that due to the different

ground levels, the I2C signals from the part need to be level

shifted for communication with other ground referenced

components. The bus voltage is measured with a resistor

string connected to ADIN. Set CA[7] in the CTRLA register

so that the ADC measures ADIN with reference to INTVCC

instead of GND. The measurement range at ADIN is then

from INTVCC to INTVCC – 2.048V.

Figure 5b shows a high side rail-to-rail power monitor

which derives power from a secondary supply greater

than 100V. The voltage at INTVCC is clamped at 6.3V

above ground in a low side shunt regulator configuration

to power the part. In low side power monitors, the device

ground and the current sense inputs are connected to the

negative terminal of the input supply as shown in Figure

5c. The low side shunt regulator configuration allows

operation with input supplies above 100V by clamping

the voltage at INTVCC. RSHUNT should be sized according

to the following equation:

S(MAX)

−V

CCZ(MIN)

ICC(ABSMAX)

≤RSHUNT ≤

S(MIN)

−V

CCZ(MAX)

ICC(MAX)+ILOAD(MAX)

VS(MAX) −5.8V

35mA ≤RSHUNT ≤VS(MIN) −6.7V

1mA +ILOAD(MAX)

(1)

where VS(MAX) and VS(MIN) are the operating maximum

and minimum limits of the supply. ILOAD(MAX) is the maxi-

mum external current load that is connected to the shunt

regulator. The shunt resistor must also be rated to safely

APPLICATIONS INFORMATION

(5c) LTC2946 Derives Power Through a Low Side Shunt

Regulator in a Low Side Current Sense Topology

(5d) LTC2946 Derives Power from the Supply Monitored

in a Low Side Current Sense Topology

(5a) LTC2946 Derives Power Through a High Side

Shunt Regulator

(5b) LTC2946 Derives Power Through a Low Side Shunt

Regulator in a High Side Current Sense Topology

SENSE+SENSE–

ADIN

INTVCC

LTC2946

GND

VOUT

RSNS

VIN

>100V

2946 F05a

VDD

RSHUNT

R1 SENSE+SENSE–

VDD

INTVCC

LTC2946

GND

VOUT

RSNS

RSHUNT

VIN

0V TO 100V

>100V

2946 F05b

SENSE–SENSE+

ADIN

INTVCC

LTC2946

VOUT

RSNS

> –100V

2946 F05c

GND

VDD

RSHUNT

SENSE+

SENSE–

INTVCC

LTC2946

VOUT

RSNS

VNEG

(–4V TO –100V)

2946 F05d

GND

VDD

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dissipate the worst-case power. As an example, consider

the –48V telecom system where the supply operates from

–36V to –72V and the shunt regulator is used to supply

an external load up to 4mA. RSHUNT needs to be between

1.9k and 5.9k according to the previous equation, and for

reduced power dissipation, a larger resistance is advan-

tageous. The worst-case power dissipated in an RSHUNT

of 5.36k is calculated to be 0.8W. Three 0.5W rated 1.8k

resistors in series would suffice for this example.

If the supply input is below 100V, the shunt resistor is not

required and VDD can be connected to GND of the supply

as shown in Figure 5d.

Supply Undervoltage Lockout

During power-up, the internal I2C logic and the ADC are

enabled when either VDD or INTVCC rises above its under-

voltage lockout threshold. During power-down, the ADC is

disabled when VDD and INTVCC fall below their respective

undervoltage lockout thresholds. The internal I2C logic is

reset when VDD and INTVCC fall below their respective I2C

reset thresholds.

Shutdown Mode

The LTC2946 includes a low quiescent current shutdown

mode, controlled by bit CB[6] in the CTRLB register

(Table 4). Setting CB[6] puts the part in shutdown mode,

powering down the ADC, internal reference and onboard

linear regulator. The internal I2C bus remains active,

and although the ADR1 and ADR0 pins are disabled, the

device will retain the most recently programmed I2C bus

address. All onboard registers retain their contents and

can be accessed through the I2C interface. To re-enable

ADC conversions, reset bit CB[6] in the CTRLB register.

The analog circuitry will power up and all registers will

retain their contents.

The onboard linear regulator is disabled in shutdown mode

to conserve power. If the onboard linear regulator is used

to power external I2C bus related circuitry such as opto-

couplers or pull-ups, I2C communication will be lost when

the part is shut down. The LTC2946 would then have to

be reset by cycling its power to come out of shutdown. If

low IQ mode is not required, ensure bit CB[6] in the CTRLB

recommended that external regulators be used in such

applications if powering down the LTC2946 is desirable.

As an added layer of protection against this scenario, bit

CB[4] in the CTRLB register can be set during system

configuration to enable the LTC2946 to automatically exit

shutdown mode when the I2C lines are low for more than

33ms (which can be a result of accidental shutdown of the

LTC2946’s linear regulator powering the I2C). The user

can elect to be alerted of this event by setting bit AL2[3]

in the ALERT2 register (Table 8). Quiescent current drops

below 40μA in shutdown mode with the internal regulator

disabled.

Configuring the GPIO Pins

The LTC2946 has three GPIO pins configurable through

the GPIO_CFG register (Table 9) to be used as general

purpose input/output pins. As general purpose inputs,

GPIO1 through GPIO3 can be either active HIGH or LOW.

In addition, GPIO2 can also be used as an accumulation

enable input by writing bits CB[3:2] = [10] to allow integra-

tion of the time counter, charge and energy accumulators.

GPIO1 through GPIO3 have comparators monitoring the

voltage on these pins with a threshold of 1.22V, the results

of which may be read from bits S2[6:4] in the STATUS2

when GPIO1 or GPIO2 are active as inputs by setting bits

AL2[6] and AL2[5], respectively, in the ALERT2 register.

GPIO1-3 can be pulled low as general purpose outputs,

which are otherwise high impedance. GPIO3 is by default

an ALERT output that pulls low when an alert event is

present. To pull GPIO3 (ALERT) low in the absence of an

alert event, set GC[7] of the GPIO3_CTRL register (Table

12). Clearing this bit will release the GPIO3 (ALERT). GC[7]

does not have an effect on GPIO3 if it is not configured as

an ALERT output. Likewise, GC[6] does not affect GPIO3

if it is not configured as a general purpose output. GC[7]

is set whenever an alert event occurs irrespective of

GPIO3's configuration. Reset GC[7] before reconfiguring

GPIO3 to ALERT.

APPLICATIONS INFORMATION

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I2C Reset

The accumulators can be programmed to reset themselves

after the host reads the last byte (3Fh) of the accumulator

data by writing bits CB[1:0] to [01] in the CTRLB register

(Table 4). This feature removes the need to issue a reset

command after polling the LTC2946 for accumulated data.

The accumulators will continue to accumulate after the

reset. To reset the accumulators without such read com-

mand, write bits CB[1:0] to [10]. The accumulators will

stay reset if CB[1:0] = [10]. All registers are reset when

CB[1:0] = [11], and these bits will then auto-reset to [00].

The ADC sequencing configuration is preserved through

the I2C reset, regardless of the CTRLA register having

reset. To change the sequencing configuration after such

resets, rewrite the CTRLA register.

Storing Minimum and Maximum Values

The LTC2946 compares each measurement including the

calculated power with the stored values in the respective

MIN and MAX registers for each parameter (Table 2). If

the new conversion is beyond the stored minimum or

maximum values, the MIN or MAX registers are updated

with the new values. The MIN and MAX of the registers

are refreshed at the end of their respective ADC conver-

sions in continuous scan modes and snapshot mode. They

are also refreshed if the ADC registers are written via the

I2C bus with values beyond the stored values. To initiate

a new peak hold cycle, write all 1’s to the MIN registers

and all 0’s to the MAX registers via the I2C bus. These

registers will be updated when the next respective ADC

conversion is done.

The LTC2946 also includes MIN and MAX threshold reg-

isters (Table 2) for the measured parameters including the

calculated power. At power-up, the maximum thresholds

are set to all 1’s, and minimum thresholds are set to all

0’s, effectively disabling them. The thresholds can be

reprogrammed to any desired value via the I2C bus.

Fault Alert and Resetting Faults

As soon as a measured quantity falls below the minimum

threshold or exceeds the maximum threshold, the LTC2946

sets the corresponding flag in the STATUS1 (Table 6) reg-

ister and latches it into the FAULT1 (Table 7) register (see

Figure 6). Other events such as GPIO state change, stuck

bus wake-up and accumulator overflow have their present

status in the STATUS2 (Table 10) register and any fault is

latched in the FAULT2 (Table 11) register. The GPIO3 pin

is pulled low if the appropriate bit in the ALERT1 (Table 5)

and ALERT2 (Table 8) registers is set and it is configured

as ALERT output. More details on the alert behavior can

be found in the Alert Response Protocol section.

An active fault indication can be reset by writing zeros

to the corresponding FAULT register bits or setting bit

CB[5] in the CTRLB register. If bit CB[5] is set, reading the

FAULT1 or FAULT2 register will cause the corresponding

if the VDD and INTVCC fall below their respective I2C logic

reset threshold. Note that faults that are still present, as

indicated in the STATUS1 and STATUS2 registers, will

immediately reappear.

When accumulators (time, charge and energy) overflow,

the corresponding bits in the STATUS2 register are set

and will stay set. The accumulator overflow bits in the

FAULT2 register will reappear after they have been cleared

via I2C since the STATUS2 register continues to indicate

overflow faults.

APPLICATIONS INFORMATION

Figure 6. LTC2946 Fault Alert Generation Blocks

DIGITAL

COMPARATOR

LOGIC LATCH

STATUS

RESET

FAULT

ALERT ENA_ALERT_RESPONSE

MEASURED

DATA

THRESHOLD

DATA

2946 F06

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Figure 7. General Data Transfer Over I2C

SDA

SCL

S P

a6 - a0 b7 - b0 b7 - b0

1 - 7 1 - 7 1 - 78 8 89 9 9

START

CONDITION

STOP

CONDITION

ADDRESS ACK DATA DATAACK ACKR/W2946 F06

Figure 8. LTC2946 Serial Bus SDA Write Byte Protocol Figure 9. LTC2946 Serial Bus SDA Write Word Protocol

Figure 10. LTC2946 Serial Bus SDA Write Page Protocol Figure 11. LTC2946 Serial Bus SDA Read Byte Protocol

Figure 12. LTC2946 Serial Bus SDA Read Word Protocol

Figure 13. LTC2946 Serial Bus SDA Read Page Protocol Protocol

S ADDRESS

1 1 0 a3:a0

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

COMMAND DATA

X X b5:b00

0 0 0b7:b0

A A A P

2946 F08

: WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

S ADDRESS

1 1 0 a3:a0

COMMAND DATA DATA

X X b5:b00

0 0 0 0

2946 F09

b7:b0b7:b0

AA A A P

S ADDRESS

1 1 0 a3:a0

COMMAND

0X X b5:b00

0 0

2946 F10

A A A P

b7:b0

DATA

b7:b0

DATA

...

b7:b0

DATA S ADDRESS

1 1 0 a3:a0 1 1 0 a3:a0 1 0

COMMAND S ADDRESS R A

b7:b0 1

DATA

X X b5:b00

0 0

2946 F11

A A AP

S ADDRESS

1 1 0 a3:a0 1 1 0 a3:a0 1 0

COMMAND S ADDRESS R A

b7:b0 1

DATA

X X b5:b00

0 0

2946 F12

b7:b0

DATA

AAP

S ADDRESS

1 1 0 a3:a0 1 1 0 a3:a0 1 0

COMMAND S ADDRESS R A

b7:b0 1

DATA

X X b5:b00

0 0

2946 F13

b7:b0

DATA

AAP

...

b7:b0

DATA

If it is necessary to clear accumulator overflow fault(s),

the recommended procedure is:

1. Read the accumulators

2. Store these values in an external memory

3. Issue a reset to the accumulators by writing bits CB[1:0]

to [10]. Then disable reset by writing bits CB[1:0] to

[00].

4. Write the stored values back to the accumulators

Steps 2 and 4 can be skipped if there is no need to continue

the accumulation from present values.

I2C Interface

The LTC2946 includes an I2C/SMBus-compatible inter-

face to provide access to the onboard registers. Figure 6

shows a general data transfer format using the I2C bus.

The LTC2946 is a read/write slave device and supports the

SMBus read byte, write byte, read word and write word

protocols. The LTC2946 also supports extended read and

write commands that allow reading or writing more than

two bytes of data. When using the read/write word or

extended read and write commands, the bus master issues

an initial register address and the internal register address

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pointer automatically increments by 1 after each byte of

data is read or written. After the register address reaches

43h, it will roll over to 00h and continue incrementing. A

STOP condition resets the register address pointer to 00h.

The data formats for the above commands are shown in

Figure 7 through Figure 13. Note that only the read byte

command is available to the E7 and E8 (MFR_SPECIAL_ID)

registers (Table 2).

I2C Device Addressing

Nine distinct I2C bus addresses are configurable using the

three-state pins ADR0 and ADR1, as shown in Table 1.

ADR0 and ADR1 should be tied to INTVCC, to GND, or

left floating (NC) to configure the lower four address bits.

During low power shutdown, the address select state

is latched into memory powered from standby supply.

Address bits a6, a5 and a4 are permanently set to 110b

and the least significant bit is the R/W bit. In addition, all

LTC2946 devices will respond to a common mass write

address 1100_110b; this allows the bus master to write

to several LTC2946s simultaneously, regardless of their

individual address settings. The LTC2946 will also respond

to the standard ARA address 0001_100b if the GPIO3

(ALERT) pin is asserted. See the Alert Response Protocol

section for more details. The LTC2946 will not respond to

the ARA address if no alerts are pending.

START and STOP Conditions

When the I2C bus is idle, both SCL and SDA are in the HIGH

state. A bus master signals the beginning of a transmission

with a START condition by transitioning SDA from high to

low while SCL stays high. When the master has finished

communicating with the slave, it issues a STOP condition

by transitioning SDA from LOW to high while SCL stays

high. The bus is then free for another transmission.

Stuck-Bus Reset

The LTC2946 I2C interface features a stuck-bus reset timer

to prevent it from holding the bus lines low indefinitely if

the SCL signal is interrupted during a transfer. The timer

starts when either SCL or SDAI is low, and resets when

both SCL and SDAI are pulled high. If either SCL or SDAI

are low for over 33ms, the stuck-bus timer will expire, and

the internal I2C interface and the SDAO pin pull-down logic

will be reset to release the bus. Normal communication

will resume at the next START command.

Acknowledge

The acknowledge signal is used for handshaking between

the master and the slave to indicate that the last byte of

data was received. The master always releases the SDA

line during the acknowledge clock pulse. The LTC2946 will

pull the SDA line low on the 9th clock cycle to acknowledge

receipt of the data. If the slave fails to acknowledge by

leaving SDA high, then the master can abort the transmis-

sion by generating a STOP condition. When the master is

receiving data from the slave, the master must acknowledge

the slave by pulling down the SDA line during the 9th clock

pulse to indicate receipt of a data byte. After the last byte

has been received by the master, it will leave the SDA line

high (not acknowledge) and issue a STOP condition to

terminate the transmission.

Write Protocol

The master begins a write operation with a START condition

followed by the seven-bit slave address and the R/W bit

set to zero. After the addressed LTC2946 acknowledges

the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

write. The LTC2946 acknowledges this and then latches

the lower six bits of the command byte into its internal

data byte and the LTC2946 acknowledges once more and

writes the data into the internal register pointed to by the

additional data bytes with a write word or extended write

command, the additional data bytes will be acknowledged

by the LTC2946, the register address pointer will auto-

matically increment by one, and data will be written as

previously stated. The write operation terminates and the

sends a STOP condition.

Read Protocol

The master begins a read operation with a START condi-

tion followed by the 7-bit slave address and the R/W bit

set to zero. After the addressed LTC2946 acknowledges

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the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

read. The LTC2946 acknowledges this and then latches the

lower six bits of the command byte into its internal register

address pointer. The master then sends a repeated START

condition followed by the same 7-bit address with the R/W

bit now set to 1. The LTC2946 acknowledges and sends

the contents of the requested register. The transmission

terminates when the master sends a STOP condition. If

the master acknowledges the transmitted data byte, as in a

read word command, the LTC2946 will send the contents

of the next register. If the master keeps acknowledging,

the LTC2946 will keep incrementing the register address

pointer and sending out data bytes. The read operation

terminates and the register address pointer resets to 00h

when the master sends a STOP condition.

Alert Response Protocol

When any of the fault bits in the FAULT1 and FAULT2

bit in the ALERT1 or ALERT2 register has been set and

GPIO3 is configured as an ALERT output. This allows the

bus master to select which faults will generate alerts. At

power-up, both ALERT registers are cleared (no alerts

enabled) and the GPIO3 (ALERT) pin is high. If an alert

is enabled, the corresponding fault causes the GPIO3

(ALERT) pin to pull low. The bus master responds to the

alert in accordance with the SMBus alert response protocol

by broadcasting the alert response address 0001_100b,

and the LTC2946 replies with its own address and re-

leases its GPIO3 (ALERT) pin, as shown in Figure 14. The

GPIO3 (ALERT) line is also released if CB[7] is set and

the LTC2946 is addressed (see Table 4) by any message.

The GPIO3 (ALERT) signal is not pulled low again until

the F LT registers indicate a different fault has occurred or

the original fault is cleared and it occurs again. Note that

this means repeated or continuing faults will not generate

additional alerts until the associated F LT register bits have

been cleared.

If two or more LTC2946s on the same bus are generat-

ing alerts when the ARA is broadcast, the bus master

will repeat the alert response protocol until the GPIO3

(ALERT) line is released. Standard I2C arbitration causes

the device with the highest priority (lowest address) to

reply first and the device with the lowest priority (highest

address) to reply last.

Opto-Isolating the I2C Bus

Opto-isolating a standard I2C device is complicated by the

bidirectional SDA pin. The LTC2946/LTC2946-1 minimize

this problem by splitting the standard I2C SDA line into SDAI

(input) and SDAO (output, LTC2946) or SDAO (inverted

output, LTC2946-1). The SCL is an input-only pin and

does not require special circuitry to isolate. For conven-

tional nonisolated I2C applications, use the LTC2946 and

tie the SDAI and SDAO pins together to form a standard

I2C SDA pin.

Low speed isolated interfaces that use standard open-

drain opto-isolators can use the LTC2946 with the SDAI

and SDAO pins separated, as shown in Figure 15. Connect

SDAI to the output of the incoming opto-isolator with a

pull-up resistor to INTVCC or a local 5V supply; connect

SDAO to the cathode of the outgoing opto-isolator with a

current-limiting resistor in series with the anode. The input

and output must be connected together on the isolated

side of the bus to allow the LTC2946 to participate in I2C

arbitration. Note that maximum I2C bus speed will gener-

ally be limited by the speed of the opto-couplers used in

this application.

The shunt regulators can supply up to 34mA of current

to drive opto-isolator and pull-up resistors, as shown in

Figure 16 and Figure 17. For identical SDAI/SCL pull-up

resistors the maximum load is:

ILOAD(MAX) =VCCZ(MAX) •

R5 +











ILOAD(MAX) =6.7V • 2

R5 +1











(2)

RSHUNT can then be calculated using Equation 1. Note that

both LTC2946 and LTC2946-1 can be used in the shunt

Figure 14. LTC2946 Serial Bus SDA Alert Response Protocol

ALERT

RESPONSE

ADDRESS

0 0 0 1 1 0 0

DEVICE

ADDRESS

a7:a0 11

2946 F14

AAP

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Figure 15. Opto-Isolation of a 10kHz I2C Interface Between LTC2946 and Microcontroller

APPLICATIONS INFORMATION

Figure 16. Low Speed 10kHz Opto-Isolators Powered from Low Side Shunt Regulator (SCL Omitted for Clarity)

Figure 17. Low Speed 10kHz Opto-Isolators Powered from High Side Shunt Regulator (SCL Omitted for Clarity)

LTC2946

SDAI

SDAO

GND

3.3V

GND

SDA

µP

1/2 MOCD207M

10k

0.47k

10k

VDD

RSHUNT

2946 F16

RSNS

0.02Ω

SENSE–SENSE+

INTVCC

VDD

1µF

VOUT

VEE

LTC2946-1

SDAI

SDAO

GND

3.3V

GND

SDA

µP

1/2 MOCD207M

10k

VDD

RSHUNT

VIN

2946 F17

RSNS

0.02Ω

SENSE+SENSE–

INTVCC

VDD

1µF

MOCD207M

1/2 MOCD207M

2946 F15

SCL

LTC2946

SDAI

SDAO

0.47k

0.82k R8

0.47k

R10

3.3V

VDD

GND

µP

SCL

SDA

10k

GND

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Figure 18. Opto-Isolation of a 1.5kHz I2C Interface Between LTC2946-1 and Microcontroller (SCL Omitted for Clarity)

Figure 19. Opto-Isolation of a I2C Interface with Low Power, High Speed Opto-Couplers (SCL Omitted for Clarity)

regulator applications mentioned. Figure 18 shows an

alternate connection for use with low speed opto-couplers

and the LTC2946-1. This circuit uses a limited-current

pull-up on the internally clamped SDAI pin and clamps

the SDAO pin with the input diode of the outgoing opto-

isolator, removing the need to use INTVCC for biasing in

the absence of an auxiliary low voltage supply. For proper

clamping:

S(MAX)

−V

SDA,SCL(MIN)

ISDA,SCL(MAX)

≤R4 ≤

S(MAX)

−V

SDA,SCL(MAX)

ISDA,SCL(MIN)

VS(MAX) −5.9V

5mA

≤R4 ≤VS(MAX) −6.9V

0.5mA

(3)

As an example, a supply that operates from 36V to 72V

would require the value of R4 to be between 13k and 58k.

The LTC2946-1 must be used in this application to ensure

that the SDAO signal polarity is correct.

The LTC2946-1 can also be used with high speed opto-

couplers with push-pull outputs and inverted logic as

shown in Figure 19. The incoming opto-isolator draws

power from the INTVCC, and the data output is connected

directly to the SDAI pin with no pull-up required. Ensure

the current drawn does not exceed the 10mA maximum

capability of the INTVCC pin. The SDAO pin is connected

to the cathode of the outgoing opto-coupler with a current

limiting resistor connected back to INTVCC. An additional

discrete N-channel MOSFET is required at the output of

the outgoing opto-coupler to provide the open-drain pull-

down that the I2C bus requires. Finally, the input of the

incoming opto-isolator is connected back to the output

as in the low speed case.

LTC2946-1

SDAI

SDAO

GND

3.3V

GND

SDA

µP

1/2 MOCD207M

VIN

48V

20k

5.6k

0.47k

VDD

2946 F18

48V 1/2 ACPL-064L*

1/2 ACPL-064L*

*CMOS OUTPUT

ISO_SDA

1µF

1µF R5

VDD INTVCC

LTC2946-1

SDAO

SDAI

GND

VCC

GND

BS170

2946 F19

3.3V

GND

SDA

µP

VDD

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Layout Considerations

A Kelvin connection between the sense resistor RSNS and

the LTC2946 is recommended to achieve accurate current

sensing (Figure 20). The recommended minimum trace

width for 1oz copper foil is 0.02" per amp to ensure the

trace stays at a reasonable temperature. Using 0.03" per

amp or wider is preferred. Note that 1oz copper exhibits

a sheet resistance of about 530μΩ per square. In very

high current applications where the sense resistor can

dissipate significant power, the PCB layout should include

good thermal management techniques such as extra vias

and wide metal area.

The crystal oscillator’s clock amplitude is sensitive to

parasitics such as stray capacitance on the CLKOUT pin

and coupling between the CLKIN and CLKOUT pins. It is

recommended that the CLKIN and CLKOUT traces from

the LTC2946 to the crystal oscillator network be as short

as practical with the load capacitors placed next to the

crystal, as shown in Figure 21. To minimize stray capaci-

tances, avoid large ground planes and digital signals near

the crystal network.

Design Example

Given a 20mΩ sense resistor, calculate the weight value per

LSB for the current, power, charge and energy registers:

Current = 25μV/LSB/RSNS

= 1.25mA/LSB

Voltage = 25mV/LSB

(SENSE+/VDD is sensing the voltage)

Power = 1.25mA/LSB • 25mV/LSB

= 31.25μW/LSB

Time = 16.39543ms/LSB (default configuration

250kHz target frequency)

Charge = 1.25mA/LSB • 16 • 16.384ms/LSB

= 327.9086μC/LSB

Energy = 31.25μW • 65536 • 16.39543ms

= 33.578mJ/LSB

Figure 20. Recommended Layout for Kelvin Connection Figure 21. Recommended Layout for Crystal Oscillator

SNS

LOAD

SENSE

–

2946 F20

611

116

GND

2946 F21

CLKIN

CLKOUT

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APPLICATIONS INFORMATION

Table 1. LTC2946 Device Addressing

DESCRIPTION

HEX DEVICE

ADDRESS BINARY DEVICE ADDRESS

LTC2946

ADDRESS PINS

h a6 a5 a4 a3 a2 a1 a0 R/WADR1 ADR0

Mass Write CC 1 1 0 0 1 1 0 0 X X

Alert Response 19 0 0 0 1 1 0 0 1 X X

0 CE 1 1 0 0 1 1 1 X H L

1 D0 1 1 0 1 0 0 0 X NC H

2 D2 1 1 0 1 0 0 1 X H H

3 D4 1 1 0 1 0 1 0 X NC NC

4 D6 1 1 0 1 0 1 1 X NC L

5 D8 1 1 0 1 1 0 0 X L H

6 DA 1 1 0 1 1 0 1 X H NC

7 DC 1 1 0 1 1 1 0 X L NC

8 DE 1101111XLL

Table 2. LTC2946 Register Addresses and Contents

00h CTRLA R/W Operation Control Register A 18h

01h CTRLB R/W Operation Control Register B 00h

02h ALERT1 R/W Selects Which Primary Faults Generate Alerts 00h

03h STATUS1 R Primary Status Information 00h

04h FAULT1 R/W Primary Fault Log 00h

05h POWER MSB2 R/W Power MSB2 Data XXh

06h POWER MSB1 R/W Power MSB1 Data XXh

07h POWER LSB R/W Power LSB Data XXh

08h MAX POWER MSB2 R/W Maximum Power MSB2 Data 00h

09h MAX POWER MSB1 R/W Maximum Power MSB1 Data 00h

0Ah MAX POWER LSB R/W Maximum Power LSB Data 00h

0Bh MIN POWER MSB2 R/W Minimum Power MSB2 Data FFh

0Ch MIN POWER MSB1 R/W Minimum Power MSB1 Data FFh

0Dh MIN POWER LSB R/W Minimum Power LSB Data FFh

0Eh MAX POWER THRESHOLD MSB2 R/W Maximum POWER Threshold MSB2 to Generate Alert FFh

0Fh MAX POWER THRESHOLD MSB1 R/W Maximum POWER Threshold MSB1 to Generate Alert FFh

10h MAX POWER THRESHOLD LSB R/W Maximum POWER Threshold LSB to Generate Alert FFh

11h MIN POWER THRESHOLD MSB2 R/W Minimum POWER Threshold MSB2 to Generate Alert 00h

12h MIN POWER THRESHOLD MSB1 R/W Minimum POWER Threshold MSB1 to Generate Alert 00h

13h MIN POWER THRESHOLD LSB R/W Minimum POWER Threshold LSB to Generate Alert 00h

14h ΔSENSE MSB R/W ΔSENSE MSB Data XXh

15h ΔSENSE LSB R/W ΔSENSE LSB Data X0h

16h MAX ΔSENSE MSB R/W Maximum ΔSENSE MSB Data 00h

17h MAX ΔSENSE LSB R/W Maximum ΔSENSE LSB Data 00h

18h MIN ΔSENSE MSB R/W Minimum ΔSENSE MSB Data FFh

19h MIN ΔSENSE LSB R/W Minimum ΔSENSE LSB Data F0h

1Ah MAX ΔSENSE THRESHOLD MSB R/W Maximum ΔSENSE Threshold MSB to Generate Alert FFh

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1Bh MAX ΔSENSE THRESHOLD LSB R/W Maximum ΔSENSE Threshold LSB to Generate Alert F0h

1Ch MIN ΔSENSE THRESHOLD MSB R/W Minimum ΔSENSE Threshold MSB to Generate Alert 00h

1Dh MIN ΔSENSE THRESHOLD LSB R/W Minimum ΔSENSE Threshold LSB to Generate Alert 00h

1Eh VIN MSB R/W ADC VIN MSB Data XXh

1Fh VIN LSB R/W ADC VIN LSB Data X0h

20h MAX VIN MSB R/W Maximum VIN MSB Data 00h

21h MAX VIN LSB R/W Maximum VIN LSB Data 00h

22h MIN VIN MSB R/W Minimum VIN MSB Data FFh

23h MIN VIN LSB R/W Minimum VIN LSB Data F0h

24h MAX VIN THRESHOLD MSB R/W Maximum VIN Threshold MSB to Generate Alert FFh

25h MAX VIN THRESHOLD LSB R/W Maximum VIN Threshold LSB to Generate Alert F0h

26h MIN VIN THRESHOLD MSB R/W Minimum VIN Threshold MSB to Generate Alert 00h

27h MIN VIN THRESHOLD LSB R/W Minimum VIN Threshold LSB to Generate Alert 00h

28h ADIN MSB R/W ADIN MSB Data XXh

29h ADIN LSB R/W ADIN LSB Data X0h

2Ah MAX ADIN MSB R/W Maximum ADIN MSB Data 00h

2Bh MAX ADIN LSB R/W Maximum ADIN LSB Data 00h

2Ch MIN ADIN MSB R/W Minimum ADIN MSB Data FFh

2Dh MIN ADIN LSB R/W Minimum ADIN LSB Data F0h

2Eh MAX ADIN THRESHOLD MSB R/W Maximum ADIN Threshold MSB to Generate Alert FFh

2Fh MAX ADIN THRESHOLD LSB R/W Maximum ADIN Threshold LSB to Generate Alert F0h

30h MIN ADIN THRESHOLD MSB R/W Minimum ADIN Threshold MSB to Generate Alert 00h

31h MIN ADIN THRESHOLD LSB R/W Minimum ADIN Threshold LSB to Generate Alert 00h

32h ALERT2 R/W Selects Which Secondary Faults Generate Alerts 00h

33h GPIO_CFG R/W GPIO Configuration 00h

34h TIME COUNTER MSB3 R/W Time Counter MSB Data3 XXh

35h TIME COUNTER MSB2 R/W Time Counter MSB Data2 XXh

36h TIME COUNTER MSB1 R/W Time Counter MSB Data1 XXh

37h TIME COUNTER LSB R/W Time Counter LSB Data XXh

38h CHARGE MSB3 R/W Charge MSB Data3 XXh

39h CHARGE MSB2 R/W Charge MSB Data2 XXh

3Ah CHARGE MSB1 R/W Charge MSB Data1 XXh

3Bh CHARGE LSB R/W Charge LSB Data XXh

3Ch ENERGY MSB3 R/W Energy MSB Data3 XXh

3Dh ENERGY MSB2 R/W Energy MSB Data2 XXh

3Eh ENERGY MSB1 R/W Energy MSB Data1 XXh

3Fh ENERGY LSB R/W Energy LSB Data XXh

40h STATUS2 R Secondary Status Information 00h

41h FAULT2 R/W Secondary Fault Log 00h

42h GPIO3_CTRL R/W GPIO3 Control Command 00h

43h CLK_DIV R/W Clock Divider Command 04h

E7h MFR_SPECIAL_ ID MSB R Manufacturer Special ID MSB Data 60h

E8h MFR_SPECIAL_ID LSB R Manufacturer Special ID LSB Data 01h

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Table 3. CTRLA Register (00h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

CA[7] ADIN Configuration [1] = ADIN Measured with Respect to INTVCC

[0] = ADIN Measured with Respect to GND

CA[6:5] Offset Calibration

Configuration

Offset Calibration

[11] = 1st Power-Up or Use Last Calibrated Result

[10] = Once Every 128 Conversions

[01] = Once Every 16 Conversions

[00] = Every Conversion

CA[4 :3] Voltage Selection [11] = SENSE+

[10] = ADIN

[01] = VDD

[00] = ΔSENSE**

CA[2 :0] Channel

Configuration

[111] = Snapshot Mode (Channel Defined by CA[4:3]). No Power, Energy or Charge Data Generated

[110] = Voltage Measurement Once Followed by Current Measurement Indefinitely*

[101] = ADIN, Voltage, Current Measurement at 1/256, 1/256 and 254/256 Duty Cycle, Respectively*

[100] = ADIN, Voltage, Current Measurement at 1/32, 1/32 and 30/32 Duty Cycle, Respectively*

[011] = Alternate ADIN, Voltage and Current Measurement*

[010] = Voltage, Current Measurement at 1/128 and 127/128 Duty Cycle, Respectively*

[001] = Voltage, Current Measurement at 1/16 and 15/16 Duty Cycle, Respectively*

[000] = Alternate Voltage, Current Measurement*

000

*Voltage defined by CA[4:3] in polling modes.

**If ΔSENSE (00) is selected and the channel configuration is other than snapshot mode (111) the voltage data is always the value in the VIN register

prior to the mode change. It is recommended that ΔSENSE be avoided when polling modes are used.

Table 4. CTRLB Register (01h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

CB[7] ALERT Clear Enable Clear ALERT if Device is Addressed by the Master

[1] = Enable

[0] = Disable

CB[6] Shutdown [1] = Shutdown

[0] = Power-Up

CB[5] Cleared on Read Control FAULT Registers Cleared on Read

[1] = Cleared on Read

[0] = Registers Not Affected by Reading

CB[4] Stuck Bus Timeout Auto Wake-Up Allows Part to Exit Shutdown Mode When Stuck-Bus Timer Is Reached

[1] = Enable

[0] = Disable

CB[3:2] Enable Accumulation [11] = Reserved

[10] = Follows ACC State (GPIO2, See Table 9)

ACC High, Accumulate

ACC Low, No Accumulate

[01] = No Accumulate

[00] = Accumulate

CB[1:0] Auto-Reset Mode/Reset [11] = Reset All Registers

[10] = Reset Accumulator (Time Counter, Charge and Energy) Registers

[01] = Enable Auto-Reset

[00] = Disable Auto-Reset

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Table 5. ALERT1 Register (02h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

AL1[7] Maximum POWER Alert Enables Alert When POWER > Maximum POWER Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[6] Minimum POWER Alert Enables Alert When POWER < Minimum POWER Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[5] Maximum ISENSE Alert Enables Alert When ISENSE > Maximum ISENSE Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[4] Minimum ISENSE Alert Enables Alert When ISENSE < Minimum ISENSE Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[3] Maximum VIN Alert Enables Alert When VIN > Maximum VIN Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[2] Minimum VIN Alert Enables Alert When VIN < Minimum VIN Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[1] Maximum ADIN Alert Enables Alert When ADIN > Maximum ADIN Threshold

[1] = Enable Alert

[0] = Disable Alert

AL1[0] Minimum ADIN Alert Enables Alert When ADIN < Minimum ADIN Threshold

[1] = Enable Alert

[0] = Disable Alert

Table 6. STATUS1 Register (03h): Read

BIT REGISTER NAME OPERATION DEFAULT

S1[7] POWER Overvalue POWER > Maximum POWER Threshold

[1] = POWER Overvalue

[0] = POWER Not Overvalue

S1[6] POWER Undervalue POWER < Minimum POWER Threshold

[1] = POWER Undervalue

[0] = POWER Not Undervalue

S1[5] ISENSE Overvalue ISENSE > Maximum ISENSE Threshold

[1] = ISENSE Overvalue

[0] = ISENSE Not Overvalue

S1[4] ISENSE Undervalue ISENSE < Minimum ISENSE Threshold

[1] = ISENSE Undervalue

[0] = ISENSE Not Undervalue

S1[3] VIN Overvalue VIN > Maximum VIN Threshold

[1] = VIN Overvalue

[0] = VIN Not Overvalue

S1[2] VIN Undervalue VIN < Minimum VIN Threshold

[1] = VIN Undervalue

[0] = VIN Not Undervalue

S1[1] ADIN Overvalue ADIN > Maximum ADIN Threshold

[1] = ADIN Overvalue

[0] = ADIN Not Overvalue

S1[0] ADIN Undervalue ADIN < Minimum ADIN Threshold

[1] = ADIN Undervalue

[0] = ADIN Not Undervalue

LTC2946

2946fa

For more information www.linear.com/LTC2946

APPLICATIONS INFORMATION

Table 7. FAULT1 Register (04h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

F1[7] POWER Overvalue Fault POWER > Maximum POWER Threshold

[1] = POWER Overvalue Fault Occurred

[0] = No POWER Overvalue Fault Occurred

F1[6] POWER Undervalue Fault POWER < Minimum POWER Threshold

[1] = POWER Undervalue Fault Occurred

[0] = No POWER Undervalue Fault Occurred

F1[5] ISENSE Overvalue Fault ISENSE > Maximum ISENSE Threshold

[1] = ISENSE Overvalue Fault Occurred

[0] = No ISENSE Overvalue Fault Occurred

F1[4] ISENSE Undervalue Fault ISENSE < Minimum ISENSE Threshold

[1] = ISENSE Undervalue Fault Occurred

[0] = No ISENSE Undervalue Fault Occurred

F1[3] VIN Overvalue Fault VIN > Maximum VIN Threshold

[1] = VIN Overvalue Fault Occurred

[0] = No VIN Overvalue Fault Occurred

F1[2] VIN Undervalue Fault VIN < Minimum VIN Threshold

[1] = VIN Undervalue Fault Occurred

[0] = No VIN Undervalue Fault Occurred

F1[1] ADIN Overvalue Fault ADIN > Maximum ADIN Threshold

[1] = ADIN Overvalue Fault Occurred

[0] = No ADIN Overvalue Fault Occurred

F1[0] ADIN Undervalue Fault ADIN < Minimum ADIN Threshold

[1] = ADIN Undervalue Fault Occurred

[0] = No ADIN Undervalue Fault Occurred

Table 8. ALERT2 Register (32h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

AL2[7] ADC Conversion Done Alert Alert When ADC Finishes a Conversion

[1] = Enable

[0] = Disable

AL2[6] GPIO1 Input Alert Alert if

GPIO1 Is Low When GP[7:6] = [01] (GPIO1 Input Active Low), or

GPIO1 Is High When GP[7:6] = [00] (GPIO1 Input Active High)

[1] = Enable Alert

[0] = Disable Alert

AL2[5] GPIO2 Input Alert Alert if

GPIO2 Is Low When GP[5:4] = [01] (GPIO2 Input Active Low), or

GPIO2 Is High When GP[5:4] = [00] (GPIO2 Input Active High)

[1] = Enable Alert

[0] = Disable Alert

AL2[4] Reserved 0

AL2[3] Stuck-Bus Timeout Wake-Up Alert Alert if Part Exits Shutdown Mode After Stuck-Bus Timer Expires with CB[4] = 1

[1] = Enable Alert

[0] = Disable Alert

AL2[2] Energy Overflow Alert Alert if Energy Register Overflow

[1] = Enable Alert

[0] = Disable Alert

LTC2946

2946fa

For more information www.linear.com/LTC2946

APPLICATIONS INFORMATION

AL2[1] Charge Overflow Alert Alert if Charge Register Overflow

[1] = Enable Alert

[0] = Disable Alert

AL2[0] Time Counter Overflow Alert Alert if Time Counter Register Overflow

[1] = Enable Alert

[0] = Disable Alert

Table 9. GPIO_CFG Register (33h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

GP[7:6] GPIO1 Configure [11] = General Purpose Input, Active High

[10] = General Purpose Input, Active Low

[01] = General Purpose Output, Hi-Z

[00] = General Purpose Output, Pulls Low

GP[5:4] GPIO2 Configure [11] = General Purpose Input, Active High

[10] = General Purpose Input, Active Low

[01] = General Purpose Output, GPIO = GP[1]

[00] = Accumulate Input

GP[3:2] GPIO3 Configure [11] = General Purpose Input, Active High

[10] = General Purpose Input, Active Low

[01] = General Purpose Output, See Register 42h (Table 12)

[00] = ALERT Output

GP[1] GPIO2 Output [1] = Pulls Low

[0] = Hi-Z

GP[0] Reserved 0

LTC2946

2946fa

For more information www.linear.com/LTC2946

APPLICATIONS INFORMATION

Table 10. STATUS2 Register (40h): Read

BIT NAME OPERATION DEFAULT

S2[7] Reserved 0

S2[6] GPIO1 State GP[7] GP[6] Function GPIO State

1 0 GPIO1 Input = Active Low [1] = GPIO1 Low

[0] = GPIO1 High

1 1 GPIO1 Input = Active High [1] = GPIO1 High

[0] = GPIO1 Low

S2[5] GPIO2 State GP[5] GP[4] Function GPIO State

0 0 GPIO2 Input = ACC [1] = ACC High

[0] = ACC Low

1 0 GPIO2 Input = Active Low [1] = GPIO2 Low

[0] = GPIO2 High

1 1 GPIO2 Input = Active High [1] = GPIO2 High

[0] = GPIO2 Low

S2[4] GPIO3 State GP[3] GP[2] Function GPIO State

1 0 GPIO3 Input = Active Low [1] = GPIO3 Low

[0] = GPIO3 High

1 1 GPIO3 Input = Active High [1] = GPIO3 High

[0] = GPIO3 Low

S2[3] ADC Busy in Snapshot Mode 0

S2[2] Energy Register Overflow Energy Register Overflow

[1] = Energy Register Overflow

[0] = Energy Register Not Overflow

S2[1] Charge Register Overflow Charge Register Overflow

[1] = Charge Register Overflow

[0] = Charge Register Not Overflow

S2[0] Time Counter Register Overflow Time Counter Register Overflow

[1] = Time Counter Register Overflow

[0] = Time Counter Register Not Overflow

LTC2946

2946fa

For more information www.linear.com/LTC2946

Table 11. FAULT2 Register (41h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

F2[7] Reserved 1

F2[6] GPIO1 Input Fault Indicates GPIO1 Was at Active Level as a General Purpose Input

[1] = GPIO1 Input Was Active

[0] = GPIO1 Input Was Inactive

F2[5] GPIO2 Input Fault Indicates GPIO2 Was at Active Level as a General Purpose Input

[1] = GPIO2 Input Was Active

[0] = GPIO2 Input Was Inactive

F2[4] GPIO3 Input Fault Indicates GPIO3 Was at Active Level as a General Purpose Input

[1] = GPIO3 Input Was Active

[0] = GPIO3 Input Was Inactive

F2[3] Stuck-Bus Timeout Wake-Up Fault With CB[4] = 1

[1] = Part Exited Shutdown Mode After Stuck-Bus Timer Expired

[0] = No Stuck Bus Timeout Wake-Up Fault Occurred

F2[2] Energy Register Overflow Fault Energy Register Overflow

[1] = Energy Register Overflow Fault

[0] = No Energy Overflow Fault

F2[1] Charge Register Overflow Fault Charge Register Overflow

[1] = Charge Register Overflow Fault

[0] = No Charge Overflow Fault

F2[0] Time Counter Register

Overflow Fault

Time Counter Register Overflow

[1] = Time Counter Register Overflow Fault

[0] = No Time Counter Overflow Fault

Table 12. GPIO3_CTRL Register (42h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

GC[7] Alert Generated If GPIO3 is configured as ALERT output, it pulls low when alert is generated. Otherwise,

this bit does not have an effect on GPIO3. This bit is set when an alert is generated or a

1 is written. To clear this bit, write 0 via I2C.

GC[6] GPIO3 Pull-Down Control Controls GPIO3 as a General Purpose Output

[1] = GPIO3 Pulls Low

[0] = GPIO3 Hi-Z

This bit does not have effect on GPIO3 if it is configured otherwise.

GC[5:0] Reserved Read Only 00000b

Table 13. CLK_DIV Register (43h): Read/Write

BIT REGISTER NAME OPERATION DEFAULT

CD[7:5] Reserved Read Only 000b

CD[4:0] Clock Divider Integer Input clock frequency at CLKIN is divided by 4× of this integer to produce the target

250kHz system clock.

00100b

APPLICATIONS INFORMATION

LTC2946

2946fa

For more information www.linear.com/LTC2946

Table 14. Register Data Format: Read/Write

ADC, Min/Max ADC, Min/Max

ADC Threshold MSB

Data (11) Data (10) Data (9) Data (8) Data (7) Data (6) Data (5) Data (4)

ADC, Min/Max ADC, Min/Max

ADC Threshold LSB

Data (3) Data (2) Data (1) Data (0) Read as 0 Read as 0 Read as 0 Read as 0

Power, Min/Max Power, Min/

Max Power Threshold MSB2

Data (23) Data (22) Data (21) Data (20) Data (19) Data (18) Data (17) Data (16)

Power, Min/Max Power, Min/

Max Power Threshold MSB1

Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8)

Power, Min/Max Power, Min/

Max Power Threshold LSB

Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0)

Time Counter, Charge, Energy

MSB3

Data (31) Data (30) Data (29) Data (28) Data (27) Data (26) Data (25) Data (24)

Time Counter, Charge, Energy

MSB2

Data (23) Data (22) Data (21) Data (20) Data (19) Data (18) Data (17) Data (16)

Time Counter, Charge, Energy

MSB1

Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8)

Time Counter, Charge, Energy

LSB

Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0)

MFR_SPECIAL_ID MSB Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8)

MFR_SPECIAL_ID LSB Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0)

APPLICATIONS INFORMATION

Table 15. Time per LSB of Timer Register

CA[6:5] SEE TABLE 3 CA[2:0] SEE TABLE 3 N

XX 110 4098.5

11 011 4099.75

010, 101 4098.5098

001, 100 4098.5806

000 4099.3333

10 011 4099.7355

010, 101 4098.5097

001, 100 4098.5800

000 4099.3549

01 011 4099.6429

010, 101 4098.5092

001, 100 4098.5758

000 4099.2692

00 011 4099

010, 101 4098.5049

001, 100 4098.5397

000 4098.8571

Time / LSB =N•

4•CLK _DIV

fCLKIN

or N • 4µs if internal clock used.

LTC2946

2946fa

For more information www.linear.com/LTC2946

TYPICAL APPLICATIONS

Power, Charge and Energy Monitoring in –48V System Using Low Side Sensing (1.5kHz I2C Interface)

VEE

VEE VEE

1µF

MOCD207M

NC = NO CONNECT

2946 TA03

ADR0

ADR1

ADIN

SCL

VDD INTVCC

SDAI

SDAO

GPIO3 ALERT

SENSE–

GND

SENSE+

LTC2946

VEE

–48V INPUT

0.47k

–48V

RTN

VOUT CA[4:3] = 01, SEE TABLE 3

0.47k

10k

R10

10k

R11

10k

3.3V

RSNS

0.02Ω

VDD

GND

µP

SCL

SDA

INT

20k

GPIO1

GPIO2

CLKIN

CLKOUT

12.1k

R12

12.1k

681k

0.1µF

Bidirectional Power Monitor with Energy and Charge Monitor in Forward Path

0.1µF

33pF

VIN

2.7V TO 5.8V

RSNS

0.2Ω VOUT

0.5A

GP OUTPUT

3.3V

VDD

SCL

SDA

INT

GND

ADR0

SCL

VDD

INTVCC

SDAI

SDAO

GPIO1

ALERT

ADR1

SENSE+

ACCUMULATE

SENSE–

LTC2946

µP

GPIO3

CLKOUT

GND

GPIO2

3.3V

CLKIN

2946 TA10

ADIN

33pF

X1: ABLS-4.000MHz-B2-T

POWER FOR REVERSE PATH = CODEADIN × CODEVDD TO BE PERFORMED BY µP

CA[7] = 1, SEE TABLE 3

LTC2946

2946fa

For more information www.linear.com/LTC2946

TYPICAL APPLICATIONS

Dual Power, Charge and Energy Monitor Using Single Opto-Coupler for Galvanic Isolation

and Blocking Diodes for Data Retention When Either Supply Fails

0.1µF SCL

VDD

VOUT1

VIN1

24V

INTVCC

SDAI

GND

LTC2946

3.9Ω

SDAO

GPIO2

GPIO3

GPIO1

GP02A

GP01A

ADR1

ADR0

ADIN

SENSE+SENSE–

RSNS1

0.02Ω

1µF

BAT54

VCC

GND

HCPL-063L

2946 TA07

0.1µF

SCL

VDD

VOUT2

KEEP

SHORT!

VIN2

48V

INTVCC

SDAI

GND

LTC2946

33.2k

18.2k

SDAO

GPIO2

GPIO3

GPIO1

GP02B

GP01B

ADR1

ADR0

ADIN

SENSE+SENSE–

RSNS2

0.02Ω

1µF

BAT54

VCC

GND

0.47k

R10

10k

R11

10k

R12

10k

3.3V

VDD

GND

µP

SCL

SDA

INT

ALERT

0.22µF

X1: ABLS-4.000MHz-B2-T

33pF

V5VGEN

CLKOUT

CLKIN

33pF

CLKOUT

CLKIN

GPO1A, GPO2A, GPO1B AND GPO2B ARE CONTROLLED BY MICROPROCESSOR WRITING COMMANDS TO LTC2946s VIA I2C

VIN2

V5VGEN

R18

10k

REDGP02B

RED: VIN2 OVERLOAD

R17

100k

VIN2

V5VGEN

R16

10k

GREENGPO1B

GREEN: VIN2 OK

R15

100k

VIN1

V5VGEN

R14

4.7k

REDGPO2A

RED: VIN1 OVERLOAD

R13

100k

VIN1

V5VGEN

4.7k

GREENGPO1A

GREEN: VIN1 OK

100k

LTC2946

2946fa

For more information www.linear.com/LTC2946

VCC

GND

RSHUNT

2 × 5k IN SERIES

1µF

HCPL-063L

VEE

HCPL-063L

2946 TA05

ADR0

ADR1

SCL

VDD

INTVCC

FAN ON

OUTPUT

TEMP

MONITOR

INPUT

SDAI

SDAO

ADIN

SENSE–

GND

SENSE+

LTC2946

C3, 33pF

C4, 33pF

VCC

GND

–48V

RTN

VEE

–48V INPUT

0.47k

VOUT

1µF R8

0.47k

R10

R11

10k

3.3V

RSNS

0.02Ω

VDD

GND

µP

SCL

SDA

INT

R12

100Ω Q1

PZTA42

1N4148WS

0.47k

732k

15k

GPIO3

CLKOUT

GPIO1

GPIO2

CLKIN

ALERT

X1: ABLS-4.000MHz-B2-T

CA[4:3] = 10, SEE TABLE 3

TYPICAL APPLICATIONS

Power, Charge and Energy Monitor in –48V Harsh Environment Using INTVCC Shunt Regulator to Tolerate 200V Transients

Power, Charge and Energy Monitor for Main Supply and Power Monitor for Secondary Supply with Single LTC2946

0.1µF

VIN1

0V TO 100V

VIN2

2.7V TO 5.8V

CA[7] = 1, SEE TABLE 3

POWER FOR SECONDARY SUPPLY = CODEADIN × CODEVDD. TO BE PERFORMED BY µP

VOUT2

0.5A (8-BIT)

VOUT1

RSNS1

0.02Ω

GP OUTPUT

3.3V

VDD

SCL

SDA

INT

GND

ADR1

SCL

ADR0

VDD

GND

SDAI

SDAO

GPIO1

ALERT

SENSE+

ACCUMULATE

SENSE–

LTC2946

µP

GPIO3

CLKOUT

GPIO2

3.3V

CLKIN

2946 TA06

INTVCC ADIN

RSNS

0.25Ω

LTC2946

2946fa

For more information www.linear.com/LTC2946

TYPICAL APPLICATIONS

6V to 300V High Side Power, Charge and Energy Monitor

VCC

GND

0.1µF

ACPL-064L

CA[7] = 1, CA[4:3] = 10, SEE TABLE 3

* DDZ9689, DIODES, INC.

FGND

ACPL-064L

2946 TA07

GPIO1 SCL

VDD

INTVCC

SDAI

SDAO

GPIO2

GND

LTC2946-1

VCC

GND

0.47k

1µF R8

0.47k

BS170

R10

3.3V

VDD

GND

µP

SCL

SDA

INT

2N3904

MMBT6520L

5.1k

750k

GPIO3

ADR1

ADR0

CLKIN

ADIN

CLKOUT

ALERT

FGND

Z1*

5.1V

2N3904

BSP135

10k

R11

100Ω

10k

BSP135

VIN VOUT

SENSE+SENSE–

RSNS

0.02Ω

LTC2946

2946fa

For more information www.linear.com/LTC2946

TYPICAL APPLICATIONS

12V, 50A Power, Charge and Energy Monitor

Wide Range –4V to –500V Negative Power, Charge and Energy Monitor (10kHz I2C Interface)

VEE

0.1µF

MOCD207M

2946 TA09

ADR0

ADR1

ADIN

SCL

VDD

INTVCC

SDAI

SDAO

GPIO3 ALERT

SENSE–

GND

SENSE+

LTC2946

0.1µF

VEE

0.47k

R13

10k

BSP135

VOUT

0.47k

10k

R10

10k

R11

10k

3.3V

RSNS

0.02Ω

VDD

GND

µP

SCL

SDA

INT

R12

6.04k

750k

4.7V

750k

RTN

GPIO1

GPIO2

CLKIN

CLKOUT

CA[4:3] = 10, SEE TABLE 3

0.1µF

0.22µF

VIN

12V

RSNS

0.002Ω, 5W VOUT

50A

VADIN

GP OUTPUT

3.3V

VDD

SCL

SDA

INT

GND

ADR0

SCL

VDD

INTVCC

SDAI

SDAO

GPIO1

ALERT

ADR1

SENSE+

ACCUMULATE

SENSE–

LTC2946

µP

GPIO3

CLKOUT

GND

GPIO2

3.3V

CLKIN

2946 TA08

ADIN

DIVB

OUT

V+V+

GND GND

LTC6930-8.00

DIVA

DIVC

LTC2946

2946fa

For more information www.linear.com/LTC2946

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

3.00 ±0.10

(2 SIDES)

4.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.70 ±0.10

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

3.15 REF

1.70 ±0.05

169

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DE16) DFN 0806 REV Ø

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

3.15 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.20 ±0.05

0.70 ±0.05

3.60 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

3.30 ±0.05

3.30 ±0.10

0.45 BSC

0.23 ±0.05

0.45 BSC

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1732 Rev Ø)

LTC2946

2946fa

For more information www.linear.com/LTC2946

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MS16) 0213 REV A

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16151413121110

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ±0.038

(.0120 ±.0015)

TYP

0.50

(.0197)

BSC

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.1016 ±0.0508

(.004 ±.002)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.280 ±0.076

(.011 ±.003)

REF

4.90 ±0.152

(.193 ±.006)

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

LTC2946

2946fa

For more information www.linear.com/LTC2946

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 03/15 Changed Y-axis of Typical Applications graph.

Corrected ISENSE(LO)– Conditions.

Corrected RSHUNT equation.

LTC2946

2946fa

For more information www.linear.com/LTC2946

 LINEAR TECHNOLOGY CORPORATION 2014

LT 0315 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2946

TYPICAL APPLICATION

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LTC2990 Quad I2C Temperature, Voltage and Current Monitor 3V to 5.5V Operation, 14-Bit ADC

LTC4150 Coulomb Counter/Battery Gas Gauge 2.7V to 8.5V Operation, Voltage-to-Frequency Converter

LTC4151 High Voltage I2C Current and Voltage Monitor 7V to 80V Operation, 12-Bit Resolution with ±1.25% TUE

LTC4215 Single Channel, Hot Swap™ Controller with I2C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 15V Operation

LTC4222 Dual Channel, Hot Swap Controller with I2C Monitoring 10-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 29V Operation

LTC4260 Positive High Voltage Hot Swap Controller with I2C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 8.5V to 80V Operation

LTC4261 Negative High Voltage Hot Swap Controller with I2C Monitoring 10-Bit ADC, Floating Topology, Adjustable Inrush

Rail-to-Rail Power, Charge and Energy Monitor

2.7V TO 5.8V

0.1µF

33pF

X1 X1: ABLS-4.000MHz-B2-T

VIN

0V TO 100V

RSNS

0.02Ω

VOUT

VADIN

GP OUTPUT

3.3V

VDD

SCL

SDA

INT

GND

ADR0

SCL

VDD

INTVCC

SDAI

SDAO

GPIO1

ALERT

ADR1

SENSE+

ACCUMULATE

SENSE–

LTC2946

µP

GPIO3

CLKOUT

GND

GPIO2

3.3V

CLKIN

2946 TA02

ADIN

33pF