512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Features DDR2 SDRAM Unbuffered DIMM (UDIMM) MT16HTF6464A - 512MB MT16HTF12864A - 1GB MT16HTF25664A - 2GB For the latest data sheet and for component data sheets, refer to Micron's Web site: www.micron.com/products/ddr2 Features Figure 1: * 240-pin, unbuffered dual in-line memory module * Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400 * Utilizes 400 MT/s, 533 MT/s, 667 MT/s, and 800 MT/s DDR2 SDRAM components * VDD = VDDQ = +1.8V * VDDSPD = +1.7V to +3.6V * JEDEC-standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4-bit prefetch architecture * DLL to align DQ and DQS transitions with CK * Single rank * Multiple internal device banks for concurrent operation * Programmable CAS# latency (CL) * Posted CAS# additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths: 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Gold edge contacts Table 1: 240-Pin UDIMM (MO-237 R/C "B") PCB height: 30.0mm (1.18in) Options Marking * Package 240-pin DIMM (lead-free) * Frequency/CAS latency1 2.5ns @ CL = 5 (DDR2-800)2 2.5ns @ CL = 6 (DDR2-800)2 3.0ns @ CL = 5 (DDR2-667) 3.75ns @ CL = 4 (DDR2-533) 5.0ns @ CL = 3 (DDR2-400) * PCB height 30mm (1.18 in) Y -80E -800 -667 -53E -40E Notes: 1. CL = CAS (READ) latency. 2. Not available in 512MB module density. Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) tRP (ns) tRC (ns) -80E -800 -667 -53E -40E PC2-6400 PC2-6400 PC2-5300 PC2-4200 PC2-3200 - 800 - - - 800 667 667 - - 533 - 533 533 400 - - 400 400 400 12.5 15 15 15 15 12.5 15 15 15 15 55 55 55 55 55 PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 1 tRCD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Features Table 2: Addressing Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: 512MB 1GB 2GB 8K 8K (A0-A12) 4 (BA0, BA1) 1KB 256Mb (32 Meg x 8) 1K (A0-A9 2 (S0#, S1#) 8K 16K (A0-A13) 4 (BA0, BA1) 1KB 512Mb (64 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 16K (A0-A13) 8 (BA0, BA1, BA2) 1KB 1Gb (128 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) Part Numbers and Timing Parameters - 512MB Modules Base device: MT47H32M8, 256Mb DDR2 SDRAM Part Number1 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) MT16HTF6464AY-667__ MT16HTF6464AY-53E__ MT16HTF6464AY-40E__ 512MB 512MB 512MB 64 Meg x 64 64 Meg x 64 64 Meg x 64 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667MT/s 3.75ns/533 MT/s 5.0ns/400MT/s 5-5-5 4-4-4 3-3-3 Table 4: Part Numbers and Timing Parameters - 1GB Modules Base device: MT47H64M8, 512Mb DDR2 SDRAM Part Number1 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) MT16HTF12864AY-80E__ MT16HTF12864AY-800__ MT16HTF12864AY-667__ MT16HTF12864AY-53E__ MT16HTF12864AY-40E__ 1GB 1GB 1GB 1GB 1GB 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 6.4 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800MT/s 3.0ns/667MT/s 3.75ns/533 MT/s 5.0ns/400MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Table 5: Part Numbers and Timing Parameters - 2GB Modules Base device: MT47H128M8, 1Gb DDR2 SDRAM Part Number1 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) MT16HTF25664AY-80E__ MT16HTF25664AY-800__ MT16HTF25664AY-667__ MT16HTF25664AY-53E__ MT16HTF25664AY-40E__ 2GB 2GB 2GB 2GB 2GB 256Meg x 64 256Meg x 64 256Meg x 64 256Meg x 64 256Meg x 64 6.4 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667MT/s 3.75ns/533 MT/s 5.0ns/400MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT16HTF12864AY-667C2. 2. For component data sheets, refer to Micron's Web site: www.micron.com/products/ddr2 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 6: Pin Assignment 240-Pin UDIMM Front 240-Pin UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VREF Vss DQ0 DQ1 Vss DQS0# DQS0 Vss DQ2 DQ3 Vss DQ8 DQ9 Vss DQS1# DQS1 Vss NC NC Vss DQ10 DQ11 Vss DQ16 DQ17 Vss DQS2# DQS2 Vss DQ18 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DQ19 Vss DQ24 DQ25 Vss DQS3# DQS3 Vss DQ26 DQ27 Vss NC NC Vss NC NC Vss NC NC Vss VDDQ CKE0 VDD NC/BA2 NC VDDQ A11 A7 VDD A5 Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 A4 VDDQ A2 VDD Vss Vss VDD NC VDD A10/AP BA0 VDDQ WE# CAS# VDDQ S1# ODT1 VDDQ Vss DQ32 DQ33 Vss DQS4# DQS4 Vss DQ34 DQ35 Vss DQ40 DQ41 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Vss DQS5# DQS5 Vss DQ42 DQ43 Vss DQ48 DQ49 Vss SA2 NC Vss DQS6# DQS6 Vss DQ50 DQ51 Vss DQ56 DQ57 Vss DQS7# DQS7 Vss DQ58 DQ59 Vss SDA SCL 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Vss DQ4 DQ5 Vss DM0 NC Vss DQ6 DQ7 Vss DQ12 DQ13 Vss DM1 NC Vss CK1 CK1# Vss DQ14 DQ15 Vss DQ20 DQ21 Vss DM2 NC Vss DQ22 DQ23 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Vss DQ28 DQ29 Vss DM3 NC Vss DQ30 DQ31 Vss NC NC Vss NC NC Vss NC NC Vss VDDQ CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6 181 VDDq 211 182 A3 212 183 A1 213 184 VDD 214 185 CK0 215 186 CK0# 216 187 VDD 217 188 A0 218 189 VDD 219 190 BA1 220 191 VDDQ 221 192 RAS# 222 193 S0# 223 194 VDDQ 224 195 ODT0 225 196 NC/A13 226 227 197 VDD 198 Vss 228 199 DQ36 229 200 DQ37 230 201 VSS 231 202 DM4 232 203 NC 233 204 Vss 234 205 DQ38 235 206 DQ39 236 237 207 VSS 208 DQ44 238 209 DQ45 239 210 Vss 240 DM5 NC Vss DQ46 DQ47 Vss DQ52 DQ53 Vss CK2 CK2# Vss DM6 NC Vss DQ54 DQ55 Vss DQ60 DQ61 VSS DM7 NC Vss DQ62 DQ63 VSS VDDSPD SA0 SA1 1. Pin 196 is NC for 512MB or A13 for 1GB and 2GB. 2. Pin 54 is NC for 512MB and 1GB or BA2 for 2GB. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 7: Pin Description Symbol Type Description ODT0, ODT1 Input (SSTL18) CK0, CK0#, CK1, CK1#, CK2, CK2# CKE0, CKE1 Input (SSTL18) On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0-BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0-BA1/BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-detect address inputs: These pins are used to configure the presence-detect device. Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. S0#, S1# RAS#, CAS#, WE# BA0, BA1 (512MB, 1GB) BA0, BA1, BA2 (2GB) A0-A12 (512MB) A0-A13 (1GB, 2GB) Input (SSTL18) Input (SSTL18) Input (SSTL18) Input (SSTL18) Input (SSTL18) SCL Input SA0-SA2 Input DQS0-DQS7, DQS0#-DQS7# I/O (SSTL18) DM0-DM7 (DQS9-DQS16) DQ0-DQ63 SDA I/O (SSTL18) I/O VDD VDDQ VREF VSS VDDSPD Supply Supply Supply Supply Supply PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN Data input mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. If RDQS is disabled, DQS0-DQS16 become DM0-DM7 and DQS9#-DQS17# are not used. Data input/output: Bidirectional data bus. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Power supply: 1.8V 0.1V. DQ power supply: 1.8V 0.1V. SSTL_18 reference voltage. Ground. Serial EEPROM positive power supply: +1.7V to +3.6V. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# 25pF S0# 25pF DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U1 CS# DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U19 DQS1# DQS1 DM1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U2 CS# DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U18 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U3 CS# DQ ODT1 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# CS# DQ DQS# U14 DM DQ DQ DQ DQ DQ DQ DQ DQ U7 DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U17 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# U4 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# CS# DQ DQS# U13 DM DQ DQ DQ DQ DQ DQ DQ DQ U8 25pF 25pF 25pF 25pF Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN BA0-BA1: DDR2 SDRAMs BA0-BA2: DDR2 SDRAMs A0-A12: DDR2 SDRAMs A0-A13: DDR2 SDRAMs RAS#: DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: U1-U4, U6-U9 CKE1: U11-U14, U16-U19 DM DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U16 7.5 ODT0 DQS# CS# DQ DQS# U12 DQS7# DQS7 DM7 DM CKE1 DQ DQ DQ DQ DQ DQ DQ DQ DQS# DQS3# DQS3 DM3 BA0-BA1 (512MB, 1GB) BA0-BA2 (2GB) A0-A12 (512M) A0-A13 (1GB, 2GB) RAS# CAS# WE# CKE0 DQ DQS6# DQS6 DM6 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# U6 DM DQS# DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQS# SCL U10 Serial PD WP A0 A1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# U9 A2 DQ DQS# U11 CK0 CK0# U4, U6 U14, U16 1pF Serial PD VDD, VDDL, VDDQ DDR2 SDRAMs VREF DDR2 SDRAMs VSS CS# 67 SDA SA0 SA1 SA2 VDDSPD DM DQ DQ DQ DQ DQ DQ DQ DQ DDR2 SDRAMs, EEPROM 67 CK1 CK1# U1-U3, U17-U19 67 CK2 CK2# U7-U10, U11-U13 ODT0: U1-U4, U6-U9 ODT1: U11-U14, U16-U19 1. Unless otherwise noted, all resistor values are 22. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM General Description General Description The MT16HTF6464A, MT16HTF12864A, and MT16HTF25664A DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 512MB, 1GB, and 2GB memory modules organized in x64 configuration. These DDR2 SDRAM modules use internally configured quad-bank (256Mb, 512Mb) or 8-bank (1Gb) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 8 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 8: Absolute Maximum DC Ratings Symbol Parameter Min Max Units VDD VDDQ VDDL VIN, VOUT TSTG Tcase TOPR II VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to Vss Voltage on any pin relative to VSS Storage temperature DDR2 SDRAM device operating temperature Operating temperature Command/Address, Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V; (All other pins not under RAS#, CAS#, WE# test = 0V) S#, CKE CK0, CK0# CK1, CK1#, CK2, CK2# DM Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = Valid VREF level -1.0 -0.5 -0.5 -0.5 -55 0 0 -80 2.3 2.3 2.3 2.3 100 85 65 80 V V V V C C C A -40 -20 -30 -10 -10 40 20 30 10 10 A -32 32 A IOZ IVREF Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM IDD Specifications IDD Specifications Table 9: DDR2 IDD Specifications and Conditions - 512MB Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Operating one bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) -1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN Symbol -667 -53E -40E Units IDD0a 760 680 640 mA IDD1a 840 760 720 mA IDD2Pb 80 80 80 mA IDD2Qb 640 560 400 mA IDD2Nb 640 560 480 mA IDD3Pb 480 400 320 mA 96 96 96 mA IDD3Nb 800 640 480 mA IDD4Wa 1,560 1,320 1,040 mA IDD4Ra 1,480 1,240 960 mA IDD5b 2,880 2,720 2,640 mA IDD6b 80 80 80 mA IDD7a 2,040 1,960 1,880 mA 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all module ranks in this operating condition. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM IDD Specifications Table 10: DDR2 IDD Specifications and Conditions - 1GB Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition t t t Operating one bank active-precharge current; CK = CK (IDD), RC = t RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN -80E/ -800 -667 -53E -40E Units a 856 776 696 696 mA IDD1a 976 896 816 776 mA IDD2Pb 112 112 112 112 mA IDD2Qb 800 720 640 560 mA IDD2Nb 880 800 720 640 mA IDD3Pb 640 560 480 400 mA 192 192 192 192 mA IDD3Nb 1,120 1,040 880 720 mA IDD4Wa 1,616 1,416 1,176 976 mA IDD4Ra 1,969 1,496 1,216 976 mA IDD5b 3,680 2,880 2,720 2,640 mA IDD6b 112 112 112 112 mA IDD7a 2,456 1,976 1,856 1,816 mA Symbol IDD0 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all module ranks in this operating condition. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM IDD Specifications Table 11: DDR2 IDD Specifications and Conditions - 2GB Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition t t t Operating one bank active-precharge current; CK = CK (IDD), RC = t RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current; All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN -80E/ -800 -667 -53E -40E Units a 856 776 696 616 mA IDD1a 936 856 816 696 mA IDD2Pb 112 112 112 112 mA IDD2Qb 1,040 880 656 560 mA IDD2Nb 1,120 960 720 640 mA IDD3Pb 720 640 560 560 mA 224 224 224 224 mA IDD3Nb 1,200 1,120 880 720 mA IDD4Wa 1,536 1,336 1,096 936 mA IDD4Ra 1,576 1,336 1,216 936 mA IDD5b 4,480 4,160 4,000 3,520 mA IDD6b 112 112 112 112 mA IDD7a 2,736 2,456 2,376 2,136 mA Symbol IDD0 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all module ranks in this operating condition. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site: www.micron.com/products/ddr2sdram. Module speed grades correlate with component speed grades as shown in the following table: Table 12: Module and Component Speed Grade Table Module Speed Grade Component Speed Grade -80E -800 -667 -53E -40E -25E -25 -3 -37E -5E Serial Presence-Detect Table 13: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 KHz Power supply current, WRITE: SCL clock frequency = 100 KHz PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 11 Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD x 0.7 -0.6 - 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3 3 4 1 3 V V V V A A A mA mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions Table 14: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Symbol t AA BUF t DH t F tHD:DAT t HD:STA t HIGH t I t LOW t R f SCL tSU:DAT tSU:STA tSU:STO tWRC SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN t Min Max Units Notes 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s KHz ns s s ms 1 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions Table 15: Serial Presence-Detect Matrix "1"/"0": serial data, "driven to HIGH"/"driven to LOW" Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Entry (Version) 128 Number of SPD bytes used by Micron 256 Total number of bytes in SPD device DDR2 SDRAM Fundamental memory type 13 or 14 Number of row addresses on SDRAM 10 Number of column addresses on SDRAM 30mm, dual rank DIMM height and module ranks 64 Module data width 0 Reserved SSTL 1.8V Module voltage interface levels -80E SDRAM cycle time, tCK -800 (CL = MAX value, see byte 18) -667 -53E -40E tAC -800/-80E SDRAM access from clock, -667 (CL = MAX value, see byte 18) -53E -40E Non-ECC Module configuration type 7.81s/SELF Refresh rate/type 8 SDRAM device width (primary SDRAM) 0 Error-checking SDRAM data width Reserved 4, 8 Burst lengths supported 4 or 8 Number of banks on SDRAM device -80E (5, 4) CAS latencies supported -800 (6, 5) -667 (5, 4, 3) -53E/-40E (4, 3) Module thickness Unbuffered DDR2 DIMM type DIMM No PLL or Reg SDRAM module attributes -800/-80E/-667 SDRAM device attributes: weak driver -53E/-40E (01) or, weak driver and 50 ODT (03) -80E/-667 SDRAM cycle time, tCK, MAX CL - 1 -800 -53E/-40E -800/-80E SDRAM access from CK, tAC, MAX CL - 1 -667 -53E -40E tCK, MAX CL - 2 -800/-80E(N/S) SDRAM cycle time, -667 -53E/-40E(N/S) -800/-80E(N/S) SDRAM access from CK, tAC, MAX CL - 2 -667 -53E/-40E(N/S) PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 13 MT16HTF6464A MT16HTF12864A MT16HTF25664A 80 08 08 0D 0A 61 40 00 05 - - 30 3D 50 - 45 50 60 00 82 08 00 00 0C 04 - - 38 18 01 02 80 08 08 0E 0A 61 40 00 05 25 25 30 3D 50 40 45 50 60 00 82 08 00 00 0C 04 30 60 38 18 01 02 80 08 08 0E 0A 61 40 00 05 25 25 30 3D 50 40 45 50 60 00 82 08 00 00 0C 08 30 60 38 18 01 02 00 - /03 01 - /3D - 50 - 45 50 60 - 50 00 - 45 00 00 03 01 3D 30 50 40 45 50 60 00 50 00 00 45 00 00 03 01 3D 30 50 40 45 50 60 00 50 00 00 45 00 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions Table 15: Serial Presence-Detect Matrix (Continued) "1"/"0": serial data, "driven to HIGH"/"driven to LOW" Byte Description t 27 MIN row precharge time, RP 28 29 MIN row active to row active, tRRD MIN RAS# to CAS# delay, tRCD 30 MIN RAS# pulse width, tRAS 31 Module rank density 32 Address and command setup time, tISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR WRITE-to-READ command delay, tWTR 38 READ-to-PRECHARGE command delay, t RTP Memory analysis probe Extension for bytes 41 and 42 39 40 41 MIN active auto refresh time, tRC (see note 1) 42 MIN AUTO REFRESH-to-ACTIVE/ auto refresh command period, tRFC SDRAM device MAX cycle time, tCKMAX SDRAM device MAX DQS-DQ skew time, t DQSQ 43 44 45 SDRAM device MAX read data hold skew factor, tQHS PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN Entry (Version) -80E -800/-667/ -53E/-40E -80E -800/-667/ -53E/-40E -800-80E/ -667/-53E -40E 256MB, 512MB,1GB -800/-80E -667 -53E -40E -800/-80E -667 -53E -40E -800/-80E -667/-53E -40E -800/-80E -667 -53E -40E -80E/-667/-53E -800/-40E -80E -800/-667 -53E/-40E -80E -800/-667/-53E -40E -800/-80E -667 -53E -40E -800/-80E -667 -53E -40E 14 MT16HTF6464A MT16HTF12864A MT16HTF25664A - -/3C 3C 1E - -/3C 3C - 2D 28 40 32 3C 3C 1E 32 3C 3C 2D 2D 28 80 32 3C 3C 1E 32 3C 3C 2D 2D 28 01 - 20 25 35 - 27 37 47 - 10 15 - 17 22 27 3C - /1E 28 1E 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 00 - -/00 00 - -/3C 37 4B 00 30 00 00 39 3C 37 69 00 36 06 06 39 3C 37 7F 80 - 18 1E 23 - 22 28 2D 80 14 18 1E 23 1E 22 28 2D 80 14 18 1E 23 1E 22 28 2D Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions Table 15: Serial Presence-Detect Matrix (Continued) "1"/"0": serial data, "driven to HIGH"/"driven to LOW" Byte Description 46 47-61 62 63 PLL relock time Optional features, not supported SPD revision Checksum for bytes 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 128- 255 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) Reserved for customer use Notes: PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN Entry (Version) N/A Release 1.2 -80E -800 -667 -53E -40E MICRON (continued) 01-12 1-9 0 MT16HTF6464A MT16HTF12864A MT16HTF25664A 00 00 12 - - ED 98 FF 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 00 00 12 90 A4 4C F7 5E 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 00 00 12 31 45 ED 98 FF 2C FF 01-0C Variable data 01-09 00 Variable data Variable data Variable data 00 FF 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Module Dimensions Module Dimensions Figure 3: 240-Pin DDR2 UDIMM 4.0 (0.157) MAX FRONT VIEW 133.50 (5.256) 133.20 (5.244) 2.00 (0.079) R (4X) U1 U2 U3 U4 U6 2.50 (0.098) D (2X) U7 U8 U9 30.50 (1.200) 29.85 (1.175) 17.78 (0.700) TYP U10 2.30 (0.091) TYP 0.76 (0.030) R PIN 1 2.20 (0.087) TYP 1.0 (0.039) TYP 1.0 (0.039) TYP 10.00 (0.394) TYP 0.80 (0.031) TYP 1.37 (0.054) 1.17 (0.046) PIN 120 70.68 (2.78) TYP 123.0 (4.840) TYP BACK VIEW U11 U12 U13 U14 U16 U17 U18 U19 3.05 (0.12) TYP PIN 240 PIN 121 5.0 (0.197) TYP 55.0 (2.165) TYP Notes: 63.0 (2.48) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80f09084/Source: 09005aef80f09068 HTF16C64_128_256x64A.fm - Rev. E 9/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.