1. General description
The 74LV165 is an 8-bit pa rallel-load or serial-in shift register with complementary serial
outputs (Q7 an d Q7) available from the last stage. When the parallel-loa d input (PL) is
LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.
When input PL is HIGH, dat a enters the r egister serially at the input DS. It shif ts one place
to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the
succeeding stage.
The clock input is a gate-OR structure which allows one input to be used as an active
LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is
arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the
input CE should only t ake place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the
data when PL is activated.
2. Features and benefits
Wide supply voltage range from 1.0 V to 5.5 V
Synchronous parallel-to-serial applications
Optimized for low voltage applications: 1.0 V to 3.6 V
Synchronous serial input for easy expansion
Latch-up performan ce exceeds 250 mA
5.5 V tolerant inputs/outputs
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
JESD8-1A (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114-A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 Cto+85C and from 40 Cto+125C
74LV165
8-bit parallel-in/serial-out shift register
Rev. 7 — 9 March 2016 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 2 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV165D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV165DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74LV165PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 3 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Fig 4. Logic diagra m
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 4 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SO16 and (T)SSOP16
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Table 2. Pin description
Symbol Pin Description
PL 1 parallel enable input (active LOW)
CP 2 clock input (LOW-to-HIGH edge-triggered)
Q7 7 complementary serial output from the last stage
GND 8 ground (0 V)
Q7 9 serial output from the last stage
DS 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs
CE 15 clock enable input (active LOW)
VCC 16 positive supply voltage
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 5 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 3. Function table[1]
Operating modes Inputs Qn registers Output
PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7
parallel load L X X X L L L to L L H
LXXXH H H to H H L
serial shift H L l X L q0 to q5 q6 q6
HLh X H q0 to q5 q6 q6
hold “do nothi ng” H H X X X q 0 q1 to q6 q7 q7
Fig 6. Timing diag ram
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 6 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1]
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V - 20 mA
VIinput voltage 0.5 +7 V
IOK output clamping current VO>V
CC or VO < 0 - 50 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO16 package [2] -500mW
(T)SSOP16 package [3] -500mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.0 3.3 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 - +85 C
t/V input transition rise and fall rate VCC = 1.0 V to 2.0 V 0 - 500 ns/V
VCC = 2.0 V to 2.7 V 0 - 200 ns/V
VCC = 2.7 V to 3.6 V 0 - 100 ns/V
VCC = 3.6 V to 5.5 V 0 - 50 ns/V
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 7 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
9. Static characteristics
[1] Typical values are measured at Tamb = 25 C.
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.3 V to 2.7 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC -0.3V
CC
VOH HIGH-level
output voltage VI = VIH or VIL; IO = 100 A
VCC = 1.2 V - 1.2 -
VCC = 2.0 V 1.8 2.0 - 1.8 - V
VCC = 2.7 V 2.5 2.7 - 2.5 - V
VCC = 3.0 V 2.8 3.0 - 2.8 - V
VCC = 4.5 V 4.3 4.5 - 4.3 - V
standard outputs: VI = VIH or VIL
VCC = 3.0 V; IO = 6 mA 2.40 2.82 - 2.20 - V
VCC = 4.5 V; IO = 12 mA 3.60 4.20 - 3.50 - V
VOL LOW-level
output voltage VI = VIH or VIL; IO = 100 A
VCC = 1.2V -0---
VCC = 2.0 V - 0 0.2 1.8 0.2 V
VCC = 2.7 V - 0 0.2 2.5 0.2 V
VCC = 3.0 V - 0 0.2 2.8 0.2 V
VCC = 4.5 V - 0 0.2 4.3 0.2 V
standard outputs: VI = VIH or VIL
VCC = 3.0 V; IO = 6 mA - 0.25 0.40 - 0.50 V
VCC = 4.5 V; IO = 12 mA - 0.35 0.55 - 0.65 V
IIinput leakage
current VI = VCC or GND; VCC =5.5V - - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V - - 20 - 160 A
ICC additional
supply current VI = VCC – 0.6 V;
VCC = 2.7 V to 3.6 V --500-850A
CIinput
capacitance -3.5---pF
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 8 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation
delay CE, CP to Q7, Q7;
see Figure 7 and Figure 8 [2]
VCC = 1.2 V - 115 - - - ns
VCC = 2.0 V - 38 61 - 76 ns
VCC = 2.7 V - 27 43 - 54 ns
VCC = 3.0 V to 3.6 V [3] -2236 - 45ns
VCC = 3.3 V; CL = 15 pF - 18 - - - ns
VCC = 4.5 V to 5.5 V [4] -1524 - 30ns
PL to Q7, Q7; see Figure 8
VCC = 1.2 V - 110 - - - ns
VCC = 2.0 V - 35 56 - 70 ns
VCC = 2.7 V - 24 39 - 49 ns
VCC = 3.0 V to 3.6 V [3] -2033 - 41ns
VCC = 3.3 V; CL = 15 pF - 18 - - - ns
VCC = 4.5 V to 5.5 V [4] -1422 - 27ns
D7 to Q7, Q7; CL = 15 pF;
see Figure 9
VCC = 1.2 V - 90 - - - ns
VCC = 2.0 V - 28 45 - 56 ns
VCC = 2.7 V - 20 32 - 40 ns
VCC = 3.0 V to 3.6 V [3] -1727 - 33ns
VCC = 3.3 V; CL = 15 pF - 14 - - - ns
VCC = 4.5 V to 5.5 V [4] -1118 - 22ns
tWpulse width CP input HIGH to LOW;
see Figure 7
VCC = 2.0 V 34 10 - 41 - ns
VCC = 2.7 V 25 8 - 30 - ns
VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns
VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns
PL input LOW; see Figure 8
VCC = 2.0 V 34 10 - 41 - ns
VCC = 2.7 V 25 8 - 30 - ns
VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns
VCC = 4.5 V to 5.5 V [4] 15 5 - 18 - ns
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 9 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
trec recovery time PL to CP, CE; see Figure 8
VCC = 1.2 V - 40 - - - ns
VCC = 2.0 V 24 15 - 30 - ns
VCC = 2.7 V 18 11 - 23 - ns
VCC = 3.0 V to 3.6 V [3] 17 10 - 21 - ns
VCC = 4.5 V to 5.5 V [4] 12 7 - 15 - ns
tsu set-up time DS to CP, CE; see Figure 10
VCC = 1.2 V - 8- - -ns
VCC = 2.0 V 22 2- 26 -ns
VCC = 2.7 V 16 1- 19 -ns
VCC = 3.0 V to 3.6 V [3] 13 1- 15 -ns
VCC = 4.5 V to 5.5 V [4] 90- 10 -ns
CE to CP, CP to CE;
see Figure 10
VCC = 1.2 V - 20 - - - ns
VCC = 2.0 V 22 7 - 26 - ns
VCC = 2.7 V 16 5 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 4 - 15 - ns
VCC = 4.5 V to 5.5 V [4] 93- 10 -ns
Dn to PL;
see Figure 11
VCC = 1.2 V - 25 - - - ns
VCC = 2.0 V 22 8 - 26 - ns
VCC = 2.7 V 16 6 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 5 - 15 - ns
VCC = 4.5 V to 5.5 V [4] 94- 10 -ns
thhold time DS to CP, CE; Dn to PL;
see Figure 10 and Figure 11
VCC = 1.2 V - 20 - - - ns
VCC = 2.0 V 22 7 - 26 - ns
VCC = 2.7 V 16 5 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 4 - 15 - ns
VCC = 4.5 V to 5.5 V [4] 93- 10 -ns
CE to CP, CP to CE;
see Figure 10
VCC = 1.2 V - 30 - - - ns
VCC = 2.0 V 5 8- 5 -ns
VCC = 2.7 V 5 6- 5 -ns
VCC = 3.0 V to 3.6 V [3] 55- 5 -ns
VCC = 4.5 V to 5.5 V [4] 54- 5 -ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 10 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH.
[3] Typical values are measured at VCC = 3.3 V.
[4] Typical values are measured at VCC = 5.0 V.
[5] CPD is used to determine the dynamic power dissipation PD = CPD VCC2 fi + (CL VCC2 fo) (PD in W), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
fmax maximum
frequency see Figure 7
VCC = 2.0 V 14 40 - 12 - MHz
VCC = 2.7 V 19 60 - 16 - MHz
VCC = 3.0 V to 3.6 V [3] 24 65 - 20 - MHz
VCC = 3.3 V; CL = 15 pF - 78 - - - MHz
VCC = 4.5 V to 5.5 V [4] 36 75 - 30 - MHz
CPD power
dissipation
capacitance
VI=GNDtoV
CC; VCC = 3.3 V [5] -35- pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); for test circuit, see Figure 12
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig 7. Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and
maximum clock frequency
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 11 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig 8. Parallel l oa d (PL) pulse wid th , pa rallel load to output (Q7 or Q7) prop agation delays, parallel load to clock
(CP) and clock enable (CE) recovery time
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The changing to output assumes that internal Q6 is opposite state from Q7.
Fig 9. Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 12 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW . The shaded areas indicate when the input is permitted to change for
predictable output performance.
Fig 10. Set-up and hold times
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Fig 11. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
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Supply voltage Input Output
VCC VMVM
< 2.7 V 0.5VCC 0.5VCC
2.7 V to 3.6 V 1.5 V 1.5 V
4.5 V 0.5VCC 0.5VCC
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 13 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 12. Test circuit for measuring switching times
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Supply voltage Input Load VEXT
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2.7 V to 3.6 V 2.7 V 2.5 ns 50 pF, 15 pF 1 kopen
4.5 V VCC 2.5 ns 50 pF 1 kopen
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 14 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
12. Package outline
Fig 13. Package outline SOT109-1 (SO16)
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 15 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Fig 14. Package outline SOT338-1 (SSOP16)
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 16 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Fig 15. Package outline SOT403-1 (TSSOP16)
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© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 17 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV16 5 v.7 20160309 Product data sheet - 74LV165 v.6
Modifications: •Type number 74HC165N (SOT38-4) removed.
74LV16 5 v.6 20140219 Product data sheet - 74LV165 v.5
Modifications: •Typo corrected in Ta ble 2 “ Pin description”
74LV16 5 v.5 20130909 Product data sheet - 74LV165 v.4
Modifications: •Typo corrected in the header of Tabl e 6 “St atic characteristics”
74LV16 5 v.4 20130830 Product data sheet - 74LV165_CNV_3
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Family data added, see Section 9 “S tatic characteristics”
74LV165_CNV_3 December 1998 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 18 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict wit h the short data sheet, th e
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminar y specification.
Product [short] data sheet Pro duction This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74LV165 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 7 — 9 March 2016 19 of 20
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor test ed
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia’s warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74LV165
8-bit parallel-in/serial-out shift register
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
09 March 2016
