VSP10T21PFBG4 - Texas Instruments

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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features

D10-bit, 21 Mega-Samples Per Second

(MSPS), A/D Converter

DSingle Power Supply Operation, 2.7 V to

3.3 V

DInternally Programmable Correlated Double

Sampler (CDS) Timing SR and ADCCLK

DVery Low Power: 109 mW Typical at 2.7-V,

1.5-mW Power-Down Mode

DFull Channel Differential Nonlinearity Error:

<±0.5 LSB Typical

DFull Channel Integral Nonlinearity Error:

<±1.0 LSB Typical

DProgrammable Optical Black (OB) Level

and Offset Calibration

DProgrammable Gain Amplifier (PGA) With

0-dB to 36-dB Gain Range (0.047 dB/Step)

for CCD Mode, 0-dB to 12-dB Gain Range

(0.047 dB/Step) for Video Mode

DAdditional Digital-to-Analog Converters

(DACs) for External Analog Setting

DSerial Interface for Register Configuration

DInternal Reference Voltages

D48-Terminal TQFP Package

applications

DDigital Still Camera

DDigital Camcorder

DDigital Video Camera

description

The VSP10T21 device is a complete charge-coupled device (CCD) and video signal processor/digitizer

designed for digital camera and camcorder applications. The VSP10T21 device performs all the analog

processing functions necessary to maximize the dynamic range, corrects various errors associated with the

CCD sensor, and then digitizes the results with an on-chip high-speed analog-to-digital converter (ADC). One

of the key features of this device is an integrated programmable delay generated for the CDS timing control,

which eases the AFE timing adjustments for optimum image quality. Other key components of the VSP10T21

device include:

DInput clamp circuitry and a CDS

DProgrammable gain amplifier (PGA) with 0-dB to 36-dB gain range (0.047 dB/step) for CCD mode, 0-dB

to 12-dB gain range (0.047 dB/step) for video mode

DInternal programmable optical black level and offset calibration

D10-bit, 21 MSPS pipeline ADC for CCD mode and 28 MSPS ADC for video mode

DParallel data port for easy microprocessor interface and a serial port for configuring internal control registers

DTwo DACs for external system control

DInternal reference voltages

Designed in advanced CMOS process, the VSP10T21 device operates from a single power supply with a

normal power consumption of 109 mW at 2.7 V and 21 MSPS and a 1.5-mW power-down mode.

High precision, single 3-V operation, very low power consumption, and fully integrated analog processing

circuitry make the VSP10T21 device an ideal CCD signal processing solution for the electronic video camcorder

and digital still camera applications.

The part is available in a 48-terminal TQFP package and is specified over an operating temperature range of

–20°C to 75°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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AVDD

CLAMP

ADCCLK

OBCLP

BLKG

DVDD

MCLK

DVSS

DIVSS

DIVDD

RBD

RPD

RMD

AVDD

AVSS

RESET

STBY

SCKP

SDIN

SCLK

5678

35 34 33 32 3136 30 28 27 2629

9 10 11 12

PFB PACKAGE

(TOP VIEW)

DACO2

AVSS

DACO1

AVDD

VSS

DIN+

DIN–

CLREF

AVDD

AVSS

AVAILABLE OPTIONS

PACKAGE

TATQFP (PFB)

–20°C to 75°C VSP10T21PFB

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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functional block diagram

1.2 V Ref

CDS

DIN+

DIN–

Clamp

Video

Clamp

CLAMP CLREF AVDD (4 PLACES)

Internal

Reference

RBDRPD RMD

PGA

Optical

Black

Loop

PGA

DVDD DIVDD

10-Bit

ADC Three-State

Latch

Timing

and

Control

Logic

BLKG

OBCLP

STBY

Thru

Serial

Port CS

SCLK

SCKP

SDIN

8-Bit

DAC DAC2

Reg

DACO2

8-Bit

DAC DAC1

Reg

DACO1

AVSS (4 PLACES) DVSS DIVSS

VSS

MCLK

RESET

ADCCLK

†

SR†

DLL

†ADCCLK and SR output signals are only enabled by setting bits D3 (ADEN) and D4 (ROEN) in the clock control register to 1.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO. I/O DESCRIPTION

ADCCLK 22 O ADCCLK clock output, for probe only

AVDD 24, 27, 33,

40 Analog supply voltage, +3 V

AVSS 25, 26, 35,

41 Analog ground

BLKG 19 I Control input. The CDS operation is disabled when BLKG is pulled low.

CLAMP 23 I CCD signal clamp control input

CLREF 28 O Clamp reference voltage output

CS 46 I Chip select. A logic low on this input enables the VSP10T21 device.

DACO1 34 O Digital-to-analog converter output 1

DACO2 36 O Digital-to-analog converter output 2

DIN–29 I Differential input signal from CCD

DIN+ 30 I Differential Input signal from CCD

DIVDD 13 Digital interface circuit supply voltage, 1.8 V to 3.6 V

DIVSS 14 Digital interface circuit ground

DVDD 17 Digital supply voltage, +3 V

DVSS 15 Digital ground

D0–D9 3–12 O 10-bit 3-state ADC output data or offset DACs test data

MCLK 16 I System clock input

NC 1, 2, 18 Not connected

OBCLP 20 I Optical black level and offset calibration control input, active low

OE 42 I Output data enable, active low

PIN 31 I Video input signal

RBD 37 O Internal bandgap reference for external decoupling

RESET 43 I Hardware reset input, active low. This signal forces a reset of all internal registers.

RMD 39 O Ref– output for external decoupling

RPD 38 O Ref+ output for external decoupling

SCKP 45 I This terminal selects the polarity of SCLK.

0 = Active low (high when SCLK is not running)

1 = Active high (low when SCLK is not running)

SCLK 48 I Serial clock input. This clock synchronizes the serial data transfer.

SDIN 47 I Serial data input to configure the internal registers.

SR 21 O CCD reference level sample clock output, for probe only

STBY 44 I Hardware power-down control input, active low

VSS 32 Analog ground

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†

Supply voltage, AVDD, DVDD, DIVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

recommended operating conditions

power supplies

PARAMETER MIN NOM MAX UNIT

AVDD Analog supply voltage 2.7 3 3.3 V

DVDD Digital supply voltage 2.7 3 3.3 V

DIVDD Digital interface supply voltage 1.8 3.6 V

digital inputs

PARAMETER TEST CONDITION MIN NOM MAX UNIT

VIH High-level input voltage DVDD = 3 V 0.8DVDD V

VIL Low-level input voltage DVDD = 3 V 0.2DVDD V

Input MCLK frequency

DVDD = 3 V, CCD mode 21 MHz

Input MCLK frequency DVDD = 3 V, video mode 28 MHz

tw(MCLKH) ADCCLK pulse duration, clock high DVDD = 3 V 23.8 ns

tw(MCLKL) ADCCLK pulse duration, clock low DVDD = 3 V 23.8 ns

Input SCLK frequency DVDD = 3 V 40 MHz

tw(SCLKH) SCLK pulse duration, clock high DVDD = 3 V 12.5 ns

tw(SCLKL) SCLK pulse duration, clock low DVDD = 3 V 12.5 ns

electrical characteristics over recommended operating free-air temperature range, TA = 25°C,

AVDD = DVDD = 3 V, MCLK = 21 MHz (unless otherwise noted)

total device

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Device power consumption AVDD = DVDD = 3 V 130 mW

Device power consumption AVDD = DVDD = 2.7 V 109 mW

Power consumption in power-down mode 1.5 mW

No missing code Assured

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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electrical characteristics over recommended operating free-air temperature range, TA = 25°C,

AVDD = DVDD = 3 V, MCLK = 21 MHz (unless otherwise noted) (continued)

analog-to-digital converter (ADC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC resolution 10 (CCD)

8 (Video) Bits

INL Integral nonlinearity AVDD = DVDD = 2.7 to 3.3 V ±1.0 LSB

DNL Differential nonlinearity AVDD = DVDD = 2.7 to 3.3 V ±0.5 LSB

SNR

ut referred signal to noise ratio

0 dB gain 60

SNR Input referred signal-to-noise ratio 36 dB gain 74 dB

correlated double sampler (CDS) and programmable gain amplifier (PGA)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CDS and PGA sample rate 21 (CCD)

28 (Video) MHz

CDS full scale input span Single-ended input 1 V

Input capacitance of CDS 4 pF

Minimum PGA gain 0 1 dB

Maximum PGA gain

CCD 36

Maximum PGA gain Video 12 dB

PGA gain resolution 0.047 dB

user digital-to-analog converters (DAC)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC resolution 8 Bits

INL Integral nonlinearity ±0.5 LSB

DNL Differential nonlinearity ±0.1 LSB

Output voltage range 0AVDD V

Output settling time 10-pF external load, settle to 1 mV 4µs

reference voltages

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Internal bandgap voltage reference 1.43 1.50 1.58 V

Temperature coefficient 100 ppm/°C

ADC Ref+ Externally decoupled 2 V

ADC Ref–Externally decoupled 1 V

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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electrical characteristics over recommended operating free-air temperature range, TA = 25°C,

AVDD = DVDD = 3 V, MCLK = 21 MHz (unless otherwise noted) (continued)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Logic Inputs

IIH High-level input current DVDD = 3 V –10 10 µA

IIL Low-level input current DVDD = 3 V –10 10 µA

CIInput capacitance 5 pF

Logic Outputs

VOH High-level output voltage IOH= 50 µA, DIVDD = 3 V DIVDD–0.4 V

VOL Low-level output voltage IOL= 50 µA, DIVDD = 3 V 0.4 V

IOZ High-impedance-state output current ±10 µA

CoOutput capacitance 5 pF

key timing requirement

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Maximum programming range for SR and ADCCLK timing

signals T†ns

SR and ADCCLK programming resolution T/30 ns

tSRW SR pulse width Measured at 50% of pulse

height, recommend to use T/4

of ADCCLK cycle 10 ns

tSRD Delay between the rising edge of external SR test output

and the actual sampling instant 2.4‡ns

tADCKD Delay between the falling edge of external ADCCLK test

output and the actual instant of sampling the video signal Measured at 50% of pulse

hiht

1.7§ns

tOD The rising edge of MCLK to output data delay height 6 ns

tCSF CS falling edge to SCLK rising edge 0 ns

tCSR SCLK falling edge to CS rising edge 5 ns

†T is the time period of MCLK.

‡SR is the internally generated timing. Due to the pad delay on the output SR, the maximum of the SR delay is 2.4 ns. It must not be delayed further

on the positive direction unless it crosses a full pixel period (refer to Figure 2). The target for the SR position is to make sure that the rising edge

of SR sample the reference level of the CCD signal.

§ADCCLK is the internally generated timing. Due to the pad delay on the output ADCCLK, the maximum of the ADCCLK delay is 1.7 ns. It must

not be delayed further on the positive direction unless it crosses a full pixel period (refer to Figure 2). The target for the SR position is to make

sure that the falling edge of ADCCLK sample the video level of the active instant of the CCD signal.

NOTE: The digital output is latched out by MCLK.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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TYPICAL CHARACTERISTICS

DUMMY ACTIVE PIXELS OB DUMMY

DUMMYDUMMY

CCD IN

BLKG

CLAMP

OBCLP

1 Line

Figure 1. CCD Horizontal Synchronization Timing Diagram

CCD IN

SR†

ADCCLK†

MCLK

ADC OUT

Latency: 5 MCLK Cycles

n+1

n–1n–2n–3n–4n–5

tSRD tADCKD tSRW

tOD

–+0

–+

†SR and ADCCLK are external signals.

Figure 2. CCD Pixel Synchronization Timing Diagram

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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TYPICAL CHARACTERISTICS

SCKP Terminal is Pulled Low

SCLK

SDIN

1234567 16

DI15

1234567 16

SCKP Terminal is Pulled High

SCLK

SDIN

DI14 DI13 DI12 DI11 DI10 DI9 DI0

tCSF tCSR

DI15 DI14 DI13 DI12 DI11 DI10 DI9

tCSF tCSR

DI0

Figure 3. Serial Interface Timing Diagram

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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APPLICATION INFORMATION

†ADCCLK and SR are test outputs only.

‡DIVDD is recommended to have a ferrite bead to filter the power transients.

NOTE: All analog outputs should be buffered if the load is resistive or if the load is capacitive with more than 2 pF loading.

The decoupling capacitors for the power supplies must be placed as close as possible to these terminals.

3 V

VSP10T21PFB

AREA

CCD

CLAMP Input

DIVDD

DVDD

AVDD 3 V

1.8 V to 3.6 V

Ground

OBCLP Input

BLKG Input

MCLK Input

DAC1 Output

DAC2 Output

SCKP Input

RESET Input

STBY Input

SDIN Input

SCLK Input

CS Input

OE Input

AVDD

D[9–0]

DVDD

AVDD

1 µF

0.1 µF

1 µF

0.1 µF

1 µF

DIVDD‡

0.1 µF

AVDD

Video

Input

0.1 µF

AVDD

RBD

RPD

RMD

AVDD

AVSS

RESET

STBY

SCKP

SDIN

SCLK

AVDD

CLAMP

ADCCLK†

SR†

OBCLP

BLKG

DVDD

MCLK

DVSS

DIVSS

DIVDD

DACO2

AVSS

DACO1

AVDD

VSS

DIN+

DIN–

CLREF

AVDD

AVSS

R0.1 µF

AVDD

Figure 4. Typical Application Connection

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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serial input data format

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0 D9–D10

0000Control register 10-bit data to be written into the selected register

0001PGA gain register

0010User DAC1 register

0011User DAC2 register

0100Reserved

0101Optical black Vb setup register

0110Video control register

0111Reserved

1000SR and ADC delay register

1001Clock control register

control register format (00H)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

STBY PDD1 PDD2 DACD x x x x x RTSY

control register description

BIT NAME DESCRIPTION

D9 STBY Device power down control

1 = Standby

0 = Active (default)

D8 PDD1 Power down the user DAC1

1 = Standby

0 = Active (default)

D7 PDD2 Power down the user DAC2

1 = Standby

0 = Active (default)

D6 DACD Sustain the user DACs when power down

0 = User DACs are powered down during global power-down (default)

1 = User DACs are not powered down during global power-down

D5 x Reserved

D4 x Reserved

D3 x Reserved

D2 x Reserved

D1 x Reserved

D0 RTSY Writing a 1 to this bit will reset entire system to the default settings (active high).

Default = 0000000000

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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PGA register format (01H)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default PGA gain = 0000000000 or 0 dB

The gain code range for CCD mode is from 0–767, which covers from 0 to 36 dB with 0.047 dB per step. Users must

use this code range. The gain stays at 36 dB when the code is from 768–1023. For the video mode, the gain code

range is from 256–512, which covers from 0 to 12 dB with 0.047 dB per step. Users must use a 256–512 code range

for the video mode. In video mode, the gain range is from 12 dB to 24 dB for the gain code range of 513 to 767;

however, the offset might be too large for this gain range.

user DAC1 and DAC2 registers format (02H and 03H)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default user DAC register value = 0000000000

The DAC1 and DAC2 codes are from 0 to 255, which cover the output voltages at DACO1 and DACO2 output

terminals from 0 to AVDD with linear correspondence.

optical black Vb setup register format (05H)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X NOB VB3 VB2 VB1 VB0

optical black Vb setup register description

BIT NAME DESCRIPTION

D9–D5 X Reserved

D4 NOB This bit controls the OB output

0 = OB output has no affect by the Vb setting, and it is always 0 (default)

1 = OB output corresponds to the Vb setting.

D3–D0 VB3–VB0 VB3

VB2

VB1

VB0

OB output

20 LSB (default)

1 1 1 1 35

Default optical black Vb setup register value = 0000000000

If NOB (D4) is set to 0, VB3–VB0 (D3–D0) has no effect. The output OB is 0.

If NOB is set to 1, the output OB is defined by VB3–VB0 from 20 LSB to 35 LSB, typically.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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video control register (06H)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X X MOD X

video control register description

BIT NAME DESCRIPTION

D9–D2 X Reserved

D1 MOD This bit defines the mode of the input

0 = CCD mode (default)

1 = Video mode

D0 X Reserved. Always program this bit to 0.

Default register value= 0000000000

SR and ADCCLK internal delay register format (08H)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ADCL4 ADCL3 ADCL2 ADCL1 ADCL0 SRL4 SRL3 SRL2 SRL1 SRL0

SR and ADCCLK internal delay register description

BIT NAME DESCRIPTION

D9–D5 ADCL4–ADCL0 These five bits set the internal ADCCLK delay. T is the period of the MCLK.

ADCL4 ADCL3 ADCL2 ADCL1 ADCL0 Typical internal delay

000000

00001T/30

001117T/30 (default)

1110129T/30

D4–D0 SRL4–SRL0 These five bits set the internal SR delay. T is the period of the MCLK.

SRL4 SRL3 SRL2 SRL1 SRL0 Typical internal delay

000000

00001T/30

010019T/30 (default)

1 1 1 0 1 29T/30

Default register value= 0011101001

NOTE: Do not program SR and ADCCLK internal delays above 29T/30.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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clock control register format

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X ROEN ADEN CKIP SRW1 SRW0

clock control register description

BIT NAME DESCRIPTION

D9–D5†X Reserved

D4 ROEN This bit controls the SR output

1 = Disables SR output (default)

0 = Enables SR output

D3 ADEN This bit controls the ADCCLK output

1 = Disables ADCCLK output (default)

0 = Enables ADCCLK output

D2 CKIP‡This bit controls the input clock (MCLK) polarity

1 = Falling edge of the MCLK latches the ADC output

0 = Rising edge of the MCLK latches the ADC output (default)

D1–D0 SRW1, SRW0 These bits control the width of the SR pulse

SRW1 SR W0 Typical width

4T/20

5T/20 (default)

6T/20

7T/20

Default register value= 0000111001

†Bit D5 is recommended to be set to 1.

‡This bit controls the polarity of the MCLK inside the VSP10T21 device which latches the ADC data output. Corresponding with this change, the

user needs to read the data with different edge of the MCLK. By switching this bit from 0 to 1 also introduces an additional half pixel clock cycle

delay.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

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PRINCIPLES OF OPERATION

CDS/PGA signal processor

In a CCD imaging system, the output from the CCD sensor is first fed to the CDS of the VSP10T21 device. The

CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting

two resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor and

obtains the voltage difference between the CCD reference level and the video level of each pixel. Only the MCLK

is required to feed into the AFE. Two clocks are generated internally based on the MCLK to perform the CDS

function. One is SR for sampling the reference level of the CCD signal. The other clock is ADCCLK which

samples the video level of the CCD signal on the falling edge. The ADCCLK is also used for the A/D conversion.

These two clocks are output on the pad for the verification purpose. The user must not use these two terminals

to drive any circuits. The digital ADC outputs are internally latched out by MCLK.

The CCD output is capacitively coupled to the VSP10T21 input. The CLAMP input clamps the ac-coupling

capacitor to establish proper dc bias during the dummy pixel interval. The bias at the input to the VSP10T21

device is set to 1.2 V. Normally, the CLAMP is applied at sensor’s line rate. A capacitor, with a value 10 times

larger than that of the input ac-coupling capacitor, must be connected between terminals 28 (CLREF) and 25

(AVSS).

The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 dB to

36 dB by programming the internal gain register via the serial port. The PGA is digitally controlled with 10-bit

resolution on a linear dB scale, resulting a 0.047 dB gain step. The gain can be expressed by the following

equation:

Gain = PGA code × 0.047 dB

where PGA code has a range of 0 to 767.

For example, if PGA code = 128, then the PGA Gain = 6 dB (or gain of 2).

In CCD mode, users must use the 0 to 767 range for PGA gain code. The gain stays at 36 dB when the code

is from 768 to 1023.

video mode operation

The VSP10T21 device also provides an analog video-processing channel that consists of an input clamp, a

PGA, and an ADC. Setting the MOD bit to 1 in video control register enables the video channel. The video signal

must be connected to terminal 31 (PIN) via a 0.1-µF capacitor as shown in Figure 4.

The video clamp circuit automatically clamps the lowest level of the video input signal, which is usually the sync

tip, to around 60 LSB.

The PGA gain in the video mode can be adjusted from 0 to 12 dB by programming the internal gain register via

the serial port. The PGA is digitally controlled with 10-bit resolution on a linear dB scale, resulting a 0.047 dB

gain step. The gain can be expressed by the following equation:

Gain = (PGA code–256) × 0.047 dB

where PGA code has a range of 256 to 512.

For the video mode, users must use the 256 to 512 range for the PGA gain code. The gain code 0–255 must

not be used, and the gain range is from 12 dB to 24 dB for the gain code range of 513 to 767; however, the offset

might be too large for this gain range.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

internal timing

As previously explained, the SR and ADCCLK clocks are required to operate the CDS. Users need to

synchronize the SR and ADCCLK clocks with the CCD signal waveform. The output from the ADC is read out

to external circuitry by the MCLK signal that is the external signal used to generate the SR and ADCCLK clocks

internally. The user can use the SR and ADCCLK internal delay register to program the delay of these clocks

based on Figure 2 in order to achieve the optimal performance. Terminals 21 (SR) and 22 (ADCCLK) are used

to monitor these two internal signals. By changing bit D2 (CKIP) in the clock control register, the AFE digital

output is latched at either the rising edge or the falling edge of the MCLK pulse.

The CLAMP signal activates the clamping circuit for the input signal. The OBCLP signal activates the optical

black calibration and the active portion (the low pulse) of this signal must be within the optical black period of

the CCD (see Figure 1).

ADC

The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully

differential implementation and digital error correction ensure 10-bit resolution.

The latency of the ADC data output is the default 5 MCLK cycles as shown in Figure 2. Pulling terminal 42 (OE)

high puts the ADC output in high impedance.

automatic optical black calibration

In the VSP10T21 device, the optical black and the system channel offset corrections are performed by an auto

analog feedback loop. During the optical black calibration interval (OBCLP = low) of each line, the optical black

pixels plus the channel offset are sampled and compared with the desired black level specified in the optical

black Vb setup register. The difference is then integrated and added to incoming pixel data at PGA input. This

analog feedback loop calibrates the PGA output to the desired black pixel level, which can be programmed

either to 0 or from 20 LSB to 35 LSB at 1 LSB/step resolution typically via the serial port. The OB calibration

settles within about 1000 OB pixels.

input blanking function

During blanking period of CCD operation, large input transients may occur at the VSP10T21 device’s input,

making the ADC output unpredictable. Activating BLKG pulse during this period ensures the digital code is zero

at the ADC output.

user DACs

The VSP10T21 device includes two user DACs that can be used for external analog settings. These are resistor

string DACs. They must be used only to drive capacitor or buffer loads, not resistor loads. The output voltage

of each DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When

the user DACs are not used in a camera system, they can be put in the standby mode by programming control

bits in the control register 1. The status of the user DACs is defined in the following table.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

SOFTWARE/HARDWARE

GLOBAL STANDBY PDD1/PDD2 DACD STATUS OF

DAC1/DAC2

Active 0 x Active

Active 1 x Standby

Standby 0 0 Standby

Standby 0 1 Active

Standby 1 x Standby

NOTE: The hardware global standby is set by pulling down terminal 44 (STBY) of the

VSP10T21 device. The software global standby is controlled by setting bit D9

(STBY) in the control register to 1.

3-wire serial interface

A simple 3-wire (terminals 48 (SCLK), 47 (SDIN), and 46 (CS)) serial interface is provided to allow writing to

the internal registers of the VSP10T21 device. The serial clock SCLK can be run at a maximum speed of

40 MHz. The serial data SDIN is 16 bits long. After two leading null bits, there are four address bits for which

internal register is to be updated, the following 10 bits are the data to be written to the register. To enable the

serial port, CS must be held low. The data transfer is initiated by the incoming SCLK after CS falls. Figure 3

shows the detailed timing for the serial interface.

The SCLK polarity is selectable by pulling terminal 45 (SCKP) either high or low.

device reset

The device is not under the default configuration when powered on. The registers are set to the default value

by a reset. When terminal 43 (RESET) is pulled low, all internal registers are set to their default values. In

addition, the VSP10T21 device has a software-reset function that resets the device when writing to a control

bit in the control register.

See REGISTER DEFINITION for the register default values.

power-down mode (standby)

The VSP10T21 device implements both hardware and software power-down modes. Pulling terminal 44

(STBY) low puts the device in the low-power standby mode. The total power drops to about 1.5 mW. Setting

bit D9 (STBY) in the control register can also activate the power-down mode. Users can still program all internal

registers during the power-down mode.

power supply

The VSP10T21 device has several power supply terminals. Each major internal analog block has a dedicated

AVDD supply terminal. All internal digital circuitry is powered by the DVDD. Both AVDD and DVDD are 3 V nominal.

The DIVDD and DIVSS terminals supply power to the output digital driver (D9–D0). The DIVDD is independent

of the DVDD and can be operated from 1.8 V to 3.6 V. This allows the outputs to interface with digital ASICs

requiring different supply voltages.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

grounding and decoupling

General practices must apply to the printed-circuit board (PCB) design to limit high frequency transients and

noise that are fed back into the supply and reference lines. This requires that the supply and reference terminals

be sufficiently bypassed. In the case of power supply decoupling, 0.1-µF ceramic chip capacitors are adequate

to keep the impedance low over a wide frequency range. Recommended external decoupling for the three

voltage reference terminals is shown in Figure 4. Since the effectiveness of the decoupling capacitors depends

largely on the proximity to the individual supply terminal, all decoupling capacitors must be placed as close as

possible to the supply terminals. An inductor is recommended for the DIVDD power supply (see Figure 4).

Common ground is also recommended.

voltage references

An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage generates the ADC

Ref– voltage of 1 V and Ref+ of 2 V. It also sets the clamp voltage. All internally generated voltages are fixed

values and cannot be adjusted. Terminals 37 (RBD), 38 (RPD), and 39 (RMD) must not be used to drive any

loads.

VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

7,20

6,80

5,50 TYP

8,80

9,20

1,05

0,95

1,20 MAX 0,08

0,50 M

0,08

0°–ā7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

VSP10T21PFB NRND TQFP PFB 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

VSP10T21PFBG4 NRND TQFP PFB 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Feb-2009

Addendum-Page 1

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