© 2002 Fairchild Semiconductor Corporation DS005967 www.fairchildsemi.com
October 1987
Revised March 2002
CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches
CD4043BC CD4044BC
Quad 3-STATE NOR R/S Latches
Quad 3-STATE NAND R/S Latches
General Description
The CD4043BC are quad cross-couple 3-STATE CMOS
NOR latches, and the CD4044BC are quad cross-couple 3-
STATE CMOS NAND latches. Each latch has a separate Q
output and individual SET and RESET inputs. There is a
common 3-STATE ENABLE input for all four latches. A
logic “1” on th e ENAB LE inpu t conne cts the latch sta tes to
the Q outputs. A logic “0” on the ENABLE input discon-
nects the latch states from the Q outputs resulting in an
open circuit condition on the Q output. The 3-STATE fea-
ture allows common bussing of the outputs.
Features
Wide supply voltage range: 3V to 15V
Low power: 100 nW (typ.)
High noise immunity: 0.45 VDD (typ.)
Separate SET and RESET inputs for each latch
NOR and NAND configuration
3-STATE output with common output enable
Applications
Multiple bus storage
Strobed register
Four bits of independent storage with output enable
General digital logic
Ordering Code:
Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er X to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4043BC
Top View
Pin Assi gnments for DIP and SOIC
CD4044BC
Top View
Order Number Package Number Package Description
CD4043BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4043BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4044BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4044BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4044BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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CD4043BC CD4044BC
Block Diagrams
CD4043BC CD4044BC
Truth Tables
CD4043BC CD4044BC
OC = 3-STATE
NC = No change
X = Dont care
= Domi nated by S = 1 input
∆∆ = Domi nated by R = 0 input
SREQ
XX0OC
001NC
1011
0110
111
SREQ
XX0OC
111NC
0111
1010
001
∆∆
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CD4043BC CD4044BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are those values beyond whic h the
safety of th e device ca nnot be guaranteed; th ey are not meant to imply th at
the devices should be operated at these limits. The tables of Recom-
mended Operating Conditions and Electrical Charac t eristics pro v ide con-
ditions f or actual device o peration.
Note 2: VSS = 0V unles s ot herwise s pecified .
DC Electrical Characteristics (Note 2)
Note 3: IOH and IOL are tes t ed one output at a ti m e.
Supply Voltage (VDD)0.5V to +18V
Input Voltage (VIN)0.5V to VDD +0.5V
Storage Temperature Range (TS)65°C to +150°C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260°C
Supply Voltage (VDD) 3.0V to 15V
Input Voltage (VIN) 0 to VDD V
Operating Temperature Range (TA)
CD4043BC, CD4044BC 55°C to +125°C
Symbol Parameter Conditions 55°C+25°C+125°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent VDD = 5V, VIN = VDD or VSS 5 0.01 5 150 µADevice Current VDD = 10V, VIN = VDD or VSS 10 0.01 10 300
VDD = 15V, VIN = VDD or VSS 20 0.02 20 600
VOL LOW Level |IO| 1 µA, VIL = 0V, VIH = VDD
Output Voltage VDD = 5.0V 0.05 0 0.05 0.05 VVDD = 10V 0.05 0 0.05 0.05
VDD = 15V 0.05 0 0.05 0.05
VOH HIGH Level |IO| 1 µA, VIL = 0V, VIH = VDD
Output Voltage VDD = 5.0V 4.95 4.95 5.0 4.95 VVDD = 10V 9.95 9.95 10 9.95
VDD = 15V 14.95 14.95 15 14.95
VIL LOW Level |IO| 1 µA
Input Voltage VDD = 5.0V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 VVDD = 10V, VO = 1.0V or 9.0V 3.0 4.5 3.0 3.0
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0
VIH HIGH Level |IO| 1 µA
Input Voltage VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 VVDD = 5.0V, VO = 1.0V or 9.0V 7.0 7.0 5.5 7.0
VDD = 15V, VO = 1.5V or 13.5V 11 11 8.25 11
IOL LOW Level VIL = 0V, VIH = VDD
Output Current VDD = 5.0V, VO = 0.4V 0.64 0.51 1.0 0.36 mA(Note 3) VDD = 10V, VO = 0.5V 1.6 1.3 2.6 0.9
VDD = 15V, VO = 1.5V 4.2 3.4 6.8 2.4
IOH HIGH Level VIL = 0V, VIH = VDD
Output Current VDD = 5.0V, VO = 4.6V 0.64 0.51 0.4 0.36 mA(Note 3) VDD = 10V, VO = 9.5V 1.6 1.3 1.0 0.9
VDD = 15V, VO = 13.5V 4.2 3.4 3.0 2.4
IIN Input Current VDD = 15V, VIN = 0V 0.1 10.5 0.1 1.0 µA
VDD = 15V, VIN = 15V 0.1 10.5 0.1 1.0
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CD4043BC CD4044BC
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise noted
Note 4: AC Parameters are guara nt eed by DC c orrelat ed testing.
Timing Waveforms
CD4043B CD4044B
Enable Timing
Symbol Parameter Conditions Min Typ Max Units
tPLH, tPHL Propagation Delay S or R to Q VDD = 5.0V 175 350 nsVDD = 10V 75 175
VDD = 15V 60 120
tPZH, tPHZ Propagation Delay Enable to Q (HIGH) VDD = 5.0V 115 230 nsVDD = 10V 55 110
VDD = 15V 40 80
tPZL, tPLZ Propagation Delay Enable to Q (LOW) VDD = 5.0V 100 200 nsVDD = 10V 50 100
VDD = 15V 40 80
tTHL, tTLH Transition Time VDD = 5.0V 100 200 nsVDD = 10V 50 100
VDD = 15V 40 80
tWO Minimum SET or RESET Pulse Width VDD = 5.0V 80 160 nsVDD = 10V 40 80
VDD = 15V 20 40
CIN Input Capacitance 5.0 7.5 pF
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CD4043BC CD4044BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
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CD4043BC CD4044BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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CD4043BC CD4044BC Quad 3-STATE NOR R/S Latches Quad 3-STATE NAND R/S Latches
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are im plied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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