Continuous Rate 10 Mbps to 2.7 Gbps Clock
and Data Recovery ICs
Data Sheet
ADN2817/ADN2818
Rev. F Document Feedback
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FEATURES
Serial data input: 10 Mbps to 2.7 Gbps
Exceeds ITU-T jitter specifications
Integrated limiting amplifier
5 mV p-p sensitivity (ADN2817 only)
Adjustable slice level: ±100 mV (ADN2817 only)
Proprietary dual-loop clock recovery architecture
Programmable LOS detect (ADN2817 only)
Integrated PRBS generator and detector
No reference clock required
Loss of lock indicator
Supports double data rate
Bit error rate monitor (BERMON) or sample phase adjust options
Rate selectivity without the use of a reference clock
I2C interface to access optional features
Single-supply operation: 3.3 V
Low power
650 mW (ADN2817)
600 mW (ADN2818)
5 mm × 5 mm 32-lead LFCSP
APPLICATIONS
SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates
Fibre Channel, 2× Fibre Channel, GbE, HDTV
WDM transponders
Regenerators/repeaters
Test equipment
GENERAL DESCRIPTION
The ADN2817/ADN2818 provide the receiver functions of
quantization, signal level detect, and clock and data recovery for
continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/
ADN2818 automatically lock to all data rates without the need for
an external reference clock or programming. All SONET jitter
requirements are exceeded, including jitter transfer, jitter generation,
and jitter tolerance. All specifications are quoted for −40°C to
+85°C ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, and low power
fiber optic receiver.
The ADN2817/ADN2818 have many optional features available
through an I2C interface. For example, the user can read back
the data rate onto which the ADN2817 or ADN2818 is locked,
or the user can set the device to lock only to one particular data
rate if provisioning of data rates is required. A BERMON circuit
provides an estimate of the received bit error rate (BER) without
interruption of the data. Alternatively, the user can adjust the
data sampling phase to optimize the received BER.
The ADN2817/ADN2818 are available in a compact 5 mm ×
5 mm, 32-lead, lead frame chip scale package.
FUNCTIONAL BLOCK DIAGRAM
LOOP
FILTER
PHASE
DET
SLICE
ADJUST
(ADN2817
ONLY)
LOS
DETECT
(ADN2817
ONLY)
DATA
RETIMING I
2
C
REGISTERS
LOOP
FILTER
FREQ/
LOCK
DET
VCC VEE
ADN2817/ADN2818
CF1 CF2
LOL
REFCLKP/REFCLKN
(OPTIONAL)
SLICEP/
SLICEN
PIN
NIN
VREF
THRADJ LOS DATAOUTP/
DATAOUTN CLKOUTP/
CLKOUTN SCK SDA
VCO
06001-001
BERMON
VBER BERMODE
PHASE
SHIFTER
ΔФ
Figure 1.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Jitter Specifications ....................................................................... 5
Output and Timing Specifications ............................................. 6
Bit Error Rate Monitor Specifications ....................................... 8
Timing Characteristics ................................................................ 9
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 12
I2C-Interface Timing and Internal Register Description .......... 14
Terminology .................................................................................... 18
Input Sensitivity and Input Overdrive ..................................... 18
Single-Ended vs. Differential .................................................... 18
LOS Response Time ................................................................... 18
Jitter Specifications ......................................................................... 19
Jitter Generation ......................................................................... 19
Jitter Transfer ............................................................................... 19
Jitter Tolerance ............................................................................ 19
Theory of Operation ...................................................................... 20
Functional Description .................................................................. 22
Frequency Acquisition ............................................................... 22
Lock Detector Operation .......................................................... 22
Harmonic Detector .................................................................... 23
Limiting Amplifier (ADN2817 Only) ..................................... 23
Slice Level Adjust (ADN2817 Only) ........................................ 23
Loss of Signal (LOS) Detector (ADN2817 Only) .................. 23
Sample Phase Adjust .................................................................. 24
Bit Error Rate (BER) Monitor ................................................... 24
Squelch Mode ............................................................................. 25
I2C Interface ................................................................................ 25
Reference Clock (Optional) ...................................................... 26
Additional Features Available via the I2C Interface ............... 28
Applications Information .............................................................. 30
PCB Design Guidelines ............................................................. 30
DC-Coupled Application .......................................................... 32
Coarse Data Rate Readback Lookup Table ................................. 33
HI_CODE and LO_CODE Lookup Table .................................. 35
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
Data Sheet ADN2817/ADN2818
Rev. F | Page 3 of 40
REVISION HISTORY
12/15—Rev. E to Rev. F
Changes to Figure 5 ......................................................................... 11
Updated Outline Dimensions ........................................................ 38
Changes to Ordering Guide ........................................................... 38
1/13—Rev. D to Rev. E
Moved Revision History Section ..................................................... 3
Change to Table 8 ............................................................................ 15
Changes to Table 15 ........................................................................ 17
Changes to Rate Selectivity Section .............................................. 28
1/12—Rev. C to Rev. D
Changes to Figure 14 ...................................................................... 12
Updated Outline Dimensions ........................................................ 37
3/10—Rev. B to Rev. C
Changes to Features Section and Applications Section ............... 1
Changes to Thermal Resistance Section ........................................ 9
Added Table 6; Renumbered Sequentially ..................................... 9
Changes to Table 7 .......................................................................... 10
Changes to Table 8 .......................................................................... 14
Changes to Table 14 ........................................................................ 15
Deleted Table 16; Renumbered Sequentially ............................... 16
Changes to Table 16 ........................................................................ 16
Changes to I2C Interface Section ................................................... 24
Changed fREF Ratio to DIV_FREF Ratio ....................................... 25
Changes to Initiate Frequency Acquisition, Rate Selectivity,
Double Data Rate Mode, and PRBS Generator/Detector
Sections ............................................................................................. 27
Changes to Table 19 ........................................................................ 32
Changes to Table 20 ........................................................................ 34
2/09—Rev. A to Rev. B
Updated Outline Dimensions ........................................................ 37
Changes to Ordering Guide ........................................................... 37
8/08—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Figure 1 ............................................................................................... 1
Added Bit Rate Monitor Specifications Section and Table 4;
Renumbered Sequentially ................................................................ 7
Changes to Figure 5 and Table 6 ................................................... 10
Changes to Table 7 and Table 8 ..................................................... 14
Changes to Table 14 ........................................................................ 15
Added Table 15 ................................................................................ 15
Added Table 1 6 ................................................................................ 16
Added Sample Phase Adjust Section and Bit Error Rate (BER)
Monitor Section ............................................................................... 23
Added Figure 32; Renumbered Sequentially ............................... 24
Changes to Figure 36 ...................................................................... 29
Added Exposed Pad Notation to Outline Dimensions .............. 37
7/07—Revision 0: Initial Version
ADN2817/ADN2818 Data Sheet
Rev. F | Page 4 of 40
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range At PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 2.0 V
Input Common-Mode Level DC-coupled (see Figure 40, Figure 41, and Figure 42) 2.3 2.5 2.8 V
Differential Input Sensitivity 223 − 1 PRBS, ac-coupled,1 BER = 1 × 10−10
ADN2817 10 5 mV p-p
ADN2818 200 mV p-p
QUANTIZER—AC CHARACTERISTICS
Data Rate
10
2700
Mbps
S11 At 2.5 GHz −15 dB
Input Resistance Differential 100 Ω
Input Capacitance 0.65 pF
QUANTIZER—SLICE ADJUSTMENT ADN2817 only
Gain SLICEP − SLICEN = ±0.5 V 0.10 0.11 0.13 V/V
Differential Control Voltage Input SLICEP − SLICEN −0.95 +0.95 V
Control Voltage Range DC level at SLICEP or SLICEN VEE 0.95 V
Slice Threshold Offset ±1 mV
LOSS OF SIGNAL DETECT (LOS) ADN2817 only
Loss of Signal Detect Range (See Figure 6) RTHRESH = 0 Ω 14.2 20.0 mV
RTHRESH = 100 kΩ 2.1 5.0 mV
Hysteresis (Electrical)
OC-48 RTHRESH = 0 Ω 6.2 8.2 dB
RTHRESH = 100 kΩ 4.7 7.7 dB
OC-1 RTHRESH = 0 Ω 4.9 7.5 dB
RTHRESH = 10 kΩ 3.0 7.3 dB
LOS Assert Time
DC-coupled2
450
ns
LOS Deassert Time DC-coupled2 500 ns
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
With respect to nominal
1000
ppm
VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm
LOL Response Time
OC-48 1.0 µs
OC-12 1.0 µs
10 Mbps 500 µs
ACQUISITION TIME
Lock to Data Mode
OC-48 1.3 ms
OC-12 2.0 ms
OC-3 3.4 ms
OC-1 9.8 ms
10 Mbps 40.0 ms
Optional Lock to REFCLK Mode 10.0 ms
DATA RATE READBACK ACCURACY
Coarse Readback See Table 19 10 %
Fine Readback In addition to REFCLK accuracy 100 ppm
Data Sheet ADN2817/ADN2818
Rev. F | Page 5 of 40
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Voltage 3.0 3.3 3.6 V
Current
ADN2817 210 247 mA
ADN2818
180
217
mA
OPERATING TEMPERATURE RANGE −40 +85 °C
1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2 When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2817
input stage.
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
OC-48 548 839 kHz
OC-12 93 137 kHz
OC-3 30 40 kHz
Jitter Peaking
OC-48 0 0.03 dB
OC-12 0 0.03 dB
OC-3
0
0.03
dB
Jitter Generation
OC-48 12 kHz to 20 MHz 0.001 0.003 UI rms
0.02 0.046 UI p-p
OC-12 12 kHz to 5 MHz 0.001 0.004 UI rms
0.01 0.036 UI p-p
OC-3 12 kHz to 1.3 MHz 0.001 0.004 UI rms
0.01 0.023 UI p-p
Jitter Tolerance 223 − 1 PRBS
OC-48 600 Hz1 92.0 UI p-p
6 kHz1 20.0 UI p-p
100 kHz 7.0 UI p-p
1 MHz1 1.00 UI p-p
20 MHz 0.53 UI p-p
OC-12 30 Hz1 100.0 UI p-p
300 Hz1 44.0 UI p-p
25 kHz 7.35 UI p-p
250 kHz
1
1.00
UI p-p
5 MHz 0.52 UI p-p
OC-3 30 Hz1 50.0 UI p-p
300 Hz1 23.5 UI p-p
6500 Hz 6.71 UI p-p
65 kHz1 1.00 UI p-p
130 kHz 0.54 UI p-p
1 Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 6 of 40
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN,
DATAOUTP/DATAOUTN)
Single-Ended Output Swing, VSE See Figure 3 300 350 600 mV
Differential Output Swing, VDIFF See Figure 3 600 700 1200 mV
Output Voltage
High, VOH VCC V
Low, V
OL
VCC − 0.6
VCC − 0.35
VCC − 0.3
V
CML Outputs Timing
Rise Time 20% to 80% 80 112 ps
Fall Time 80% to 20% 80 123 ps
Setup Time, tS See Figure 2, OC-48 150 200 250 ps
Hold Time, tH See Figure 2, OC-48 150 200 250 ps
Setup Time, tDDRS See Figure 4, OC-48 140 170 200 ps
Hold Time, tDDRH See Figure 4, OC-48 200 230 260 ps
I2C INTERFACE DC CHARACTERISTICS
LVCMOS
Input Voltage
High, VIH 0.7 VCC V
Low, VIL 0.3 VCC V
Input Current VIN = 0.1 VCC or VIN = 0.9 VCC −10.0 +10.0 µA
Output Low Voltage VOL, IOL = 3.0 mA 0.4 V
I2C INTERFACE TIMING See Figure 22
SCK Clock Frequency 400 kHz
SCK Pulse Width High
High, tHIGH 600 ns
Low, tLOW 1300 ns
Start Condition
Hold Time, tHD;STA 600 ns
Setup Time, tSU;STA 600 ns
Data
Setup Time, tSU;DAT 100 ns
Hold Time, tHD;DAT 300 ns
SCK/SDA Rise/Fall Time, tR/tF 20 + 0.1 Cb 300 ns
Stop Condition Setup Time, tSU;STO 600 ns
Bus Free Time Between a Stop and a Start, tBUF 1300 ns
REFCLK CHARACTERISTICS Optional lock to REFCLK mode
Input Voltage Range At REFCLKP or REFCLKN
VIL 0 V
VIH VCC V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 200 MHz
Required Accuracy 100 ppm
Data Sheet ADN2817/ADN2818
Rev. F | Page 7 of 40
Parameter Test Conditions/Comments Min Typ Max Unit
LVTTL DC INPUT CHARACTERISTICS
Input Voltage
High, VIH 2.0 V
Low, VIL 0.8 V
Input Current
High IIH, VIN = 2.4 V +5 µA
Low IIL, VIN = 0.4 V −5 µA
LVTTL DC OUTPUT CHARACTERISTICS
Output Voltage
High VOH, IOH = −2.0 mA 2.4 V
Low VOL, IOL = +2.0 mA 0.4 V
ADN2817/ADN2818 Data Sheet
Rev. F | Page 8 of 40
BIT ERROR RATE MONITOR SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
BERMON Extrapolation Mode I2C-controlled eye profiling
Final Computed BER Accuracy Input BER range 1 × 10−3 to 1 × 10−12,
input deterministic jitter (DJ) < 0.4 UI,
DJ ceiling > 1 × 10−2; asymmetry < 0.1 UI;
requires external data processing algorithms
to implement Q factor extrapolation
±1 Decades
Number of Bits (NUMBITS) Number of data bits to collect pseudo errors;
user programmable in increment factors of
23 over the range 218 to 239
218 239 UI
Pseudo BER (PBER) Measurement
Time
NUMBITS/
data rate
sec
BER Range 5 × 10−2 BER
Sample Phase Adjust Resolution 6 Degrees
Sample Phase Adjust Accuracy <6 Degrees
Sample Phase Adjust Range With respect to normal sampling instant −0.5 +0.5 UI
Minimum Input Signal Level Differential peak to peak 4 mV
Power Increase BER enabled 160 mW
BER standby 77 mW
BERMON Voltage Output Mode Analog voltage output
BER Accuracy Input BER range 1 × 10−3 to 1 × 10−9,
input DJ = 0 UI, DJ ceiling > 1 × 10−2;
asymmetry = 0 UI; BER is read as a voltage on
the VBER pin, when the BER mode pin = VEE
±1 Decades
Input BER range 1 × 10−3 to 1 × 10−9,
input DJ = 0.2 UI, DJ ceiling > 1 × 10−2;
asymmetry = 0 UI; BER is read as a voltage on
the VBER pin, when the BER mode pin = VEE
+1/−2 Decades
NUMBITS Number of data bits to collect pseudo errors 227 UI
Measurement Time 2.5 Gbps 0.054 sec
1 Gbps 0.134 sec
155 Mbps 0.865 sec
10 Mbps 1.34 sec
VBER Voltage Range Via 3 kΩ resistor to VEE 0.1 0.9 V
Minimum Input Signal Level Differential peak to peak 4 mV
Power Increase BER voltage mode 160 mW
Sample Phase Adjust Mode
Sample Phase Adjust Step Size Monotonic 6 Degrees
Sample Phase Adjust Accuracy <6 Degrees
Sample Phase Adjust Range
With respect to normal sampling instant
−0.5
+0.5
UI
Power Increase 160 mW
Data Sheet ADN2817/ADN2818
Rev. F | Page 9 of 40
TIMING CHARACTERISTICS
CLKOUTP
DATAOUTP/
DATAOUTN
t
S
t
H
06001-002
Figure 2. Default Mode Output Timing
OUTP
OUTN
OUTP – OUTN
0V
V
SE
V
CML
V
SE
V
DIFF
06001-003
Figure 3. Single-Ended vs. Differential Output Specifications
CLKOUTP/
CLKOUTN
t
DDRS
t
DDRH
DATAOUTP/
CLKOUTN
06001-042
Figure 4. Double Data Rate Mode Output Timing
ADN2817/ADN2818 Data Sheet
Rev. F | Page 10 of 40
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V,
CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted.
Table 5.
Parameter Rating
Supply Voltage (VCC)
4.2 V
Input Voltage (All Inputs)
Minimum VEE − 0.4 V
Maximum VCC + 0.4 V
Junction Temperature, Maximum 125°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, on a
4-layer board with the exposed paddle soldered to VEE.
Table 6. Thermal Resistance
Package Type θJA Unit
32-Lead LFCSP 28 °C/W
ESD CAUTION
Data Sheet ADN2817/ADN2818
Rev. F | Page 11 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06001-004
BERMODE
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
1
2
3
4
5
6
7
8
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE
24
23
22
21
20
19
18
17
THRADJ
REFCLKP
REFCLKN
VCC
VEE
CF2
CF1
LOL
9
10
11
12
13
14
15
16
VBER
VCC
VEE
DATAOUTP
DATAOUTN
SQUELCH
CLKOUTP
CLKOUTN
32
31
30
29
28
27
26
25
TOP VIEW
(No t t o Scal e)
ADN2817/
ADN2818
NOTES
1. THE EX P OSE D P ADDLE O N THE BOT TOM OF THE P ACKAGE
MUST BE CONNECTED TO VEE.
PIN 1
INDICATOR
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1
BERMODE
DI
Set this pin to logic low to enable analog voltage output mode for BER monitor.
2 VCC P Power for Input Stage, LOS.
3 VREF AO Internal VREF Voltage. Decouple to ground with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7
SLICEN
AI
Differential Slice Level Adjust Input.
8 VEE P GND for the Limiting Amplifier, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 200 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 200 MHz.
12
VCC
P
VCO Power.
13 VEE P VCO Ground.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss of Lock Indicator. Active high, LVTTL.
17 VEE P FLL Detector Ground.
18
VCC
P
FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 LOS DO Loss of Signal Detect Output. Active high, LVTTL.
23 VEE P Output Buffer, I2C Ground.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. CML.
26 CLKOUTP DO Differential Recovered Clock Output. CML.
27 SQUELCH DI Disable Clock and Data Outputs. Active high, LVTTL.
28 DATAOUTN DO Differential Recovered Data Output. CML.
29
DATAOUTP
DO
Differential Recovered Data Output. CML.
30 VEE P Phase Detector, Phase Shifter Ground.
31 VCC P Phase Detector, Phase Shifter Power.
32 VBER AO This pin represents BER when analog BERMON is enabled with 3 kΩ to VEE.
EPAD P Exposed Paddle. The Exposed paddle on the bottom of the package must be connected to VEE.
1 P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 12 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
110 100 R
TH
(Ω)
1k 100k10k 1M
0
TRIP POINT (mV p-p)
06001-005
0.002
0.004
0.006
0.008
0.010
0.012
0.014
0.016
0.018
0.020
Figure 6. LOS Comparator Trip Point Programming
–20
–15
–10
–5
0
5
100 1k 10k 100k 1M
06001-032
JIT TER FREQUENCY ( Hz )
GAI N (dB)
SONET
ADN2817
Figure 7. Jitter Transfer, OC-1
–20
–15
–10
–5
0
5
100 1k 10k 100k 1M 10M
06001-034
JIT TER FREQUENCY ( Hz )
GAI N ( dB)
SONET
ADN2817
Figure 8. Jitter Transfer, OC-3
06001-040
50ps/DIV
200mV/DIV
Figure 9. Output Eye, OC-48
0.110 100 1k 10k 100k 1M
06001-039
JIT TER FREQUENCY ( Hz )
JITTER AMPLITUDE (UI)
1
10
100
ADN2817
EQUIPMENT LIMIT
SONE T G R- 253 CORE 004
Figure 10. Jitter Tolerance, OC-1
0.110 100 1k 10k 100k 10M1M
06001-038
JIT TER FREQUENCY ( Hz )
JITTER AMPLITUDE (UI)
1
10
100
ADN2817
EQUIPMENT LIMIT
SONE T G R- 253 CORE 004
Figure 11. Jitter Tolerance, OC-3
Data Sheet ADN2817/ADN2818
Rev. F | Page 13 of 40
–20
–15
–10
–5
0
5
1k 10k 100k 1M 10M
06001-033
JIT TER FREQUENCY ( Hz )
GAI N (dB)
SONET
ADN2817
Figure 12. Jitter Transfer, OC-12
–20
–15
–10
–5
0
5
10k 100k 1M 10M 100M
06001-035
JIT TER FREQUENCY ( Hz )
GAI N ( dB)
SONET
ADN2817
Figure 13. Jitter Transfer, OC-48
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
CLKO UTP ADN2817
CLKO UTN ADN2817
06001-043
DATA RATE (Hz )
OUTPUT SWING (V)
100M 600M 1.1G 1.6G 2.1G 2.6G 3.1G
Figure 14. Output Swing vs. Data Rate
0.110 100 1k 10k 100k 10M
1M
06001-037
JIT TER FREQUENCY ( Hz )
JITTER AMPLITUDE (UI)
1
10
100
1000
ADN2817
EQUIPMENT LIMIT
SONE T G R- 253 CORE 004
Figure 15. Jitter Tolerance, OC-12
0.110 100 1k 10k 100k 100M10M1M
06001-036
JIT TER FREQUENCY ( Hz )
JITTER AMPLITUDE (UI)
1
10
100
1000
ADN2817
EQUIPMENT LIMIT
SONE T G R- 253 CORE 004
Figure 16. Jitter Tolerance, OC-48
06001-041
INPUT LEVEL (mV)
BIT ERRO R RATE
0.000000001
0.00000001
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Figure 17. Bit Error Rate vs. Input Level
ADN2817/ADN2818 Data Sheet
Rev. F | Page 14 of 40
I2C-INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
1A500000X
MSB = 1 SET BY
PIN 19 0 = W R
1 = RD
SLAVE ADDRESS [6: 0] R/
W
CTRL.
06001-007
Figure 18. Slave Address Configuration
S SLAVE ADDR, L SB = 0 ( WR) A(S) A(S) A(S)DATASUB ADDR A(S) PDATA
06001-008
Figure 19. I2C Write Data Transfer
S
S = START BI T P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDG E BY MASTER A(M) = L ACK OF ACKNOWLE DGE BY M AS TER
SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, L S B = 1 (RD)A(S) A(S)SUB ADDR A(S) DATA A(M) DATA PA(M)
0
6001-009
Figure 20. I2C Read Data Transfer
START BIT
S
STOP BIT
P
ACKACKWR ACK
D0D7A0A7A5A6
SLADDR[4:0]
SLAVE ADDRESS SUB ADDRESS DATA
SUB ADDR[6:1] DATA[6:1]
SCK
SDA
06001-010
Figure 21. I2C Data Transfer Timing
t
BUF
SDA
SSPS
SCK
t
F
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
HD;STA
t
R
06001-011
Figure 22. I2C Port Timing Diagram
Data Sheet ADN2817/ADN2818
Rev. F | Page 15 of 40
Table 8. Internal Register Map1
Reg Name R/W Addr D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x00 MSB LSB
FREQ1 R 0x01 MSB LSB
FREQ2 R 0x02 0 MSB LSB
Rate R 0x03 COARSE_RD[8:1]
MISC R 0x04 X X LOS status Static
LOL
LOL status Data rate
measurement
complete
X COARSE_RD[0]
(LSB)
CTRLA W 0x08 fREF range Data rate/DIV_FREF ratio Measure
data rate
Lock to REFCLK
CTRLA_RD R 0x05 Readback CTRLA
CTRLB W 0x09 Config
LOL
Reset
MISC[4]
Initiate freq
acquisition
0 Reset
MISC[2]
0 0 0
CTRLB_RD R 0x06 Readback CTRLB
CTRLC W 0x11 0 0 0 0 0 Config LOS Squelch
mode
0
CTRLD
W
0x22
CDR
bypass
Disable
DATAOUT
buffer
Disable
CLKOUT
buffer
0
Initiate
PRBS
sequence
PRBS mode
CTRLE/BERCTLB2 W 0x1F 0 0 Enable
BERMON
BER
stdby
mode
0 PRBS/DDR enable and output mode
SEL_MODE W 0x34 0 0 0 0 Limited
rate mode
0 CLK
holdover
mode
0
HI_CODE W 0x35 HI_CODE[8:1]
LO_CODE W 0x36 LO_CODE[8:1]
CODE_LSB W 0x39 0 0 0 0 0 0 HI_CODE[0]
(LSB)
LO_CODE[0]
(LSB)
BERCTLA
W
0x1E
BER timer (NUMBITS)
0
BER start
pulse
Error count byte select, for example, 011 = Byte 3
of 5 (NUMERRORS[39:0])
BERSTS R 0x20 X X X X X X X End of BER
measurement
(EOBM)
BER_RES R 0x21 BER_RES[7:0], one byte of pseudo BER measurement result (NUMERRORS[39:0])
BER_DAC R 0x24 X X BER_DAC[5:0], input to BER DAC in analog BERMON mode
Phase W 0x37 0 0 Phase[5:0], twos complement sample phase adjustment,
phase code range is from −30 decimal to +30 decimal,
which gives a sampling phase offset range from −0.5 UI to +0.5 UI;
for example, phase = 111010 is−6 decimal,
which gives a sampling phase offset of −6/+60 = −0.1 UI
1 X = don’t care.
2 Both CTRLE and BERCTLB registers are used, depending on the application.
Table 9. Miscellaneous Register, MISC
LOS Status Static LOL LOL Status Data Rate Measurement Complete COARSE_RD[0] (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
X X 0 = no loss of signal 0 = waiting for next LOL 0 = locked 0 = measuring data rate X COARSE_RD[0]
1 = loss of signal 1 = static LOL until reset 1 = acquiring 1 = measurement complete
ADN2817/ADN2818 Data Sheet
Rev. F | Page 16 of 40
Table 10. Control Register, CTRLA
fREF Range Data Rate/DIV_FREF Ratio Measure Data Rate Lock to REFCLK
D7 D6 Range D5 D4 D3 D2 Ratio D1 D0
Set to 0 Set to 0 10 MHz to 25 MHz 0 0 0 0 1 Set to 1 to measure data rate 0 = lock to input data
Set to 0 Set to 1 25 MHz to 50 MHz 0 0 0 1 2 1 = lock to reference clock
Set to 1 Set to 0 50 MHz to 100 MHz 0 0 1 0 4
Set to 1 Set to 1 100 MHz to 200 MHz n 2n
1 0 0 0 256
Table 11. Control Register, CTRLB
Config LOL Reset MISC[4] Initiate Freq Acquisition Reset MISC[2]
D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal
operation
1 = LOL pin is static LOL
Write a 1 followed
by 0 to reset MISC[4]
Write a 1 followed
by 0 to initiate a
frequency acquisition
Set
to 0
Write a 1 followed
by 0 to reset MISC[2]
Set
to 0
Set
to 0
Set
to 0
Table 12. Control Register, CTRLC
Configure LOS Squelch Mode
D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 0 = active high LOS 0 = squelch CLK and DATA Set to 0
1 = active low LOS 1 = squelch CLK or DATA
Table 13. Control Register, CTRLD
CDR Bypass
Disable
DATAOUT Buffer
Disable
CLKOUT Buffer
Initiate PRBS
Sequence PRBS Mode
D7 D6 D5 D4 D3 D2 D1 D0 Function
0 = CDR enabled 0 = data buffer enabled 0 = CLK buffer enabled Set to 0 Write a 1 followed
by 0 to initiate a
PRBS generate
sequence
0 0 0 Power-down PRBS
1 = CDR disabled 1 = data buffer disabled 1 = CLK buffer disabled 0 0 1 Generate mode
1 0 0 Detect mode
Table 14. Control Registers, CTRLE/BERCTLB
Enable BERMON BER Stdby Mode PRBS/DDR Enable and Output Mode
D7 D6 D5 D4 D3 D2 D1 D0 Function
Set to 0 Set to 0 1 = BERMON
enabled
1 = place BERMON in low
power standby mode
Set to 0 0 0 0 Normal data rate output mode
0 0 1 Offset decision circuit (ODC) output
mode1
0 1 0 Enable DDR mode (double data rate
mode)
0 = BERMON
disabled
0 = BERMON ready 0 1 1 Offset decision circuit (ODC) output
in DDR mode1
1 0 1 Enable PRBS detector/generator
All other combinations reserved
1 See the AN-941 Application Note, BER Monitor User Guide.
Data Sheet ADN2817/ADN2818
Rev. F | Page 17 of 40
Table 15. Mode Select Register, SEL_MODE
CLK Holdover Mode
D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Default 0
Limited rate enable = 1
Set to 0 Set to 1 for clock holdover mode Set to 0
Table 16. BER Control Register, BERCTLA
BER Timer (NUMBITS) BER Start Pulse Error Count Byte Select (NUMERRORS[39:0])
D7 D6 D5 No. of Bits D4 D3 D2 D1 D0 Byte Selection
0 0 0 218 bits Set to 0 Write a 1 followed by a 0 to initiate BER
measurement
0 0 0 Byte 0
0 0 1 221 bits 0 0 1 Byte 1
0
1
0
224 bits
0
1
0
Byte 2
0 1 1 227 bits 0 1 1 Byte 3
1 0 0 230 bits 1 0 0 Byte 4
1 0 1 233 bits
1 1 0 236 bits
1 1 1 239 bits
ADN2817/ADN2818 Data Sheet
Rev. F | Page 18 of 40
TERMINOLOGY
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the logic
output of the quantizer and the analog voltage input is shown in
Figure 23. For sufficiently large positive input voltages, the output
is always Logic 1 and, similarly for negative inputs, the output is
always Logic 0. However, the transitions between Output Logic
Level 1 and Output Logic Level 0 are not at precisely defined
input voltage levels but occur over a range of input voltages. Within
this range of input voltages, the output may be either 1 or 0, or
it may even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage. Input
overdrive is the magnitude of signal required to guarantee the
correct logic level with 1 × 10−10 confidence level.
NOISE
OUTPUT
INPUT (V p-p)
OFFSET
OVERDRIVE
SENSITIVITY
(2× OVERDRIVE)
1
0
06001-012
Figure 23. Input Sensitivity and Input Overdrive
SINGLE-ENDED vs. DIFFERENTIAL
AC coupling is typically used to drive the inputs to the quantizer.
The inputs are internally dc biased to a common-mode potential
of approximately 2.5 V. Driving the ADN2817/ADN2818
single-ended and observing the quantizer input with an
oscilloscope probe at the point indicated in Figure 24 shows a
binary signal with an average value equal to the common-mode
potential and instantaneous values both above and below the
average value. It is convenient to measure the peak-to-peak
amplitude of this signal and call the minimum required value
the quantizer sensitivity. Referring to Figure 24, because both
positive and negative offsets need to be accommodated, the
sensitivity is twice the overdrive. The ADN2817 quantizer
typically has 5 mV p-p sensitivity. The ADN2818 does not have
a limiting amplifier at its input. The input sensitivity for the
ADN2818 is 200 mV p-p.
+
–
QUANTIZER
50Ω50Ω
3kΩ
2.5V
VREF
SCOPE
PROBE
PIN
VREF
10mV p-p
06001-013
Figure 24. Single-Ended Sensitivity Measurement
Differentially driving the ADN2817 (see Figure 25), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a single-
ended probe. A 5 mV p-p signal appears to drive the ADN2817
quantizer. However, the single-ended probe measures only half
the signal. The true quantizer input signal is twice this value
because the other quantizer input is a complementary signal to
the signal being observed.
SCOPE
PROBE
PIN
50Ω
3kΩ
2.5V
50Ω
VREF
QUANTIZER
+
–
NIN
5mV p-
p
VREF
5mV p-p
VREF
06001-014
Figure 25. Differential Sensitivity Measurement
LOS RESPONSE TIME
The LOS response time is the delay between the removal of the
input signal and the indication of the loss of signal at the LOS
output, Pin 22. When the inputs are dc-coupled, the LOS assert
time of the ADN2817 is 450 ns typically and the deassert time is
500 ns typically. In practice, the time constant produced by the
ac coupling at the quantizer input and the 50 Ω on-chip input
termination determine the LOS response time.
Data Sheet ADN2817/ADN2818
Rev. F | Page 19 of 40
JITTER SPECIFICATIONS
The ADN2817/ADN2818 CDR is designed to achieve the best
bit error rate (BER) performance and exceeds the jitter transfer,
generation, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia® Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can cause
dynamic phase errors on the recovered clock sampling edge. Jitter
on the recovered clock causes jitter on the retimed data.
The following sections briefly summarize the specifications
of jitter generation, transfer, and tolerance in accordance with
the Telcordia document (GR-253-CORE, Issue 3, September
2000) for the optical interface at the equipment level and the
ADN2817/ADN2818 performance with respect to those
specifications.
JITTER GENERATION
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter
has a 12 kHz high-pass cutoff frequency with a roll-off of
20 dB/decade and a low-pass cutoff frequency of at least
20 MHz. The jitter generated must be less than 0.01 UI rms
and must be less than 0.1 UI p-p.
JITTER TRANSFER
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on
an input signal that can be transferred to the output signal
(see Figure 26).
0.1
ACCEPTABLE
RANGE
f
C
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
JITTER GAIN (dB)
0
6001-015
Figure 26. Jitter Transfer Curve
JITTER TOLERANCE
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating conditions
(see Figure 27).
15.00
1.50
0.15
f
0
f
1
f
2
f
3
f
4
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
INPUT JITTER AMPLITUDE (UI p-p)
06001-016
Figure 27. SONET Jitter Tolerance Mask
ADN2817/ADN2818 Data Sheet
Rev. F | Page 20 of 40
THEORY OF OPERATION
The ADN2817/ADN2818 are delay- and phase-locked loop
circuits for clock recovery and data retiming from an NRZ
encoded data stream. The phase of the input data signal is tracked
by two separate feedback loops that share a common control
voltage. A high speed delay-locked loop path uses a voltage
controlled phase shifter to track the high frequency components
of input jitter. A separate phase control loop, composed of the
VCO, tracks the low frequency components of input jitter. The
initial frequency of the VCO is set by a third loop, which
compares the VCO frequency with the input data frequency
and sets the coarse tuning voltage. The jitter tracking phase-
locked loop controls the VCO by the fine-tuning control.
The delay- and phase-locked loops together track the phase of
the input data signal. For example, when the clock lags input
data, the phase detector drives the VCO to a higher frequency
and increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while, simultaneously, the
delayed data loses phase. Because the loop filter is an integrator,
the static phase error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 28 shows that
the jitter transfer function, Z(s)/X(s), is second-order low-pass,
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 29). This makes this circuit ideal for signal regene-
rator applications, where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
X(s)
Z(s)
RECOVERED
CLOCK
e(s)
INPU
T
DATA d/sc
psh
o/s
1/n
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
p
sh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
=1
cn
do
s
2
+n psh
o
s+ 1
Z(s)
X(s)
JITTER TRANSFER FUNCTION
=s
2
s
2
d psh
c
s++
do
cn
e(s)
X(s)
TRACKING ERROR TRANSFER FUNCTION
06001-017
Figure 28. ADN2817/ADN2818 PLL/DLL Architecture
ADN28xx
Z(s)
X(s)
FREQUENCY (kHz)
JITTER PEAKING
IN ORDINARY PLL
JITTER GAIN (dB)
o
n psh d psh
c
06001-018
Figure 29. ADN2817/ADN2818 Jitter Response vs. Conventional PLL
The delay- and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to track
large jitter amplitudes with small phase error. In this case, the
VCO is frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider tuning
range gives larger accommodation of low frequency jitter. The
internal loop control voltage remains small for small phase
errors, so the phase shifter remains close to the center of its
range and thus contributes little to the low frequency jitter
accommodation.
Data Sheet ADN2817/ADN2818
Rev. F | Page 21 of 40
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or the other.
The size of the VCO tuning range, therefore, has only a small
effect on the jitter accommodation. The delay-locked loop control
voltage is now larger, and so the phase shifter takes on the
burden of tracking the input jitter. The phase shifter range, in
UI, can be seen as a broad plateau on the jitter tolerance curve.
The phase shifter has a minimum range of 2 UI at all data rates.
The gain of the loop integrator is small for high jitter frequencies,
so that larger phase differences are needed to make the loop
control voltage big enough to tune the range of the phase shifter.
Large phase errors at high jitter frequencies cannot be tolerated.
In this region, the gain of the integrator determines the jitter
accommodation. Because the gain of the loop integrator declines
linearly with frequency, jitter accommodation is lower with higher
jitter frequency. At the highest frequencies, the loop gain is very
small, and little tuning of the phase shifter can be expected. In this
case, jitter accommodation is determined by the eye opening of the
input data, the static phase error, and the residual loop jitter
generation. The jitter accommodation is roughly 0.5 UI in this
region. The corner frequency between the declining slope and
the flat region is the closed-loop bandwidth of the delay-locked
loop, which is roughly 3 MHz at OC-48.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 22 of 40
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2817/ADN2818 acquire frequency from the data over
a range of data frequencies from 10 Mbps to 2.7 Gbps. The lock
detector circuit compares the frequency of the VCO and the
frequency of the incoming data. When these frequencies differ
by more than 1000 ppm, LOL is asserted. This initiates a fre-
quency acquisition cycle. The VCO frequency is reset to the
bottom of its range, which is 10 MHz. The frequency detector
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned off.
The phase- and delay-locked loop (PLL/DLL) pulls in the VCO
frequency until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 µF ± 20%, X7R ceramic
chip capacitor with <10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 µF capacitor, approximately
3 V, by the insulation resistance of the capacitor. The insulation
resistance of the 0.47 μF capacitor should be greater than
300 MΩ.
LOCK DETECTOR OPERATION
The lock detector on the ADN2817/ADN2818 has three modes
of operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2817/ADN2818 function as continuous
rate CDRs that lock onto any data rate from 10 Mbps to 2.7 Gbps
without the use of a reference clock as an acquisition aid. In this
mode, the lock detector monitors the frequency difference between
the VCO and the input data frequency, and deasserts the loss of
lock signal that appears on LOL (Pin 16) when the VCO is within
250 ppm of the data frequency. This enables the delay- and phase-
locked loop (DLL/PLL), which pulls the VCO frequency in the
remaining amount and acquires phase lock. When locked, if the
input frequency error exceeds 1000 ppm (0.1%), the loss of lock
signal is reasserted and control returns to the frequency loop,
which begins a new frequency acquisition starting at the lowest
point in the VCO operating range, 10 MHz. The LOL pin remains
asserted until the VCO locks onto a valid input data stream to
within 250 ppm frequency error. This hysteresis is shown in
Figure 30.
LOL
0–250 250 1000 f
VCO
ERROR
(ppm)
–1000
1
06001-019
Figure 30. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2817/ADN2818 VCO. Lock to reference mode is
enabled by setting CTRLA[0] to 1. The user also needs to write
to the CTRLA[7:6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with respect
to the reference frequency. For more details, see the Reference
Clock (Optional) section. In this mode, the lock detector monitors
the difference in frequency between the divided down VCO and
the divided down reference clock. The loss of lock signal, which
appears on LOL (Pin 16), is deasserted when the VCO is within
250 ppm of the desired frequency. This enables the DLL/ PLL,
which pulls the VCO frequency in the remaining amount with
respect to the input data and acquires phase lock. Once locked, if
the input frequency error exceeds 1000 ppm (0.1%), the loss of
lock signal is reasserted and control returns to the frequency loop,
which reacquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of the
desired frequency. This hysteresis is shown in Figure 30.
Static LOL Mode
The ADN2817/ADN2818 implement a static LOL feature, which
indicates if a loss of lock condition has ever occurred and remains
asserted, even if the ADN2817/ADN2818 regain lock, until the
static LOL bit is manually reset. I2C Register Bit MISC[4] is the
static LOL bit. If there is ever an occurrence of a loss of lock
condition, this bit is internally asserted to logic high. The MISC[4]
bit remains high even after the ADN2817/ADN2818 reacquire
lock to a new data rate. This bit can be reset by writing a 1 followed
by 0 to I2C Register Bit CTRLB[6]. When reset, the MISC[4] bit
remains deasserted until another loss of lock condition occurs.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the function-
ality described previously. The CTRLB[7] bit defaults to 0. In
this mode, the LOL pin operates in the normal operating mode,
that is, it is asserted only when the ADN2817/ADN2818 are in
acquisition mode and deasserts when the ADN2817/ADN2818
reacquire lock.
Data Sheet ADN2817/ADN2818
Rev. F | Page 23 of 40
HARMONIC DETECTOR
The ADN2817/ADN2818 provide a harmonic detector, which
detects whether the input data has changed to a lower harmonic
of the data rate onto which the VCO is currently locked. For
example, if the input data instantaneously changes from an OC-48,
2.488 Gbps to an OC-12, 622.080 Mbps bit stream, this could be
perceived as a valid OC-48 bit stream, because the OC-12 data
pattern is exactly 4× slower than the OC-48 pattern. Therefore,
if the change in data rate is instantaneous, a 101 pattern at OC-12 is
perceived by the ADN2817/ADN2818 as a 111100001111 pattern
at OC-48. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2817/ADN2818 implement a harmonic detector that
automatically identifies whether the input data has switched to a
lower harmonic of the data rate onto which the VCO is currently
locked. When a harmonic is identified, the LOL pin is asserted
and a new frequency acquisition is initiated. The ADN2817/
ADN2818 automatically lock onto the new data rate, and the
LOL pin is deasserted.
However, the harmonic detector does not detect higher har-
monics of the data rate. If the input data rate switches to a
higher harmonic of the data rate onto which the VCO is currently
locked, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2817/ADN2818
automatically lock onto the new data rate.
The time to detect lock to harmonic is
16,384 × (Td/ρ)
where:
1/Td is the new data rate. For example, if the data rate is switched
from OC-48 to OC-12, then Td = 1/622 MHz.
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS or 8b/10b encoding.
When the ADN2817/ADN2818 is placed in lock to reference
mode, the harmonic detector is disabled.
LIMITING AMPLIFIER (ADN2817 ONLY)
The limiting amplifier on the ADN2817 has differential inputs
(PIN/NIN) that internally terminate with 50 Ω to an on-chip
voltage reference (VREF = 2.5 V typically). The inputs are typically
ac-coupled externally, although dc coupling is possible as long
as the input common-mode voltage remains above 2.5 V (see
Figure 40, Figure 41, and Figure 42). Input offset is factory
trimmed to achieve better than 6 mV typical sensitivity with
minimal drift. The limiting amplifier can be driven differentially
or single-ended.
SLICE LEVEL ADJUST (ADN2817 ONLY)
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or duty
cycle distortion by applying a differential voltage input of up to
±0.95 V to SLICEP/SLICEN inputs. If no adjustment of the slice
level is needed, SLICEP/SLICEN should be tied to VEE. The gain
of the slice adjustment is approximately 0.1 V/V.
LOSS OF SIGNAL (LOS) DETECTOR
(ADN2817 ONLY)
The receiver front-end LOS detector circuit detects when the input
signal level has fallen below a user-adjustable threshold. The
threshold is set with a single external resistor from Pin 9, THRADJ,
to VEE. The LOS comparator trip point vs. resistor value is shown
in Figure 6. If the input level to the ADN2817 drops below the
programmed LOS threshold, the output of the LOS detector, Pin 22
(LOS), is asserted to a Logic 1. The LOS detector response time is
450 ns by design but is dominated by the RC time constant in ac-
coupled applications. The LOS pin defaults to active high.
However, by setting Bit CTRLC[2] to 1, the LOS pin is configured
as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means that,
if the input level drops below the programmed LOS threshold
causing the LOS pin to assert, the LOS pin is not deasserted until
the input level has increased to 6 dB (2×) above the LOS threshold
(see Figure 31).
06001-020
HYSTERESIS
LOS OUTPUT
INPUT LEVEL
LOS THRESHOLD
t
INPUT VOLTAGE (VDIFF)
Figure 31. ADN2817 LOS Detector Hysteresis
The LOS detector and the slice level adjust can be used simul-
taneously on the ADN2817. This means that any offset added to
the input signal by the slice adjust pins does not affect the LOS
detector measurement of the absolute input level.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 24 of 40
SAMPLE PHASE ADJUST
If the user is not using the BER monitoring function, sample
phase adjustment can be used to optimize the horizontal samp-
ling point of the incoming data eye. The ADN2817 automatically
centers the sampling point to the best of its ability. However,
sample phase adjustment can be used to compensate for any
static phase offset of the CDR and data eye jitter profile asymmetry.
Sample phase adjustment is applied to the incoming eye via the
phase register. The sampling phase can be adjusted by ±0.5 UI,
in 6 degree steps, relative to the normal CDR data sampling
instant. Using the sample phase adjustment capability uses an
additional 160 mW of power. The AN-941 Application Note
gives additional information on the use of this feature.
BIT ERROR RATE (BER) MONITOR
The ADN2817 has a BER measurement feature that estimates
the actual bit error rate of the IC. This feature also allows data
eye jitter profiling and Q-factor estimation.
By knowing the BER at a sampling phase offset from the ideal
sampling phase (known as pseudo BER [PBER] values), it is
possible to extrapolate to obtain an estimate of the BER at the
actual sampling instant. This extrapolation relies on the assumption
that the input jitter is composed of deterministic and random
(Gaussian) components. The implementation requires off-chip
control and data processing to estimate the actual BER. A lower
accuracy voltage output mode is also supported that requires no
data processing or I2C control.
Brief Overview of Modes of Operation
The following two modes of operation are available for the BER
feature: the BER extrapolation mode and the voltage output mode.
Only one mode can be operational at a time. The BER extra-
polation mode scans the input eye in the range of ±0.5 UI of the
data center and reads the measured PBER over the I2C. The user
then applies a data processing algorithm to determine the BER.
Using the BER feature in this way provides for the greatest accuracy
in BER estimation as the magnitude of both random (Gaussian)
jitter and deterministic jitter can be estimated and used to predict
the actual BER.
In the voltage output mode, the part autonomously samples the
PBER at 0.1 UI offset and decodes this value to provide an estimate
of the input BER. This estimate is output via a DAC as an analog
current output. The AN-941 Application Note gives detailed
information on the use of the BER monitor features.
BER Extrapolation Mode
Power Saving
The following three power settings are available in BER
extrapolation mode: BER off, BER on, and BER standby.
In BER off mode (BERCTLB[5] = 0), the BER circuitry is
powered down with the ADN2817 providing normal CDR
operation.
In BER on mode (BERCTLB[5] = 1), the internal BER circuitry
is powered up. The user can perform pseudo BER measurements
through the I2C.
In BER standby mode (BERCTLB[5:4] = 11b), the BER is placed
into a lower power mode. This setting can only be set after
applying the BER on setting.
These modes are defined to allow optimal power saving
opportunities. It is not possible to switch between the BER
off setting and the BER on setting without losing lock. Switching
between the BER standby setting and the BER on setting is
achieved without interrupting data recovery. The incremental
power between the BER off setting and the BER standby setting
is 77 mW and between the BER off setting and the BER on setting
it is 160 mW.
BER On Mode
The BER on mode allows the user to scan the incoming data eye
in the time dimension and build up a profile of the BER statistics.
The following is a brief overview of user protocol:
The user powers up BER circuitry through the I2C.
The user initiates the PBER measurement. Sample phase offset
and number of data bits to be counted (NUMBITS is a choice
among 218, 221, 224, 227, 230, 233, 236, and 239) are supplied by the
user through the I2C.
The user initiates the pseudo BER measurement by writing
a 1-to-0 transition on BERCTLA[3].
BER logic indicates the end of the BER measurement with
an EOBM signal and updates the number of counted errors
on NUMERRORS[39:0]. The user must poll the I2C to
determine if the EOBM bit, BERSTS[0], has been asserted.
The user reads back NUMERRORS[39:0] through the I2C.
NUMERRORS[39:0] is read back through the 8-bit register
BER_RES at Address 0x21. The user sets BERCTLA[2:0] to
address one of the five NUMERRORS bytes and then reads
the selected byte from BER_RES.
PBER for programmed sample phase is calculated as
NUMERRORS/NUMBITS.
The user initiates another PBER measurement.
The user sweeps the phase over −0.5 UI to +0.5 UI with
respect to the normal sampling instant to obtain the BER
profile required.
The ADN2817 does not output the BER at the normal decision
instant. It outputs PBER measurements to the left and right of
the normal decision instants from which the user must calculate
what the BER is at the normal decision instant. A microprocessor is
required to parse the data and to use the remaining data for BER
estimation. Suitable algorithms are suggested in the AN-941
Application Note, BER Monitor User Guide.
Data Sheet ADN2817/ADN2818
Rev. F | Page 25 of 40
Voltage Output Mode of Operation
A second mode of operation is the voltage output mode. This
mode is to give easy access to a coarse estimate of the BER. The
functionality is similar to that already described in the Brief
Overview of Modes of Operation section except that the
measurement is performed autonomously by the ADN2817,
and the result is output as a voltage on a pin from which the
actual BER can be inferred. Because this mode does not perform
scanning of the eye to separate out deterministic jitter from
random jitter effects, this method is less accurate under normal
applied jitter conditions.
The user merely has to bring the BERMODE pin low and read
the voltage on the VBER pin (see Figure 32). Alternatively, a
6-bit value can be read over the I2C.
LOG (BER)
VBER PIN VOLTAGE RELATIVE T O VEE (V)
0.9
0.7
0.5
0.3
0.1
VBER VOLTAGE IS
GUARANTEED TO
SATURATE FOR
INPUT BERs
GREATER T HAN 0.001
VBER VOLTAGE IS
GUARANTEED TO
SATURATE FOR
INPUT BERs LES S
THAN 0. 000000001
0.001 0.00001 0.0000001 0.000000001
06001-024
Figure 32. VBER vs. Bit Error Rate
SQUELCH MODE
Two squelch modes are available with the ADN2817/ADN2818:
squelch DATAOUT and CLKOUT mode, and squelch DATAOUT
or CLKOUT mode.
Squelch DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the squelch
input, Pin 27, is driven to a TTL high state, both the clock and
data outputs are set to the zero state to suppress downstream
processing. If the squelch function is not required, Pin 27 should be
tied to VEE.
Squelch DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the squelch input is driven
to a high state, the DATAOUT pins are squelched. When the
squelch input is driven to a low state, the CLKOUT pins are
squelched. This is especially useful in repeater applications,
where the recovered clock may not be needed.
I2C INTERFACE
The ADN2817/ADN2818 support a 2-wire, I2C-compatible
serial bus driving multiple peripherals. Two inputs, serial data
(SDA) and serial clock (SCK), carry information between any
devices connected to the bus. Each slave device is recognized by
a unique address. The ADN2817/ADN2818 have two possible
7-bit slave addresses for both read and write operations. The
MSB of the 7-bit slave address is factory programmed to 1. Bit 5
of the slave address is set by Pin 19, SADDR5. Slave Address
Bits[4:0] are defaulted to all 0s. The slave address consists of the
7 MSBs of an 8-bit word. The LSB of the word either sets a read
or write operation (see Figure 18). Logic 1 corresponds to a read
operation and Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
used. First, the master initiates a data transfer by establishing a
start condition, defined by a high-to-low transition on SDA
while SCK remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCK lines waiting for
the start condition and correct transmitted address. The R/W
bit determines the direction of the data. Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADN2817/ADN2818 act as standard slave devices on the
bus. The data on the SDA pin is eight bits long, supporting the
7-bit addresses plus the R/W bit. The ADN2817/ADN2818 have
eight subaddresses to enable the user-accessible internal registers
(see Table 8 through Table 16). It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. Auto-increment mode is supported, allowing data
to be read from, or written to, the starting subaddress and each
subsequent address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2817/ADN2818
do not issue an acknowledge and return to the idle condition.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 26 of 40
If the user exceeds the highest subaddress while reading back in
auto-increment mode, the highest subaddress register contents
continue to be output until the master device issues a no acknowl-
edge. This indicates the end of a read. In a no acknowledge
condition, the SDA line is not pulled low on the ninth pulse. See
Figure 19 and Figure 20 for sample read and write data transfers
and Figure 21 for a more detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2817/ADN2818. However, support for
an optional reference clock is provided. The reference clock can
be driven differentially or single-ended. If the reference clock is not
used, tie REFCLKP to VCC, and either leave REFCLKN floating or
tie it to VEE (the inputs are internally terminated to VCC/2). See
Figure 33 through Figure 35 for sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility. Phase
noise and duty cycle of the reference clock are not critical and
100 ppm accuracy is sufficient.
BUFFER
100kΩ100kΩ
VCC/2
10
11
REFCLKN
REFCLKP
ADN2817/ADN2818
06001-021
Figure 33. Differential REFCLK Configuration
BUFFER
100kΩ100kΩ
VCC/2
10
11
REFCLKN
REFCLKP
ADN2817/ADN2818
CLK
OSC OUT
VCC
06001-022
Figure 34. Single-Ended REFCLK Configuration
BUFFER
100kΩ100kΩ
VCC/2
10
11
REFCLKN
REFCLKP
A
DN2817/ADN2818
V
CC
06001-023
Figure 35. No REFCLK Configuration
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2817/ADN2818 to lock onto data, or to measure the fre-
quency of the incoming data to within 0.01%. (There is the
capability to measure the data rate to approximately ±10%
without the use of a reference clock.) The modes are mutually
exclusive because, in the first use, the user knows exactly what
the data rate is and wants to force the part to lock onto only that
data rate; in the second use, the user does not know what the
data rate is and wants to measure it.
Lock to reference mode is enabled by writing 1 to I2C Register
Bit CTRLA[0]. Data rate readback mode is enabled by writing 1
to I2C Register Bit CTRLA[1]. Writing a 1 to both of these bits at
the same time causes an indeterminate state and is not supported.
Using the Reference Clock to Lock onto Data
Writing CTRLA[0] = 1 puts the ADN2817/ADN2818 into lock
to REFCLK (LTR) mode. In this mode, the ADN2817/ADN2818
lock onto a frequency derived from the reference clock according
to the following equation:
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The user must know exactly what the data rate is and provide
a reference clock that is a function of this rate. The ADN2817/
ADN2818 can still be used as continuous rate devices in this
configuration if a reference clock with a variable frequency is
provided (see the AN-632 Application Note).
The reference clock can be anywhere between 10 MHz and
200 MHz. By default, the ADN2817/ADN2818 expect a reference
clock of between 10 MHz and 25 MHz. If it is between 25 MHz
and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz,
the user needs to configure the ADN2817/ADN2818 to use the
correct reference frequency range by setting two bits of the
CTRLA register, CTRLA[7:6].
Table 17. CTRLA[7:6] (fREF Range) with CTRLA[5:2]
(DIV_FREF Ratio) Settings
CTRLA[7:6] Range (MHz) CTRLA[5:2] Ratio
00 10 to 25 0000 1
01 25 to 50 0001 2
10 50 to 100 n 2n
11 100 to 200 1000 256
Data Sheet ADN2817/ADN2818
Rev. F | Page 27 of 40
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_FREF and DIV_FREF represents the
divided-down reference referred to the 10 MHz to 25 MHz band.
For example, if the reference clock frequency is 38.88 MHz and
the input data rate is 622.08 Mbps, then CTRLA[7:6] is set to 01
to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2]
is set to 0101, that is, 5, because
622.08 Mbps/19.44 MHz = 25
When the CTRLA[7:2] value is correct and CTRLA[0] has been
written to a Logic 1, it is recommended that a 1-to-0 transition
be written to CTRLB[5] to initiate a new frequency acquisition
with respect to the reference clock.
In this mode, if the ADN2817/ADN2818 lose lock for any
reason, they relock onto the reference clock and continue to
output a stable clock.
Though the ADN2817/ADN2818 operate in LTR mode, if
the user ever changes the reference frequency, the fREF range
(CTRLA[7:6]), or the DIV_FREF ratio (CTRLA[5:2]), this must
be followed by writing a 1-to-0 transition into the CTRLB[5] bit
to initiate a new frequency acquisition.
A frequency acquisition can also be initiated in LTR mode by
writing a 0-to-1 transition into CTRLA[0]; however, it is rec-
ommended that a frequency acquisition be initiated by writing
a 1-to-0 transition into CTRLB[5], as explained previously.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2817/ADN2818 compare the
frequency of the incoming data to the incoming reference clock
and return a ratio of the two frequencies to 0.01% (100 ppm).
The accuracy error of the reference clock is added to the accuracy
of the ADN2817/ADN2818 data rate measurement. For example,
if a 100 ppm accuracy reference clock is used, the total accuracy
of the measurement is within 200 ppm.
The reference clock can range from 10 MHz to 200 MHz. The
ADN2817/ADN2818 expects a reference clock between 10 MHz
and 25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2817/ADN2818 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6]. Using the reference clock to determine
the frequency of the incoming data does not affect the manner
in which the part locks onto data. In this mode, the reference
clock is used only to determine the frequency of the data. For
this reason, the user does not need to know the data rate to use
the reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
1. Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2817/ADN2818.
This bit is level sensitive and does not need to be reset
to perform subsequent frequency measurements.
2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
3. Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and
the data rate can be read back on FREQ[22:0]. The time for
a data rate measurement is typically 80 ms.
4. Read back the data rate from the FREQ2[6:0], FREQ1[7:0],
and FREQ0[7:0] registers.
Use the following equation to determine the data rate:
fDATARATE = (FREQ[22..0] × fREFCLK)/2(14 + SEL_RATE) (1)
where:
FREQ[22:0] is the reading from FREQ2[6:0] (most significant
byte), FREQ1[7:0], and FREQ0[7:0] (least significant byte). See
Table 18.
fDATA R ATE is the data rate (Mbps).
fREFCLK is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
Table 18.
D22 D21:D17 D16 D15 D14:D9 D8 D7 D6:D1 D0
FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]
For example, if the reference clock frequency is 32 MHz, it falls
within the 25 MHz to 50 MHz range; therefore, the CTRLA[7:6]
setting is 01 resulting in SEL_RATE = 1. For this example, the
input data rate is 2.488 Gbps (OC-48). After following Step 1
through Step 4, the value that is read back on FREQ[22:0] =
0x26E010, which is equal to 2.5477 × 106. Plugging this value
into Equation 1 yields
((2.5477 × 106) × (32 × 106))/(2(14 + 1)) = 2.488 Gbps
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The measure-
ment process is reset by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement. Follow Step 2 through
Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 28 of 40
ADDITIONAL FEATURES AVAILABLE VIA THE I2C
INTERFACE
Coarse Data Rate Readback
The data rate can be read back over the I2C interface to
approximately ±10% without needing an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the Rate[7:0] register. The LSB of the COARSE_RD
register is Bit MISC[0].
Table 19 is a lookup table (LUT) that provides coarse data rate
readback values to within ±10%.
LOS Configuration
The LOS detector output, Pin 22 (LOS), can be configured as
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures
the LOS pin to be active low when a loss of signal condition
is detected.
Initiate Frequency Acquisition
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2817/ADN2818
in the operating mode that was previously programmed in the
CTRLA, CTRLB, CTRLC, CTRLD, and CTRLE registers.
Rate Selectivity
The ADN2817/ADN2818 can operate in a limited range mode
in situations where the user wants to restrict the data rates to
which the device can lock. In this mode, the frequency acquisition
range of the device is limited to a specific range of data rates.
The acquisition range is determined by programming an upper
and lower 9-bit code into the HI_CODE[8:1], LO_CODE[8:1],
and CODE_LSB[1:0] I2C registers. See Table 20 for a lookup table
(LUT) showing the correct register settings for each data rate.
Table 20 has three columns: code, high limit, and low limit. The
user programs the code value for the high limit data rate into
HI_CODE and the code value for the low limit data rate into
LO_CODE to set the appropriate range.
For example, if the user wants to limit the acquisition range of
the ADN2817/ADN2818 to lock between 1 Gbps and 1.25 Gbps,
the following steps must be taken:
1. Find the first code in Table 20 that corresponds to a data
rate below 1.0 Gbps in the low limit column, that is, Code 236
or 011101100b. Set LO_CODE[8:1] = 01110110b
(LO_CODE[0] is set in Register Bit CODE_LSB[0].)
2. Find the first code in Table 20 that corresponds to a data
rate above 1.25 Gbps in the high limit column, that is,
Code 258 or 100000010b. Set HI_CODE[8:1] = 10000001b
(HI_CODE[0] is set in Register Bit CODE_LSB[1].)
3. Set CODE_LSB = 00000000b given that the HI_CODE[0]
= 0 and LO_CODE[0] = 0.
4. Set SEL_MODE[3] = 1.
5. When there is a valid input to the device between 1.0 Gbps
and 1.25 Gbps, write a 1-to-0 transition into CTRLB[5] to
initiate a new frequency acquisition.
Double Data Rate Mode
Setting CTRLE = 0x02 puts the ADN2817/ADN2818 clock
output through divide-by-two circuitry allowing direct
interfacing to FPGAs that support data clocking on both
rising and falling edges.
PRBS Generator/Detector
The ADN2817/ADN2818 have an integrated PRBS generator/
detector for system testing purposes. The devices are configurable
as either a PRBS detector or a PRBS generator. The two functions
cannot be used at the same time.
The following steps configure the PRBS detector (PRBS 7 only):
1. Set CTRLE[2:0] = 0x5.
2. Set CTRLD[2:0] = 0x4 to enable the PRBS detector.
The PRBS error signal outputs on the DATAOUTP/DATAOUTN
pins. Every time the PRBS detector detects an error, the
DATAOUTP/DATAOUTN outputs pulse twice to a Logic 1,
that is, DATAOUTP = 1, DATAOUTN = 0.
The following steps configure the PRBS generator (PRBS 7 only):
1. Set CTRLE[2:0] = 0x5.
2. Set CTRLD[2:0] = 0x1 to enable the PRBS generator.
3. Write a 1-to-0 transition into CTRLD[3] to initiate a
PRBS 7 pattern.
Note that the PRBS generator is clocked by the VCO; therefore,
the user needs to feed in a clock at half the desired frequency.
For example, for an OC-48 PRBS pattern, input a 1.244 GHz
clock to PIN/NIN. This appears as a 2.488 Gbps NRZ data
pattern to the ADN2817/ADN2818. The recovered clock is
2.488 GHz, which clocks the PRBS generator to produce an
OC-48 PRBS pattern on the outputs.
Data Sheet ADN2817/ADN2818
Rev. F | Page 29 of 40
CLK Holdover Mode
This mode of operation is available in LTD mode. In CLK
holdover mode, the output clock frequency remains within
±5% if the input data is removed or changed. To operate in
this mode, the user writes to the I2C to put the part into CLK
holdover mode by setting SEL_MODE[1] = 1. The user must
then initiate a frequency acquisition by writing a 1-to-0 transi-
tion into CTRLB[5], at which time the device locks onto the
input data rate. At this point, the output frequency remains
within ±5% of the initial acquired value regardless of whether
the input data is removed or the data rate changes.
It is important to note that all frequency acquisitions in this
mode must be initiated by writing a 1-to-0 transition into
CTRLB[5]. In this mode, the device does not automatically
initiate a new frequency acquisition when the input is momen-
tarily interrupted or if the input data rate changes.
CDR Bypass Mode
The CDR on the ADN2817/ADN2818 can be bypassed by setting
Bit CTRLD[7] = 1. In this mode, the ADN2817/ADN2818 feed
the input directly through the input amplifiers to the output
buffer, completely bypassing the CDR.
Disable Output Buffers
The ADN2817/ADN2818 provide the option of disabling the
output buffers for power savings. The clock output buffers
can be disabled by setting Bit CTRLD[5] = 1. This reduces
the total power consumption of the device by approximately
100 mW. For an additional 100 mW power savings, such as in
low power standby mode, the data output buffers can also be
disabled by setting Bit CTRLD[6] = 1.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 30 of 40
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
For best practice, the use of one low impedance ground plane is
recommended. To reduce series inductance, solder the VEE pins
directly to the ground plane. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. Connect the exposed pad to the ground
plane using plugged vias so that solder does not leak through
the vias during reflow.
Use of a 10 µF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply (VCC and VEE),
as close as possible to the ADN2817/ADN2818 VCC pins.
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/DATAOUTN
output buffers. See the schematic in Figure 36 for recommended
connections.
By using adjacent power supply and ground planes, excellent
high frequency decoupling can be realized by using close
spacing between the planes. This capacitance is given by
CPLANE = 0.88εr A/d (pF)
where:
ε
r is the dielectric constant of the PCB material.
A is the area of the overlap of power and ground planes (cm2).
d is the separation between planes (mm).
For FR-4, εr = 4.4 and 0.25 mm spacing, C ≈ 15 pF/cm2.
VBER
32
VCC
31
VEE
30
DATAOUTP
29
DATAOUTN
28
SQUELCH
27
CLKOUTP
26
CLKOUTN
25
THRADJ
R
TH
9
REFCLKP
10
REFCLKN
11
VCC
12
VEE
13
CF2
14
CF1
15
LOL
16
BERMODE
1
VCC
2
VREF
3
NIN
4
PIN
5
SLICEP
6
SLICEN
7
VEE
8
VCC
24
VEE
23
LOS
22
SDA
21
SCK
EXPOSED PAD
TIED OFF TO VEE
PLANE WITH V IAS.
20
SADDR5
19
VCC
18
VEE
17
ADN2817/
ADN2818
TOP VIEW
(No t t o Scal e)
1nF0.1µF
VCC
0.47µ F +20%
>300MΩ
INSULATION RESISTANCE
µC
I
2
C CONTROLLER
µC
VCC
VCC
1nF 0.1µF
1nF 0.1µF
C
IN
VCC
TIA
50Ω
50Ω
1nF0.1µF
0.1µF
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
50Ω TRANSMISSION
LINES
VCC
4 × 100Ω
1nF
0.1µF
+
VCC
10µF
06001-025
10kΩ
10kΩ
Figure 36. Typical ADN2817/ADN2818 Applications Circuit
Data Sheet ADN2817/ADN2818
Rev. F | Page 31 of 40
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also
REFCLKP, REFCLKN, if using a high frequency reference clock,
such as 155 MHz). It is also necessary for the PIN/NIN input
traces to be matched in length, and the CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN output traces to be matched
in length to avoid skew between the differential traces.
All high speed CML outputs (CLKOUTP, CLKOUTN, DATAOUTP,
and DATAOUTN) require 100 Ω back termination chip resis-
tors connected between the output pin and VCC. Place these
resistors as close as possible to the output pins. These 100 Ω
resistors are in parallel with on-chip 100 Ω termination resistors
to create a 50 Ω back termination (see Figure 37).
The high speed inputs (PIN and NIN) are internally terminated
with 50 Ω to an internal reference voltage (see Figure 38). A 0.1 μF
capacitor is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
50Ω
50Ω
V
TERM
V
TERM
50Ω
0.1µF
0.1µF
100Ω100Ω
VCC
100Ω100Ω
VCC
ADN2817/ADN2818
0
6001-026
Figure 37. Typical ADN2817/ADN2818 Applications Circuit
50Ω
50Ω
50Ω
2.5V
ADN2817/ADN2818
VCC
TIA
C
IN
C
IN
PIN
NIN
3kΩ
VREF
0.1µF
TIA
06001-027
Figure 38. ADN2817/ADN2818 AC-Coupled Input Configuration
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width. Center the land on the pad to ensure that the solder joint
size is maximized. The bottom of the lead frame chip scale package
has a central exposed pad. The pad on the printed circuit board
should be at least as large as this exposed pad. The user must
connect the exposed pad to VEE using plugged vias to prevent
solder from leaking through the vias during reflow. This ensures a
solid connection from the exposed pad to VEE.
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2817/ADN2818
must be chosen such that the device works properly over the
full range of data rates used in the application. When choosing
the capacitors, the time constant formed with the two 50 Ω
resistors in the signal path must be considered. When a large
number of consecutive identical digits (CIDs) are applied, the
capacitor voltage can droop due to baseline wander (see Figure 39),
causing pattern dependent jitter (PDJ).
The user must determine how much droop is tolerable and choose
an ac coupling capacitor based on that amount of droop. The
amount of PDJ can then be approximated based on the capacitor
selection. The actual capacitor value selection may require some
trade-offs between droop and PDJ.
For example, assuming that 2% droop can be tolerated, the
maximum differential droop is 4%. Normalizing to peak-to-
peak voltage,
Droop = Δ V = 0.04 V = 0.5 V p-p (1 − e–t/τ) ; therefore, τ = 12t
where:
τ is the RC time constant (C is the ac coupling capacitor, and
R = 100 Ω seen by C).
t is the total discharge time, which is equal to n
.
n is the number of CIDs.
T is the bit period.
Calculate the capacitor value by combining the equations
for τ and t.
C = 12nT/R
When the capacitor value is selected, the PDJ can be
approximated as
PDJps p-p = 0.5tr(1 − e(−nT/RC))/0.6
where:
PDJps p-p is the amount of pattern-dependent jitter allowed;
<0.01 UI p-p typical.
tr is the rise time, which is equal to 0.22/BW, where BW ≈ 0.7
(bit rate).
Note that this expression for tr is accurate only for the inputs.
The output rise time for the ADN2817/ADN2818 is
approximately 100 ps regardless of data rate.
ADN2817/ADN2818 Data Sheet
Rev. F | Page 32 of 40
NOTES
1. DURING THE DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF
LEVEL WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE
INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER
HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER DOES NOT
RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2817. THE
QUANTIZER RECOGNIZES BOTH HIGH AND LOW STATES AT THIS POINT.
V1
V1b
V2
V2b
VDIFF
VDIFF = V2 – V2b
VTH = ADN2817 QUANTIZER THRESHOLD
2341
VREF
VTH
CDR
LIMAMP
V
REF
50Ω
50Ω
PIN
NIN
ADN2817
C
OUT
DATAOUTP
DATAOUTN
C
IN
V2
V2b
V1
V1b
TIA
V
C
C
06001-028
Figure 39. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2817/ADN2818 can also be dc-coupled.
This can be necessary in burst mode applications with long periods
of CIDs and where baseline wander cannot be tolerated. If the
inputs to the ADN2817/ADN2818 are dc-coupled, care must be
taken not to violate the input range and common-mode level
requirements of the ADN2817/ADN2818 (see Figure 40 through
Figure 42). If dc coupling is required, and the output levels of
the TIA do not adhere to the levels shown in Figure 41, level
shifting and/or attenuation must occur between the TIA
outputs and the ADN2817/ADN2818 inputs.
50Ω
50Ω
50Ω
2.5V
ADN2817/ADN2818
VCC
TIA
PIN
NIN
3kΩ
VREF
0.1µF
TIA
06001-029
Figure 40. DC-Coupled Application
PIN
INPUT (V)
V p-p = PIN – NIN = 2 × V
SE
= 10mV AT SENSITIVITY
V
SE
= 5mV MIN
V
CM
= 2.3V MIN
(DC-COUPLED)
NIN
06001-030
Figure 41. Minimum Allowed DC-Coupled Input Levels
PIN
INPUT (V)
V p-p = PIN – NIN = 2 × V
SE
= 2.0V MAX
V
SE
= 1.0V MAX
V
CM
= 2.3V
(DC-COUPLED)
NIN
06001-031
Figure 42. Maximum Allowed DC-Coupled Input Levels
Data Sheet ADN2817/ADN2818
Rev. F | Page 33 of 40
COARSE DATA RATE READBACK LOOKUP TABLE
Code is the 9-bit value read back from COARSE_RD[8:0].
Table 19. Coarse Data Rate Readback Look-Up Table
Code fMID (Hz)
0 5.3205 × 106
1
5.3202 × 10
6
2 5.4294 × 106
3 5.5473 × 106
4 5.6735 × 106
5 5.8086 × 106
6
5.9533 × 106
7 6.1087 × 106
8 6.2771 × 106
9 6.4716 × 106
10 6.6702 × 106
11 6.8884 × 106
12
7.1269 × 10
6
13 7.3889 × 106
14 7.6789 × 106
15 7.9990 × 106
16 7.6264 × 106
17 7.6263 × 106
18 7.7893 × 106
19 7.9650 × 106
20 8.1539 × 106
21 8.3566 × 106
22 8.5749 × 106
23
8.8103 × 10
6
24 9.0650 × 106
25 9.3584 × 106
26 9.6606 × 106
27 9.9906 × 106
28 10.3514 × 106
29 10.7475 × 106
30 11.1821 × 106
31 11.6571 × 106
32 10.6409 × 106
33 10.6403 × 106
34
10.8588 × 106
35 11.0945 × 106
36 11.3469 × 106
37 11.6173 × 106
38 11.9065 × 106
39 12.2174 × 106
40 12.5543 × 106
41 12.9432 × 106
42 13.3403 × 106
43 13.7767 × 106
44 14.2539 × 106
45 14.7778 × 106
46 15.3577 × 106
47 15.9980 × 106
48 15.2529 × 106
Code fMID (Hz)
49 15.2526 × 106
50
15.5785 × 10
6
51 15.9300 × 106
52 16.3078 × 106
53 16.7133 × 106
54 17.1498 × 106
55
17.6205 × 106
56 18.1300 × 106
57 18.7169 × 106
58 19.3212 × 106
59 19.9811 × 106
60 20.7027 × 106
61
21.4950 × 10
6
62 22.3642 × 106
63 23.3143 × 106
64 21.2818 × 106
65 21.2806 × 106
66 21.7177 × 106
67 22.1891 × 106
68 22.6939 × 106
69 23.2346 × 106
70 23.8130 × 106
71 24.4348 × 106
72
25.1085 × 10
6
73 25.8864 × 106
74 26.6807 × 106
75 27.5535 × 106
76 28.5078 × 106
77 29.5555 × 106
78 30.7155 × 106
79 31.9959 × 106
80 30.5057 × 106
81 30.5052 × 106
82 31.1570 × 106
83
31.8599 × 106
84 32.6155 × 106
85 33.4265 × 106
86 34.2996 × 106
87 35.2411 × 106
88 36.2600 × 106
89 37.4338 × 106
90 38.6424 × 106
91 39.9623 × 106
92 41.4055 × 106
93 42.9900 × 106
94 44.7284 × 106
95 46.6285 × 106
96 42.5637 × 106
97 42.5613 × 106
Code fMID (Hz)
98 43.4353 × 106
99
44.3782 × 10
6
100 45.3877 × 106
101 46.4691 × 106
102 47.6260 × 106
103 48.8696 × 106
104
50.2170 × 106
105 51.7728 × 106
106 53.3614 × 106
107 55.1069 × 106
108 57.0156 × 106
109 59.1111 × 106
110
61.4309 × 10
6
111 63.9919 × 106
112 61.0114 × 106
113 61.0103 × 106
114 62.3141 × 106
115 63.7198 × 106
116 65.2310 × 106
117 66.8530 × 106
118 68.5992 × 106
119 70.4821 × 106
120 72.5199 × 106
121
74.8675 × 10
6
122 77.2849 × 106
123 79.9245 × 106
124 82.8109 × 106
125 85.9801 × 106
126 89.4567 × 106
127 93.2571 × 106
128 85.1274 × 106
129 85.1226 × 106
130 86.8707 × 106
131 88.7564 × 106
132
90.7755 × 106
133 92.9383 × 106
134 95.2521 × 106
135 97.7392 × 106
136 100.4340 × 106
137 103.5457 × 106
138 106.7228 × 106
139 110.2139 × 106
140 114.0312 × 106
141 118.2222 × 106
142 122.8619 × 106
143 127.9838 × 106
144 122.0229 × 106
145 122.0206 × 106
146 124.6282 × 106
Code fMID (Hz)
147 127.4396 × 106
148
130.4620 × 10
6
149 133.7061 × 106
150 137.1983 × 106
151 140.9643 × 106
152 145.0399 × 106
153
149.7350 × 106
154 154.5698 × 106
155 159.8491 × 106
156 165.6218 × 106
157 171.9601 × 106
158 178.9134 × 106
159
186.5142 × 10
6
160 170.2547 × 106
161 170.2451 × 106
162 173.7413 × 106
163 177.5128 × 106
164 181.5509 × 106
165 185.8765 × 106
166 190.5041 × 106
167 195.4784 × 106
168 200.8681 × 106
169 207.0913 × 106
170
213.4455 × 10
6
171 220.4277 × 106
172 228.0624 × 106
173 236.4443 × 106
174 245.7237 × 106
175 255.9676 × 106
176 244.0458 × 106
177 244.0412 × 106
178 249.2563 × 106
179 254.8792 × 106
180 260.9240 × 106
181
267.4122 × 106
182 274.3966 × 106
183 281.9286 × 106
184 290.0798 × 106
185 299.4700 × 106
186 309.1396 × 106
187 319.6981 × 106
188 331.2437 × 106
189 343.9202 × 106
190 357.8269 × 106
191 373.0284 × 106
192 340.5094 × 106
193 340.4903 × 106
194 347.4826 × 106
195 355.0256 × 106
ADN2817/ADN2818 Data Sheet
Rev. F | Page 34 of 40
Code fMID (Hz)
196 363.1019 × 106
197 371.7531 × 106
198 381.0083 × 106
199 390.9568 × 106
200
401.7362 × 106
201 414.1826 × 106
202 426.8911 × 106
203 440.8554 × 106
204 456.1247 × 106
205 472.8887 × 106
206
491.4474 × 10
6
207 511.9351 × 106
208 488.0916 × 106
209 488.0824 × 106
210 498.5126 × 106
211 509.7584 × 106
212 521.8480 × 106
213 534.8244 × 106
214 548.7933 × 106
215 563.8571 × 106
216 580.1596 × 106
217
598.9401 × 106
218 618.2792 × 106
Code fMID (Hz)
219 639.3962 × 106
220 662.4874 × 106
221 687.8404 × 106
222 715.6537 × 106
223
746.0568 × 106
224 681.0188 × 106
225 680.9806 × 106
226 694.9652 × 106
227 710.0511 × 106
228 726.2037 × 106
229
743.5062 × 10
6
230 762.0166 × 106
231 781.9136 × 106
232 803.4724 × 106
233 828.3653 × 106
234 853.7822 × 106
235 881.7109 × 106
236 912.2494 × 106
237 945.7774 × 106
238 982.8948 × 106
239 1.0239 × 109
240
976.1832 × 106
241 976.1648 × 106
Code fMID (Hz)
242 997.0253 × 106
243 1.0195 × 109
244 1.0437 × 109
245 1.0696 × 109
246
1.0976 × 109
247 1.1277 × 109
248 1.1603 × 109
249 1.1979 × 109
250 1.2366 × 109
251 1.2788 × 109
252
1.3250 × 10
9
253 1.3757 × 109
254 1.4313 × 109
255 1.4921 × 109
256 1.3620 × 109
257 1.3620 × 109
258 1.3899 × 109
259 1.4201 × 109
260 1.4524 × 109
261 1.4870 × 109
262 1.5240 × 109
263
1.5638 × 109
264 1.6069 × 109
Code fMID (Hz)
265 1.6567 × 109
266 1.7076 × 109
267 1.7634 × 109
268 1.8245 × 109
269
1.8916 × 109
270 1.9658 × 109
271 2.0477 × 109
272 1.9524 × 109
273 1.9523 × 109
274 1.9941 × 109
275
2.0390 × 10
9
276 2.0874 × 109
277 2.1393 × 109
278 2.1952 × 109
279 2.2554 × 109
280 2.3206 × 109
281 2.3958 × 109
282 2.4731 × 109
283 2.5576 × 109
284 2.6499 × 109
285 2.7514 × 109
286
2.8626 × 109
287 2.9842 × 109
Data Sheet ADN2817/ADN2818
Rev. F | Page 35 of 40
HI_CODE AND LO_CODE LOOKUP TABLE
Code is the 9-bit value to be written into HI_CODE[8:0] and LO_CODE[8:0]. Use the high limit code for HI_CODE and the low limit
code for LO_CODE.
Table 20.
Code Low Limit High Limit
0
5.7633 × 106
4.8677 × 106
1 5.7631 × 106 4.8674 × 106
2 5.8777 × 106 4.9708 × 106
3 6.0011 × 106 5.0827 × 106
4 6.1328 × 106 5.2027 × 106
5 6.2738 × 106 5.3312 × 106
6 6.4245 × 106 5.4692 × 106
7 6.5859 × 106 5.6188 × 106
8 6.7593 × 106 5.7807 × 106
9 6.9599 × 106 5.9680 × 106
10 7.1641 × 106 6.1614 × 106
11
7.3860 × 106
6.3740 × 106
12 7.6292 × 106 6.6070 × 106
13 7.8947 × 106 6.8660 × 106
14 8.1855 × 106 7.1541 × 106
15 8.5061 × 106 7.4742 × 106
16 8.2705 × 106 6.9705 × 106
17
8.2701 × 10
6
6.9703 × 10
6
18 8.4414 × 106 7.1241 × 106
19 8.6260 × 106 7.2904 × 106
20 8.8239 × 106 7.4696 × 106
21 9.0356 × 106 7.6624 × 106
22
9.2629 × 106
7.8705 × 106
23 9.5073 × 106 8.0958 × 106
24 9.7707 × 106 8.3404 × 106
25 10.0733 × 106 8.6236 × 106
26 10.3832 × 106 8.9165 × 106
27 10.7202 × 106 9.2377 × 106
28
11.0869 × 10
6
9.5915 × 10
6
29 11.4873 × 106 9.9825 × 106
30 11.9244 × 106 10.4145 × 106
31 12.3996 × 106 10.8902 × 106
32 11.5265 × 106 9.7355 × 106
33 11.5261 × 106 9.7347 × 106
34 11.7554 × 106 9.9415 × 106
35 12.0022 × 106 10.1654 × 106
36 12.2655 × 106 10.4053 × 106
37 12.5475 × 106 10.6624 × 106
38 12.8490 × 106 10.9384 × 106
39
13.1718 × 10
6
11.2376 × 10
6
40 13.5186 × 106 11.5615 × 106
41 13.9198 × 106 11.9360 × 106
42 14.3282 × 106 12.3228 × 106
43 14.7719 × 106 12.7480 × 106
44 15.2584 × 106 13.2140 × 106
45 15.7894 × 106 13.7321 × 106
46 16.3711 × 106 14.3081 × 106
47 17.0122 × 106 14.9484 × 106
Code Low Limit High Limit
48
16.5410 × 106
13.9411 × 106
49 16.5402 × 106 13.9407 × 106
50 16.8827 × 106 14.2483 × 106
51 17.2521 × 106 14.5807 × 106
52 17.6479 × 106 14.9392 × 106
53 18.0712 × 106 15.3247 × 106
54 18.5258 × 106 15.7411 × 106
55 19.0145 × 106 16.1915 × 106
56 19.5415 × 106 16.6807 × 106
57 20.1465 × 106 17.2471 × 106
58 20.7665 × 106 17.8330 × 106
59
21.4403 × 106
18.4754 × 106
60 22.1738 × 106 19.1829 × 106
61 22.9747 × 106 19.9651 × 106
62 23.8487 × 106 20.8291 × 106
63 24.7993 × 106 21.7805 × 106
64 23.0530 × 106 19.4710 × 106
65
23.0523 × 10
6
19.4695 × 10
6
66 23.5108 × 106 19.8831 × 106
67 24.0044 × 106 20.3308 × 106
68 24.5310 × 106 20.8107 × 106
69 25.0951 × 106 21.3248 × 106
70
25.6980 × 106
21.8768 × 106
71 26.3436 × 106 22.4751 × 106
72 27.0373 × 106 23.1230 × 106
73 27.8396 × 106 23.8720 × 106
74 28.6564 × 106 24.6457 × 106
75 29.5438 × 106 25.4960 × 106
76
30.5167 × 10
6
26.4281 × 10
6
77 31.5787 × 106 27.4641 × 106
78 32.7422 × 106 28.6162 × 106
79 34.0244 × 106 29.8968 × 106
80 33.0819 × 106 27.8821 × 106
81 33.0805 × 106 27.8813 × 106
82 33.7655 × 106 28.4965 × 106
83 34.5041 × 106 29.1615 × 106
84 35.2957 × 106 29.8783 × 106
85 36.1424 × 106 30.6494 × 106
86 37.0517 × 106 31.4822 × 106
87
38.0290 × 10
6
32.3831 × 10
6
88 39.0830 × 106 33.3615 × 106
89 40.2930 × 106 34.4942 × 106
90 41.5329 × 106 35.6659 × 106
91 42.8807 × 106 36.9508 × 106
92 44.3477 × 106 38.3658 × 106
93 45.9493 × 106 39.9301 × 106
94 47.6975 × 106 41.6582 × 106
95 49.5986 × 106 43.5610 × 106
ADN2817/ADN2818 Data Sheet
Rev. F | Page 36 of 40
Code Low Limit High Limit
96 46.1061 × 106 38.9419 × 106
97 46.1045 × 106 38.9390 × 106
98 47.0217 × 106 39.7661 × 106
99 48.0087 × 106 40.6617 × 106
100
49.0620 × 106
41.6214 × 106
101 50.1902 × 106 42.6496 × 106
102 51.3960 × 106 43.7535 × 106
103 52.6872 × 106 44.9502 × 106
104 54.0746 × 106 46.2459 × 106
105 55.6792 × 106 47.7440 × 106
106
57.3128 × 10
6
49.2913 × 10
6
107 59.0876 × 106 50.9920 × 106
108 61.0334 × 106 52.8561 × 106
109 63.1575 × 106 54.9282 × 106
110 65.4843 × 106 57.2324 × 106
111 68.0487 × 106 59.7936 × 106
112 66.1639 × 106 55.7643 × 106
113 66.1609 × 106 55.7626 × 106
114 67.5309 × 106 56.9931 × 106
115 69.0082 × 106 58.3229 × 106
116 70.5914 × 106 59.7566 × 106
117
72.2848 × 106
61.2989 × 106
118 74.1034 × 106 62.9643 × 106
119 76.0580 × 106 64.7662 × 106
120 78.1660 × 106 66.7230 × 106
121 80.5861 × 106 68.9885 × 106
122 83.0658 × 106 71.3318 × 106
123
85.7613 × 10
6
73.9016 × 10
6
124 88.6953 × 106 76.7317 × 106
125 91.8987 × 106 79.8603 × 106
126 95.3950 × 106 83.3164 × 106
127 99.1972 × 106 87.1220 × 106
128 92.2121 × 106 77.8839 × 106
129 92.2090 × 106 77.8780 × 106
130 94.0434 × 106 79.5323 × 106
131 96.0174 × 106 81.3234 × 106
132 98.1240 × 106 83.2427 × 106
133 100.3804 × 106 85.2993 × 106
134
102.7920 × 10
6
87.5071 × 10
6
135 105.3744 × 106 89.9004 × 106
136 108.1491 × 106 92.4919 × 106
137 111.3583 × 106 95.4879 × 106
138 114.6257 × 106 98.5827 × 106
139 118.1753 × 106 101.9841 × 106
140 122.0668 × 106 105.7122 × 106
141 126.3150 × 106 109.8565 × 106
142 130.9686 × 106 114.4648 × 106
143 136.0974 × 106 119.5872 × 106
144 132.3278 × 106 111.5286 × 106
145
132.3218 × 106
111.5252 × 106
146 135.0619 × 106 113.9862 × 106
147 138.0164 × 106 116.6459 × 106
148 141.1829 × 106 119.5132 × 106
Code Low Limit High Limit
149 144.5697 × 106 122.5977 × 106
150 148.2068 × 106 125.9286 × 106
151 152.1160 × 106 129.5324 × 106
152 156.3320 × 106 133.4459 × 106
153
161.1721 × 106
137.9770 × 106
154 166.1317 × 106 142.6637 × 106
155 171.5227 × 106 147.8032 × 106
156 177.3906 × 106 153.4634 × 106
157 183.7974 × 106 159.7205 × 106
158 190.7899 × 106 166.6328 × 106
159
198.3944 × 10
6
174.2440 × 10
6
160 184.4242 × 106 155.7678 × 106
161 184.4181 × 106 155.7560 × 106
162 188.0868 × 106 159.0645 × 106
163 192.0348 × 106 162.6467 × 106
164 196.2480 × 106 166.4855 × 106
165 200.7608 × 106 170.5985 × 106
166 205.5841 × 106 175.0142 × 106
167 210.7488 × 106 179.8008 × 106
168 216.2983 × 106 184.9838 × 106
169 222.7166 × 106 190.9759 × 106
170
229.2514 × 106
197.1654 × 106
171 236.3506 × 106 203.9681 × 106
172 244.1336 × 106 211.4245 × 106
173 252.6300 × 106 219.7129 × 106
174 261.9373 × 106 228.9296 × 106
175 272.1948 × 106 239.1744 × 106
176
264.6556 × 10
6
223.0571 × 10
6
177 264.6437 × 106 223.0505 × 106
178 270.1237 × 106 227.9723 × 106
179 276.0329 × 106 233.2917 × 106
180 282.3657 × 106 239.0265 × 106
181 289.1393 × 106 245.1954 × 106
182 296.4136 × 106 251.8572 × 106
183 304.2321 × 106 259.0647 × 106
184 312.6640 × 106 266.8919 × 106
185 322.3443 × 106 275.9539 × 106
186 332.2633 × 106 285.3273 × 106
187
343.0453 × 10
6
295.6065 × 10
6
188 354.7812 × 106 306.9268 × 106
189 367.5947 × 106 319.4411 × 106
190 381.5798 × 106 333.2656 × 106
191 396.7887 × 106 348.4879 × 106
192 368.8485 × 106 311.5355 × 106
193 368.8362 × 106 311.5120 × 106
194 376.1735 × 106 318.1291 × 106
195 384.0696 × 106 325.2934 × 106
196 392.4961 × 106 332.9710 × 106
197 401.5216 × 106 341.1971 × 106
198
411.1681 × 106
350.0283 × 106
199 421.4977 × 106 359.6016 × 106
200 432.5966 × 106 369.9675 × 106
201 445.4332 × 106 381.9518 × 106
Data Sheet ADN2817/ADN2818
Rev. F | Page 37 of 40
Code Low Limit High Limit
202 458.5027 × 106 394.3307 × 106
203 472.7012 × 106 407.9363 × 106
204 488.2673 × 106 422.8489 × 106
205 505.2599 × 106 439.4259 × 106
206
523.8745 × 106
457.8593 × 106
207 544.3897 × 106 478.3487 × 106
208 529.3112 × 106 446.1142 × 106
209 529.2874 × 106 446.1009 × 106
210 540.2475 × 106 455.9446 × 106
211 552.0658 × 106 466.5834 × 106
212
564.7314 × 10
6
478.0529 × 10
6
213 578.2786 × 106 490.3908 × 106
214 592.8272 × 106 503.7145 × 106
215 608.4642 × 106 518.1295 × 106
216 625.3279 × 106 533.7838 × 106
217 644.6885 × 106 551.9079 × 106
218 664.5266 × 106 570.6547 × 106
219 686.0907 × 106 591.2129 × 106
220 709.5624 × 106 613.8536 × 106
221 735.1895 × 106 638.8822 × 106
222 763.1596 × 106 666.5311 × 106
223
793.5774 × 106
696.9759 × 106
224 737.6969 × 106 623.0711 × 106
225 737.6724 × 106 623.0240 × 106
226 752.3471 × 106 636.2582 × 106
227 768.1392 × 106 650.5869 × 106
228 784.9921 × 106 665.9419 × 106
229
803.0432 × 10
6
682.3941 × 10
6
230 822.3363 × 106 700.0567 × 106
231 842.9953 × 106 719.2032 × 106
232 865.1931 × 106 739.9350 × 106
233 890.8664 × 106 763.9035 × 106
234 917.0055 × 106 788.6615 × 106
235 945.4024 × 106 815.8726 × 106
236 976.5346 × 106 845.6979 × 106
237 1.0105 × 109 878.8518 × 106
238 1.0477 × 109 915.7186 × 106
239 1.0888 × 109 956.6975 × 106
240
1.0586 × 10
9
892.2284 × 10
6
241 1.0586 × 109 892.2018 × 106
242 1.0805 × 109 911.8893 × 106
243 1.1041 × 109 933.1668 × 106
244 1.1295 × 109 956.1059 × 106
245 1.1566 × 109 980.7817 × 106
246 1.1857 × 109 1.0074 × 109
Code Low Limit High Limit
247 1.2169 × 109 1.0363 × 109
248 1.2507 × 109 1.0676 × 109
249 1.2894 × 109 1.1038 × 109
250 1.3291 × 109 1.1413 × 109
251
1.3722 × 109
1.1824 × 109
252 1.4191 × 109 1.2277 × 109
253 1.4704 × 109 1.2778 × 109
254 1.5263 × 109 1.3331 × 109
255 1.5872 × 109 1.3940 × 109
256 1.4754 × 109 1.2461 × 109
257
1.4753 × 10
9
1.2460 × 10
9
258 1.5047 × 109 1.2725 × 109
259 1.5363 × 109 1.3012 × 109
260 1.5700 × 109 1.3319 × 109
261 1.6061 × 109 1.3648 × 109
262 1.6447 × 109v 1.4001 × 109
263 1.6860 × 109 1.4384 × 109
264 1.7304 × 109 1.4799 × 109
265 1.7817 × 109 1.5278 × 109
266 1.8340 × 109 1.5773 × 109
267 1.8908 × 109 1.6317 × 109
268
1.9531 × 109
1.6914 × 109
269 2.0210 × 109 1.7577 × 109
270 2.0955 × 109 1.8314 × 109
271 2.1776 × 109 1.9134 × 109
272 2.1172 × 109 1.7845 × 109
273 2.1171 × 109 1.7844 × 109
274
2.1610 × 10
9
1.8238 × 10
9
275 2.2083 × 109 1.8663 × 109
276 2.2589 × 109 1.9122 × 109
277 2.3131 × 109 1.9616 × 109
278 2.3713 × 109 2.0149 × 109
279 2.4339 × 109 2.0725 × 109
280 2.5013 × 109 2.1351 × 109
281 2.5788 × 109 2.2076 × 109
282 2.6581 × 109 2.2826 × 109
283 2.7444 × 109 2.3649 × 109
284 2.8382 × 109 2.4554 × 109
285
2.9408 × 10
9
2.5555 × 10
9
286 3.0526 × 109 2.6661 × 109
287 3.1743 × 109 2.7879 × 109
ADN2817/ADN2818 Data Sheet
Rev. F | Page 38 of 40
OUTLINE DIMENSIONS
COM P LIANT T O JEDEC S TANDARDS M O-220- WHHD.
1
0.50
BSC
3.50 REF
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
32
9
16
17
24
25
8
EXPOSED
PAD
PIN 1
INDICATOR
3.65
3.50 SQ
3.45
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70 FOR P ROPE R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 M IN
04-02-2012-A
Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity
ADN2817ACPZ −40°C to +85°C 32-Lead LFCSP CP-32-11 490
ADN2817ACPZ-RL −40°C to +85°C 32-Lead LFCSP, 13” Tape and Reel CP-32-11 5,000
ADN2817ACPZ-RL7 −40°C to +85°C 32-Lead LFCSP, 7” Tape and Reel CP-32-11 1,500
ADN2818ACPZ −40°C to +85°C 32-Lead LFCSP CP-32-11 490
ADN2818ACPZ-RL −40°C to +85°C 32-Lead LFCSP, 13” Tape and Reel CP-32-11 5,000
ADN2818ACPZ-RL7 −40°C to +85°C 32-Lead LFCSP, 7” Tape and Reel CP-32-11 1,500
EVAL-ADN2817EBZ Evaluation Board for ADN2817
EVAL-ADN2818EBZ Evaluation Board for ADN2818
1 Z = RoHS Compliant Part.
Data Sheet ADN2817/ADN2818
Rev. F | Page 39 of 40
NOTES
ADN2817/ADN2818 Data Sheet
Rev. F | Page 40 of 40
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06001-0-12/15(F)
