PIC32MX330/350/370/430/450/470 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog Operating Conditions: 2.3V to 3.6V Timers/Output Compare/Input Capture * -40C to +105C (DC to 80 MHz) * -40C to +85C (DC to 100 MHz) * 0C to +70C (DC to 120 MHz) * Five General Purpose Timers: - Five 16-bit and up to two 32-bit Timers/Counters * Five Output Compare (OC) modules * Five Input Capture (IC) modules * Peripheral Pin Select (PPS) to allow function remap * Real-Time Clock and Calendar (RTCC) module Core: 120 MHz/150 DMIPS MIPS32(R) M4K(R) * MIPS16e(R) mode for up to 40% smaller code size * Code-efficient (C and Assembly) architecture * Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Clock Management * * * * * 0.9% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer Fast wake-up and start-up Power Management * Low-power management modes (Sleep and Idle) * Integrated Power-on Reset, Brown-out Reset, and High Voltage Detect * 0.5 mA/MHz dynamic current (typical) * 50 A IPD current (typical) Audio/Graphics/Touch HMI Features * * * * External graphics interface with up to 34 PMP pins Audio data communication: I2S, LJ, RJ, USB Audio data control interface: SPI and I2C Audio data master clock: - Generation of fractional clock frequencies - Can be synchronized with USB clock - Can be tuned in run-time * Charge Time Measurement Unit (CTMU): - Supports mTouchTM capacitive touch sensing - Provides high-resolution time measurement (1 ns) Advanced Analog Features * ADC Module: - 10-bit 1 Msps rate with one Sample and Hold (S&H) - Up to 28 analog inputs - Can operate during Sleep mode * Flexible and independent ADC trigger sources * On-chip temperature measurement capability * Comparators: - Two dual-input Comparator modules - Programmable references with 32 voltage points Communication Interfaces * USB 2.0-compliant Full-speed OTG controller * Up to five UART modules (20 Mbps): - LIN 2.1 protocols and IrDA(R) support * Two 4-wire SPI modules (25 Mbps) * Two I2C modules (up to 1 Mbaud) with SMBus support * PPS to allow function remap * Parallel Master Port (PMP) Direct Memory Access (DMA) * Four channels of hardware DMA with automatic data size detection * 32-bit Programmable Cyclic Redundancy Check (CRC) * Two additional channels dedicated to USB Input/Output * 15 mA or 12 mA source/sink for standard VOH/VOL and up to 22 mA for non-standard VOH1 * 5V-tolerant pins * Selectable open drain, pull-ups, and pull-downs * External interrupts on all I/O pins Qualification and Class B Support * AEC-Q100 REVH (Grade 2 -40C to +105C) planned * Class B Safety Library, IEC 60730 Debugger Development Support * * * * In-circuit and in-application programming 4-wire MIPS(R) Enhanced JTAG interface Unlimited program and six complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Packages Type QFN Pin Count 64 64 I/O Pins (up to) 53 53 Contact/Lead Pitch 0.50 0.50 Dimensions 9x9x0.9 10x10x1 Note: All dimensions are in millimeters (mm) unless specified. 2012-2017 Microchip Technology Inc. TQFP 100 85 0.40 12x12x1 VTLA 100 85 0.50 14x14x1 124 85 0.50 9x9x0.9 DS60001185G-page 1 PIC32MX330/350/370/430/450/470 TABLE 1: PIC32MX330/350/370/430/450/470 CONTROLLER FAMILY FEATURES PIC32MX450F128L PIC32MX450F256H PIC32MX450F256L PIC32MX470F512H PIC32MX470F512L Note 1: 2: 3: USB On-The-Go (OTG) CTMU I2C PMP RTCC DMA Channels (Programmable/Dedicated) I/O Pins JTAG Trace PIC32MX450F128H Analog Comparators PIC32MX430F064L 10-bit 1 Msps ADC (Channels) PIC32MX430F064H External Interrupts(3) PIC32MX370F512L SPI/I2S PIC32MX370F512H UART PIC32MX350F256L Timers/Capture/Compare(2) PIC32MX350F256H Remappable Pins PIC32MX350F128L Data Memory (KB) PIC32MX350F128H Program Memory (KB)(1) PIC32MX330F064L Packages PIC32MX330F064H QFN, TQFP 64+12 16 37 5/5/5 4 2/2 5 28 2 N Y 2 Y Y 4/0 53 Y N 64+12 16 54 5/5/5 5 2/2 5 28 2 N Y 2 Y Y 4/0 85 Y Y 64 QFN, 128+12 TQFP 32 37 5/5/5 4 2/2 5 28 2 N Y 2 Y Y 4/0 53 Y N 100 TQFP 124 VTLA 128+12 32 54 5/5/5 5 2/2 5 28 2 N Y 2 Y Y 4/0 85 Y Y 64 QFN, 256+12 TQFP 64 37 5/5/5 4 2/2 5 28 2 N Y 2 Y Y 4/0 53 Y N 100 TQFP 124 VTLA 64 54 5/5/5 5 2/2 5 28 2 N Y 2 Y Y 4/0 85 Y Y 64 QFN, 512+12 128 TQFP 37 5/5/5 4 2/2 5 28 2 N Y 2 Y Y 4/0 53 Y N 100 TQFP 124 VTLA 512+12 128 54 5/5/5 5 2/2 5 28 2 N Y 2 Y Y 4/0 85 Y Y 64 QFN, TQFP 64+12 16 34 5/5/5 4 2/2 5 28 2 Y Y 2 Y Y 4/2 49 Y N 100 TQFP 124 VTLA 64+12 16 51 5/5/5 5 2/2 5 28 2 Y Y 2 Y Y 4/2 81 Y Y 64 QFN, 128+12 TQFP 32 34 5/5/5 4 2/2 5 28 2 Y Y 2 Y Y 4/2 49 Y N Pins Device Remappable Peripherals 64 100 TQFP 124 VTLA 256+12 100 TQFP 124 VTLA 128+12 32 51 5/5/5 5 2/2 5 28 2 Y Y 2 Y Y 4/2 81 Y Y 64 QFN, 256+12 TQFP 64 34 5/5/5 4 2/2 5 28 2 Y Y 2 Y Y 4/2 49 Y N 100 TQFP 124 VTLA 64 51 5/5/5 5 2/2 5 28 2 Y Y 2 Y Y 4/2 81 Y Y 64 QFN, 512+12 128 TQFP 34 5/5/5 4 2/2 5 28 2 Y Y 2 Y Y 4/2 49 Y N 100 TQFP 124 VTLA 51 5/5/5 5 2/2 5 28 2 Y Y 2 Y Y 4/2 81 Y Y 256+12 512+12 128 All devices feature 12 KB of Boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. DS60001185G-page 2 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Device Pin Tables TABLE 2: PIN NAMES FOR 64-PIN DEVICES 64-PIN QFN(1,2,3,4) AND TQFP(1,2,3,4) (TOP VIEW) PIC32MX330F064H PIC32MX350F128H PIC32MX350F256H PIC32MX370F512H 64 1 64 QFN(4) 1 TQFP Pin # Full Pin Name Pin # Full Pin Name 1 AN22/RPE5/PMD5/RE5 33 RPF3/RF3 2 AN23/PMD6/RE6 34 RPF2/RF2 3 AN27/PMD7/RE7 35 RPF6/SCK1/INT0/RF6 4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 SDA1/RG3 5 AN17/C1INC/RPG7/PMA4/RG7 37 SCL1/RG2 6 AN18/C2IND/RPG8/PMA3/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC12 8 AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15 9 VSS 41 VSS 10 VDD 42 RPD8/RTCC/RD8 11 AN5/C1INA/RPB5/RB5 43 RPD9/RD9 12 AN4/C1INB/RB4 44 RPD10/PMCS2/RD10 13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMCS1/RD11 14 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 46 RPD0/RD0 15 PGEC1/VREF-/CVREF-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13 16 PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14 17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1 18 PGED2/AN7/RPB7/CTED3//RB7 50 AN25/RPD2/RD2 19 AVDD 51 AN26/RPD3/RD3 20 AVSS 52 RPD4/PMWR/RD4 21 AN8/RPB8/CTED10//RB8 53 RPD5/PMRD/RD5 22 AN9/RPB9/CTED4/PMA7/RB9 54 RD6 23 TMS/CVREFOUT/AN10/RPB10/CTED11//PMA13/RB10 55 RD7 24 TDO/AN11/PMA12/RB11 56 VCAP 25 VSS 57 VDD 26 VDD 58 RPF0/RF0 27 TCK/AN12/PMA11/RB12 59 RPF1/RF1 28 TDI/AN13/PMA10/RB13 60 PMD0/RE0 29 AN14/RPB14/CTED5/PMA1/RB14 61 PMD1/RE1 30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 AN20/PMD2/RE2 31 RPF4/SDA2/PMA9/RF4 63 RPE3/CTPLS/PMD3/RE3 32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RBx-RGx), with the exception of RF6, can be used as a change notification pin (CNBx-CNGx). See Section 12.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. RPF6 (pin 35) is only available for output functions. 2012-2017 Microchip Technology Inc. DS60001185G-page 3 PIC32MX330/350/370/430/450/470 TABLE 3: PIN NAMES FOR 64-PIN DEVICES 64-PIN QFN(1,2) AND TQFP(1,2) (TOP VIEW) PIC32MX430F064H PIC32MX450F128H PIC32MX450F256H PIC32MX470F512H 64 1 64 QFN(3) 1 TQFP Pin # Full Pin Name Pin # Full Pin Name 1 AN22/RPE5/PMD5/RE5 33 USBID/RF3 2 AN23/PMD6/RE6 34 VBUS 3 AN27/PMD7/RE7 35 VUSB3V3 4 AN16/C1IND/RPG6/SCK2/PMA5/RG6 36 D- 5 AN17/C1INC/RPG7/PMA4/RG7 37 D+ 6 AN18/C2IND/RPG8/PMA3/RG8 38 VDD 7 MCLR 39 OSC1/CLKI/RC12 8 AN19/C2INC/RPG9/PMA2/RG9 40 OSC2/CLKO/RC15 9 VSS 41 VSS 10 VDD 42 RPD8/RTCC/RD8 11 AN5/C1INA/RPB5/VBUSON/RB5 43 RPD9/SDA1/RD9 12 AN4/C1INB/RB4 44 RPD10/SCL1/PMCS2/RD10 13 PGED3/AN3/C2INA/RPB3/RB3 45 RPD11/PMCS1/RD11 14 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 46 RPD0/INT0/RD0 15 PGEC1/VREF-/CVREF-/AN1/RPB1/CTED12/RB1 47 SOSCI/RPC13/RC13 16 PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14 17 PGEC2/AN6/RPB6/RB6 49 AN24/RPD1/RD1 18 PGED2/AN7/RPB7/CTED3//RB7 50 AN25/RPD2/SCK1/RD2 19 AVDD 51 AN26/RPD3/RD3 20 AVSS 52 RPD4/PMWR/RD4 21 AN8/RPB8/CTED10//RB8 53 RPD5/PMRD/RD5 22 AN9/RPB9/CTED4/PMA7/RB9 54 RD6 23 TMS/CVREFOUT/AN10/RPB10/CTED11//PMA13/RB10 55 RD7 24 TDO/AN11/PMA12/RB11 56 VCAP 25 VSS 57 VDD 26 VDD 58 RPF0/RF0 27 TCK/AN12/PMA11/RB12 59 RPF1/RF1 28 TDI/AN13/PMA10/RB13 60 PMD0/RE0 29 AN14/RPB14/CTED5/PMA1/RB14 61 PMD1/RE1 30 AN15/RPB15/OCFB/CTED6/PMA0/RB15 62 AN20/PMD2/RE2 31 RPF4/SDA2/PMA9/RF4 63 RPE3/CTPLS/PMD3/RE3 32 RPF5/SCL2/PMA8/RF5 64 AN21/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 "I/O Ports" for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS60001185G-page 4 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 4: PIN NAMES FOR 100-PIN DEVICES 100-PIN TQFP (TOP VIEW)(1,2,3) PIC32MX330F064L PIC32MX350F128L PIC32MX350F256L PIC32MX370F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 RG15 36 VSS 2 VDD 37 VDD 3 AN22/RPE5/PMD5/RE5 38 TCK/CTED2/RA1 4 AN23/PMD6/RE6 39 RPF13/RF13 5 AN27/PMD7/RE7 40 RPF12/RF12 6 RPC1/RC1 41 AN12/PMA11/RB12 7 RPC2/RC2 42 AN13/PMA10/RB13 8 RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14 9 RPC4/CTED7/RC4 44 AN15/RPB15/OCFB/CTED6/PMA0/RB15 10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 VSS 11 AN17/C1INC/RPG7/PMA4/RG7 46 VDD 12 AN18/C2IND/RPG8/PMA3/RG8 47 RPD14/RD14 13 MCLR 48 RPD15/RD15 14 AN19/C2INC/RPG9/PMA2/RG9 49 RPF4/PMA9/RF4 15 VSS 50 RPF5/PMA8/RF5 16 VDD 51 RPF3/RF3 17 TMS/CTED1/RA0 52 RPF2/RF2 18 RPE8/RE8 53 RPF8/RF8 19 RPE9/RE9 54 RPF7/RF7 20 AN5/C1INA/RPB5/RB5 55 RPF6/SCK1/INT0/RF6 21 AN4/C1INB/RB4 56 SDA1/RG3 22 PGED3/AN3/C2INA/RPB3/RB3 57 SCL1/RG2 23 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 58 SCL2/RA2 24 PGEC1/AN1/RPB1/CTED12/RB1 59 SDA2/RA3 25 PGED1/AN0/RPB0/RB0 60 TDI/CTED9/RA4 26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5 27 PGED2/AN7/RPB7/CTED3/RB7 62 VDD 28 VREF-/CVREF-/PMA7/RA9 63 OSC1/CLKI/RC12 29 VREF+/CVREF+/PMA6/RA10 64 OSC2/CLKO/RC15 30 AVDD 65 VSS 31 AVSS 66 RPA14/RA14 32 AN8/RPB8/CTED10/RB8 67 RPA15/RA15 33 AN9/RPB9/CTED4/RB9 68 RPD8/RTCC/RD8 34 CVREFOUT/AN10/RPB10/CTED11PMA13/RB10 69 RPD9/RD9 35 AN11/PMA12/RB11 70 RPD10/PMCS2/RD10 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information. RPF6 (pin 55) and RPF7 (pin 54) are only remappable for input functions. 2012-2017 Microchip Technology Inc. DS60001185G-page 5 PIC32MX330/350/370/430/450/470 TABLE 4: PIN NAMES FOR 100-PIN DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW)(1,2,3) PIC32MX330F064L PIC32MX350F128L PIC32MX350F256L PIC32MX370F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 71 RPD11/PMCS1/RD11 86 VDD 72 RPD0/RD0 87 RPF0/PMD11/RF0 73 SOSCI/RPC13/RC13 88 RPF1/PMD10/RF1 74 SOSCO/RPC14/T1CK/RC14 89 RPG1/PMD9/RG1 75 VSS 90 RPG0/PMD8/RG0 76 AN24/RPD1/RD1 91 TRCLK/RA6 77 AN25/RPD2/RD2 92 TRD3/CTED8/RA7 78 AN26/RPD3/RD3 93 PMD0/RE0 79 RPD12/PMD12/RD12 94 PMD1/RE1 80 PMD13/RD13 95 TRD2/RG14 81 RPD4/PMWR/RD4 96 TRD1/RG12 82 RPD5/PMRD/RD5 97 TRD0/RG13 83 PMD14/RD6 98 AN20/PMD2/RE2 84 PMD15/RD7 99 RPE3/CTPLS/PMD3/RE3 85 VCAP 100 AN21/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information. RPF6 (pin 55) and RPF7 (pin 54) are only remappable for input functions. DS60001185G-page 6 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 5: PIN NAMES FOR 100-PIN DEVICES 100-PIN TQFP (TOP VIEW)(1,2) PIC32MX430F064L PIC32MX450F128L PIC32MX450F256L PIC32MX470F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 1 RG15 36 VSS 2 VDD 37 VDD 3 AN22/RPE5/PMD5/RE5 38 TCK/CTED2/RA1 4 AN23/PMD6/RE6 39 RPF13/RF13 5 AN27/PMD7/RE7 40 RPF12/RF12 6 RPC1/RC1 41 AN12/PMA11/RB12 7 RPC2/RC2 42 AN13/PMA10/RB13 8 RPC3/RC3 43 AN14/RPB14/CTED5/PMA1/RB14 9 RPC4/CTED7/RC4 44 AN15/RPB15/OCFB/CTED6/PMA0/RB15 10 AN16/C1IND/RPG6/SCK2/PMA5/RG6 45 VSS 11 AN17/C1INC/RPG7/PMA4/RG7 46 VDD 12 AN18/C2IND/RPG8/PMA3/RG8 47 RPD14/RD14 13 MCLR 48 RPD15/RD15 14 AN19/C2INC/RPG9/PMA2/RG9 49 RPF4/PMA9/RF4 15 VSS 50 RPF5/PMA8/RF5 16 VDD 51 USBID/RF3 17 TMS/CTED1/RA0 52 RPF2/RF2 18 RPE8/RE8 53 RPF8/RF8 19 RPE9/RE9 54 VBUS 20 AN5/C1INA/RPB5/VBUSON/RB5 55 VUSB3V3 21 AN4/C1INB/RB4 56 D- 22 PGED3/AN3/C2INA/RPB3/RB3 57 D+ 23 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 58 SCL2/RA2 24 PGEC1/AN1/RPB1/CTED12/RB1 59 SDA2/RA3 25 PGED1/AN0/RPB0/RB0 60 TDI/CTED9/RA4 26 PGEC2/AN6/RPB6/RB6 61 TDO/RA5 27 PGED2/AN7/RPB7/CTED3/RB7 62 VDD 28 VREF-/CVREF-/PMA7/RA9 63 OSC1/CLKI/RC12 29 VREF+/CVREF+/PMA6/RA10 64 OSC2/CLKO/RC15 30 AVDD 65 VSS 31 AVSS 66 SCL1/RPA14/RA14 32 AN8/RPB8/CTED10/RB8 67 SDA1/RPA15/RA15 33 AN9/RPB9/CTED4/RB9 68 RPD8/RTCC/RD8 34 CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 69 RPD9/RD9 35 AN11/PMA12/RB11 70 RPD10/SCK1/PMCS2/RD10 Note 1: 2: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 "I/O Ports" for more information. 2012-2017 Microchip Technology Inc. DS60001185G-page 7 PIC32MX330/350/370/430/450/470 TABLE 5: PIN NAMES FOR 100-PIN DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW)(1,2) PIC32MX430F064L PIC32MX450F128L PIC32MX450F256L PIC32MX470F512L 100 1 Pin # Full Pin Name Pin # Full Pin Name 71 RPD11/PMCS1/RD11 86 VDD 72 RPD0/INT0/RD0 87 RPF0/PMD11/RF0 73 SOSCI/RPC13/RC13 88 RPF1/PMD10/RF1 74 SOSCO/RPC14/T1CK/RC14 89 RPG1/PMD9/RG1 75 VSS 90 RPG0/PMD8/RG0 76 AN24/RPD1/RD1 91 TRCLK/RA6 77 AN25/RPD2/RD2 92 TRD3/CTED8/RA7 78 AN26/RPD3/RD3 93 PMD0/RE0 79 RPD12/PMD12/RD12 94 PMD1/RE1 80 PMD13/RD13 95 TRD2/RG14 81 RPD4/PMWR/RD4 96 TRD1/RG12 82 RPD5/PMRD/RD5 97 TRD0/RG13 83 PMD14/RD6 98 AN20/CTPLS/PMD2/RE2 84 PMD15/RD7 99 RPE3/PMD3/RE3 85 VCAP 100 AN21/PMD4/RE4 Note 1: 2: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 "I/O Ports" for more information. DS60001185G-page 8 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 6: PIN NAMES FOR 124-PIN DEVICES 124-PIN VTLA (BOTTOM VIEW)(1,2,3,4,5) PIC32MX330F064L PIC32MX350F128L PIC32MX350F256L PIC32MX370F512L A34 A17 B13 B1 Full Pin Name B56 Conductive Thermal Pad B41 A51 A1 A68 Polarity Indicator Package Bump # B29 Package Bump # Full Pin Name A1 No Connect A38 SDA1/RG3 A2 RG15 A39 SCL2/RA2 A3 VSS A40 TDI/CTED9/RA4 A4 AN23/PMD6/RE6 A41 VDD A5 RPC1/RC1 A42 OSC2/CLKO/RC15 A6 RPC3/RC3 A43 VSS A7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 A44 RPA15/RA15 A8 AN18/C2IND/RPG8/PMA3/RG8 A45 RPD9/RD9 A9 AN19/C2INC/RPG9/PMA2/RG9 A46 RPD11/PMCS1/RD11 A10 VDD A47 SOSCI/RPC13/RC13 A11 RPE8/RE8 A48 VDD A12 AN5/C1INA/RPB5/RB5 A49 No Connect A13 PGED3/AN3/C2INA/RPB3/RB3 A50 No Connect A14 VDD A51 No Connect A15 PGEC1/AN1/RPB1/CTED12/RB1 A52 AN24/RPD1/RD1 A16 No Connect A53 AN26/RPD3/RD3 A17 No Connect A54 PMD13/RD13 A18 No Connect A55 RPD5/PMRD/RD5 A19 No Connect A56 PMD15/RD7 A20 PGEC2/AN6/RPB6/RB6 A57 No Connect A21 VREF-/CVREF-/PMA7/RA9 A58 No Connect A22 AVDD A59 VDD A23 AN8/RPB8/CTED10/RB8 A60 RPF1/PMD10/RF1 A24 CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 A61 RPG0/PMD8/RG0 A25 VSS A62 TRD3/CTED8/RA7 A26 TCK/CTED2/RA1 A63 VSS PMD1/RE1 A27 RPF12/RF12 A64 A28 AN13/PMA10/RB13 A65 TRD1/RG12 A29 AN15/RPB15/OCFB/CTED6/PMA0/RB15 A66 AN20/PMD2/RE2 A30 VDD A67 AN21/PMD4/RE4 A31 RPD15/RD15 A68 No Connect A32 RPF5/PMA8/RF5 B1 VDD A33 No Connect B2 AN22/RPE5/PMD5/RE5 A34 No Connect B3 AN27/PMD7/RE7 A35 RPF3/RF3 B4 RPC2/RC2 A36 RPF2/RF2 B5 RPC4/CTED7/RC4 A37 RPF7/RF7 B6 AN17/C1INC/RPG7/PMA4/RG7 Note 1: 2: 3: 4: 5: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information. RPF6 (bump B30) and RPF7 (bump A37) are only remappable for input functions. Shaded package bumps are 5V tolerant. It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout. 2012-2017 Microchip Technology Inc. DS60001185G-page 9 PIC32MX330/350/370/430/450/470 TABLE 6: PIN NAMES FOR 124-PIN DEVICES (CONTINUED) 124-PIN VTLA (BOTTOM VIEW)(1,2,3,4,5) PIC32MX330F064L PIC32MX350F128L PIC32MX350F256L PIC32MX370F512L A34 A17 B1 Full Pin Name Conductive Thermal Pad B41 B56 A51 A1 A68 Polarity Indicator Package Bump # B29 B13 Package Bump # Full Pin Name B7 MCLR B32 B8 VSS B33 SDA2/RA3 TDO/RA5 B9 TMS/CTED1/RA0 B34 OSC1/CLKI/RC12 B10 RPE9/RE9 B35 No Connect B11 AN4/C1INB/RB4 B36 RPA14/RA14 B12 VSS B37 RPD8/RTCC/RD8 B13 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 B38 RPD10/PMCS2/RD10 B14 PGED1/AN0/RPB0/RB0 B39 RPD0/RD0 B15 No Connect B40 SOSCO/RPC14/T1CK/RC14 B16 PGED2/AN7/RPB7/CTED3/RB7 B41 VSS B17 VREF+/CVREF+/PMA6/RA10 B42 AN25/RPD2/RD2 B18 AVSS B43 RPD12/PMD12/RD12 B19 AN9/RPB9/CTED4/RB9 B44 RPD4/PMWR/RD4 B20 AN11/PMA12/RB11 B45 PMD14/RD6 B21 VDD B46 No Connect B22 RPF13/RF13 B47 No Connect B23 AN12/PMA11/RB12 B48 VCAP B24 AN14/RPB14/CTED5/PMA1/RB14 B49 RPF0/PMD11/RF0 B25 VSS B50 RPG1/PMD9/RG1 B26 RPD14/RD14 B51 TRCLK/RA6 B27 RPF4/PMA9/RF4 B52 PMD0/RE0 B28 No Connect B53 VDD B29 RPF8/RF8 B54 TRD2/RG14 B30 RPF6/SCKI/INT0/RF6 B55 TRD0/RG13 B31 SCL1/RG2 B56 RPE3/CTPLS/PMD3/RE3 Note 1: 2: 3: 4: 5: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx), with the exception of RF6, can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information. RPF6 (bump B30) and RPF7 (bump A37) are only remappable for input functions. Shaded package bumps are 5V tolerant. It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout. DS60001185G-page 10 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 7: PIN NAMES FOR 124-PIN DEVICES 124-PIN VTLA (BOTTOM VIEW)(1,2,3,4) PIC32MX430F064L PIC32MX450F128L PIC32MX450F256L PIC32MX470F512L A34 A17 B13 B1 Full Pin Name B56 Conductive Thermal Pad B41 A51 A1 A68 Polarity Indicator Package Bump # B29 Package Bump # Full Pin Name A1 No Connect A38 D- A2 RG15 A39 SCL2/RA2 A3 VSS A40 TDI/CTED9/RA4 A4 AN23/PMD6/RE6 A41 VDD A5 RPC1/RC1 A42 OSC2/CLKO/RC15 A6 RPC3/RC3 A43 VSS A7 AN16/C1IND/RPG6/SCK2/PMA5/RG6 A44 SDA1/RPA15/RA15 A8 AN18/C2IND/RPG8/PMA3/RG8 A45 RPD9/RD9 A9 AN19/C2INC/RPG9/PMA2/RG9 A46 RPD11/PMCS1/RD11 A10 VDD A47 SOSCI/RPC13/RC13 A11 RPE8/RE8 A48 VDD A12 AN5/C1INA/RPB5/VBUSON/RB5 A49 No Connect A13 PGED3/AN3/C2INA/RPB3/RB3 A50 No Connect No Connect A14 VDD A51 A15 PGEC1/AN1/RPB1/CTED12/RB1 A52 AN24/RPD1/RD1 A16 No Connect A53 AN26/RPD3/RD3 A17 No Connect A54 PMD13/RD13 A18 No Connect A55 RPD5/PMRD/RD5 A19 No Connect A56 PMD15/RD7 A20 PGEC2/AN6/RPB6/RB6 A57 No Connect A21 VREF-/CVREF-/PMA7/RA9 A58 No Connect A22 AVDD A59 VDD A23 AN8/RPB8/CTED10/RB8 A60 RPF1/PMD10/RF1 A24 CVREFOUT/AN10/RPB10/CTED11/PMA13/RB10 A61 RPG0/PMD8/RG0 A25 VSS A62 TRD3/CTED8/RA7 A26 TCK/CTED2/RA1 A63 VSS PMD1/RE1 A27 RPF12/RF12 A64 A28 AN13/PMA10/RB13 A65 TRD1/RG12 A29 AN15/RPB15/OCFB/CTED6/PMA0/RB15 A66 AN20/PMD2/RE2 A30 VDD A67 AN21/PMD4/RE4 A31 RPD15/RD15 A68 No Connect A32 RPF5/PMA8/RF5 B1 VDD A33 No Connect B2 AN22/RPE5/PMD5/RE5 A34 No Connect B3 AN27/PMD7/RE7 A35 USBID/RF3 B4 RPC2/RC2 A36 RPF2/RF2 B5 RPC4/CTED7/RC4 A37 VBUS B6 AN17/C1INC/RPG7/PMA4/RG7 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information. Shaded package bumps are 5V tolerant. It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout. 2012-2017 Microchip Technology Inc. DS60001185G-page 11 PIC32MX330/350/370/430/450/470 TABLE 7: PIN NAMES FOR 124-PIN DEVICES (CONTINUED) 124-PIN VTLA (BOTTOM VIEW)(1,2,3,4) PIC32MX430F064L PIC32MX450F128L PIC32MX450F256L PIC32MX470F512L A34 A17 B1 Full Pin Name Conductive Thermal Pad B41 B56 A51 A1 A68 Polarity Indicator Package Bump # B29 B13 Package Bump # Full Pin Name B7 MCLR B32 B8 VSS B33 SDA2/RA3 TDO/RA5 B9 TMS/CTED1/RA0 B34 OSC1/CLKI/RC12 B10 RPE9/RE9 B35 No Connect B11 AN4/C1INB/RB4 B36 SCL1/RPA14/RA14 B12 VSS B37 RPD8/RTCC/RD8 B13 PGEC3/AN2/C2INB/RPB2/CTED13/RB2 B38 RPD10/SCK1/PMCS2/RD10 B14 PGED1/AN0/RPB0/RB0 B39 RPD0/INT0/RD0 B15 No Connect B40 SOSCO/RPC14/T1CK/RC14 B16 PGED2/AN7/RPB7/CTED3/RB7 B41 VSS B17 VREF+/CVREF+/PMA6/RA10 B42 AN25/RPD2/RD2 B18 AVSS B43 RPD12/PMD12/RD12 B19 AN9/RPB9/CTED4/RB9 B44 RPD4/PMWR/RD4 B20 AN11/PMA12/RB11 B45 PMD14/RD6 B21 VDD B46 No Connect B22 RPF13/RF13 B47 No Connect B23 AN12/PMA11/RB12 B48 VCAP B24 AN14/RPB14/CTED5/PMA1/RB14 B49 RPF0/PMD11/RF0 B25 VSS B50 RPG1/PMD9/RG1 B26 RPD14/RD14 B51 TRCLK/RA6 B27 RPF4/PMA9/RF4 B52 PMD0/RE0 B28 No Connect B53 VDD B29 RPF8/RF8 B54 TRD2/RG14 B30 VUSB3V3 B55 TRD0/RG13 B31 D+ B56 RPE3/CTPLS/PMD3/RE3 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select" for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information. Shaded package bumps are 5V tolerant. It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout. DS60001185G-page 12 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 17 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 27 3.0 CPU............................................................................................................................................................................................ 35 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Flash Program Memory.............................................................................................................................................................. 53 6.0 Resets ........................................................................................................................................................................................ 59 7.0 Interrupt Controller ..................................................................................................................................................................... 63 8.0 Oscillator Configuration .............................................................................................................................................................. 73 9.0 Prefetch Cache........................................................................................................................................................................... 83 10.0 Direct Memory Access (DMA) Controller ................................................................................................................................... 93 11.0 USB On-The-Go (OTG)............................................................................................................................................................ 113 12.0 I/O Ports ................................................................................................................................................................................... 137 13.0 Timer1 ...................................................................................................................................................................................... 167 14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 171 15.0 Watchdog Timer (WDT) ........................................................................................................................................................... 177 16.0 Input Capture............................................................................................................................................................................ 181 17.0 Output Compare....................................................................................................................................................................... 185 18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 189 19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 197 20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 205 21.0 Parallel Master Port (PMP)....................................................................................................................................................... 213 22.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 223 23.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 233 24.0 Comparator .............................................................................................................................................................................. 243 25.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 247 26.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 251 27.0 Power-Saving Features ........................................................................................................................................................... 257 28.0 Special Features ...................................................................................................................................................................... 261 29.0 Instruction Set .......................................................................................................................................................................... 273 30.0 Development Support............................................................................................................................................................... 275 31.0 Electrical Characteristics .......................................................................................................................................................... 279 32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 329 33.0 Packaging Information.............................................................................................................................................................. 333 The Microchip Web Site ..................................................................................................................................................................... 361 Customer Change Notification Service .............................................................................................................................................. 361 Customer Support .............................................................................................................................................................................. 361 Product Identification System ............................................................................................................................................................ 362 2012-2017 Microchip Technology Inc. DS60001185G-page 13 PIC32MX330/350/370/430/450/470 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS60001185G-page 14 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Referenced Sources This device data sheet is based on the following individual sections of the "PIC32 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature. Note: * * * * * * * * * * * * * * * * * * * * * * * * * * * To access the following documents, refer to the Documentation > Reference Manuals section of the Microchip PIC32 website: http://www.microchip.com/pic32. Section 1. "Introduction" (DS60001127) Section 2. "CPU" (DS60001113) Section 3. "Memory Organization" (DS60001115) Section 4. "Prefetch Cache" (DS60001119) Section 5. "Flash Program Memory" (DS60001121) Section 6. "Oscillator Configuration" (DS60001112) Section 7. "Resets" (DS60001118) Section 8. "Interrupt Controller" (DS60001108) Section 9. "Watchdog Timer and Power-up Timer" (DS60001114) Section 10. "Power-Saving Features" (DS60001130) Section 12. "I/O Ports" (DS60001120) Section 13. "Parallel Master Port (PMP)" (DS60001128) Section 14. "Timers" (DS60001105) Section 15. "Input Capture" (DS60001122) Section 16. "Output Compare" (DS60001111) Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) Section 19. "Comparator" (DS60001110) Section 20. "Comparator Voltage Reference (CVREF)" (DS60001109) Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107) Section 23. "Serial Peripheral Interface (SPI)" (DS60001106) Section 24. "Inter-Integrated Circuit (I2C)" (DS60001116) Section 27. "USB On-The-Go (OTG)" (DS60001126) Section 29. "Real-Time Clock and Calendar (RTCC)" (DS60001125) Section 31. "Direct Memory Access (DMA) Controller" (DS60001117) Section 32. "Configuration" (DS60001124) Section 33. "Programming and Diagnostics" (DS60001129) Section 37. "Charge Time Measurement Unit (CTMU)" (DS60001167) 2012-2017 Microchip Technology Inc. DS60001185G-page 15 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 16 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 1.0 Note: This document contains device-specific information for PIC32MX330/350/370/430/450/470 devices. DEVICE OVERVIEW This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the documents listed in the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). FIGURE 1-1: Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX330/350/ 370/430/450/470 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. PIC32MX330/350/370/430/450/470 BLOCK DIAGRAM VCAP OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators Power-up Timer FRC/LPRC Oscillators Voltage Regulator Oscillator Start-up Timer PLL PLL-USB Watchdog Timer USBCLK SYSCLK Timing Generation MCLR Power-on Reset Precision Band Gap Reference DIVIDERS VDD, VSS Brown-out Reset PBCLK Peripheral Bus Clocked by SYSCLK CTMU PORTA/CNA USB EJTAG PORTC/CNC MIPS32 PORTD/CND (R) DMAC CPU Core DS 32 PORTE/CNE 32 INT M4K(R) IS 32 ICD 32 32 32 32 Bus Matrix PORTF/CNF PORTG/CNG 32 Cache & Prefetch Module 32 PWM OC1-5 IC1-5 32 SPI1,2 I2C1,2 PMP 10-bit ADC Data RAM Peripheral Bridge UART1-5 Remappable Pins 128 128-bit wide Program Flash Memory Note: 32 Peripheral Bus Clocked by PBCLK PORTB/CNB Timer1-5 Priority Interrupt Controller JTAG BSCAN RTCC Flash Controller Comparators 1-2 Not all features are available on all devices. Refer to TABLE 1: "PIC32MX330/350/370/430/450/470 Controller Family Features" for the list of features by device. 2012-2017 Microchip Technology Inc. DS60001185G-page 17 PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type B14 A15 B13 A13 B11 A12 A20 B16 A23 B19 A24 B20 B23 A28 B24 A29 A7 B6 A8 A9 A66 A67 B2 A4 A52 B42 A53 B3 I I I I I I I I I I I I I I I I I I I I I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog 63 B34 I ST/CMOS 40 64 A42 O OSC1 39 63 B34 I OSC2 40 64 A42 O SOSCI 47 73 A47 I 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 4 5 6 8 62 64 1 2 49 50 51 3 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 10 11 12 14 98 100 3 4 76 77 78 5 CLKI 39 CLKO Pin Name SOSCO Legend: Note 1: 2: 3: Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions -- as CLKO in RC and EC modes. Always associated with the OSC2 pin function. Oscillator crystal input. ST buffer when configured in ST/CMOS RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or reso-- nator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. 32.768 kHz low-power oscillator crystal input; CMOS ST/CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output. Analog = Analog input P = Power O = Output I = Input 48 74 B40 O CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. DS60001185G-page 18 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name IC1 IC2 IC3 IC4 IC5 OC1 OC2 OC3 OC4 OC5 OCFA OCFB INT0 INT1 INT2 INT3 INT4 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 Legend: Note 1: 2: 3: 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 30 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 44 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS A29 35(1), 46(2) 55(1), 72(2) B30(1), B39(2) PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS -- 17 B9 -- 38 A26 -- 58 A39 -- 59 B32 -- 60 A40 -- 61 B33 -- 91 B51 -- 92 A62 -- 28 A21 -- 29 B17 -- 66 B36 -- 67 A44 Pin Type Buffer Type I I I I I O O O O O I I ST ST ST ST ST ST ST ST ST ST ST ST I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST Description Capture Input 1-5 Output Compare Output 1 Output Compare Output 2 Output Compare Output 3 Output Compare Output 4 Output Compare Output 5 Output Compare Fault A Input Output Compare Fault B Input External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 PORTA is a bidirectional I/O port CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. 2012-2017 Microchip Technology Inc. P = Power I = Input DS60001185G-page 19 PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 Legend: Note 1: 2: 3: 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 B14 A15 B13 A13 B11 A12 A20 B16 A23 B19 A24 B20 B23 A28 B24 A29 A5 B4 A6 B5 B34 A47 B40 A42 B39 A52 B42 A53 B44 A55 B45 A56 B37 A45 B38 A46 B43 A54 B26 A31 Pin Type Buffer Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST Description PORTB is a bidirectional I/O port PORTC is a bidirectional I/O port PORTD is a bidirectional I/O port CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. DS60001185G-page 20 P = Power I = Input 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-pin QFN/ TQFP RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 60 61 62 63 64 1 2 3 -- -- 58 59 34(1) RF3 RF4 RF5 RF6 RF7 RF8 RF12 RF13 RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 T1CK T2CK T3CK T4CK T5CK 33 31 32 35(1) -- -- -- -- -- -- 37(1) 36(1) 4 5 6 8 -- -- -- -- 48 PPS PPS PPS PPS Legend: Note 1: 2: 3: Pin Type Buffer Type B52 A64 A66 B56 A67 B2 A4 B3 A11 B10 B49 A60 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST ST ST ST ST ST ST ST ST ST ST ST A36 A35 B27 A32 B30(1) A37(1) B29 A27 B22 A61 B50 B31 A38 A7 B6 A8 A9 A65 B55 B54 A2 B40 PPS PPS PPS PPS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST 100-pin TQFP 124-pin VTLA 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 55(1) 54(1) 53 40 39 90 89 57(1) 56(1) 10 11 12 14 96 97 95 1 74 PPS PPS PPS PPS Description PORTE is a bidirectional I/O port PORTF is a bidirectional I/O port PORTG is a bidirectional I/O port Timer1 External Clock Input Timer2 External Clock Input Timer3 External Clock Input Timer4 External Clock Input Timer5 External Clock Input CMOS = CMOS compatible input or output Analog = Analog input ST = Schmitt Trigger input with CMOS levels O = Output TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. 2012-2017 Microchip Technology Inc. P = Power I = Input DS60001185G-page 21 PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type PPS I ST UART1 Clear to Send PPS PPS PPS PPS PPS PPS O I O -- ST -- UART1 Ready to Send UART1 Receive UART1 Transmit PPS PPS PPS I ST UART2 Clear to Send U2RTS U2RX U2TX PPS PPS PPS PPS PPS PPS PPS PPS PPS O I O -- ST -- UART2 Ready to Send UART2 Receive UART2 Transmit U3CTS PPS PPS PPS I ST UART3 Clear to Send U3RTS U3RX U3TX PPS PPS PPS PPS PPS PPS PPS PPS PPS O I O -- ST -- UART3 Ready to Send UART3 Receive UART3 Transmit U4CTS PPS PPS PPS I ST UART4 Clear to Send U4RTS U4RX U4TX PPS PPS PPS PPS PPS PPS PPS PPS PPS O I O -- ST -- UART4 Ready to Send UART4 Receive UART4 Transmit -- PPS PPS I ST UART5 Clear to Send O I O I/O O I/O -- ST -- ST -- ST UART5 Ready to Send UART5 Receive UART5 Transmit Synchronous Serial Clock Input/Output for SPI1 SPI1 Data In SPI1 Data Out I/O I/O O I/O -- ST -- ST SPI1 Slave Synchronization for Frame Pulse I/O Synchronous Serial Clock Input/Output for SPI2 SPI2 Data In SPI2 Data Out 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA U1CTS PPS PPS U1RTS U1RX U1TX PPS PPS PPS U2CTS Pin Name U5CTS(3) U5RTS(3) U5RX(3) U5TX(3) SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 SCL1 SDA1 SCL2 SDA2 TMS TCK TDI TDO RTCC Legend: Note 1: 2: 3: -- PPS PPS -- PPS PPS -- PPS PPS (1) (2) (1) (2) (1) 35 , 50 55 , 70 B30 , B38(2) PPS PPS PPS PPS PPS PPS PPS 4 PPS PPS PPS 10 PPS PPS PPS A7 PPS PPS Description PPS PPS PPS I/O -- SPI2 Slave Synchronization for Frame Pulse I/O 37(1), 44(2) 57(1), 66(2) B31(1), B36(2) I/O ST Synchronous Serial Clock Input/Output for I2C1 ST Synchronous Serial Data Input/Output for I2C1 36(1), 43(2) 56(1), 67(2) A38(1), A44(2) I/O 32 58 A39 I/O ST Synchronous Serial Clock Input/Output for I2C2 31 59 B32 I/O ST Synchronous Serial Data Input/Output for I2C2 23 17 B9 I ST JTAG Test Mode Select Pin 27 38 A26 I ST JTAG Test Clock Input Pin 28 60 A40 I -- JTAG Test Clock Input Pin 24 61 B33 O -- JTAG Test Clock Output Pin 42 68 B37 O -- Real-Time Clock Alarm Output CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. DS60001185G-page 22 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type A21 I Analog Comparator Voltage Reference (Low) B17 A24 A12 B11 B6 A7 A13 B13 A9 A8 PPS PPS A29 B24 I I I I I I I I I I O O O O Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog -- -- TTL/ST TTL/ST Comparator Voltage Reference (High) Comparator Voltage Reference (Output) 44 A29 O TTL/ST 29 43 B24 O TTL/ST 8 14 A9 O TTL/ST 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA 15 28 16 23 11 12 5 4 13 14 8 6 PPS PPS 30 29 29 34 20 21 11 10 22 23 14 12 PPS PPS 44 43 PMA0 30 PMA1 PMA2 Pin Name CVREFCVREF+ CVREFOUT C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C1OUT C2OUT PMALL PMALH PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2 PMD0 PMD1 PMD2 Legend: Note 1: 2: 3: Description Comparator 1 Inputs Comparator 2 Inputs Comparator 1 Output Comparator 2 Output Parallel Master Port Address Latch Enable Low Byte Parallel Master Port Address Latch Enable High Byte Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes) Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes) 6 12 A8 O TTL/ST 5 11 B6 O TTL/ST 4 10 A7 O TTL/ST 16 29 B17 O TTL/ST 22 28 A21 O TTL/ST 32 50 A32 O TTL/ST 31 49 B27 O TTL/ST 28 42 A28 O TTL/ST Parallel Master Port data (Demultiplexed Master 27 41 B23 O TTL/ST mode) or Address/Data (Multiplexed Master modes) 24 35 B20 O TTL/ST 23 34 A24 O TTL/ST 45 71 A46 O TTL/ST 44 70 B38 O TTL/ST 45 71 A46 O TTL/ST 44 70 B38 O TTL/ST 60 93 B52 I/O TTL/ST 61 94 A64 I/O TTL/ST 62 98 A66 I/O TTL/ST CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. 2012-2017 Microchip Technology Inc. DS60001185G-page 23 PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA Pin Type Buffer Type PMD3 63 99 B56 I/O TTL/ST PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMRD PMWR VBUS(2) 64 1 2 3 -- -- -- -- -- -- -- -- 53 52 34 100 3 4 5 90 89 88 87 79 80 83 84 82 81 54 A67 B2 A4 B3 A61 B50 A60 B49 B43 A54 B45 A56 A55 B44 A37 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST -- -- Analog VUSB3V3(2) 35 55 B30 P VBUSON(2) D+(2) D-(2) USBID(2) 11 37 36 33 20 57 56 51 A12 B31 A38 A35 O I/O I/O I PGED1 16 25 B14 I/O PGEC1 15 24 A15 I PGED2 18 27 B16 I/O PGEC2 17 26 A20 I PGED3 13 22 A13 I/O PGEC3 14 23 B13 I TRCLK TRD0 TRD1 TRD2 TRD3 CTED1 CTED2 CTED3 Legend: Note 1: 2: 3: Description Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes) Parallel Master Port Read Strobe Parallel Master Port Write Strobe USB Bus Power Monitor USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD. -- USB Host and OTG bus power control Output Analog USB D+ Analog USB DST USB OTG ID Detect Data I/O pin for Programming/Debugging ST Communication Channel 1 Clock Input pin for Programming/Debugging ST Communication Channel 1 Data I/O Pin for Programming/Debugging ST Communication Channel 2 Clock Input Pin for Programming/Debugging ST Communication Channel 2 Data I/O Pin for Programming/Debugging ST Communication Channel 3 Clock Input Pin for Programming/Debugging ST Communication Channel 3 -- Trace clock -- Trace Data bit 0 -- Trace Data bit 1 -- Trace Data bit 2 -- Trace Data bit 3 ST CTMU External Edge Input 1 ST CTMU External Edge Input 2 ST CTMU External Edge Input 3 Analog = Analog input P = Power O = Output I = Input -- -- 91 B51 O -- 97 B55 O -- 96 A65 O -- 95 B54 O -- 92 A62 O -- 17 B9 I -- 38 A26 I 18 27 B16 I CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. DS60001185G-page 24 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type B19 B24 A29 B5 A62 A40 A23 A24 A15 B13 I I I I I I I I I I ST ST ST ST ST ST ST ST ST ST 13 B7 I/P ST 19 30 A22 P P 20 31 P P Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules P -- Positive supply for peripheral logic and I/O pins P -- Capacitor for Internal Voltage Regulator 64-pin QFN/ TQFP 100-pin TQFP 124-pin VTLA CTED4 CTED5 CTED6 CTED7 CTED8 CTED9 CTED10 CTED11 CTED12 CTED13 22 29 30 -- -- -- 21 23 15 14 33 43 44 9 92 60 32 34 24 23 MCLR 7 AVDD AVSS Pin Name VDD VCAP VSS VREF+ VREFLegend: Note 1: 2: 3: B18 B1, A10, A14, 10, 26, 38, 2, 16, 37, B21, A30, 57 46, 62, 86 A41, A48, A59, B53 56 85 B48 Description CTMU External Edge Input 4 CTMU External Edge Input 5 CTMU External Edge Input 6 CTMU External Edge Input 7 CTMU External Edge Input 8 CTMU External Edge Input 9 CTMU External Edge Input 10 CTMU External Edge Input 11 CTMU External Edge Input 12 CTMU External Edge Input 13 A3, B8, B12, 15, 36, 45, A25, B25, 9, 25, 41 P -- Ground reference for logic and I/O pins 65, 75 A43, B41, A63 16 29 B17 I Analog Analog Voltage Reference (High) Input 15 28 A21 I Analog Analog Voltage Reference (Low) Input CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer This pin is only available on devices without a USB module. This pin is only available on devices with a USB module. This pin is not available on 64-pin devices. 2012-2017 Microchip Technology Inc. DS60001185G-page 25 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 26 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 2.0 Note: 2.1 GUIDELINES FOR GETTING STARTED WITH 32-BIT MCUS This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the documents listed in the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). Basic Connection Requirements Getting started with the PIC32MX330/350/370/430/ 450/470 family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins, even if the ADC module is not used (see 2.2 "Decoupling Capacitors") * VCAP pin (see 2.3 "Capacitor on Internal Voltage Regulator (VCAP)") * MCLR pin (see 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSPTM) and debugging purposes (see 2.5 "ICSP Pins") * OSC1 and OSC2 pins, when external oscillator source is used (see 2.8 "External Oscillator Pins") The following pins may be required: VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented. Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source. 2012-2017 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A value of 0.1 F (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within onequarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. DS60001185G-page 27 PIC32MX330/350/370/430/450/470 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION Tantalum or ceramic 10 F ESR 3(3) R1 MCLR C VSS VCAP R 0.1 F Ceramic VDD VDD VUSB3V3(1) PIC32 VDD VSS Connect(2) 0.1 F Ceramic 0.1 F Ceramic VSS VDD AVSS 0.1 F Ceramic AVDD VDD VSS 0.1 F Ceramic L1(2) Note 1: If the USB module is not used, this pin must be connected to VDD. 2: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 3 and the inductor capacity greater than 10 mA. 2.4 Master Clear (MCLR) Pin The MCLR functions: 1: 2.2.1 Aluminum or electrolytic capacitors should not be used. ESR 3 from -40C to 125C @ SYSCLK frequency (i.e., MIPS). 2.3 2.3.1 Capacitor on Internal Voltage Regulator (VCAP) specific device For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R 0.1 F(2) 10k C R1(1) 1 k MCLR PIC32 Note 1 5 4 2 3 6 VDD VSS NC PGECx(3) PGEDx(3) 1: 470 R1 1k will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met without interfering with the Debug/Programmer tools. 2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins. BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible. two Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. ICSPTM 2 1 L = ----------------------- 2f C provides * Device Reset * Device programming and debugging Where: F CNV f = ------------(i.e., ADC conversion rate/2) 2 1 f = ---------------------- 2 LC pin INTERNAL REGULATOR MODE A low-ESR (3 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 "Electrical Characteristics" for additional information on CEFC specifications. DS60001185G-page 28 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 2.5 ICSP Pins 2.7 Trace The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. The trace pins can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. When used for trace, the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.8 Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 3 or MPLAB REAL ICETM. For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. * "Using MPLAB(R) ICD 3" (poster) DS50001765 * "MPLAB(R) ICD 3 Design Advisory" DS50001764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS50001616 * "Using MPLAB(R) REAL ICETM Emulator" (poster) DS50001749 2.6 JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Oscillator Secondary Guard Trace Guard Ring Main Oscillator Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2012-2017 Microchip Technology Inc. DS60001185G-page 29 PIC32MX330/350/370/430/450/470 FIGURE 2-4: The following example assumptions are used to calculate the Primary Oscillator loading capacitor values: Circuit A Typical XT (4-10 MHz) C1 * CIN = PIC32_OSC2_Pin Capacitance = ~4-5 pF * COUT = PIC32_OSC1_Pin Capacitance = ~4-5 pF * C1 and C2 = XTAL manufacturing recommended loading capacitance * Estimated PCB stray capacitance, (i.e.,12 mm length) = 2.5 pF 1M OSC2 EXAMPLE 2-1: CRYSTAL LOAD CAPACITOR CALCULATION Circuit B = {( [5 + 15][5 + 15] ) / [5 + 15 + 15 + 5] } + 2.5 pF C1 Therefore: = {( [CIN + C1] * [COUT + C2] ) / [CIN + C1 + C2 + COUT] } + estimated oscillator PCB stray capacitance OSC1 Typical HS (10-25 MHz) Crystal manufacturer recommended: C1 = C2 = 15 pF CLOAD PRIMARY CRYSTAL OSCILLATOR CIRCUIT RECOMMENDATIONS C2 CRYSTAL OSCILLATOR DESIGN CONSIDERATION C2 2.8.1 = {( [20][20]) / [40] } + 2.5 = 10 + 2.5 = 12.5 pF OSC2 Rounded to the nearest standard value or 13 pF in this example for Primary Oscillator crystals "C1" and "C2". Circuit C The following tips are used to increase oscillator gain, (i.e., to increase peak-to-peak oscillator signal): Note: 2.8.1.1 Do not add excessive gain such that the oscillator signal is clipped, flat on top of the sine wave. If so, you need to reduce the gain or add a series resistor, RS, as shown in circuit "C" in Figure 2-4. Failure to do so will stress and age the crystal, which can result in an early failure. Adjust the gain to trim the max peak-to-peak to ~VDD-0.6V. When measuring the oscillator signal you must use a FET scope probe or a probe with 1.5 pF or the scope probe itself will unduly change the gain and peak-to-peak levels. C2 Typical XT/HS (4-25 MHz) C1 * Select a crystal with a lower "minimum" power drive rating * Select an crystal oscillator with a lower XTAL manufacturing "ESR" rating. * Add a parallel resistor across the crystal. The smaller the resistor value the greater the gain. It is recommended to stay in the range of 600k to 1M * C1 and C2 values also affect the gain of the oscillator. The lower the values, the higher the gain. * C2/C1 ratio also affects gain. To increase the gain, make C1 slightly smaller than C2, which will also help start-up performance. OSC1 Rs 1M OSC2 OSC1 Circuit D Not Recommended 1M Rs OSC1 OSC2 Circuit E Not Recommended Additional Microchip References * AN588 "PICmicro(R) Microcontroller Oscillator Design Guide" * AN826 "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849 "Basic PICmicro(R) Oscillator Design" DS60001185G-page 30 Rs 1M OSC2 OSC1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 2.9 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. 2.10 EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression Considerations The use of LDO regulators is preferred to reduce overall system noise and provide a cleaner power source. However, when utilizing switching Buck/ Boost regulators as the local power source for PIC32 devices, as well as in electrically noisy environments or test conditions required for IEC 61000-4-4 and IEC 61000-4-2, users should evaluate the use of T-Filters (i.e., L-C-L) on the power pins, as shown in Figure 2-5. In addition to a more stable power source, use of this type of T-Filter can greatly reduce susceptibility to EMI sources and events. FIGURE 2-5: EMI/EMC/EFT SUPPRESSION CIRCUIT Ferrite Chip SMD DCR = 0.15 (max) 600 ma ISAT 300 @ 100 MHz PN#: 1-1624117-3 VDD 0.01 F Ferrite Chips 0.1 F VSS VDD VDD VSS 0.1 F VSS VDD VSS VDD VSS 0.1 F PIC32 AVDD AVSS 0.1 F VDD 0.1 F VSS VUSB3V3 VSS VDD VSS 0.1 F VDD 0.1 F 0.1 F 0.1 F Ferrite Chips VDD 0.01 F 2012-2017 Microchip Technology Inc. DS60001185G-page 31 PIC32MX330/350/370/430/450/470 2.11 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-6, Figure 2-7, and Figure 2-8. FIGURE 2-6: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION PIC32MX430F064L Current Source To AN6 To AN7 To AN8 To AN9 To AN11 To AN0 CTMU AN0 AN1 ADC R1 R1 R1 R1 C1 C2 C3 C4 C5 To AN1 Read the Touch Sensors Microchip mTouchTM Library R1 R2 R2 R2 R2 R2 C1 C2 C3 C4 C5 R3 R3 R3 R3 R3 C1 C2 C3 C4 C5 AN9 To AN5 Process Samples AN11 User Application Display Data Microchip Graphics Library FIGURE 2-7: USB Host Parallel Master Port LCD Controller PMD<7:0> Display Controller Frame Buffer PMWR LCD Panel AUDIO PLAYBACK APPLICATION PMD<7:0> USB PMP Display PMWR PIC32MX450F256L I2S SPI Stereo Headphones 3 REFCLKO 3 Audio Codec Speaker 3 MMC SD SDI DS60001185G-page 32 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 2-8: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH PROJECTED CAPACITIVE TOUCH PIC32MX430F064L CTMU ADC ANx Microchip mTouchTM GFX Libraries DMA LCD Display Projected Capacitive Touch Overlay PMP SRAM 2012-2017 Microchip Technology Inc. External Frame Buffer DS60001185G-page 33 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 34 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 3.0 Note: CPU This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "CPU" (DS60001113), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). Resources for the MIPS32(R) M4K(R) Processor Core are available at http://www.imgtec.com. The the MIPS32(R) M4K(R) Processor Core is the heart of the PIC32MX330/350/370/430/450/470 device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 3.1 Features * 5-stage pipeline * 32-bit address and data paths * MIPS32(R) Enhanced Architecture (Release 2): - Multiply-accumulate and multiply-subtract instructions - Targeted multiply instruction - Zero/One detect instructions - WAIT instruction - Conditional move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions FIGURE 3-1: * MIPS16e(R) Code Compression: - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types * Simple Fixed Mapping Translation (FMT) Mechanism: * Simple Dual Bus Interface: - Independent 32-bit address and data buses - Transactions can be aborted to improve interrupt latency * Autonomous Multiply/Divide Unit (MDU): - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) * Power Control: - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks * EJTAG Debug and Instruction Trace: - Support for single stepping - Virtual instruction and data address/value - Breakpoints MIPS32(R) M4K(R) PROCESSOR CORE BLOCK DIAGRAM CPU EJTAG MDU TAP Execution Core (RF/ALU/Shift) System Co-processor 2012-2017 Microchip Technology Inc. FMT Bus Interface Off-chip Debug Interface Dual Bus Interface Bus Matrix Power Management DS60001185G-page 35 PIC32MX330/350/370/430/450/470 3.2 3.2.2 Architecture Overview The MIPS32(R) M4K(R) processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: * * * * * * * * Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e(R) Support Enhanced JTAG (EJTAG) Controller 3.2.1 EXECUTION UNIT The MIPS32(R) M4K(R) processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter and store aligner TABLE 3-1: MULTIPLY/DIVIDE UNIT (MDU) The MIPS32(R) M4K(R) processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. MIPS32(R) M4K(R) PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/ DIVIDE UNIT LATENCIES AND REPEAT RATES Op code MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU DS60001185G-page 36 Operand Size (mul rt) (div rs) Latency Repeat Rate 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits 1 2 2 3 12 19 26 33 1 2 1 2 11 18 25 32 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32(R) architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e(R), is also available by accessing the CP0 registers, listed in Table 3-2. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. TABLE 3-2: Register Number 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Note 1: 2: COPROCESSOR 0 REGISTERS Register Name Reserved HWREna BadVAddr(1) Function Reserved in the PIC32MX330/350/370/430/450/470 family core. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Count(1) Processor cycle count. Reserved Reserved in the PIC32MX330/350/370/430/450/470 family core. Compare(1) Timer interrupt control. Status(1) Processor status and control. (1) IntCtl Interrupt system status and control. SRSCtl(1) Shadow register set status and control. (1) SRSMap Provides mapping from vectored interrupt to a shadow set. Cause(1) Cause of last general exception. EPC(1) Program counter at last exception. PRId Processor identification and revision. EBASE Exception vector base register. Config Configuration register. Config1 Configuration register 1. Config2 Configuration register 2. Config3 Configuration register 3. Reserved Reserved in the PIC32MX330/350/370/430/450/470 family core. Debug(2) Debug control and exception status. DEPC(2) Program counter at last debug exception. Reserved Reserved in the PIC32MX330/350/370/430/450/470 family core. ErrorEPC(1) Program counter at last error. DESAVE(2) Debug handler scratchpad register. Registers used in exception processing. Registers used during debug. 2012-2017 Microchip Technology Inc. DS60001185G-page 37 PIC32MX330/350/370/430/450/470 Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: MIPS32(R) M4K(R) PROCESSOR CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a reserved instruction. CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. 3.3 Power Management MIPS(R) M4K(R) The processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 27.0 "Power-Saving Features". 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX330/350/370/430/450/470 family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption. DS60001185G-page 38 3.4 EJTAG Debug Support The MIPS(R) M4K(R) processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the M4K(R) core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 3. "Memory Organization" (DS60001115), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). PIC32MX330/350/370/430/450/470 microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX330/350/370/430/450/470 devices to execute from data memory. 4.1 Memory Layout PIC32MX330/350/370/430/450/470 microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX330/350/370/430/ 450/470 devices are illustrated in Figure 4-1 through Figure 4-4. Key features include: * 32-bit native data width * Separate User (KUSEG) and Kernel (KSEG0/ KSEG1) mode address space * Flexible program Flash memory partitioning * Flexible data RAM partitioning for data and program space * Separate boot Flash memory for protected code * Robust bus exception handling to intercept runaway code * Simple memory mapping with Fixed Mapping Translation (FMT) unit * Cacheable (KSEG0) and non-cacheable (KSEG1) address regions 2012-2017 Microchip Technology Inc. DS60001185G-page 39 PIC32MX330/350/370/430/450/470 FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 64 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers Boot Flash 0xBFC00000 Reserved SFRs 0xBF800000 0xBD010000 0xBD00FFFF Reserved KSEG1 0xBF900000 0xBF8FFFFF Reserved Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF Reserved RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Device Configuration Registers Reserved Device Configuration Registers 0x1FC00000 Reserved Reserved 0x9D010000 0x9D00FFFF KSEG0 0x9FC00000 Program Flash(2) Reserved 0x1F800000 Reserved 0x80000000 2: DS60001185G-page 40 0x1D010000 0x1D00FFFF Program Flash(2) 0x1D000000 RAM(2) Note 1: 0x1F900000 0x1F8FFFFF SFRs 0x9D000000 0x00000000 0x1FC02FF0 0x1FC02FEF Boot Flash Boot Flash 0x80004000 0x80003FFF 0x1FC03000 0x1FC02FFF Reserved Reserved RAM(2) 0x00004000 0x00003FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 128 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers Boot Flash 0xBFC00000 Reserved SFRs 0xBF800000 0xBD020000 0xBD01FFFF Reserved KSEG1 0xBF900000 0xBF8FFFFF Reserved Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF Reserved RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Device Configuration Registers Reserved Device Configuration Registers 0x1FC00000 Reserved Reserved 0x9D020000 0x9D01FFFF KSEG0 0x9FC00000 Program Flash(2) Reserved 0x1F800000 Reserved 0x80000000 2: 0x1D020000 0x1D01FFFF Program Flash(2) 0x1D000000 RAM(2) Note 1: 0x1F900000 0x1F8FFFFF SFRs 0x9D000000 0x00000000 0x1FC02FF0 0x1FC02FEF Boot Flash Boot Flash 0x80008000 0x80007FFF 0x1FC03000 0x1FC02FFF Reserved Reserved RAM(2) 0x00008000 0x00007FFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2012-2017 Microchip Technology Inc. DS60001185G-page 41 PIC32MX330/350/370/430/450/470 FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 256 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers Boot Flash 0xBFC00000 Reserved SFRs 0xBF800000 0xBD040000 0xBD03FFFF Reserved KSEG1 0xBF900000 0xBF8FFFFF Reserved Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF Reserved RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Device Configuration Registers Reserved Device Configuration Registers 0x1FC00000 Reserved Reserved 0x9D040000 0x9D03FFFF KSEG0 0x9FC00000 Program Flash(2) Reserved 0x1F800000 Reserved 0x80000000 2: DS60001185G-page 42 0x1D040000 0x1D03FFFF Program Flash(2) 0x1D000000 RAM(2) Note 1: 0x1F900000 0x1F8FFFFF SFRs 0x9D000000 0x00000000 0x1FC02FF0 0x1FC02FEF Boot Flash Boot Flash 0x80010000 0x8000FFFF 0x1FC03000 0x1FC02FFF Reserved Reserved RAM(2) 0x00010000 0x0000FFFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers Boot Flash 0xBFC00000 Reserved SFRs 0xBF800000 0xBD080000 0xBD07FFFF Reserved KSEG1 0xBF900000 0xBF8FFFFF Reserved Program Flash(2) 0xBD000000 0xA0020000 0xA001FFFF Reserved RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Device Configuration Registers Reserved Device Configuration Registers 0x1FC00000 Reserved Reserved 0x9D080000 0x9D07FFFF KSEG0 0x9FC00000 Program Flash(2) Reserved 0x1F800000 Reserved 0x80000000 2: 0x1D080000 0x1D07FFFF Program Flash(2) 0x1D000000 RAM(2) Note 1: 0x1F900000 0x1F8FFFFF SFRs 0x9D000000 0x00000000 0x1FC02FF0 0x1FC02FEF Boot Flash Boot Flash 0x80020000 0x8001FFFF 0x1FC03000 0x1FC02FFF Reserved Reserved RAM(2) 0x00020000 0x0001FFFF 0x00000000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS60001115) in the "PIC32 Family Reference Manual") and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information). 2012-2017 Microchip Technology Inc. DS60001185G-page 43 PIC32MX330/350/370/430/450/470 TABLE 4-1: SFR MEMORY MAP Virtual Address Peripheral Base Offset Start Watchdog Timer 0x0000 RTCC 0x0200 Timer1-5 0x0600 Input Capture 1-5 0x2000 Output Compare 1-5 0x3000 I2C1 and I2C2 0x5000 SPI1 and SPI2 0x5800 UART1 and UART2 0x6000 PMP ADC 0xBF80 0x7000 0x9000 CVREF 0x9800 Comparator 0xA000 CTMU 0xA200 Oscillator 0xF000 Device and Revision ID 0xF200 Flash Controller 0xF400 Reset 0xF600 PPS 0xFA04 Interrupts 0x1000 Bus Matrix 0x2000 DMA Prefetch 0xBF88 USB DS60001185G-page 44 0x4000 0x5040 PORTA-PORTG Configuration 0x3000 0x6000 0xBFC0 0x2FF0 2012-2017 Microchip Technology Inc. Bus Matrix Registers BUS MATRIX REGISTER MAP 2010 BMXDKPBA(1) 2020 BMXDUDBA(1) 2030 BMXDUPBA(1) 2040 BMXDRMSZ (1) 2050 BMXPUPBA 2060 BMXPFMSZ 2070 BMXBOOTSZ 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 -- -- -- -- -- BMXCHEDMA -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- BMXWSDRM -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- 0000 -- -- -- -- -- -- 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 15:0 15:0 31:16 15:0 17/1 16/0 BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 041F BMXARB<2:0> -- 0047 0000 -- 0000 BMXDUPBA<15:0> 0000 xxxx BMXDRMSZ<31:0> 15:0 31:16 18/2 BMXDUDBA<15:0> 31:16 31:16 19/3 BMXDKPBA<15:0> 15:0 31:16 20/4 All Resets BMXCON(1) Bit Range 2000 Bits xxxx -- -- -- -- -- -- -- -- -- -- BMXPUPBA<15:0> BMXPFMSZ<31:0> -- -- BMXPUPBA<19:16> 0000 0000 xxxx xxxx BMXBOOTSZ<31:0> 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. DS60001185G-page 45 PIC32MX330/350/370/430/450/470 Register Name TABLE 4-2: Virtual Address (BF88_#) 2012-2017 Microchip Technology Inc. 4.2 PIC32MX330/350/370/430/450/470 REGISTER 4-1: Bit Range BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R/W-1 U-0 U-0 -- -- 31:24 23:16 15:8 7:0 -- -- -- -- -- BMX CHEDMA U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 BMX ERRICD BMX ERRDMA BMX ERRDS BMX ERRIS U-0 -- -- -- BMX ERRIXI U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 -- BMX WSDRM -- -- -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set BMXARB<2:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared bit 31-27 Unimplemented: Read as `0' bit 26 BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit 1 = Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data caching enabled) 0 = Disable program Flash memory (data) cacheability for DMA accesses (hits are still read from the cache, but misses do not update the cache) bit 25-21 Unimplemented: Read as `0' bit 20 BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD bit 18 BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access bit 15-7 Unimplemented: Read as `0' bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup bit 5-3 Unimplemented: Read as `0' bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111 = Reserved (using these configuration modes will produce undefined behavior) * * * 011 = Reserved (using these configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 (default) 000 = Arbitration Mode 0 DS60001185G-page 46 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 R-0 BMXDKPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM bit 9-0 BMXDKPBA<9:0>: Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: 2012-2017 Microchip Technology Inc. DS60001185G-page 47 PIC32MX330/350/370/430/450/470 REGISTER 4-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUDBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM, the value must be greater than BMXDKPBA. bit 9-0 BMXDUDBA<9:0>: Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: DS60001185G-page 48 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 R-0 BMXDUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM, BMXDUPBA must be greater than BMXDUDBA. bit 9-0 BMXDUPBA<9:0>: Read-Only bits Value is always `0', which forces 1 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXDRMSZ. 2: 2012-2017 Microchip Technology Inc. DS60001185G-page 49 PIC32MX330/350/370/430/450/470 REGISTER 4-5: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R R R R BMXDRMSZ<23:16> R R R R R BMXDRMSZ<15:8> R 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER R R R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: 0x00004000 = Device has 16 KB RAM 0x00008000 = Device has 32 KB RAM 0x00010000 = Device has 64 KB RAM 0x00020000 = Device has 128 KB RAM REGISTER 4-6: Bit Range 31:24 23:16 15:8 BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 R/W-0 R/W-0 BMXPUPBA<19:16> R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXPUPBA<15:8> R-0 7:0 x = Bit is unknown R-0 R-0 R-0 R-0 BMXPUPBA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as `0' bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits bit 10-0 BMXPUPBA<10:0>: Read-Only bits Value is always `0', which forces 2 KB increments Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernel mode data usage. The value in this register must be less than or equal to BMXPFMSZ. 2: DS60001185G-page 50 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R R R R R R R BMXPFMSZ<23:16> R R BMXPFMSZ<15:8> R R R R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00010000 = Device has 64 KB Flash 0x00020000 = Device has 128 KB Flash 0x00040000 = Device has 256 KB Flash 0x00080000 = Device has 512 KB Flash REGISTER 4-8: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXBOOTSZ<31:24> R R R R R BMXBOOTSZ<23:16> R R R R R BMXBOOTSZ<15:8> R R R R R BMXBOOTSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00003000 = Device has 12 KB Boot Flash 2012-2017 Microchip Technology Inc. DS60001185G-page 51 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 52 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Program Memory" (DS60001121), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). PIC32MX330/350/370/430/450/470 devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: * Run-Time Self-Programming (RTSP) * EJTAG Programming * In-Circuit Serial ProgrammingTM (ICSPTM) RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. "Flash Program Memory" (DS60001121) in the "PIC32 Family Reference Manual". EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. The EJTAG and ICSP methods are described in the "PIC32 Flash Programming Specification" (DS60001145), which can be downloaded from the Microchip web site. Note: 2012-2017 Microchip Technology Inc. On PIC32MX330/350/370/430/450/470 devices, the Flash page size is 4 KB and the row size is 512 bytes (1024 IW and 128 IW, respectively). DS60001185G-page 53 Control Registers Virtual Address (BF80_#) TABLE 5-1: NVMKEY F420 NVMADDR(1) F430 NVMDATA F440 NVMSRC ADDR Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 -- WR -- WREN -- WRERR 28/12 27/11 -- -- LVDERR LVDSTAT 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0> 18/2 17/1 -- -- NVMOP<3:0> 16/0 -- All Resets Bit Range Register Name Bits F400 NVMCON(1) F410 FLASH CONTROLLER REGISTER MAP 0000 0000 0000 0000 0000 0000 0000 0000 31:16 0000 NVMSRCADDR<31:0> 15:0 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 54 5.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 5-1: Bit Range NVMCON: PROGRAMMING CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 7:0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R-0 R-0 R-0 U-0 U-0 U-0 WR WREN U-0 U-0 U-0 U-0 -- -- -- -- Legend: R = Readable bit -n = Value at POR WRERR(1) LVDERR(1) LVDSTAT(1) W = Writable bit `1' = Bit is set R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 NVMOP<3:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 WR: Write Control bit This bit is writable when WREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes 0 = Flash operation complete or inactive bit 14 WREN: Write Enable bit 1 = Enable writes to WR bit and enables LVD circuit 0 = Disable writes to WR bit and disables LVD circuit This is the only bit in this register reset by a device Reset. bit 13 WRERR: Write Error bit(1) This bit is read-only and is automatically set by hardware. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set by hardware. 1 = Low-voltage detected (possible data corruption, if WRERR is set) 0 = Voltage level is acceptable for programming bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set, and cleared, by hardware. 1 = Low-voltage event active 0 = Low-voltage event NOT active bit 10-4 Unimplemented: Read as `0' bit 3-0 NVMOP<3:0>: NVM Operation bits These bits are writable when WREN = 0. 1111 = Reserved * * * 0111 = Reserved 0110 = No operation 0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation Note 1: This bit is cleared by setting NVMOP = 0000, and initiating a Flash operation (i.e., WR). 2012-2017 Microchip Technology Inc. DS60001185G-page 55 PIC32MX330/350/370/430/450/470 REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> W-0 W-0 W-0 W-0 W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: NVMKEY<31:0>: Unlock Register bits These bits are write-only, and read as `0' on any read This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. REGISTER 5-3: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown NVMADDR: FLASH ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<23:16> R/W-0 NVMADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown NVMADDR<31:0>: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored Page Erase: Address identifies the page to erase Row Program: Address identifies the row to program Word Program: Address identifies the word to program DS60001185G-page 56 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 NVMDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<15:8> R/W-0 NVMDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 Note: NVMDATA<31:0>: Flash Programming Data bits The bits in this register are only reset by a Power-on Reset (POR). REGISTER 5-5: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown NVMSRCADDR<31:0>: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming. 2012-2017 Microchip Technology Inc. DS60001185G-page 57 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 58 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 6.0 Note: RESETS This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS60001118), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). FIGURE 6-1: The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * * POR: Power-on Reset MCLR: Master Clear Reset pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset HVDR: High Voltage Detect Reset A simplified block diagram of the Reset module is illustrated in Figure 6-1. SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle WDTR WDT Time-out Voltage Regulator Enabled Power-up Timer VDD MCLR POR SYSRST VDD Rise Detect Configuration Mismatch Reset Brown-out Reset Brown-out Reset Software Reset BOR CMR SWR VCAP HVD Detect and Reset 2012-2017 Microchip Technology Inc. HVDR DS60001185G-page 59 Reset Control Registers SYSTEM CONTROL REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 6-1: 31:16 -- -- HVDR -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- CMR VREGS EXTR SWR -- WDTO SLEEP IDLE BOR POR xxxx(2) 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 F610 RSWRST 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SWRST 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 2: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. F600 RCON PIC32MX330/350/370/430/450/470 DS60001185G-page 60 6.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 RCON: RESET CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 R/W-0 U-0 -- -- HVDR -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 -- -- -- -- -- -- CMR VREGS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS EXTR SWR -- WDTO SLEEP IDLE R/W-1, HS (1) R/W-1, HS (1) Legend: R = Readable bit -n = Value at POR HS = Set by hardware W = Writable bit `1' = Bit is set BOR POR U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29 HVDR: High Voltage Detect Reset Flag bit 1 = High Voltage Detect (HVD) Reset has occurred 0 = HVD Reset has not occurred bit 28-10 Unimplemented: Read as `0' bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred bit 8 VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during Sleep mode 0 = Regulator is set to Stand-by Tracking mode bit 7 EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset as not executed bit 5 Unimplemented: Read as `0' bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred bit 3 SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode bit 2 IDLE: Wake From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred Note 1: User software must clear this bit to view next detection. 2012-2017 Microchip Technology Inc. DS60001185G-page 61 PIC32MX330/350/370/430/450/470 REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 -- U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC -- -- -- -- -- -- -- SWRST(1) Legend: HC = Cleared by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-1 Unimplemented: Read as `0' bit 0 SWRST: Software Reset Trigger bit(1) 1 = Enable software Reset event 0 = No effect Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001185G-page 62 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS60001108), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). PIC32MX330/350/370/430/450/470 devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. * * * * * * * * * * * interrupt Up to 76 interrupt sources Up to 46 interrupt vectors Single and multi-vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Dedicated shadow set configurable for any priority level (see the FSRSSEL<2:0> bits (DEVCFG3<18:16>) in 28.0 "Special Features" for more information) Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM Interrupt Requests FIGURE 7-1: The PIC32MX330/350/370/430/450/470 module includes the following features: Vector Number Interrupt Controller 2012-2017 Microchip Technology Inc. Priority Level CPU Core Shadow Set Number DS60001185G-page 63 PIC32MX330/350/370/430/450/470 TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt Highest Natural Order Priority CT - Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No CS0 - Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No CS1 - Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No INT0 - External Interrupt 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No T1 - Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No IC1E - Input Capture 1 Error 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes IC1 - Input Capture 1 6 5 IFS0<6> IEC0<6> IPC1<12:10> IPC1<9:8> Yes OC1 - Output Compare 1 7 6 IFS0<7> IEC0<7> IPC1<20:18> IPC1<17:16> No INT1 - External Interrupt 1 8 7 IFS0<8> IEC0<8> IPC1<28:26> IPC1<25:24> No T2 - Timer2 9 8 IFS0<9> IEC0<9> IPC2<4:2> IPC2<1:0> No IC2E - Input Capture 2 10 9 IFS0<10> IEC0<10> IPC2<12:10> IPC2<9:8> Yes IC2 - Input Capture 2 11 9 IFS0<11> IEC0<11> IPC2<12:10> IPC2<9:8> Yes OC2 - Output Compare 2 12 10 IFS0<12> IEC0<12> IPC2<20:18> IPC2<17:16> No INT2 - External Interrupt 2 13 11 IFS0<13> IEC0<13> IPC2<28:26> IPC2<25:24> No T3 - Timer3 14 12 IFS0<14> IEC0<14> IPC3<4:2> IPC3<1:0> No IC3E - Input Capture 3 15 13 IFS0<15> IEC0<15> IPC3<12:10> IPC3<9:8> Yes IC3 - Input Capture 3 16 13 IFS0<16> IEC0<16> IPC3<12:10> IPC3<9:8> Yes OC3 - Output Compare 3 17 14 IFS0<17> IEC0<17> IPC3<20:18> IPC3<17:16> No INT3 - External Interrupt 3 18 15 IFS0<18> IEC0<18> IPC3<28:26> IPC3<25:24> No T4 - Timer4 19 16 IFS0<19> IEC0<19> IPC4<4:2> IPC4<1:0> No IC4E - Input Capture 4 Error 20 17 IFS0<20> IEC0<20> IPC4<12:10> IPC4<9:8> Yes IC4 - Input Capture 4 21 17 IFS0<21> IEC0<21> IPC4<12:10> IPC4<9:8> Yes OC4 - Output Compare 4 22 18 IFS0<22> IEC0<22> IPC4<20:18> IPC4<17:16> No INT4 - External Interrupt 4 23 19 IFS0<23> IEC0<23> IPC4<28:26> IPC4<25:24> No T5 - Timer5 24 20 IFS0<24> IEC0<24> IPC5<4:2> IPC5<1:0> No IC5E - Input Capture 5 Error 25 21 IFS0<25> IEC0<25> IPC5<12:10> IPC5<9:8> Yes Yes IC5 - Input Capture 5 26 21 IFS0<26> IEC0<26> IPC5<12:10> IPC5<9:8> OC5 - Output Compare 5 27 22 IFS0<27> IEC0<27> IPC5<20:18> IPC5<17:16> No AD1 - ADC1 Convert done 28 23 IFS0<28> IEC0<28> IPC5<28:26> IPC5<25:24> Yes FSCM - Fail-Safe Clock Monitor 29 24 IFS0<29> IEC0<29> IPC6<4:2> IPC6<1:0> No RTCC - Real-Time Clock and Calendar 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8> No FCE - Flash Control Event 31 26 IFS0<31> IEC0<31> IPC6<20:18> IPC6<17:16> No CMP1 - Comparator Interrupt 32 27 IFS1<0> IEC1<0> IPC6<28:26> IPC6<25:24> No CMP2 - Comparator Interrupt 33 28 IFS1<1> IEC1<1> IPC7<4:2> IPC7<1:0> No USB - USB Interrupts 34 29 IFS1<2> IEC1<2> IPC7<12:10> IPC7<9:8> Yes SPI1E - SPI1 Fault 35 30 IFS1<3> IEC1<3> IPC7<20:18> IPC7<17:16> Yes SPI1RX - SPI1 Receive Done 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> Yes SPI1TX - SPI1 Transfer Done 37 30 IFS1<5> IEC1<5> IPC7<20:18> IPC7<17:16> Yes U1E - UART1 Fault 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24> Yes U1RX - UART1 Receive Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24> Yes U1TX - UART1 Transfer Done 40 31 IFS1<8> IEC1<8> IPC7<28:26> IPC7<25:24> Yes I2C1B - I2C1 Bus Collision Event 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0> Yes I2C1S - I2C1 Slave Event 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0> Yes I2C1M - I2C1 Master Event 43 32 IFS1<11> IEC1<11> IPC8<4:2> IPC8<1:0> Yes CNA - PORTA Input Change Interrupt 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8> Yes Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX330/350/370/430/450/470 Controller Family Features" for the list of available peripherals. DS60001185G-page 64 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Bit Location Interrupt Source(1) IRQ # Vector # Flag Enable Priority Sub-priority Persistent Interrupt CNB - PORTB Input Change Interrupt 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8> Yes CNC - PORTC Input Change Interrupt 46 33 IFS1<14> IEC1<14> IPC8<12:10> IPC8<9:8> Yes CND - PORTD Input Change Interrupt 47 33 IFS1<15> IEC1<15> IPC8<12:10> IPC8<9:8> Yes CNE - PORTE Input Change Interrupt 48 33 IFS1<16> IEC1<16> IPC8<12:10> IPC8<9:8> Yes CNF - PORTF Input Change Interrupt 49 33 IFS1<17> IEC1<17> IPC8<12:10> IPC8<9:8> Yes CNG - PORTG Input Change Interrupt 50 33 IFS1<18> IEC1<18> IPC8<12:10> IPC8<9:8> Yes PMP - Parallel Master Port 51 34 IFS1<19> IEC1<19> IPC8<20:18> IPC8<17:16> Yes PMPE - Parallel Master Port Error 52 34 IFS1<20> IEC1<20> IPC8<20:18> IPC8<17:16> Yes SPI2E - SPI2 Fault 53 35 IFS1<21> IEC1<21> IPC8<28:26> IPC8<25:24> Yes SPI2RX - SPI2 Receive Done 54 35 IFS1<22> IEC1<22> IPC8<28:26> IPC8<25:24> Yes SPI2TX - SPI2 Transfer Done 55 35 IFS1<23> IEC1<23> IPC8<28:26> IPC8<25:24> Yes U2E - UART2 Error 56 36 IFS1<24> IEC1<24> IPC9<4:2> IPC9<1:0> Yes U2RX - UART2 Receiver 57 36 IFS1<25> IEC1<25> IPC9<4:2> IPC9<1:0> Yes U2TX - UART2 Transmitter 58 36 IFS1<26> IEC1<26> IPC9<4:2> IPC9<1:0> Yes I2C2B - I2C2 Bus Collision Event 59 37 IFS1<27> IEC1<27> IPC9<12:10> IPC9<9:8> Yes I2C2S - I2C2 Slave Event 60 37 IFS1<28> IEC1<28> IPC9<12:10> IPC9<9:8> Yes I2C2M - I2C2 Master Event 61 37 IFS1<29> IEC1<29> IPC9<12:10> IPC9<9:8> Yes U3E - UART3 Error 62 38 IFS1<30> IEC1<30> IPC9<20:18> IPC9<17:16> Yes U3RX - UART3 Receiver 63 38 IFS1<31> IEC1<31> IPC9<20:18> IPC9<17:16> Yes U3TX - UART3 Transmitter 64 38 IFS2<0> IEC2<0> IPC9<20:18> IPC9<17:16> Yes U4E - UART4 Error 65 39 IFS2<1> IEC2<1> IPC9<28:26> IPC9<25:24> Yes U4RX - UART4 Receiver 66 39 IFS2<2> IEC2<2> IPC9<28:26> IPC9<25:24> Yes U4TX - UART4 Transmitter 67 39 IFS2<3> IEC2<3> IPC9<28:26> IPC9<25:24> Yes U5E - UART5 Error 68 40 IFS2<4> IEC2<4> IPC10<4:2> IPC10<1:0> Yes U5RX - UART5 Receiver 69 40 IFS2<5> IEC2<5> IPC10<4:2> IPC10<1:0> Yes U5TX - UART5 Transmitter 70 40 IFS2<6> IEC2<6> IPC10<4:2> IPC10<1:0> Yes CTMU - CTMU Event 71 41 IFS2<7> IEC2<7> IPC10<12:10> IPC10<9:8> Yes DMA0 - DMA Channel 0 72 42 IFS2<8> IEC2<8> IPC10<20:18> IPC10<17:16> No DMA1 - DMA Channel 1 73 43 IFS2<9> IEC2<9> IPC10<28:26> IPC10<25:24> No DMA2 - DMA Channel 2 74 44 IFS2<10> IEC2<10> IPC11<4:2> IPC11<1:0> No DMA3 - DMA Channel 3 75 45 IFS2<11> IEC2<11> IPC11<12:10> IPC11<9:8> No Lowest Natural Order Priority Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX330/350/370/430/450/470 Controller Family Features" for the list of available peripherals. 2012-2017 Microchip Technology Inc. DS60001185G-page 65 Interrupts Control Registers Virtual Address (BF88_#) Register Name TABLE 7-2: 1000 INTCON 1010 INTSTAT INTERRUPT REGISTER MAP 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 1060 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 2012-2017 Microchip Technology Inc. 10A0 IPC1 10B0 IPC2 10C0 IPC3 10D0 IPC4 10E0 IPC5 31/15 30/14 29/13 28/12 27/11 26/10 31:16 -- -- 15:0 -- -- -- -- -- -- -- MVEC -- 31:16 -- 15:0 -- -- -- -- -- -- -- -- -- 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- -- -- -- INT4EP INT3EP -- -- -- -- -- -- TPC<2:0> -- -- -- SRIPL<2:0> 31:16 19/3 18/2 17/1 16/0 -- -- SS0 0000 INT2EP INT1EP INT0EP 0000 -- -- -- -- VEC<5:0> 0000 0000 0000 IPTMR<31:0> 15:0 0000 31:16 FCEIF RTCCIF FSCMIF AD1IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000 15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000 31:16 U3RXIF U3EIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2EIF PMPEIF PMPIF CNGIF CNFIF CNEIF 0000 15:0 CNDIF CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- DMA3IF DMA2IF DMA1IF DMA0IF CTMUIF U5TXIF(1) U5RXIF(1) U5EIF(1) U4TXIF U4RXIF U4EIF 31:16 FCEIE RTCCIE FSCMIE AD1IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000 15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 U3RXIE U3EIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2EIE PMPEIE PMPIE CNGIE CNFIE CNEIE 0000 15:0 CNDIE CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- DMA3IE DMA2IE DMA1IE DMA0IE CTMUIE 31:16 -- -- -- INT0IP<2:0> INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 15:0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 15:0 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 15:0 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 15:0 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This bit is only available on 100-pin devices. This bit is only implemented on devices with a USB module. 1: 2: 20/4 All Resets Bit Range Bits SPI2TXIF SPI2RXIF U1RXIF U1EIF SPI2TXIE SPI2RXIE U1RXIE U1EIE -- SPI1TXIF SPI1RXIF SPI1EIF USBIF(2) CMP2IF CMP1IF 0000 -- 0000 U3TXIF 0000 SPI1TXIE SPI1RXIE SPI1EIE USBIE(2) CMP2IE CMP1IE 0000 -- U5TXIE(1) U5RXIE(1) -- -- -- -- U5EIE(1) U4TXIE U4RXIE U4EIE -- 0000 U3TXIE 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 66 7.1 Virtual Address (BF88_#) Register Name 10F0 IPC6 INTERRUPT REGISTER MAP (CONTINUED) 1100 IPC7 1110 IPC8 1120 IPC9 IPC10 1140 IPC11 30/14 29/13 28/12 27/11 31:16 -- -- -- CMP1IP<2:0> 15:0 -- -- -- RTCCIP<2:0> 31:16 -- -- -- 15:0 -- -- 31:16 -- 15:0 23/7 22/6 21/5 CMP1IS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 U1IP<2:0> U1IS<1:0> -- -- -- SPI1IP<2:0> SPI1IS<1:0> 0000 -- USBIP<2:0>(2) USBIS<1:0>(2) -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 -- -- -- CNIP<2:0> CNIS<1:0> -- -- -- I2C1IP<2:0> I2C1IS<1:0> 0000 31:16 -- -- -- U4IP<2:0> U4IS<1:0> -- -- -- U3IP<2:0> U3IS<1:0> 0000 15:0 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 0000 31:16 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 15:0 -- -- -- CTMUIP<2:0> CTMUIS<1:0> -- -- -- U5IP<2:0> U5IS<1:0> 0000 31:16 -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- DMA3IS<1:0> -- -- -- -- -- DMA3IP<2:0> 26/10 -- 25/9 24/8 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note This bit is only available on 100-pin devices. This bit is only implemented on devices with a USB module. 1: 2: 20/4 -- 19/3 -- DMA2IP<2:0> 18/2 -- 17/1 16/0 -- DMA2IS<1:0> 0000 DS60001185G-page 67 PIC32MX330/350/370/430/450/470 1130 31/15 All Resets Bits Bit Range 2012-2017 Microchip Technology Inc. TABLE 7-2: PIC32MX330/350/370/430/450/470 REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SS0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- MVEC -- U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set TPC<2:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-17 Unimplemented: Read as `0' bit 16 SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow register set 0 = Single vector is not presented with a shadow register set bit 15-13 Unimplemented: Read as `0' bit 12 MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for multi vectored mode 0 = Interrupt controller configured for single vectored mode bit 11 Unimplemented: Read as `0' bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits 111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer 110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer 101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer 100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer 011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer 010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer 001 = Interrupts of group priority 1 start the Interrupt Proximity timer 000 = Disables Interrupt Proximity timer bit 7-5 Unimplemented: Read as `0' bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge DS60001185G-page 68 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- Legend: R = Readable bit -n = Value at POR SRIPL<2:0>(1) R/W-0 R/W-0 R/W-0 VEC<5:0>(1) W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as `0' bit 10-8 SRIPL<2:0>: Requested Priority Level bits(1) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-6 Unimplemented: Read as `0' bit 5-0 VEC<5:0>: Interrupt Vector bits(1) 11111-00000 = The interrupt vector that is presented to the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode. REGISTER 7-3: Bit Range 31:24 23:16 15:8 7:0 IPTMR: INTERRUPT PROXIMITY TIMER REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR<23:16> R/W-0 IPTMR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR<7:0> Legend: R = Readable bit -n = Value at POR bit 31-0 Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IPTMR<31:0>: Interrupt Proximity Timer Reload bits Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by an interrupt event. 2012-2017 Microchip Technology Inc. DS60001185G-page 69 PIC32MX330/350/370/430/450/470 REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 30/22/14/6 Note: 31:24 23:16 15:8 7:0 Note: Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS9 IFS8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IFS31-IFS0: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit definitions. IECx: INTERRUPT ENABLE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 R/W-0 IEC31 IEC30 IEC29 R/W-0 R/W-0 R/W-0 IEC23 IEC22 IEC21 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 IEC28 IEC27 IEC26 IEC25 IEC24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC20 IEC19 IEC18 IEC17 IEC16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC9 IEC8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC7 IEC6 IEC5 IEC4 IEC3 IEC2 IEC1 IEC0 Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 26/18/10/2 R/W-0 REGISTER 7-5: Bit Range Bit Bit 28/20/12/4 27/19/11/3 IFS31 Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 29/21/13/5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown IEC31-IEC0: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit definitions. DS60001185G-page 70 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 7-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit `1' = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP3<2:0> R/W-0 R/W-0 IS3<1:0> R/W-0 IP2<2:0> R/W-0 R/W-0 R/W-0 IP0<2:0> R/W-0 IS2<1:0> R/W-0 IP1<2:0> R/W-0 R/W-0 R/W-0 R/W-0 IS1<1:0> R/W-0 R/W-0 R/W-0 IS0<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as `0' bit 28-26 IP3<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS3<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 23-21 Unimplemented: Read as `0' bit 20-18 IP2<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS2<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as `0' bit 12-10 IP1<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. 2012-2017 Microchip Technology Inc. DS60001185G-page 71 PIC32MX330/350/370/430/450/470 REGISTER 7-6: bit 9-8 bit 7-5 bit 4-2 IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) IS1<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as `0' IP0<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 * * * bit 1-0 Note: 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS0<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. DS60001185G-page 72 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of the PIC32MX330/350/370/430/450/ 470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. "Oscillator Configuration" (DS60001112), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The PIC32MX330/350/370/430/450/470 oscillator system has the following modules and features: * A Total of four external and internal oscillator options as clock sources * On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources * On-Chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown * Dedicated On-Chip PLL for USB peripheral A block diagram of the oscillator system is provided in Figure 8-1. 2012-2017 Microchip Technology Inc. DS60001185G-page 73 PIC32MX330/350/370/430/450/470 FIGURE 8-1: PIC32MX330/350/370/430/450/470 FAMILY CLOCK DIAGRAM USB PLL(5) USB Clock (48 MHz) UFIN div x div 2 PLL x24 UFIN 4 MHz UPLLIDIV<2:0> UPLLEN USBPLL (96 MHz) REFCLKI PLL FVCO ROSEL<3:0> RS(1) C2(3) OSC2(4) FPLL div y XTPLL, HSPLL, ECPLL, FRCPLL FOSC RF(2) RP(1) To SPI PLLODIV<2:0> OSC1 XTAL REFCLKO M 2 N + --------512 RODIV<14:0> (N) PLLMULT<2:0> Primary Oscillator (POSC) C1(3) OE System PLL FPLLIDIV<2:0> COSC<2:0> (001 = FRC, 011 = POSC) ROTRIM<8:0> (M) POSC FRC LPRC SOSC PBCLK SYSCLK System PLL FPLLI (i.e., FIN) 4 MHz FIN 5 MHz div x UFRCEN POSC (XT, HS, EC) To Internal Logic Enable FRC div 16 div 2 CPU and Select Peripherals Postscaler SYSCLK FRCDIV FRCDIV<2:0> TUN<5:0> LPRC Oscillator PBDIV<1:0> FRC/16 To ADC FRC Oscillator 8 MHz typical Postscaler Peripherals div x PBCLK (TPB) 31.25 kHz typical LPRC Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSC COSC<2:0> SOSCEN and FSOSCEN Clock Control Logic Fail-Safe Clock Monitor SOSCI FSCM INT FSCM Event NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC Notes: 1. 2. 3. 4. 5. A series resistor, RS, may be required for AT strip cut crystals or eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP, with a value of 1 M The internal feedback resistor, RF, is typically in the range of 2 M to 10 M Refer to Section 6. "Oscillator Configuration" (DS60001112) in the "PIC32 Family Reference Manual" for help in determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. USB PLL is available on PIC32MX4XX devices only. DS60001185G-page 74 2012-2017 Microchip Technology Inc. Oscillator Control Registers TABLE 8-1: Virtual Address (BF80_#) OSCILLATOR CONTROL REGISTER MAP 31:16 15:0 31:16 F010 OSCTUN 15:0 31:16 F020 REFOCON 15:0 F000 OSCCON Legend: Note 1: 2: 3: 30/14 -- -- -- -- -- -- ON -- -- -- 29/13 28/12 27/11 PLLODIV<2:0> COSC<2:0> -- -- -- -- SIDL OE 26/10 -- -- -- -- -- RSLP -- ROTRIM<8:0> 25/9 24/8 FRCDIV<2:0> NOSC<2:0> -- -- DIVSWEN -- -- ACTIVE 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0> x1xx(2) CLKLOCK ULOCK(4) SLOCK SLPEN CF UFRCEN(4) SOSCEN OSWEN xxxx(2) -- -- -- -- -- -- -- -- 0000 -- -- TUN<5:0> 0000 RODIV<14:0> 0000 -- -- -- -- -- -- -- ROSEL<3:0> -- -- -- 0000 -- 0000 15:0 -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. This bit is only available on devices with a USB module. DS60001185G-page 75 PIC32MX330/350/370/430/450/470 F030 REFOTRIM 31:16 31/15 All Resets Bit Range Bits Register Name(1) 2012-2017 Microchip Technology Inc. 8.1 PIC32MX330/350/370/430/450/470 REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 OSCCON: OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 R/W-y -- -- U-0 -- U-0 R-0 R/W-y R-0 Bit 26/18/10/2 R/W-y R/W-0 PLLODIV<2:0> R-1 SOSCRDY PBDIVRDY -- Bit Bit 28/20/12/4 27/19/11/3 R-0 R/W-y R-0 Bit 24/16/8/0 R/W-0 R/W-1 FRCDIV<2:0> R/W-y R/W-y PBDIV<1:0> COSC<2:0> Bit 25/17/9/1 R/W-y R/W-y PLLMULT<2:0> U-0 R/W-y -- R/W-y R/W-y NOSC<2:0> R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0 CLKLOCK ULOCK(1) SLOCK SLPEN CF UFRCEN(1) SOSCEN OSWEN Legend: R = Readable bit -n = Value at POR y = Value set from Configuration bits on POR W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-27 PLLODIV<2:0>: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 bit 23 Unimplemented: Read as `0' bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary Oscillator is still warming up or is turned off bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit 1 = PBDIV<1:0> bits can be written 0 = PBDIV<1:0> bits cannot be written bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits 11 = PBCLK is SYSCLK divided by 8 (default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note 1: Note: This bit is available on PIC32MX4XX devices only. Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001185G-page 76 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as `0' bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC (FRC) Oscillator divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast RC (FRC) Oscillator bit 11 Unimplemented: Read as `0' bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits 110 = Internal Fast RC Oscillator (FRC) divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast Internal RC Oscillator (FRC) On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If clock switching and monitoring is disabled (FCKSM<1:0> = 1x): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified bit 7 bit 6 bit 5 bit 4 bit 3 Note If clock switching and monitoring is enabled (FCKSM<1:0> = 0x): Clock and PLL selections are never locked and may be modified. ULOCK: USB PLL Lock Status bit(1) 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected 1: This bit is available on PIC32MX4XX devices only. Note: Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2012-2017 Microchip Technology Inc. DS60001185G-page 77 PIC32MX330/350/370/430/450/470 REGISTER 8-1: bit 2 bit 1 bit 0 Note 1: Note: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) UFRCEN: USB FRC Clock Enable bit(1) 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete This bit is available on PIC32MX4XX devices only. Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001185G-page 78 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- R/W-0 (1) TUN<5:0> Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-6 Unimplemented: Read as `0' bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 100000 = Center frequency -1.5% 100001 = * * * 111111 = 000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz) 000001 = * * * 011110 = 011111 = Center frequency +1.5% x = Bit is unknown Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized nor tested. Note: Writes to this register require an unlock sequence. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 2012-2017 Microchip Technology Inc. DS60001185G-page 79 PIC32MX330/350/370/430/450/470 REGISTER 8-3: Bit Range 31:24 23:16 15:8 7:0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- R/W-0 RODIV<14:8> R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC -- DIVSWEN ACTIVE R/W-0 R/W-0 R/W-0 (1,3) RODIV<7:0>(3) R/W-0 U-0 R/W-0 R/W-0 ON -- SIDL OE U-0 U-0 U-0 U-0 -- -- -- -- Legend: R = Readable bit -n = Value at POR R/W-0 RSLP (2) R/W-0 ROSEL<3:0>(1) HC = Hardware Clearable HS = Hardware Settable W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31 Unimplemented: Read as `0' bit 30-16 RODIV<14:0>: Reference Clock Divider bits(1,3) This value selects the Reference Clock Divider bits. See Figure 8-1 for more information. bit 15 ON: Output Enable bit 1 = Reference Oscillator Module is enabled 0 = Reference Oscillator Module is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on REFCLKO pin 0 = Reference clock is not driven out on REFCLKO pin bit 11 RSLP: Reference Oscillator Module Run in Sleep bit(2) 1 = Reference Oscillator Module output continues to run in Sleep 0 = Reference Oscillator Module output is disabled in Sleep bit 10 Unimplemented: Read as `0' bit 9 DIVSWEN: Divider Switch Enable bit 1 = Divider switch is in progress 0 = Divider switch is complete bit 8 ACTIVE: Reference Clock Request Status bit 1 = Reference clock request is active 0 = Reference clock request is not active bit 7-4 Unimplemented: Read as `0' Note 1: 2: 3: The ROSEL and RODIV bits should not be written while the ACTIVE bit is `1', as undefined behavior may result. This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. While the ON bit is set to `1', writes to these bits do not take effect until the DIVSWEN bit is also set to `1'. DS60001185G-page 80 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 8-3: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (CONTINUED) bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(1) 1111 = Reserved; do not use * * * 1001 = Reserved; do not use 1000 = REFCLKI 0111 = System PLL output 0110 = USB PLL output 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = PBCLK 0000 = SYSCLK Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is `1', as undefined behavior may result. This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001. While the ON bit is set to `1', writes to these bits do not take effect until the DIVSWEN bit is also set to `1'. 2: 3: 2012-2017 Microchip Technology Inc. DS60001185G-page 81 PIC32MX330/350/370/430/450/470 REGISTER 8-4: Bit Range 31:24 23:16 15:8 7:0 REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ROTRIM<8:1> R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ROTRIM<0> -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits 111111111 = 511/512 divisor added to RODIV value 111111110 = 510/512 divisor added to RODIV value * * * 100000000 = 256/512 divisor added to RODIV value * * * 000000010 = 2/512 divisor added to RODIV value 000000001 = 1/512 divisor added to RODIV value 000000000 = 0/512 divisor added to RODIV value bit 22-0 Note: Unimplemented: Read as `0' While the ON bit (REFOCON<15>) is `1', writes to this register do not take effect until the DIVSWEN bit is also set to `1'. DS60001185G-page 82 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 9.0 The following are some of the key features of the Prefetch Cache module. PREFETCH CACHE Note: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. "Prefetch Cache" (DS60001119), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). * * * * * * * * Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. FIGURE 9-1: A simplified block diagram of the Prefetch Cache module is illustrated in Figure 9-1. PREFETCH CACHE MODULE BLOCK DIAGRAM CTRL FSM Cache Line Tag Logic CTRL BMX/CPU BMX/CPU 16 fully associative lockable cache lines 16-byte cache lines Up to four cache lines allocated to data Two cache lines with address mask to hold repeated instructions Pseudo LRU replacement policy All cache lines are software writable 16-byte parallel memory fetch Predictive instruction prefetch Bus Control Cache Control Prefetch Control Cache Line Address Encode Hit LRU Miss LRU RDATA Hit Logic Prefetch Prefetch CTRL RDATA PFM 2012-2017 Microchip Technology Inc. DS60001185G-page 83 Control Registers Virtual Address (BF88_#) TABLE 9-1: 4010 CHEACC(1) 4020 CHETAG(1) 4030 CHEMSK(1) 4040 CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 CHELRU 4090 40A0 CHEHIT CHEMIS 2012-2017 Microchip Technology Inc. 40C0 CHEPFABT Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 CHEWEN -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 15:0 -- 31:16 LTAGBOOT -- -- -- -- -- 15:0 23/7 22/6 -- -- DCSZ<1:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LMASK<15:5> -- 31:16 31:16 31:16 31:16 31:16 15:0 31:16 -- -- -- -- -- 18/2 17/1 -- -- -- -- -- -- CHEIDX<3:0> 16/0 -- CHECOH 0000 PFMWS<2:0> 0007 -- LTAG<23:16> -- -- -- -- -- -- -- -- -- -- 0000 00xx LVALID LLOCK LTYPE -- xxx0 xxx2 -- -- -- -- -- -- 0000 -- -- xxxx -- -- xxxx xxxx xxxx xxxx xxxx xxxx xxxx CHEW3<31:0> 15:0 15:0 -- -- PREFEN<1:0> 19/3 CHEW2<31:0> 15:0 15:0 20/4 CHEW1<31:0> 15:0 31:16 21/5 CHEW0<31:0> 15:0 31:16 24/8 LTAG<15:4> 15:0 31:16 25/9 All Resets Bit Range Register Name Bits 4000 CHECON(1) 4080 PREFETCH REGISTER MAP xxxx CHELRU<24:16> CHELRU<15:0> CHEHIT<31:0> CHEMIS<31:0> CHEPFABT<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx PIC32MX330/350/370/430/450/470 DS60001185G-page 84 9.1 PIC32MX330/350/370/430/450/470 REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 CHECON: CACHE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- CHECOH U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 -- -- PREFEN<1:0> -- DCSZ<1:0> R/W-1 R/W-1 PFMWS<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-17 Unimplemented: Write `0'; ignore read bit 16 CHECOH: Cache Coherency Setting on a PFM Program Cycle bit 1 = Invalidate all data and instruction lines 0 = Invalidate all data lnes and instruction lines that are not locked bit 15-10 Unimplemented: Write `0'; ignore read bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits 11 = Enable data caching with a size of 4 Lines 10 = Enable data caching with a size of 2 Lines 01 = Enable data caching with a size of 1 Line 00 = Disable data caching Changing these bits induce all lines to be reinitialized to the "invalid" state. bit 7-6 Unimplemented: Write `0'; ignore read bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits 11 = Enable predictive prefetch for both cacheable and non-cacheable regions 10 = Enable predictive prefetch for non-cacheable regions only 01 = Enable predictive prefetch for cacheable regions only 00 = Disable predictive prefetch bit 3 Unimplemented: Write `0'; ignore read bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits 111 = Seven Wait states 110 = Six Wait states 101 = Five Wait states 100 = Four Wait states 011 = Three Wait states 010 = Two Wait states 001 = One Wait state 000 = Zero Wait state 2012-2017 Microchip Technology Inc. DS60001185G-page 85 PIC32MX330/350/370/430/450/470 REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 CHEACC: CACHE ACCESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CHEWEN -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- CHEIDX<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown CHEWEN: Cache Access Enable bits for registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3 1 = The cache line selected by CHEIDX<3:0> is writeable 0 = The cache line selected by CHEIDX<3:0> is not writeable bit 30-4 Unimplemented: Write `0'; ignore read bit 3-0 CHEIDX<3:0>: Cache Line Index bits The value selects the cache line for reading or writing. DS60001185G-page 86 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 CHETAG: CACHE TAG REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 LTAGBOOT -- -- -- -- -- -- -- R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1 U-0 LVALID LLOCK LTYPE -- LTAG<19:12> R/W-x LTAG<11:4> R/W-x R/W-x R/W-x R/W-x LTAG<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31 x = Bit is unknown LTAGBOOT: Line TAG Address Boot bit 1 = The line is in the 0x1D000000 (physical) area of memory 0 = The line is in the 0x1FC00000 (physical) area of memory bit 30-24 Unimplemented: Write `0'; ignore read bit 23-4 LTAG<19:0>: Line TAG Address bits LTAG<19:0> bits are compared against physical address to determine a hit. Because its address range and position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses, (system) physical addresses, and PFM physical addresses. bit 3 LVALID: Line Valid bit 1 = The line is valid and is compared to the physical address for hit detection 0 = The line is not valid and is not compared to the physical address for hit detection bit 2 LLOCK: Line Lock bit 1 = The line is locked and will not be replaced 0 = The line is not locked and can be replaced bit 1 LTYPE: Line Type bit 1 = The line caches instruction words 0 = The line caches data words bit 0 Unimplemented: Write `0'; ignore read 2012-2017 Microchip Technology Inc. DS60001185G-page 87 PIC32MX330/350/370/430/450/470 REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 CHEMSK: CACHE TAG MASK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LMASK<10:3> LMASK<2:0> U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Write `0'; ignore read bit 15-5 LMASK<10:0>: Line Mask bits 1 = Enables mask logic to force a match on the corresponding bit position in the LTAG<19:0> bits (CHETAG<23:4>) and the physical address. 0 = Only writeable for values of CHEIDX<3:0> bits (CHEACC<3:0>) equal to 0x0A and 0x0B. Disables mask logic. bit 4-0 Unimplemented: Write `0'; ignore read REGISTER 9-5: Bit Range 31:24 23:16 15:8 7:0 CHEW0: CACHE WORD 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW0<31:24> R/W-x R/W-x CHEW0<23:16> R/W-x CHEW0<15:8> R/W-x CHEW0<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by the CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. DS60001185G-page 88 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 CHEW1: CACHE WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<31:24> R/W-x R/W-x CHEW1<23:16> R/W-x CHEW1<15:8> R/W-x CHEW1<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by the CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. REGISTER 9-7: Bit Range 31:24 23:16 15:8 7:0 CHEW2: CACHE WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW2<31:24> R/W-x R/W-x CHEW2<23:16> R/W-x CHEW2<15:8> R/W-x CHEW2<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by the CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. 2012-2017 Microchip Technology Inc. DS60001185G-page 89 PIC32MX330/350/370/430/450/470 REGISTER 9-8: Bit Range 31:24 23:16 15:8 7:0 CHEW3: CACHE WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<31:24> R/W-x R/W-x CHEW3<23:16> R/W-x CHEW3<15:8> R/W-x CHEW3<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEW3<31:0>: Word 3 of the cache line selected by the CHEIDX<3:0> bits (CHEACC<3:0>) Readable only if the device is not code-protected. Note: This register is a window into the cache data array and is readable only if the device is not code-protected. REGISTER 9-9: Bit Range 31:24 23:16 15:8 7:0 CHELRU: CACHE LRU REGISTER Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R-0 -- -- -- -- -- -- -- CHELRU<24> R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHELRU<23:16> R-0 CHELRU<15:8> R-0 CHELRU<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Write `0'; ignore read bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits Indicates the pseudo-LRU state of the cache. DS60001185G-page 90 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 9-10: Bit Range 31:24 23:16 15:8 7:0 CHEHIT: CACHE HIT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<31:24> R/W-x R/W-x CHEHIT<23:16> R/W-x CHEHIT<15:8> R/W-x CHEHIT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEHIT<31:0>: Cache Hit Count bits Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable accesses do not modify this value. REGISTER 9-11: Bit Range 31:24 23:16 15:8 7:0 CHEMIS: CACHE MISS STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEMIS<31:24> R/W-x R/W-x CHEMIS<23:16> R/W-x CHEMIS<15:8> R/W-x CHEMIS<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEMIS<31:0>: Cache Miss Count bits Incremented each time the processor issues an instruction fetch from a cacheable region that misses the prefetch cache. Non-cacheable accesses do not modify this value. 2012-2017 Microchip Technology Inc. DS60001185G-page 91 PIC32MX330/350/370/430/450/470 REGISTER 9-12: Bit Range 31:24 23:16 15:8 7:0 CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<31:24> R/W-x R/W-x CHEPFABT<23:16> R/W-x R/W-x CHEPFABT<15:8> R/W-x R/W-x CHEPFABT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load or store. DS60001185G-page 92 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 10.0 Note: DIRECT MEMORY ACCESS (DMA) CONTROLLER This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS60001117), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The PIC32 Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32 (such as Peripheral Bus (PBUS) devices: SPI, UART, PMP, etc.) or memory itself. Following are some of the key features of the DMA controller module: * Four identical channels, each featuring: - Auto-increment source and destination address registers - Source and destination pointers - Memory to memory and memory to peripheral transfers * Automatic word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination FIGURE 10-1: INT Controller Peripheral Bus * Fixed priority channel arbitration * Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA channel status interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA debug support features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable DMA BLOCK DIAGRAM System IRQ Address Decoder SE Channel 0 Control I0 Channel 1 Control I1 L Y Bus Interface Device Bus + Bus Arbitration I2 Global Control (DMACON) Channel n Control In L SE Channel Priority Arbitration 2012-2017 Microchip Technology Inc. DS60001185G-page 93 Control Registers DMA GLOBAL REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) TABLE 10-1: 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- -- SUSPEND DMABUSY -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3010 DMASTAT 15:0 -- -- -- -- -- -- -- -- -- -- -- -- RDWR DMACH<2:0> 0000 31:16 0000 3020 DMAADDR DMAADDR<31:0> 15:0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 3000 DMACON DMA CRC REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) TABLE 10-2: 31:16 -- -- BYTO<1:0> WBO -- -- BITO -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- PLEN<4:0> CRCEN CRCAPP CRCTYP -- -- CRCCH<2:0> 0000 31:16 0000 3040 DCRCDATA DCRCDATA<31:0> 15:0 0000 31:16 0000 3050 DCRCXOR DCRCXOR<31:0> 15:0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 3030 DCRCCON PIC32MX330/350/370/430/450/470 DS60001185G-page 94 10.1 2012-2017 Microchip Technology Inc. DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP 31/15 29/13 -- -- -- -- -- -- -- -- -- -- 28/12 27/11 -- -- -- -- -- -- CHSIRQ<7:0> -- -- -- -- 26/10 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- CHCHNS -- -- CHEN -- CHAED -- CHCHN -- -- -- -- -- -- CFORCE CABORT CHSDIE CHSHIE CHSDIF CHSHIF CHSSA<31:0> CHDSA<31:0> PATEN CHDDIE CHDDIF 20/4 19/3 -- -- CHAEN -- CHAIRQ<7:0> SIRQEN AIRQEN CHDHIE CHBCIE CHDHIF CHBCIF 18/2 -- CHEDET -- CHCCIE CHCCIF 17/1 16/0 -- -- CHPRI<1:0> -- CHTAIE CHTAIF 0000 0000 00FF -- FFF8 CHERIE 0000 CHERIF 0000 0000 0000 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CHSSIZ<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 30C0 DCH0DSIZ 15:0 CHDSIZ<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 30D0 DCH0SPTR 15:0 CHSPTR<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 30E0 DCH0DPTR 15:0 CHDPTR<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 30F0 DCH0CSIZ 15:0 CHCSIZ<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3100 DCH0CPTR 15:0 CHCPTR<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3110 DCH0DAT 15:0 -- -- -- -- -- -- -- -- CHPDAT<7:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3120 DCH1CON 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET CHPRI<1:0> 0000 31:16 -- -- -- -- -- -- -- -- CHAIRQ<7:0> 00FF 3130 DCH1ECON 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FFF8 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 3140 DCH1INT 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 3150 DCH1SSA CHSSA<31:0> 15:0 0000 31:16 0000 3160 DCH1DSA CHDSA<31:0> 15:0 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 30B0 DCH0SSIZ DS60001185G-page 95 PIC32MX330/350/370/430/450/470 31:16 -- 15:0 CHBUSY 31:16 -- 3070 DCH0ECON 15:0 31:16 -- 3080 DCH0INT 15:0 -- 31:16 3090 DCH0SSA 15:0 31:16 30A0 DCH0DSA 15:0 3060 DCH0CON 30/14 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) 2012-2017 Microchip Technology Inc. TABLE 10-3: Virtual Address (BF88_#) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON DCH2INT 3210 DCH2SSA 3220 DCH2DSA 2012-2017 Microchip Technology Inc. 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 15:0 -- -- -- -- -- -- -- 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHSIRQ<7:0> -- -- -- -- -- -- -- -- -- -- 31:16 -- 15:0 -- 31:16 -- 15:0 CHBUSY 31:16 -- 15:0 31:16 -- 15:0 -- 31:16 15:0 31:16 15:0 31:16 -- 15:0 31:16 -- 15:0 31:16 -- 15:0 31:16 -- 15:0 31:16 -- 15:0 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- CHSSIZ<15:0> -- -- -- -- -- -- -- 0000 0000 -- -- CHDSIZ<15:0> -- -- CHSPTR<15:0> -- -- CHDPTR<15:0> -- -- CHCSIZ<15:0> -- -- CHCPTR<15:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- CHEN -- CHAED -- CHCHN CFORCE CABORT CHSDIE CHSHIE CHSDIF CHSHIF PATEN CHDDIE CHDDIF -- -- CHPDAT<7:0> -- -- CHAEN -- CHAIRQ<7:0> SIRQEN AIRQEN CHDHIE CHBCIE CHDHIF CHBCIF -- CHEDET -- CHCCIE CHCCIF CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Resets Bit Range Register Name(1) Bits 3170 DCH1SSIZ 3200 DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED) -- -- CHSSIZ<15:0> -- -- CHDSIZ<15:0> -- -- CHSPTR<15:0> -- -- CHDPTR<15:0> -- -- CHCSIZ<15:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 -- -- 0000 CHPRI<1:0> 0000 00FF -- -- FFF8 CHTAIE CHERIE 0000 CHTAIF CHERIF 0000 0000 0000 0000 0000 -- -- 0000 0000 -- -- 0000 0000 -- -- 0000 0000 -- -- 0000 0000 -- -- 0000 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 96 TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 3 REGISTER MAP (CONTINUED) 3280 DCH2CPTR 3290 DCH2DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 -- -- -- -- -- -- -- 15:0 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCPTR<15:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) 2012-2017 Microchip Technology Inc. TABLE 10-3: 0000 0000 CHPDAT<7:0> 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 97 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 32A0 DCH3CON 15:0 CHBUSY -- -- -- -- -- -- CHCHNS CHEN CHAED CHCHN CHAEN -- CHEDET CHPRI<1:0> 0000 31:16 -- -- -- -- -- -- -- -- CHAIRQ<7:0> 00FF 32B0 DCH3ECON 15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- FFF8 31:16 -- -- -- -- -- -- -- -- CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 32C0 DCH3INT 15:0 -- -- -- -- -- -- -- -- CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 0000 32D0 DCH3SSA CHSSA<31:0> 15:0 0000 31:16 0000 32E0 DCH3DSA CHDSA<31:0> 15:0 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 32F0 DCH3SSIZ 15:0 CHSSIZ<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3300 DCH3DSIZ 15:0 CHDSIZ<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3310 DCH3SPTR 15:0 CHSPTR<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3320 DCH3DPTR 15:0 CHDPTR<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3330 DCH3CSIZ 15:0 CHCSIZ<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3340 DCH3CPTR 15:0 CHCPTR<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 3350 DCH3DAT 15:0 -- -- -- -- -- -- -- -- CHPDAT<7:0> 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- ON SUSPEND DMABUSY(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as `0' bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally bit 11 DMABUSY: DMA Module Busy bit(1) 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data bit 10-0 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001185G-page 98 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- RDWR DMACH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3 RDWR: Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write bit 2-0 DMACH<2:0>: DMA Channel bits These bits contain the value of the most recent active DMA channel. REGISTER 10-3: Bit Range 31:24 23:16 15:8 7:0 DMAADDR: DMA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR<31:24> R-0 R-0 R-0 R-0 R-0 DMAADDR<23:16> R-0 R-0 R-0 R-0 R-0 DMAADDR<15:8> R-0 R-0 R-0 R-0 R-0 DMAADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR<31:0>: DMA Module Address bits These bits contain the address of the most recent DMA access. 2012-2017 Microchip Technology Inc. DS60001185G-page 99 PIC32MX330/350/370/430/450/470 REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 R/W-0 WBO(1) -- -- BITO(1) U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BYTO<1:0> PLEN<4:0> R/W-0 R/W-0 R/W-0 U-0 U-0 CRCEN CRCAPP(1) CRCTYP -- -- R/W-0 CRCCH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (i.e., reverse source byte order) 00 = No swapping (i.e., source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO<1:0> 0 = Source data is written to the destination unaltered bit 26-25 Unimplemented: Read as `0' bit 24 BITO: CRC Bit Order Selection bit(1) When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected) When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected) 0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected) bit 23-13 Unimplemented: Read as `0' bit 12-8 PLEN<4:0>: Polynomial Length bits(1) When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial - 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS60001185G-page 100 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination bit 5 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC bit 4-3 Unimplemented: Read as `0' bit 2-0 CRCCH<2:0>: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. 2012-2017 Microchip Technology Inc. DS60001185G-page 101 PIC32MX330/350/370/430/450/470 REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA<31:0>: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return `0' on any read. When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always `0'. Data written to this register is converted and read back in 1's complement form (i.e., current IP header checksum value). When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return `0' on any read. REGISTER 10-6: Bit Range 31:24 23:16 15:8 7:0 DCRCXOR: DMA CRCXOR ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<31:24> R/W-0 R/W-0 DCRCXOR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode): 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register DS60001185G-page 102 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL `x' CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY -- -- -- -- -- -- CHCHNS(1) R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0 CHAED CHCHN CHAEN -- CHEDET R/W-0 (2) CHEN CHPRI<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14-9 Unimplemented: Read as `0' bit 8 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) bit 7 CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled bit 6 CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled bit CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete bit 3 Unimplemented: Read as `0' bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI<1:0>: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 Note 1: 2: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. 2012-2017 Microchip Technology Inc. DS60001185G-page 103 PIC32MX330/350/370/430/450/470 REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL `x' EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABORT PATEN SIRQEN AIRQEN -- -- -- Legend: R = Readable bit -n = Value at POR S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag * * * bit 15-8 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer * * * bit 2-0 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a `1' 0 = This bit always reads `0' CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a `1' 0 = This bit always reads `0' PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as `0' Note 1: See Table 7-1: "Interrupt IRQ, Vector and Bit Location" for the list of available interrupt IRQ sources. bit 7 bit 6 bit 5 bit 4 bit 3 DS60001185G-page 104 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL `x' INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 15-8 Unimplemented: Read as `0' bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ) 0 = No interrupt is pending bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2) 0 = No interrupt is pending bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending 2012-2017 Microchip Technology Inc. DS60001185G-page 105 PIC32MX330/350/370/430/450/470 REGISTER 10-9: DCHxINT: DMA CHANNEL `x' INTERRUPT CONTROL REGISTER (CONTINUED) bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected Either the source or the destination address is invalid. 0 = No interrupt is pending DS60001185G-page 106 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-10: DCHxSSA: DMA CHANNEL `x' SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<23:16> 15:8 R/W-0 R/W-0 CHSSA<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-0 x = Bit is unknown CHSSA<31:0> Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 10-11: DCHxDSA: DMA CHANNEL `x' DESTINATION START ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination. 2012-2017 Microchip Technology Inc. DS60001185G-page 107 PIC32MX330/350/370/430/450/470 REGISTER 10-12: DCHxSSIZ: DMA CHANNEL `x' SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> 7:0 R/W-0 CHSSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHSSIZ<15:0>: Channel Source Size bits 1111111111111111 = 65,535 byte source size * * * 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 10-13: DCHxDSIZ: DMA CHANNEL `x' DESTINATION SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSIZ<15:8> 7:0 R/W-0 CHDSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size * * * 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS60001185G-page 108 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-14: DCHxSPTR: DMA CHANNEL `x' SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source * * * 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source When in Pattern Detect mode, this register is reset on a pattern detect. Note: REGISTER 10-15: DCHxDPTR: DMA CHANNEL `x' DESTINATION POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHDPTR<15:8> 7:0 R-0 R-0 CHDPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination * * * 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination 2012-2017 Microchip Technology Inc. DS60001185G-page 109 PIC32MX330/350/370/430/450/470 REGISTER 10-16: DCHxCSIZ: DMA CHANNEL `x' CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> 7:0 R/W-0 CHCSIZ<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event * * * 0000000000000010 = 2 bytes transferred on an event 0000000000000001= 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 10-17: DCHxCPTR: DMA CHANNEL `x' CELL POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHCPTR<15:8> 7:0 R-0 R-0 CHCPTR<7:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event * * * 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note: When in Pattern Detect mode, this register is reset on a pattern detect. DS60001185G-page 110 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 10-18: DCHxDAT: DMA CHANNEL `x' PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 CHPDAT<7:0>: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All other modes: Unused. 2012-2017 Microchip Technology Inc. DS60001185G-page 111 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 112 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 11.0 Note: USB ON-THE-GO (OTG) This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. "USB On-TheGo (OTG)" (DS60001126), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 11-1. The PIC32 USB module includes the following features: * * * * * * * * * USB full-speed support for host and device Low-speed host support USB OTG support Integrated signaling resistors Integrated analog comparators for VBUS monitoring Integrated USB transceiver Transaction handshaking performed by hardware Endpoint buffering anywhere in system RAM Integrated DMA to access system RAM and Flash Note: The implementation and use of the USB specifications, and other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. 2012-2017 Microchip Technology Inc. DS60001185G-page 113 PIC32MX330/350/370/430/450/470 FIGURE 11-1: PIC32MX430/450/470 USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(3) Primary Oscillator (POSC) Div x UFIN(4) PLL Div 2 UFRCEN(2) OSC1 UPLLEN(5) UPLLIDIV(5) USB Suspend OSC2 (PB Out)(1) To Clock Generator for Core and Peripherals Sleep or Idle USB Module SRP Charge Bus SRP Discharge USB Voltage Comparators 48 MHz USB Clock(6) Full Speed Pull-up D+ Registers and Control Interface Host Pull-down SIE Transceiver Low Speed Pull-up DDMA System RAM Host Pull-down ID Pull-up ID(7) VBUSON(7) Transceiver Power 3.3V VUSB3V3 Note 1: 2: 3: 4: 5: 6: 7: PB clock is only available on this pin for select EC modes. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled. DS60001185G-page 114 2012-2017 Microchip Technology Inc. Control Registers TABLE 11-1: USB REGISTER MAP 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 15:0 31:16 5050 U1OTGIE 15:0 31:16 5060 U1OTGSTAT(3) 15:0 31:16 5070 U1OTGCON 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UACTPND(4) -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- STALLIF 31:16 -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- STALLIE 31:16 -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- BTSEF 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- 5040 U1OTGIR(2) 5080 U1PWRC 5200 U1IR(2) 5210 U1IE 5220 U1EIR(2) 5230 U1EIE 5240 U1STAT(3) 5250 U1CON 23/7 22/6 21/5 20/4 -- -- -- -- IDIF T1MSECIF LSTATEIF ACTVIF -- -- -- -- IDIE T1MSECIE LSTATEIE ACTVIE -- -- -- -- ID -- LSTATE -- -- -- -- -- DPPULUP DMPULUP DPPULDWN DMPULDWN ATTACHIF RESUMEIF -- 18/2 17/1 -- -- USLPGRD USBBUSY -- -- -- -- USUSPEND USBPWR -- -- -- -- IDLEIF TRNIF SOFIF UERRIF -- -- -- -- TRNIE SOFIE UERRIE -- -- -- -- BMXEF DMAEF BTOEF -- -- -- -- -- BTSEE BMXEE DMAEE BTOEE -- -- -- -- -- -- -- -- CRC5EF EOFEF -- CRC5EE EOFEE -- -- -- -- -- JSTATE ATTACHIE RESUMEIE DS60001185G-page 115 -- -- ENDPT<3:0> -- -- PKTDIS SE0 TOKBUSY -- -- -- -- USBRST 16/0 -- -- -- -- 0000 SESVDIF SESENDIF -- VBUSVDIF 0000 -- -- -- -- 0000 SESVDIE SESENDIE -- VBUSVDIE 0000 -- -- -- -- 0000 SESVD SESEND -- VBUSVD 0000 -- -- -- -- 0000 VBUSON OTGEN VBUSCHG VBUSDIS 0000 IDLEIE -- -- 19/3 DFN8EF CRC16EF -- -- DFN8EE CRC16EE -- DIR -- -- PPBI -- HOSTEN RESUME PPBRST -- URSTIF DETACHIF -- URSTIE DETACHIE -- PIDEF -- PIDEE -- -- -- USBEN SOFEN -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- LSPDEN DEVADDR<6:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5270 U1BDTP1 15:0 -- -- -- -- -- -- -- -- BDTPTRL<15:9> -- Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 2: This register does not have associated SET and INV registers. 3: This register does not have associated CLR, SET and INV registers. 4: Reset value for this bit is undefined. 5260 U1ADDR PIC32MX330/350/370/430/450/470 31/15 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) 2012-2017 Microchip Technology Inc. 11.1 Virtual Address (BF88_#) Register Name(1) 2012-2017 Microchip Technology Inc. 5280 U1FRML(3) 5290 U1FRMH(3) 52A0 U1TOK 52B0 U1SOF 52C0 U1BDTP2 52D0 U1BDTP3 52E0 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 5370 U1EP7 5380 U1EP8 USB REGISTER MAP (CONTINUED) Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 15:0 31:16 15:0 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PID<3:0> 31:16 15:0 31:16 15:0 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UTEYE -- LSPD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UOEMON -- RETRYDIS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20/4 19/3 -- -- FRML<7:0> -- -- -- -- -- -- -- -- CNT<7:0> -- -- BDTPTRH<23:16> -- -- BDTPTRU<31:24> -- USBSIDL -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- -- -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN 18/2 17/1 16/0 -- -- -- -- -- FRMH<2:0> -- -- EP<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- All Resets Bit Range Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- 0000 -- UASUSPND 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 -- -- 0000 EPSTALL EPHSHK 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX330/350/370/430/450/470 DS60001185G-page 116 TABLE 11-1: Virtual Address (BF88_#) Register Name(1) 5390 U1EP9 53A0 U1EP10 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 53E0 U1EP14 53F0 U1EP15 USB REGISTER MAP (CONTINUED) 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK -- EPHSHK 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 31:16 15:0 31:16 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN -- -- EPCONDIS EPRXEN -- EPTXEN -- EPTXEN -- EPSTALL -- EPSTALL -- EPHSHK -- EPHSHK 0000 0000 0000 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. DS60001185G-page 117 PIC32MX330/350/370/430/450/470 Legend: Note 1: All Resets Bits Bit Range 2012-2017 Microchip Technology Inc. TABLE 11-1: PIC32MX330/350/370/430/450/470 REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF -- VBUSVDIF Legend: WC = Write `1' to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No change in ID state is detected bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1millisecond, but different from last time 0 = USB line state has not been stable for 1 millisecond bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = A change on the session end input was detected 0 = No change on the session end input was detected bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit 1 = Change on the session valid input is detected 0 = No change on the session valid input is detected DS60001185G-page 118 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE -- VBUSVDIE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt is enabled 0 = ID interrupt is disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt is enabled 0 = 1 millisecond timer interrupt is disabled bit 5 LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt is enabled 0 = Line state interrupt is disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = ACTIVITY interrupt is enabled 0 = ACTIVITY interrupt is disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt is enabled 0 = Session valid interrupt is disabled bit 2 SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt is enabled 0 = B-session end interrupt is disabled bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit 1 = A-VBUS valid interrupt is enabled 0 = A-VBUS valid interrupt is disabled 2012-2017 Microchip Technology Inc. DS60001185G-page 119 PIC32MX330/350/370/430/450/470 REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID -- LSTATE -- SESVD SESEND -- VBUSVD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a Type-B cable has been plugged into the USB receptacle 0 = A Type-A cable has been plugged into the USB receptacle bit 6 Unimplemented: Read as `0' bit 5 LSTATE: Line State Stable Indicator bit 1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms 0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms bit 4 Unimplemented: Read as `0' bit 3 SESVD: Session Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A or B device 0 = VBUS voltage is below Session Valid on the A or B device bit 2 SESEND: B-Device Session End Indicator bit 1 = VBUS voltage is below Session Valid on the B device 0 = VBUS voltage is above Session Valid on the B device bit 1 Unimplemented: Read as `0' bit 0 VBUSVD: A-Device VBUS Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A device 0 = VBUS voltage is below Session Valid on the A device DS60001185G-page 120 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VBUSON OTGEN VBUSCHG VBUSDIS DPPULUP DMPULUP DPPULDWN DMPULDWN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled bit 4 DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled bit 3 VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered bit 2 OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control bit 1 VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor bit 0 VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor 2012-2017 Microchip Technology Inc. DS60001185G-page 121 PIC32MX330/350/370/430/450/470 REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND -- -- USLPGRD USBBUSY(1) -- USUSPEND USBPWR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = An interrupt is not pending bit 6-5 Unimplemented: Read as `0' bit 4 USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry bit 3 USBBUSY: USB Module Busy bit(1) 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results. bit 2 Unimplemented: Read as `0' bit 1 USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.) 0 = USB module operates normally bit 0 USBPWR: USB Operation Enable bit 1 = USB module is turned on 0 = USB module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) DS60001185G-page 122 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS (5) IDLEIF TRNIF(3) SOFIF UERRIF(4) STALLIF ATTACHIF(1) RESUMEIF(2) Legend: R = Readable bit -n = Value at POR WC = Write `1' to clear W = Writable bit `1' = Bit is set URSTIF DETACHIF(6) HS = Hardware Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 STALLIF: STALL Handshake Interrupt bit 1 = In Host mode, a STALL handshake was received during the handshake phase of the transaction In Device mode, a STALL handshake was transmitted during the handshake phase of the transaction 0 = STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 s 0 = K-State is not observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 Note 1: 2: 3: 4: 5: 6: This bit is valid only if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for 2.5 s, and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode. 2012-2017 Microchip Technology Inc. DS60001185G-page 123 PIC32MX330/350/370/430/450/470 REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IDLEIE TRNIE SOFIE UERRIE(1) STALLIE ATTACHIE RESUMEIE URSTIE(2) DETACHIE(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt is enabled 0 = STALL interrupt is disabled bit 6 ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt is enabled 0 = ATTACH interrupt is disabled bit 5 RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt is enabled 0 = RESUME interrupt is disabled bit 4 IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt is enabled 0 = Idle interrupt is disabled bit 3 TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt is enabled 0 = TRNIF interrupt is disabled bit 2 SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt is enabled 0 = SOFIF interrupt is disabled bit 1 UERRIE: USB Error Interrupt Enable bit(1) 1 = USB Error interrupt is enabled 0 = USB Error interrupt is disabled bit 0 URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt is enabled 0 = URSTIF interrupt is disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt is enabled 0 = DATTCHIF interrupt is disabled Note 1: 2: 3: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. Device mode. Host mode. DS60001185G-page 124 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF CRC5EF(4) EOFEF(3,5) Legend: WC = Write `1' to clear HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared PIDEF x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Packet is rejected due to bit stuff error 0 = Packet is accepted bit 6 BMXEF: Bus Matrix Error Flag bit 1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid. 0 = No address error bit 5 DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted Note 1: 2: 3: 4: 5: This type of error occurs when the module's request for the DMA bus is not granted in time to service the module's demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. 2012-2017 Microchip Technology Inc. DS60001185G-page 125 PIC32MX330/350/370/430/450/470 REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) bit 1 CRC5EF: CRC5 Host Error Flag bit(4) 1 = Token packet is rejected due to CRC5 error 0 = Token packet is accepted EOFEF: EOF Error Flag bit(3,5) 1 = EOF error condition is detected 0 = No EOF error condition bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check is failed 0 = PID check is passed Note 1: 2: 3: 4: 5: This type of error occurs when the module's request for the DMA bus is not granted in time to service the module's demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. DS60001185G-page 126 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set CRC5EE(1) EOFEE(2) PIDEE U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt is enabled 0 = BTSEF interrupt is disabled bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt is enabled 0 = BMXEF interrupt is disabled bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt is enabled 0 = DMAEF interrupt is disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt is enabled 0 = BTOEF interrupt is disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt is enabled 0 = DFN8EF interrupt is disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt is enabled 0 = CRC16EF interrupt is disabled bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(1) 1 = CRC5EF interrupt is enabled 0 = CRC5EF interrupt is disabled EOFEE: EOF Error Interrupt Enable bit(2) 1 = EOF interrupt is enabled 0 = EOF interrupt is disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt is enabled 0 = PIDEF interrupt is disabled Note 1: 2: Note: Device mode. Host mode. For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set. 2012-2017 Microchip Technology Inc. DS60001185G-page 127 PIC32MX330/350/370/430/450/470 REGISTER 11-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI -- -- ENDPT<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits (Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 * * * 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = Last transaction was a transmit transfer (TX) 0 = Last transaction was a receive transfer (RX) bit 2 PPBI: Ping-Pong BD Pointer Indicator bit 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank bit 1-0 Unimplemented: Read as `0' Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only valid when the TRNIF bit (U1IR<3>) is active. Clearing the TRNIF bit advances the FIFO. Data in register is invalid when the TRNIF bit = 0. DS60001185G-page 128 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 U-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 PKTDIS(4) TOKBUSY(1,5) USBRST HOSTEN(2) RESUME(3) PPBRST USBEN(4) SOFEN(5) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE detected on the USB 0 = No JSTATE detected bit 6 SE0: Live Single-Ended Zero flag bit 1 = Single Ended Zero detected on the USB 0 = No Single Ended Zero detected bit 5 PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing disabled (set upon SETUP token received) 0 = Token and packet processing enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token being executed by the USB module 0 = No token being executed bit 4 USBRST: Module Reset bit(5) 1 = USB reset is generated 0 = USB reset is terminated bit 3 HOSTEN: Host Mode Enable bit(2) 1 = USB host capability is enabled 0 = USB host capability is disabled bit 2 RESUME: RESUME Signaling Enable bit(3) 1 = RESUME signaling is activated 0 = RESUME signaling is disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 11-15). All host control logic is reset any time that the value of this bit is toggled. Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. 2012-2017 Microchip Technology Inc. DS60001185G-page 129 PIC32MX330/350/370/430/450/470 REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks 0 = Even/Odd buffer pointers not being Reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry is enabled 0 = USB module and supporting circuitry is disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token is disabled Note 1: 2: 3: 4: 5: Software is required to check this bit before issuing another token command to the U1TOK register (see Register 11-15). All host control logic is reset any time that the value of this bit is toggled. Software must set the RESUME bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. DS60001185G-page 130 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 LSPDEN: Low Speed Enable Indicator bit 1 = Next token command to be executed at Low Speed 0 = Next token command to be executed at Full Speed bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits REGISTER 11-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 FRML<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. 2012-2017 Microchip Technology Inc. DS60001185G-page 131 PIC32MX330/350/370/430/450/470 REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- -- -- FRMH<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as `0' bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Numbers bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. REGISTER 11-15: U1TOK: USB TOKEN REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID<3:0> EP<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-4 PID<3:0>: Token Type Indicator bits(1) 0001 = OUT (TX) token type transaction 1001 = IN (RX) token type transaction 1101 = SETUP (TX) token type transaction Note: All other values are reserved and must not be used. bit 3-0 EP<3:0>: Token Command Endpoint Address bits The four bit value must specify a valid endpoint. Note 1: All other values are reserved and must not be used. DS60001185G-page 132 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 CNT<7:0>: SOF Threshold Value bits Typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet REGISTER 11-17: U1BDTP1: USB BDT PAGE 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 BDTPTRL<15:9> -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-1 BDTPTRL<15:9>: BDT Base Address bits This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. bit 0 Unimplemented: Read as `0' 2012-2017 Microchip Technology Inc. DS60001185G-page 133 PIC32MX330/350/370/430/450/470 REGISTER 11-18: U1BDTP2: USB BDT PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 BDTPTRH<23:16>: BDT Base Address bits This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. REGISTER 11-19: U1BDTP3: USB BDT PAGE 3 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRU<31:24> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7-0 BDTPTRU<31:24>: BDT Base Address bits This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. DS60001185G-page 134 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 UTEYE UOEMON -- USBSIDL -- -- -- UASUSPND Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern Test is enabled 0 = Eye-Pattern Test is disabled bit 6 UOEMON: USB OE Monitor Enable bit 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive bit 5 Unimplemented: Read as `0' bit 4 USBSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 3-1 Unimplemented: Read as `0' bit 0 UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (U1PWRC<1>) in Register 11-5. 0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock 2012-2017 Microchip Technology Inc. DS60001185G-page 135 PIC32MX330/350/370/430/450/470 REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as `0' bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled; hub required with PRE_PID bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NAKed transactions is disabled 0 = Retry NAKed transactions is enabled; retry done in hardware bit 5 Unimplemented: Read as `0' bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN = 1 and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed Otherwise, this bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint Handshake is enabled 0 = Endpoint Handshake is disabled (typically used for isochronous endpoints) DS60001185G-page 136 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 12.0 Following are key features of the I/O Port module: I/O PORTS Note: * Individual output pin open-drain enable/disable * Individual input pin weak pull-up and pull-down * Monitor selective inputs and generate interrupt when change in pin state is detected * Operation during CPU Sleep and Idle modes * Fast bit manipulation using CLR, SET, and INV registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port. This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS60001120), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). General purpose I/O pins are the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus D PBCLK Q ODC CK EN Q WR ODC 1 RD TRIS 0 I/O Cell 0 1 D Q 1 TRIS CK EN Q 0 WR TRIS Output Multiplexers D Q I/O Pin LAT CK EN Q WR LAT WR PORT RD LAT 1 RD PORT 0 Sleep Q Q D CK Q Q D CK PBCLK Synchronization Peripheral Input Legend: Note: R Peripheral Input Buffer R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. 2012-2017 Microchip Technology Inc. DS60001185G-page 137 PIC32MX330/350/370/430/450/470 12.1 Parallel I/O (PIO) Ports All port pins have ten registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. 12.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the presence of outputs higher than VDD (e.g., 5V) on any desired 5V-tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the "Device Pin Tables" section for the available pins and their functionality. 12.1.2 CONFIGURING ANALOG AND DIGITAL PORT PINS The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRIS bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared. 12.1.3 One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP. 12.1.4 When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. INPUT CHANGE NOTIFICATION The input change notification function of the I/O ports allows the PIC32MX330/350/370/430/450/470 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state. Five control registers are associated with the CN functionality of each I/O port. The CNENx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. Each I/O pin also has a weak pull-up and every I/O pin has a weak pull-down connected to it. The pullups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. Note: The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are analog (not digital) by default. If the TRIS bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or Comparator module. I/O PORT WRITE/READ TIMING Pull-ups and pull-downs on change notification pins should always be disabled when the port pin is configured as a digital output. They should also be disabled on 5V tolerant pins when the pin voltage can exceed VDD. An additional control register (CNCONx) is shown in Register 12-3. 12.2 CLR, SET, and INV Registers Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. DS60001185G-page 138 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 12.3 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only options. Peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to these I/O pins. Peripheral pin select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 12.3.1 AVAILABLE PINS The number of available pins is dependent on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation "RPn" in their full pin designation, where "RP" designates a remappable peripheral and "n" is the remappable port number. 12.3.2 AVAILABLE PERIPHERALS The peripherals managed by the peripheral pin select are all digital-only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. 12.3.3 Peripheral pin select features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped. 12.3.4 INPUT MAPPING The inputs of the peripheral pin select options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 12-1, are used to configure peripheral input mapping (see Register 12-1). Each register contains sets of 4 bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 12-1. For example, Figure 12-2 illustrates the remappable pin selection for the U1RX input. FIGURE 12-2: REMAPPABLE INPUT EXAMPLE FOR U1RX U1RXR<3:0> 0 RPA2 1 In comparison, some digital-only peripheral modules are never included in the peripheral pin select feature. This is because the peripheral's function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). RPB6 A key difference between remappable and non-remappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. RPn 2012-2017 Microchip Technology Inc. CONTROLLING PERIPHERAL PIN SELECT 2 RPA4 U1RX input to peripheral n Note: For input only, peripheral pin select functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to `1'). DS60001185G-page 139 PIC32MX330/350/370/430/450/470 TABLE 12-1: INPUT PIN SELECTION [pin name]R Value to RPn Pin Selection Peripheral Pin [pin name]R SFR [pin name]R bits INT3 INT3R INT3R<3:0> T2CK T2CKR T2CKR<3:0> IC3 IC3R IC3R<3:0> U1RX U1RXR U1RXR<3:0> U2RX U2RXR U2RXR<3:0> U5CTS U5CTSR(3) U5CTSR<3:0> REFCLKI REFCLKIR REFCLKIR<3:0> INT4 INT4R INT4R<3:0> T5CK T5CKR T5CKR<3:0> IC4 IC4R IC4R<3:0> U3RX U3RXR U3RXR<3:0> U4CTS U4CTSR U4CTSR<3:0> SDI1 SDI1R SDI1R<3:0> SDI2 SDI2R SDI2R<3:0> INT2 INT2R INT2R<3:0> T4CK T4CKR T4CKR<3:0> IC2 IC2R IC2R<3:0> IC5 IC5R IC5R<3:0> U1CTS U1CTSR U1CTSR<3:0> U2CTS U2CTSR U2CTSR<3:0> SS1 SS1R SS1R<3:0> Note 1: 2: 3: 4: 0000 = RPD2 0001 = RPG8 0010 = RPF4 0011 = RPD10 0100 = RPF1 0101 = RPB9 0110 = RPB10 0111 = RPC14 1000 = RPB5 1001 = Reserved 1010 = RPC1(3) 1011 = RPD14(3) 1100 = RPG1(3) 1101 = RPA14(3) 1110 = Reserved 1111 = RPF2(1) 0000 = RPD3 0001 = RPG7 0010 = RPF5 0011 = RPD11 0100 = RPF0 0101 = RPB1 0110 = RPE5 0111 = RPC13 1000 = RPB3 1001 = Reserved 1010 = RPC4(3) 1011 = RPD15(3) 1100 = RPG0(3) 1101 = RPA15(3) 1110 = RPF2(1) 1111 = RPF7(2) 0000 = RPD9 0001 = RPG6 0010 = RPB8 0011 = RPB15 0100 = RPD4 0101 = RPB0 0110 = RPE3 0111 = RPB7 1000 = Reserved 1001 = RPF12(3) 1010 = RPD12(3) 1011 = RPF8(3) 1100 = RPC3(3) 1101 = RPE9(3) 1110 = Reserved 1111 = RPB2 This selection is not available on 64-pin USB devices. This selection is only available on 100-pin General Purpose devices. This selection is not available on 64-pin USB and General Purpose devices. This selection is only available on General Purpose devices. DS60001185G-page 140 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 12-1: INPUT PIN SELECTION (CONTINUED) Peripheral Pin [pin name]R SFR [pin name]R bits INT1 INT1R INT1R<3:0> T3CK T3CKR T3CKR<3:0> IC1 IC1R IC1R<3:0> U3CTS U3CTSR U3CTSR<3:0> U4RX U4RXR U4RXR<3:0> U5RX U5RXR(3) U5RXR<3:0> SS2 SS2R SS2R<3:0> OCFA OCFAR OCFAR<3:0> Note 1: 2: 3: 4: [pin name]R Value to RPn Pin Selection 0000 = RPD1 0001 = RPG9 0010 = RPB14 0011 = RPD0 0100 = RPD8 0101 = RPB6 0110 = RPD5 0111 = RPB2 1000 = RPF3(4) 1001 = RPF13(3) 1010 = Reserved 1011 = RPF2(1) 1100 = RPC2(3) 1101 = RPE8(3) 1110 = Reserved 1111 = Reserved This selection is not available on 64-pin USB devices. This selection is only available on 100-pin General Purpose devices. This selection is not available on 64-pin USB and General Purpose devices. This selection is only available on General Purpose devices. 2012-2017 Microchip Technology Inc. DS60001185G-page 141 PIC32MX330/350/370/430/450/470 12.3.5 OUTPUT MAPPING 12.3.6.1 In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 12-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields. The value of the bit field corresponds to one of the peripherals, and that peripheral's output is mapped to the pin (see Table 12-2 and Figure 12-3). A null output is associated with the output register reset value of `0'. This is done to ensure that remappable outputs remain disconnected from all output pins by default. FIGURE 12-3: EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPA0 RPA0R<3:0> Default U1TX Output U1RTS Output 0 1 2 RPA0 Control Register Lock Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit (CFGCON<13>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 12.3.6.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPnR and [pin name]R registers. The IOL1WAY Configuration bit (DEVCFG3<29>) blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Output Data 14 15 12.3.6 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to the peripheral map: * Control register lock sequence * Configuration bit select lock DS60001185G-page 142 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 12-2: OUTPUT PIN SELECTION RPn Port Pin RPnR SFR RPnR bits RPD2 RPD2R RPD2R<3:0> RPG8 RPG8R RPG8R<3:0> RPF4 RPF4R RPF4R<3:0> RPD10 RPD10R RPD10R<3:0> RPF1 RPF1R RPF1R<3:0> RPB9 RPB9R RPB9R<3:0> RPB10 RPB10R RPB10R<3:0> RPC14 RPC14R RPC14R<3:0> RPB5 RPB5R RPB5R<3:0> RPC1(4) RPC1R RPC1R<3:0> RPD14(4) RPD14R RPD14R<3:0> RPG1(4) RPG1R RPG1R<3:0> RPA14(4) RPA14R RPA14R<3:0> RPD3 RPD3R RPD3R<3:0> RPG7 RPG7R RPG7R<3:0> RPF5 RPF5R RPF5R<3:0> RPD11 RPD11R RPD11R<3:0> RPF0 RPF0R RPF0R<3:0> RPB1 RPB1R RPB1R<3:0> RPE5 RPE5R RPE5R<3:0> RPC13 RPC13R RPC13R<3:0> RPB3 RPB3R RPB3R<3:0> RPF3(2) RPF3R RPF3R<3:0> RPC4(4) RPC4R RPC4R<3:0> RPD15(4) RPD15R RPD15R<3:0> RPG0(4) RPG0R RPG0R<3:0> (4) RPA15R RPA15R<3:0> RPA15 Note 1: 2: 3: 4: 5: RPnR Value to Peripheral Selection 0000 = No Connect 0001 = U3TX 0010 = U4RTS 0011 = Reserved 0100 = Reserved 0101 = Reserved 0110 = SDO2 0111 = Reserved 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = OC3 1100 = Reserved 1101 = C2OUT 1110 = Reserved 1111 = Reserved 0000 = No Connect 0001 = U2TX 0010 = Reserved 0011 = U1TX 0100 = U5RTS(4) 0101 = Reserved 0110 = SDO2 0111 = Reserved 1000 = SDO1 1001 = Reserved 1010 = Reserved 1011 = OC4 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved This selection is only available on General Purpose devices. This selection is only available on 64-pin General Purpose devices. This selection is only available on 100-pin General Purpose devices. This selection is only available on 100-pin USB and General Purpose devices. This selection is not available on 64-pin USB devices. 2012-2017 Microchip Technology Inc. DS60001185G-page 143 PIC32MX330/350/370/430/450/470 TABLE 12-2: OUTPUT PIN SELECTION (CONTINUED) RPn Port Pin RPnR SFR RPnR bits RPD9 RPD9R RPD9R<3:0> RPG6 RPG6R RPG6R<3:0> RPB8 RPB8R RPB8R<3:0> RPB15 RPB15R RPB15R<3:0> RPD4 RPD4R RPD4R<3:0> RPB0 RPB0R RPB0R<3:0> RPE3 RPE3R RPE3R<3:0> RPB7 RPB7R RPB7R<3:0> RPB2 RPB2R RPB2R<3:0> RPF12(4) RPF12R RPF12R<3:0> RPD12(4) RPD12R RPD12R<3:0> RPF8(4) RPF8R RPF8R<3:0> RPC3(4) RPC3R RPC3R<3:0> RPE9(4) RPE9R RPE9R<3:0> RPD1 RPD1R RPD1R<3:0> RPG9 RPG9R RPG9R<3:0> RPB14 RPB14R RPB14R<3:0> RPD0 RPD0R RPD0R<3:0> RPD8 RPD8R RPD8R<3:0> RPB6 RPB6R RPB6R<3:0> RPD5 RPD5R RPD5R<3:0> RPF3(3) RPF3R RPF3R<3:0> RPF6(1) RPF6R RPF6R<3:0> RPF13(4) RPF13R RPF13R<3:0> RPC2(4) RPC2R RPC2R<3:0> RPE8(4) RPE8R RPE8R<3:0> RPF2(5) RPF2R RPF2R<3:0> Note 1: 2: 3: 4: 5: RPnR Value to Peripheral Selection 0000 = No Connect 0001 = U3RTS 0010 = U4TX 0011 = REFCLKO 0100 = U5TX(4) 0101 = Reserved 0110 = Reserved 0111 = SS1 1000 = SDO1 1001 = Reserved 1010 = Reserved 1011 = OC5 1100 = Reserved 1101 = C1OUT 1110 = Reserved 1111 = Reserved 0000 = No Connect 0001 = U2RTS 0010 = Reserved 0011 = U1RTS 0100 = U5TX(4) 0101 = Reserved 0110 = SS2 0111 = Reserved 1000 = SDO1 1001 = Reserved 1010 = Reserved 1011 = OC2 1100 = OC1 1101 = Reserved 1110 = Reserved 1111 = Reserved This selection is only available on General Purpose devices. This selection is only available on 64-pin General Purpose devices. This selection is only available on 100-pin General Purpose devices. This selection is only available on 100-pin USB and General Purpose devices. This selection is not available on 64-pin USB devices. DS60001185G-page 144 2012-2017 Microchip Technology Inc. Control Registers ANSELA 6010 6030 6040 6050 6060 PORTA LATA ODCA CNPUA CNPDA 6070 CNCONA 6080 CNENA Legend: Note 1: 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- 0060 -- -- -- -- -- -- -- -- -- -- 0000 TRISA10 TRISA9 -- TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 xxxx 0000 30/14 29/13 28/12 27/11 31:16 -- -- -- -- -- 15:0 -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- 15:0 TRISA15 TRISA14 ANSELA10 ANSELA9 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 RA15 RA14 -- -- -- RA10 RA9 -- RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 LATA15 LATA14 -- -- -- LATA10 LATA9 -- LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- ODCA10 ODCA9 -- ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CNPUA15 CNPUA14 -- -- -- 31:16 -- -- -- -- -- -- 15:0 31:16 ODCA15 ODCA14 -- -- -- -- 15:0 CNPDA15 CNPDA14 CNPUA10 CNPUA9 -- -- CNPDA10 CNPDA9 -- -- -- CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 xxxx -- -- -- -- -- -- -- -- 0000 CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- CNIEA10 CNIEA9 -- CNIEA7 CNIEA6 CNIEA5 CNIEA4 CNIEA3 CNIEA2 CNIEA1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- CN STATA10 CN STATA9 -- CN STATA7 CN STATA6 CN STATA5 CN STATA4 CN STATA3 CN STATA2 CN STATA1 CN STATA0 xxxx 15:0 31:16 6090 CNSTATA 26/10 31/15 15:0 CNIEA15 CNIEA14 -- -- CN CN STATA15 STATA14 -- -- CNIEA0 xxxx DS60001185G-page 145 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 6020 TRISA Bits All Resets 6000 PORTA REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY Bit Range Register Name(1) TABLE 12-3: Virtual Address (BF88_#) 2012-2017 Microchip Technology Inc. 12.4 6100 ANSELB 6110 TRISB 6120 PORTB 6130 LATB 6140 ODCB 6150 CNPUB 6160 CNPDB 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ANSELB15 ANSELB14 ANSELB13 ANSELB12 ANSELB11 ANSELB10 ANSELB9 ANSELB8 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 31:16 -- -- -- -- -- -- -- -- -- -- -- 15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 -- CNPDB4 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) PORTB REGISTER MAP 0000 FFFF 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx -- -- -- -- 0000 CNPDB3 CNPDB2 CNPDB1 CNPDB0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6180 CNENB 15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6190 CNSTATB CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN 15:0 xxxx STATB15 STATB14 STATB13 STATB12 STATB11 STATB10 STATB9 STATB8 STATB7 STATB6 STATB5 STATB4 STATB3 STATB2 STATB1 STATB0 Legend: x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 6170 CNCONB PIC32MX330/350/370/430/450/470 DS60001185G-page 146 TABLE 12-4: 2012-2017 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 6210 TRISC 6220 PORTC 6230 LATC 6240 ODCC 6250 CNPUC PORTC REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- TRISC15 -- RC15 -- LATC15 -- ODCC15 -- CNPUC15 -- TRISC14 -- RC14 -- LATC14 -- ODCC14 -- CNPUC14 -- TRISC13 -- RC13 -- LATC13 -- ODCC13 -- CNPUC13 -- TRISC12 -- RC12 -- LATC12 -- ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISC4 -- RC4 -- LATC4 -- ODCC4 -- -- TRISC3 -- RC3 -- LATC3 -- ODCC3 -- -- TRISC2 -- RC2 -- LATC2 -- ODCC2 -- -- TRISC1 -- RC1 -- LATC1 -- ODCC1 -- -- -- -- -- -- -- -- -- -- 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 CNPUC12 -- -- -- -- -- -- -- CNPUC4 CNPUC3 CNPUC2 CNPUC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6260 CNPDC 15:0 CNPDC15 CNPDC14 CNPDC13 CNPDC12 -- -- -- -- -- -- -- CNPDC4 CNPDC3 CNPDC2 CNPDC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6270 CNCONC 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6280 CNENC 15:0 CNIEC15 CNIEC14 CNIEC13 CNIEC12 -- -- -- -- -- -- -- CNIEC4 CNIEC3 CNIEC2 CNIEC1 -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6290 CNSTATC 15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 -- -- -- -- -- -- -- CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1 -- xxxx Legend: x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. DS60001185G-page 147 PIC32MX330/350/370/430/450/470 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 All Resets Bits Bit Range 2012-2017 Microchip Technology Inc. TABLE 12-5: Virtual Address (BF88_#) Register Name(1) 6210 TRISC 6220 PORTC 6230 LATC 6240 ODCC 6250 CNPUC 6260 CNPDC PORTC REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits -- TRISC15 -- RC15 -- LATC15 -- ODCC15 -- CNPUC15 -- CNPDC15 -- TRISC14 -- RC14 -- LATC14 -- ODCC14 -- CNPUC14 -- CNPDC14 -- TRISC13 -- RC13 -- LATC13 -- ODCC13 -- CNPUC13 -- CNPDC13 -- TRISC12 -- RC12 -- LATC12 -- ODCC12 -- CNPUC12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 CNPDC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6270 CNCONC 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6280 CNENC 15:0 CNIEC15 CNIEC14 CNIEC13 CNIEC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6290 CNSTATC 15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 -- -- -- -- -- -- -- -- -- -- -- -- xxxx Legend: x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 148 TABLE 12-6: 2012-2017 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 6300 ANSELD 6310 TRISD 5320 PORTD 6330 LATD 6340 ODCD PORTD REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY 31/15 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- -- -- TRISD14 -- RD14 -- LATD14 -- ODCD14 -- -- -- TRISD13 -- RD13 -- LATD13 -- ODCD13 -- -- -- TRISD12 -- RD12 -- LATD12 -- ODCD12 -- -- -- TRISD11 -- RD11 -- LATD11 -- ODCD11 -- -- -- TRISD10 -- RD10 -- LATD10 -- ODCD10 -- -- -- TRISD9 -- RD9 -- LATD9 -- ODCD9 -- -- -- TRISD8 -- RD8 -- LATD8 -- ODCD8 -- -- -- TRISD7 -- RD7 -- LATD7 -- ODCD7 -- -- -- TRISD6 -- RD6 -- LATD6 -- ODCD6 -- -- -- TRISD5 -- RD5 -- LATD5 -- ODCD5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- 0000 -- ANSELD3 ANSELD2 ANSELD1 -- 000E -- -- -- -- -- 0000 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 xxxx -- -- -- -- -- 0000 RD4 RD3 RD2 RD1 RD0 xxxx -- -- -- -- -- 0000 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx -- -- -- -- -- 0000 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6360 CNPDD 15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6370 CNCOND 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6380 CNEND 15:0 CNIED15 CNIED14 CNIED13 CNIED12 CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6390 CNSTATD CNS CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN 15:0 xxxx TATD15 STATD14 STATD13 STATD12 STATD11 STATD10 STATD9 STATD8 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0 Legend: x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 6350 CNPUD DS60001185G-page 149 PIC32MX330/350/370/430/450/470 31:16 -- 15:0 -- 31:16 -- 15:0 TRISD15 31:16 -- 15:0 RD15 31:16 -- 15:0 LATD15 31:16 -- 15:0 ODCD15 30/14 All Resets Bits Bit Range 2012-2017 Microchip Technology Inc. TABLE 12-7: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISD11 -- RD11 -- LATD11 -- ODCD11 -- -- -- -- TRISD10 -- RD10 -- LATD10 -- ODCD10 -- -- -- -- TRISD9 -- RD9 -- LATD9 -- ODCD9 -- -- -- -- TRISD8 -- RD8 -- LATD8 -- ODCD8 -- -- -- -- TRISD7 -- RD7 -- LATD7 -- ODCD7 -- -- -- -- TRISD6 -- RD6 -- LATD6 -- ODCD6 -- -- -- -- TRISD5 -- RD5 -- LATD5 -- ODCD5 -- 15:0 31:16 6360 CNPDD 15:0 31:16 6370 CNCOND 15:0 31:16 6380 CNEND 15:0 31:16 6390 CNSTATD 15:0 -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- 6300 ANSELD 6310 TRISD 5320 PORTD 6330 LATD 6340 ODCD 6350 CNPUD Legend: Note 1: 20/4 19/3 18/2 17/1 -- -- -- -- -- ANSELD3 ANSELD2 ANSELD1 -- -- -- -- TRISD4 TRISD3 TRISD2 TRISD1 -- -- -- -- RD4 RD3 RD2 RD1 -- -- -- -- LATD4 LATD3 LATD2 LATD1 -- -- -- -- ODCD4 ODCD3 ODCD2 ODCD1 -- -- -- -- 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) PORTD REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, PIC32MX470F512H DEVICES ONLY -- -- -- TRISD0 -- RD0 -- LATD0 -- ODCD0 -- 0000 000E 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 CNPUD11 CNPUD10 CNPUD9 CNPUD8 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNPDD11 CNPDD10 CNPDD9 CNPDD8 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNIED11 CNIED10 CNIED9 CNIED8 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN CN CN -- -- -- -- xxxx STATD11 STATD10 STATD9 STATD8 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 150 TABLE 12-8: 2012-2017 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 6400 ANSELE 6410 TRISE 6420 PORTE 6440 LATE 6440 ODCE PORTE REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, PIC32MX470F512L DEVICES ONLY 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISE9 -- RE9 -- LATE9 -- -- -- -- TRISE8 -- RE8 -- LATE8 -- 15:0 31:16 6450 CNPUE 15:0 31:16 6460 CNPDE 15:0 31:16 6470 CNCONE 15:0 31:16 6480 CNENE 15:0 31:16 6490 CNSTATE 15:0 -- -- -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Legend: Note 1: 23/7 22/6 21/5 20/4 -- -- -- -- ANSELE7 ANSELE6 ANSELE5 ANSELE4 -- -- -- -- TRISE7 TRISE6 TRISE5 TRISE4 -- -- -- -- RE7 RE6 RE5 RE4 -- -- -- -- LATE7 LATE6 LATE5 LATE4 -- -- -- -- 19/3 18/2 17/1 16/0 -- -- -- TRISE3 -- RE3 -- LATE3 -- -- ANSELE2 -- TRISE2 -- RE2 -- LATE2 -- -- -- -- TRISE1 -- RE1 -- LATE1 -- -- -- -- TRISE0 -- RE0 -- LATE0 -- 0000 00F4 0000 xxxx 0000 xxxx 0000 xxxx 0000 ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 xxxx -- -- -- -- -- -- -- -- -- -- 0000 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 xxxx -- -- -- -- -- -- -- -- -- -- 0000 CNPDE9 CNPDE8 CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 xxxx -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- 0000 CNIEE9 CNIEE8 CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 xxxx -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN -- -- -- -- -- -- xxxx STATE9 STATE8 STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. DS60001185G-page 151 PIC32MX330/350/370/430/450/470 31/15 All Resets Bits Bit Range 2012-2017 Microchip Technology Inc. TABLE 12-9: Virtual Address (BF88_#) Register Name(1) 6400 ANSELE 6410 TRISE 6420 PORTE 6440 LATE 6440 ODCE 6450 CNPUE 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ANSELE7 ANSELE6 ANSELE5 ANSELE4 -- -- -- -- TRISE7 TRISE6 TRISE5 TRISE4 -- -- -- -- RE7 RE6 RE5 RE4 -- -- -- -- LATE7 LATE6 LATE5 LATE4 -- -- -- -- ODCE7 ODCE6 ODCE5 ODCE4 -- -- -- -- 15:0 31:16 6460 CNPDE 15:0 31:16 6470 CNCONE 15:0 31:16 6480 CNENE 15:0 31:16 6490 CNSTATE 15:0 -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUE7 -- CNPDE7 -- -- -- CNIEE7 -- Legend: Note 1: 23/7 22/6 CNPUE6 -- CNPDE6 -- -- -- CNIEE6 -- CN STATE6 21/5 CNPUE5 -- CNPDE5 -- -- -- CNIEE5 -- CN STATE5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits -- -- -- TRISE3 -- RE3 -- LATE3 -- ODCE3 -- -- ANSELE2 -- TRISE2 -- RE2 -- LATE2 -- ODCE2 -- -- -- -- TRISE1 -- RE1 -- LATE1 -- ODCE1 -- -- -- -- TRISE0 -- RE0 -- LATE0 -- ODCE0 -- 0000 00F4 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 CNPUE4 CNPDE3 CNPUE2 CNPUE1 CNPUE0 xxxx -- -- -- -- -- 0000 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 xxxx -- -- -- -- -- 0000 -- -- -- -- -- 0000 -- -- -- -- -- 0000 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 xxxx -- -- -- -- -- 0000 CN CN CN CN CN xxxx STATE4 STATE3 STATE2 STATE1 STATE0 CN STATE7 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. -- -- -- -- -- -- -- -- PIC32MX330/350/370/430/450/470 DS60001185G-page 152 TABLE 12-10: PORTE REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY 2012-2017 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF Bits 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF13 -- RF13 -- LATF13 -- ODCF13 -- -- TRISF12 -- RF12 -- LATF12 -- ODCF12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF8 -- RF8 -- LATF8 -- ODCF8 -- -- TRISF7 -- RF7 -- LATF7 -- ODCF7 -- -- TRISF6 -- RF6 -- LATF6 -- ODCF6 -- -- TRISF5 -- RF5 -- LATF5 -- ODCF5 -- -- TRISF4 -- RF4 -- LATF4 -- ODCF4 -- -- TRISF3 -- RF3 -- LATF3 -- ODCF3 -- -- TRISF2 -- RF2 -- LATF2 -- ODCF2 -- -- TRISF1 -- RF1 -- LATF1 -- ODCF1 -- -- TRISF0 -- RF0 -- LATF0 -- ODCF0 -- 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 15:0 31:16 6560 CNPDF 15:0 31:16 6570 CNCONF 15:0 31:16 6580 CNENF 15:0 31:16 6590 CNSTATF 15:0 -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- -- Legend: Note 1: CNPUF13 CNPUF12 -- -- -- CNPUF8 CNPUF7 CNPUF6 CNPUF5 CNPUF4 CNPDF3 CNPUF2 CNPUF1 CNPUF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNPDF13 CNPDF12 -- -- -- CNPDF8 CNPDF7 CNPDF6 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNIEF13 CNIEF12 -- -- -- CNIEF8 CNIEF7 -- CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN CN -- -- -- -- -- -- xxxx STATF13 STATF12 STATF8 STATF7 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. DS60001185G-page 153 PIC32MX330/350/370/430/450/470 31/15 All Resets Bit Range 2012-2017 Microchip Technology Inc. TABLE 12-11: PORTF REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, AND PIC32MX370F512L DEVICES ONLY Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF 6560 CNPDF 31/15 30/14 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 6570 CNCONF 15:0 31:16 6580 CNENF 15:0 31:16 6590 CNSTATF 15:0 -- -- ON -- -- -- -- -- -- -- -- -- Legend: Note 1: 29/13 28/12 -- -- TRISF13 TRISF12 -- -- RF13 RF12 -- -- LATF13 LATF12 -- -- ODCF13 ODCF12 -- -- CNPUF13 CNPUF12 -- -- 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF8 -- RF8 -- LATF8 -- ODCF8 -- CNPUF8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF5 -- RF5 -- LATF5 -- ODCF5 -- CNPUF5 -- -- TRISF4 -- RF4 -- LATF4 -- ODCF4 -- CNPUF4 -- -- TRISF3 -- RF3 -- LATF3 -- ODCF3 -- CNPDF3 -- -- TRISF2 -- RF2 -- LATF2 -- ODCF2 -- CNPUF2 -- -- TRISF1 -- RF1 -- LATF1 -- ODCF1 -- CNPUF1 -- -- TRISF0 -- RF0 -- LATF0 -- ODCF0 -- CNPUF0 -- 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 CNPDF13 CNPDF12 -- -- -- CNPDF8 -- -- CNPDF5 CNPFF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CNIEF13 CNIEF12 -- -- -- CNIEF8 -- -- CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 xxxx -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN CN CN CN -- -- -- -- -- -- -- xxxx STATF8 STATF13 STATF12 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 154 TABLE 12-12: PORTF REGISTER MAP FOR PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY 2012-2017 Microchip Technology Inc. Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF Bits 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF6 -- RF6 -- LATF6 -- ODCF6 -- -- TRISF5 -- RF5 -- LATF5 -- ODCF5 -- -- TRISF4 -- RF4 -- LATF4 -- ODCF4 -- -- TRISF3 -- RF3 -- LATF3 -- ODCF3 -- -- TRISF2 -- RF2 -- LATF2 -- ODCF2 -- -- TRISF1 -- RF1 -- LATF1 -- ODCF1 -- -- TRISF0 -- RF0 -- LATF0 -- ODCF0 -- 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 15:0 31:16 6560 CNPDF 15:0 31:16 6570 CNCONF 15:0 31:16 6580 CNENF 15:0 31:16 6590 CNSTATF 15:0 -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUF6 -- CNPDF6 -- -- -- -- -- CNPUF5 -- CNPDF5 -- -- -- CNIEF5 -- -- -- -- -- -- -- -- -- -- CN STATF5 CNPUF3 -- CNPDF3 -- -- -- CNIEF3 -- CN STATF3 CNPUF2 -- CNPDF2 -- -- -- CNIEF2 -- CN STATF2 CNPUF1 -- CNPDF1 -- -- -- CNIEF1 -- CN STATF1 CNPUF0 -- CNPDF0 -- -- -- CNIEF0 -- CN STATF0 xxxx 0000 xxxx 0000 0000 0000 xxxx 0000 -- CNPUF4 -- CNPDF4 -- -- -- CNIEF4 -- CN STATF4 Legend: Note 1: xxxx x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. DS60001185G-page 155 PIC32MX330/350/370/430/450/470 31/15 All Resets Bit Range 2012-2017 Microchip Technology Inc. TABLE 12-13: PORTF REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, AND PIC32MX370F512H DEVICES ONLY Virtual Address (BF88_#) Register Name(1) 6510 TRISF 6520 PORTF 6530 LATF 6540 ODCF 6550 CNPUF 6560 CNPDF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF5 -- RF5 -- LATF5 -- ODCF5 -- CNPUF5 -- -- TRISF4 -- RF4 -- LATF4 -- ODCF4 -- CNPUF4 -- -- TRISF3 -- RF3 -- LATF3 -- ODCF3 -- CNPUF3 -- -- -- -- -- -- -- -- -- -- -- -- -- TRISF1 -- RF1 -- LATF1 -- ODCF1 -- CNPUF1 -- -- TRISF0 -- RF0 -- LATF0 -- ODCF0 -- CNPUF0 -- 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 15:0 31:16 6570 CNCONF 15:0 31:16 6580 CNENF 15:0 31:16 6590 CNSTATF 15:0 -- -- ON -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPDF5 -- -- -- CNIEF5 -- CNPDF1 -- -- -- CNIEF1 -- -- -- -- -- -- -- -- -- CN STATF5 -- CN STATF1 CNPDF0 -- -- -- CNIEF0 -- CN STATF0 xxxx 0000 0000 0000 xxxx 0000 -- CNPDF3 -- -- -- CNIEF3 -- CN STATF3 -- -- -- -- -- -- -- CNPDF4 -- -- -- CNIEF4 -- CN STATF4 Legend: Note 1: xxxx x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 156 TABLE 12-14: PORTF REGISTER MAP FOR PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY 2012-2017 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF88_#) 2012-2017 Microchip Technology Inc. TABLE 12-15: PORTG REGISTER MAP FOR PIC32MX330F064L, PIC32MX350F128L, PIC32MX350F256L, PIC32MX370F512L, PIC32MX430F064L, PIC32MX450F128L, PIC32MX450F256L, AND PIC32MX470F512L DEVICES ONLY 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- ANSELG9 ANSELG8 ANSELG7 ANSELG6 -- -- -- -- -- -- 01C0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6610 TRISG 15:0 TRISG15 TRISG14 TRISG13 TRISG12 -- -- TRISG9 TRISG8 TRISG7 TRISG6 -- -- TRISG3 TRISG2 TRISG1 TRISG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6620 PORTG 15:0 RG15 RG14 RG13 RG12 -- -- RG9 RG8 RG7 RG6 -- -- RG3(2) RG2(2) RG1 RG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6630 LATG 15:0 LATG15 LATG14 LATG13 LATG12 -- -- LATG9 LATG8 LATG7 LATG6 -- -- LATG3 LATG2 LATG1 LATG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6640 ODCG 15:0 ODCG15 ODCG14 ODCG13 ODCG12 -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 ODCG1 ODCG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6650 CNPUG 15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12 -- -- CNPUG9 CNPUG8 CNPUG7 CNPUG6 -- -- CNPUG3 CNPUG2 CNPUG1 CNPUG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6660 CNPDG 15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12 -- -- CNPDG9 CNPDG8 CNPDG7 CNPDG6 -- -- CNPDG3 CNPDG2 CNPDG1 CNPDG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6670 CNCONG 15:0 ON -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6680 CNENG 15:0 CNIEG15 CNIEG14 CNIEG13 CNIEG12 -- -- CNIEG9 CNIEG8 CNIEG7 CNIEG6 -- -- CNIEG3 CNIEG2 CNIEG1 CNIEG0 xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 6690 CNSTATG CN CN CN CN CN CN CN CN CN CN CN CN 15:0 -- -- -- -- xxxx STATG15 STATG14 STATG13 STATG12 STATG8 STATG7 STATG6 STATG9 STATG3 STATG2 STATG1 STATG0 Legend: x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 2: This bit only implemented on devices without a USB module. 6600 ANSELG PIC32MX330/350/370/430/450/470 DS60001185G-page 157 31/15 30/14 29/13 28/12 27/11 26/10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ANSELG9 ANSELG8 ANSELG7 ANSELG6 -- -- -- -- TRISG9 TRISG8 TRISG7 TRISG6 -- -- -- -- RG9 RG8 RG7 RG6 -- -- -- -- LATG9 LATG8 LATG7 LATG6 -- -- -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- -- -- 15:0 31:16 6660 CNPDG 15:0 31:16 6670 CNCONG 15:0 31:16 6680 CNENG 15:0 31:16 6690 CNSTATG 15:0 -- -- -- -- ON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNPUG9 -- CNPDG9 -- -- -- CNIEG9 -- 6600 ANSELG 6610 TRISG 6620 PORTG 6630 LATG 6640 ODCG 6650 CNPUG Legend: Note 1: 2012-2017 Microchip Technology Inc. 2: 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF88_#) Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRISG3 -- RG3(2) -- LATG3 -- ODCG3 -- -- -- -- TRISG2 -- RG2(2) -- LATG2 -- ODCG2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 01C0 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 CNPUG8 CNPUG7 CNPUG6 -- -- CNPUG3 CNPUG2 -- -- xxxx -- -- -- -- -- -- -- -- -- 0000 CNPDG8 CNPDG7 CNPDG6 -- -- CNPDG3 CNPDG2 -- -- xxxx -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- 0000 CNIEG8 CNIEG7 CNIEG6 -- -- CNIEG3 CNIEG2 -- -- xxxx -- -- -- -- -- -- -- -- -- 0000 CN CN CN CN CN CN -- -- -- -- -- -- -- -- -- -- xxxx STATG8 STATG7 STATG6 STATG9 STATG3 STATG2 x = Unknown value on Reset; -- = Unimplemented, read as `0'; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. This bit is only available on devices without a USB module. PIC32MX330/350/370/430/450/470 DS60001185G-page 158 TABLE 12-16: PORTG REGISTER MAP FOR PIC32MX330F064H, PIC32MX350F128H, PIC32MX350F256H, PIC32MX370F512H, PIC32MX430F064H, PIC32MX450F128H, PIC32MX450F256H, AND PIC32MX470F512H DEVICES ONLY Register Name FA04 INT1R FA08 INT2R FA0C INT3R FA10 INT4R FA18 T2CKR FA1C T3CKR FA20 T4CKR FA24 T5CKR FA28 IC1R FA2C IC2R FA30 IC3R FA34 IC4R FA38 IC5R FA48 OCFAR FA50 U1RXR Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register is not available on 64-pin devices. INT1R<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U1RXR<3:0> 0000 0000 -- OCFAR<3:0> -- 0000 0000 IC5R<3:0> -- 0000 0000 IC4R<3:0> -- 0000 0000 IC3R<3:0> -- 0000 0000 IC2R<3:0> -- 0000 0000 IC1R<3:0> -- 0000 0000 T5CKR<3:0> -- 0000 0000 T4CKR<3:0> -- 0000 0000 T3CKR<3:0> -- 0000 0000 T2CKR<3:0> -- 0000 0000 INT4R<3:0> -- 0000 0000 INT3R<3:0> -- 0000 0000 INT2R<3:0> -- All Resets Bit Range Bits 0000 0000 -- 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 159 Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. TABLE 12-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP Virtual Address (BF80_#) Register Name FA54 U1CTSR FA58 U2RXR FA5C U2CTSR FA60 U3RXR FA64 U3CTSR FA68 U4RXR FA6C U4CTSR FA70 U5RXR(1) FA74 U5CTSR(1) 2012-2017 Microchip Technology Inc. FA84 SDI1R FA88 SS1R FA90 SDI2R FA94 SS2R FAD0 REFCLKIR Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- 31:16 -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- -- -- -- -- x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register is not available on 64-pin devices. 18/2 17/1 16/0 -- -- -- U1CTSR<3:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- REFCLKIR<3:0> 0000 0000 -- SS2R<3:0> -- 0000 0000 SDI2R<3:0> -- 0000 0000 SS1R<3:0> -- 0000 0000 SDI1R<3:0> -- 0000 0000 U5CTSR<3:0> -- 0000 0000 U5RXR<3:0> -- 0000 0000 U4CTSR<3:0> -- 0000 0000 U4RXR<3:0> -- 0000 0000 U3CTSR<3:0> -- 0000 0000 U3RXR<3:0> -- 0000 0000 U2CTSR<3:0> -- 0000 0000 U2RXR<3:0> -- All Resets Bit Range Bits 0000 0000 -- 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 160 TABLE 12-17: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 RPA14R(1) 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18/2 17/1 -- -- RPA14<3:0> -- -- RPA15<3:0> -- -- RPB0<3:0> -- -- RPB1<3:0> -- -- RPB2<3:0> -- -- RPB3<3:0> -- -- RPB5<3:0> -- -- RPB6<3:0> -- -- RPB7<3:0> -- -- RPB8<3:0> -- -- RPB9<3:0> -- -- RPB10<3:0> -- -- RPB14<3:0> -- -- RPB15<3:0> -- -- RPC1<3:0> -- -- RPC2<3:0> -- -- RPC3<3:0> 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 161 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- (1) 31:16 FB3C RPA15R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB40 RPB0R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB44 RPB1R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB48 RPB2R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB4C RPB3R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB54 RPB5R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB58 RPB6R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB5C RPB7R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB60 RPB8R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB64 RPB9R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB68 RPB10R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB78 RPB14R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FB7C RPB15R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FB84 RPC1R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FB88 RPC2R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FB8C RPC3R -- -- -- -- -- -- -- -- 15:0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is only available on devices without a USB module. 3: This register is not available on 64-pin devices with a USB module. FB38 23/7 All Resets Bit Range Bits Register Name Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. TABLE 12-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 2012-2017 Microchip Technology Inc. 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBB4 RPC13R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBB8 RPC14R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBC0 RPD0R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBC4 RPD1R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBC8 RPD2R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBCC RPD3R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBD0 RPD4R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBD4 RPD5R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBE0 RPD8R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBE4 RPD9R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBE8 RPD10R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FBEC RPD11R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- (1) 31:16 FBF0 RPD12R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- (1) 31:16 FBF8 RPD14R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- (1) 31:16 FBFC RPD15R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC0C RPE3R -- -- -- -- -- -- -- -- 15:0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is only available on devices without a USB module. 3: This register is not available on 64-pin devices with a USB module. FB90 RPC4R(1) 23/7 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18/2 17/1 -- -- RPC4<3:0> -- -- RPC13<3:0> -- -- RPC14<3:0> -- -- RPD0<3:0> -- -- RPD1<3:0> -- -- RPD2<3:0> -- -- RPD3<3:0> -- -- RPD4<3:0> -- -- RPD5<3:0> -- -- RPD8<3:0> -- -- RPD9<3:0> -- -- RPD10<3:0> -- -- RPD11<3:0> -- -- RPD12<3:0> -- -- RPD14<3:0> -- -- RPD15<3:0> -- -- RPE3<3:0> 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 162 TABLE 12-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 RPE5R 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18/2 17/1 -- -- RPE5<3:0> -- -- RPE8<3:0> -- -- RPE9<3:0> -- -- RPF0<3:0> -- -- RPF1<3:0> -- -- RPF2<3:0> -- -- RPF3<3:0> -- -- RPF4<3:0> -- -- RPF5<3:0> -- -- RPF6<3:0> -- -- RPF8<3:0> -- -- RPF12<3:0> -- -- RPF13<3:0> -- -- RPG0<3:0> -- -- RPG1<3:0> -- -- RPG6<3:0> -- -- RPG7<3:0> 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 163 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FC20 RPE8R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FC24 RPE9R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC40 RPF0R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC44 RPF1R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (3) FC48 RPF2R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (2) FC4C RPF3R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC50 RPF4R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC54 RPF5R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (2) FC58 RPF6R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FC60 RPF8R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- (1) 31:16 FC70 RPF12R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- (1) 31:16 FC74 RPF13R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FC80 RPG0R -- -- -- -- -- -- -- -- 15:0 31:16 -- -- -- -- -- -- -- -- (1) FC84 RPG1R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC98 RPG6R -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FC9C RPG7R -- -- -- -- -- -- -- -- 15:0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is only available on devices without a USB module. 3: This register is not available on 64-pin devices with a USB module. FC14 23/7 All Resets Bit Range Bits Register Name Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. TABLE 12-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- -- 31:16 FCA4 RPG9R -- -- -- -- -- -- -- -- 15:0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is only available on devices without a USB module. 3: This register is not available on 64-pin devices with a USB module. FCA0 RPG8R 23/7 22/6 21/5 20/4 19/3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 18/2 17/1 -- -- RPG8<3:0> -- -- RPG9<3:0> 16/0 -- -- All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 164 TABLE 12-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- [pin name]R<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as `0' bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 12-1 for input pin selection values. Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0. REGISTER 12-2: Bit Range 31:24 23:16 15:8 7:0 RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- RPnR<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-4 Unimplemented: Read as `0' bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits See Table 12-2 for output pin selection values. Note: x = Bit is unknown Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0. 2012-2017 Microchip Technology Inc. DS60001185G-page 165 PIC32MX330/350/370/430/450/470 REGISTER 12-3: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A - G) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 U-0 -- R/W-0 U-0 U-0 U-0 U-0 U-0 ON -- SIDL -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = CPU Idle Mode halts CN operation 0 = CPU Idle does not affect CN operation bit 12-0 Unimplemented: Read as `0' DS60001185G-page 166 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 13.0 The following modes are supported: TIMER1 Note: * * * * This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). 13.1 Additional Supported Features * Selectable clock prescaler * Timer operation during CPU Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) This family of PIC32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a freerunning interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. FIGURE 13-1: Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer TIMER1 BLOCK DIAGRAM Data Bus<31:0> TSYNC <15:0> 1 Reset Sync TMR1 0 Equal 16-bit Comparator PR1 T1IF Event Flag 0 Q 1 TGATE D Q TGATE TCS ON SOSCO/T1CK x1 SOSCEN SOSCI Gate Sync PBCLK 10 00 Prescaler 1, 8, 64, 256 2 TCKPS<1:0> Note: The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1. 2012-2017 Microchip Technology Inc. DS60001185G-page 167 Control Registers TIMER1 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 13-1: 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- SIDL TWDIS TWIP -- -- -- TGATE -- TCKPS<1:0> -- TSYNC TCS -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0610 TMR1 15:0 TMR1<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0620 PR1 15:0 PR1<15:0> FFFF Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 0600 T1CON PIC32MX330/350/370/430/450/470 DS60001185G-page 168 13.2 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON -- SIDL TWDIS TWIP -- -- -- R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE -- -- TSYNC TCS -- TCKPS<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Timer On bit(1) 1 = Timer is enabled 0 = Timer is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode bit 12 TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) bit 11 TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as `0'. bit 10-8 Unimplemented: Read as `0' bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Unimplemented: Read as `0' bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 169 PIC32MX330/350/370/430/450/470 REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored. bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001185G-page 170 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 14.0 Note: Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: TIMER2/3, TIMER4/5 This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). * Synchronous internal 32-bit timer * Synchronous internal 32-bit gated timer * Synchronous external 32-bit timer Note: The PIC32MX330/350/370/430/450/470 family of devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: 14.1 Additional Supported Features * Selectable clock prescaler * Timers operational during CPU idle * Time base for Input Capture and Output Compare modules (Timer2 and Timer3 only) * ADC event trigger (Timer3 in 16-bit mode, Timer2/ 3 in 32-bit mode) * Fast bit manipulation using CLR, SET, and INV registers * Synchronous internal 16-bit timer * Synchronous internal 16-bit gated timer * Synchronous external 16-bit timer FIGURE 14-1: In this chapter, references to registers, TxCON, TMRx and PRx, use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5. TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) Data Bus<31:0> <15:0> Reset ADC Event Trigger(1) Equal Sync TMRx Comparator x 16 PRx TxIF Event Flag 0 1 TGATE Q TGATE D Q TCS ON TxCK x1 Gate Sync PBCLK Note 1: ADC event trigger is available on Timer3 only. 2012-2017 Microchip Technology Inc. 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS DS60001185G-page 171 PIC32MX330/350/370/430/450/470 TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) FIGURE 14-2: Data Bus<31:0> <31:0> Reset TMRy(1) MS Half Word ADC Event Trigger(2) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx(1) PRx 0 1 TGATE Q D TGATE Q TCS ON TxCK x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: 2: In this diagram, the use of `x' in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of `y' in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. ADC event trigger is available only on the Timer2/3 pair. DS60001185G-page 172 2012-2017 Microchip Technology Inc. Control Register TABLE 14-1: TIMER2 THROUGH TIMER5 REGISTER MAP 30/14 29/13 28/12 27/11 26/10 25/9 -- ON -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- 24/8 23/7 -- -- -- TGATE -- -- TMR2<15:0> -- -- PR2<15:0> -- -- 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- TCKPS<2:0> -- -- -- T32 -- -- -- -- -- TCS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 FFFF 0000 DS60001185G-page 173 -- TGATE TCKPS<2:0> -- -- TCS -- 0000 31:16 -- -- -- -- -- -- -- -- -- 0000 0A10 TMR3 15:0 TMR3<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0A20 PR3 15:0 PR3<15:0> FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0C00 T4CON 15:0 ON -- SIDL -- -- -- -- -- TGATE TCKPS<2:0> T32 -- TCS -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0C10 TMR4 15:0 TMR4<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0C20 PR4 15:0 PR4<15:0> FFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0E00 T5CON 15:0 ON -- SIDL -- -- -- -- -- TGATE TCKPS<2:0> -- -- TCS -- 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0E10 TMR5 15:0 TMR5<15:0> 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0E20 PR5 15:0 PR5<15:0> FFFF Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 31:16 15:0 31:16 0810 TMR2 15:0 31:16 0820 PR2 15:0 31:16 0A00 T3CON 15:0 0800 T2CON 31/15 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. 14.2 PIC32MX330/350/370/430/450/470 REGISTER 14-1: Bit Range 31:24 23:16 15:8 7:0 TxCON: TYPE B TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1,3) -- SIDL(4) -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 T32(2) -- TCS(3) -- TGATE(3) TCKPS<2:0>(3) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Timer On bit(1,3) 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit(4) 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode bit 12-8 Unimplemented: Read as `0' bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS = 1: This bit is ignored and is read as `0'. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is available only on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: DS60001185G-page 174 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 14-1: TxCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 2 Unimplemented: Read as `0' bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as `0' Note 1: When using 1:1 PBCLK divisor, the user's software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is available only on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer3 and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. 2: 3: 4: 2012-2017 Microchip Technology Inc. DS60001185G-page 175 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 176 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 15.0 WATCHDOG TIMER (WDT) Note: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. "Watchdog, Deadman, and Power-up Timers" (DS60001114), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). FIGURE 15-1: The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM PWRT Enable WDT Enable LPRC Control PWRT Enable 1:64 Output LPRC Oscillator PWRT 1 Clock 25-bit Counter WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 25 0 1 WDT Counter Reset Device Reset NMI (Wake-up) Power Save Decoder FWDTPS<4:0> (DEVCFG1<20:16>) 2012-2017 Microchip Technology Inc. DS60001185G-page 177 Watchdog Timer Control Registers 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range 31/15 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- -- -- -- -- -- -- -- SWDTPS<4:0> WDTWINEN WDTCLR 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 0000 WDTCON Legend: Note 1: WATCHDOG TIMER CONTROL REGISTER MAP Bits Register Name(1) Virtual Address (BF80_#) TABLE 15-1: PIC32MX330/350/370/430/450/470 DS60001185G-page 178 15.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 15-1: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- R-y R-y R-y R-y R-y R/W-0 R/W-0 R/W-0 (1,2) ON U-0 -- SWDTPS<4:0> WDTWINEN WDTCLR Legend: y = Values set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Watchdog Timer Enable bit(1,2) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software bit 14-7 Unimplemented: Read as `0' bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits. bit 1 WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer bit 0 WDTCLR: Watchdog Timer Reset bit 1 = Writing a `1' will clear the WDT 0 = Software cannot force this bit to a `0' Note 1: 2: A read of this bit results in a `1' if the Watchdog Timer is enabled by the device configuration or software. When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 179 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 180 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 16.0 Note: * Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin INPUT CAPTURE This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS60001122), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values Interrupt optionally generated after 1, 2, 3, or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events: * Simple capture event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin - Capture timer value on every edge (rising and falling) - Capture timer value on every edge (rising and falling), specified edge first. FIGURE 16-1: INPUT CAPTURE BLOCK DIAGRAM FEDGE Specified/Every Edge Mode ICM<2:0> 110 Prescaler Mode (16th Rising Edge) 101 Prescaler Mode (4th Rising Edge) 100 TMR2 TMR3 C32 | ICTMR CaptureEvent ICx pin Rising Edge Mode 011 Falling Edge Mode 010 Edge Detection Mode 001 To CPU FIFO CONTROL ICxBUF FIFO ICI<1:0> ICM<2:0> Set Flag ICxIF (In IFSx Register) /N Sleep/Idle Wake-up Mode 001 111 Note: An `x' in a signal, register or bit name denotes the number of the capture channel. 2012-2017 Microchip Technology Inc. DS60001185G-page 181 PIC32MX330/350/370/430/450/470 16.1 Control Register REGISTER 16-1: Bit Range Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- R/W-0 (1) U-0 R/W-0 -- SIDL R/W-0 R/W-0 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE `X' CONTROL REGISTER ON ICTMR Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- FEDGE C32 R-0 R-0 R/W-0 R/W-0 R/W-0 ICOV ICBNE R/W-0 ICI<1:0> ICM<2:0> Legend: R = Readable bit W = Writable bit -n = Bit Value at POR: (`0', `1', x = unknown) U = Unimplemented bit P = Programmable bit r = Reserved bit bit 31-16 Unimplemented: Read as `0' bit 15 ON: Input Capture Module Enable bit(1) 1 = Module is enabled 0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Control bit 1 = Halt in CPU Idle mode 0 = Continue to operate in CPU Idle mode bit 12-10 Unimplemented: Read as `0' bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110) 1 = Capture rising edge first 0 = Capture falling edge first bit 8 C32: 32-bit Capture Select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is `1') 0 = Timer3 is the counter source for capture 1 = Timer2 is the counter source for capture bit 6-5 ICI<1:0>: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow has occurred 0 = No input capture overflow has occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001185G-page 182 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 16-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE `X' CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode - every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode - every sixteenth rising edge 100 = Prescaled Capture Event mode - every fourth rising edge 011 = Simple Capture Event mode - every rising edge 010 = Simple Capture Event mode - every falling edge 001 = Edge Detect mode - every edge (rising and falling) 000 = Input Capture module is disabled When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 183 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 184 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 17.0 Note: The following are key features of the Output Compare module: OUTPUT COMPARE This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Compare" (DS60001111), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). * Multiple Output Compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Can operate from either of two available 16-bit time bases or a single 32-bit time base The Output Compare module is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the Output Compare module generates an event based on the selected mode of operation. FIGURE 17-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) Output Logic OCxR(1) 3 OCM<2:0> Mode Select Comparator 0 16 Timer2 OCTSEL 1 0 S R Output Enable Q OCx(1) Output Enable Logic OCFA or OCFB(2) 1 16 Timer3 Timer2 Rollover Timer3 Rollover Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 2012-2017 Microchip Technology Inc. DS60001185G-page 185 Control Registers OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 5 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 15:0 31:16 OC1R 15:0 31:16 OC1RS 15:0 31:16 OC2CON 15:0 31:16 OC2R 15:0 31:16 OC2RS 15:0 -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- 31:16 15:0 31:16 15:0 -- ON -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- 3000 OC1CON 3010 3020 3200 3210 3220 3400 OC3CON 3410 OC3R 3420 OC3RS 3600 OC4CON 2012-2017 Microchip Technology Inc. 3610 OC4R 3620 OC4RS OC1R<31:0> OC1RS<31:0> -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- 31:16 15:0 -- -- OC2R<31:0> OC2RS<31:0> -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- OC3R<31:0> 31:16 15:0 31:16 15:0 31:16 15:0 -- -- OC3RS<31:0> -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- OC4R<31:0> OC4RS<31:0> -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> -- All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 17-1: 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15:0 ON -- SIDL -- -- -- -- -- -- -- OC32 OCFLT OCTSEL OCM<2:0> 31:16 3810 OC5R OC5R<31:0> 15:0 31:16 3820 OC5RS OC5RS<31:0> 15:0 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 3800 OC5CON PIC32MX330/350/370/430/450/470 DS60001185G-page 186 17.1 PIC32MX330/350/370/430/450/470 REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE `x' CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 ON(1) -- SIDL -- -- -- -- -- U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- OC32 OCFLT(2) OCTSEL OCM<2:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Output Compare Peripheral On bit(1) 1 = Output Compare peripheral is enabled 0 = Output Compare peripheral is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation in Idle mode bit 12-6 Unimplemented: Read as `0' bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source bit 4 OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this Output Compare module 0 = Timer2 is the clock source for this Output Compare module bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin is enabled 110 = PWM mode on OCx; Fault pin is disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit is only used when OCM<2:0> = `111'. It is read as `0' in all other modes. 2: 2012-2017 Microchip Technology Inc. DS60001185G-page 187 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 188 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 18.0 Note: The following are some of the key features of the SPI module: SERIAL PERIPHERAL INTERFACE (SPI) * * * * * Master and Slave modes support Four different clock formats Enhanced Framed SPI protocol support User-configurable 8-bit, 16-bit and 32-bit data width Separate SPI FIFO buffers for receive and transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width * Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer * Operation during CPU Sleep and Idle mode * Audio Codec Support: - I2S protocol - Left-justified - Right-justified - PCM This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (SPI)" (DS60001106), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola(R) SPI and SIOP interfaces. FIGURE 18-1: SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read Write SPIxRXB FIFO FIFOs Share Address SPIxBUF SPIxTXB FIFO Transmit Receive SPIxSR SDIx bit 0 SDOx SSx/FSYNC Slave Select and Frame Sync Control Shift Control Clock Control MCLKSEL Edge Select SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. 2012-2017 Microchip Technology Inc. 1 REFCLK 0 PBCLK Baud Rate Generator MSTEN DS60001185G-page 189 Control Registers SPI2 AND SPI2 REGISTER MAP 31:16 15:0 31:16 SPI1STAT 5810 15:0 31:16 5820 SPI1BUF 15:0 31:16 5830 SPI1BRG 15:0 31:16 5840 SPI1CON2 15:0 5800 SPI1CON 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31/15 FRMEN ON -- -- 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 MCLKSEL -- FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> -- SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP -- -- RXBUFELM<4:0> -- -- -- -- FRMERR SPIBUSY -- -- SPITUR SRMT SPIROV 21/5 20/4 -- MSTEN -- SPIRBE -- DISSDI -- 19/3 18/2 17/1 16/0 -- -- SPIFE ENHBUF STXISEL<1:0> SRXISEL<1:0> TXBUFELM<4:0> SPITBE -- SPITBF SPIRBF DATA<31:0> -- -- -- SPI SGNEXT FRMEN ON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRG<8:0> -- -- -- -- MSTEN -- SPIRBE -- DISSDI FRM SPI SPI -- -- -- IGNROV IGNTUR AUDEN ERREN ROVEN TUREN MCLKSEL -- FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> -- SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP -- -- RXBUFELM<4:0> -- -- -- -- FRMERR SPIBUSY -- -- SPITUR SRMT SPIROV DATA<31:0> -- -- -- -- -- -- -- -- -- AUD -- AUDMOD<1:0> MONO -- -- SPIFE ENHBUF STXISEL<1:0> SRXISEL<1:0> TXBUFELM<4:0> SPITBE -- SPITBF SPIRBF All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 18-1: 0000 0000 0000 19EB 0000 0000 0000 0000 0000 0000 0000 0000 0000 19EB 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRG<8:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5A40 SPI2CON2 SPI AUD FRM SPI SPI 15:0 -- -- -- -- -- -- AUDMOD<1:0> 0000 IGNROV IGNTUR AUDEN SGNEXT MONO ERREN ROVEN TUREN Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 5A30 SPI2BRG PIC32MX330/350/370/430/450/470 DS60001185G-page 190 18.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRMCNT<2:0> R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MCLKSEL(2) -- -- -- -- -- SPIFE ENHBUF(2) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON(1) -- SIDL DISSDO MODE32 MODE16 SMP CKE(3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN CKP(4) MSTEN DISSDI Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set STXISEL<1:0> SRXISEL<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low bit 28 MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit. 0 = Slave select SPI support is disabled. bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode. 111 = Reserved; do not use 110 = Reserved; do not use 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character bit 23 MCLKSEL: Master Clock Enable bit(2) 1 = REFCLK is used by the Baud Rate Generator 0 = PBCLK is used by the Baud Rate Generator bit 22-18 Unimplemented: Read as `0' Note 1: 2: 3: 4: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI module functions as if the CKP bit is equal to `1', regardless of the actual value of CKP. 2012-2017 Microchip Technology Inc. DS60001185G-page 191 PIC32MX330/350/370/430/450/470 REGISTER 18-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits When AUDEN = 1: MODE32 MODE16 Communication 1 1 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 1 0 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 0 1 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame 0 0 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame When AUDEN = 0: MODE32 MODE16 Communication 1 x 32-bit 0 1 16-bit 0 0 8-bit SMP: SPI Data Input Sample Phase bit Master mode (MSTEN = 1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode (MSTEN = 0): SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode, pin controlled by port function. CKP: Clock Polarity Select bit(4) 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 9 bit 8 bit 7 bit 6 bit 5 Note 1: 2: 3: 4: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI module functions as if the CKP bit is equal to `1', regardless of the actual value of CKP. DS60001185G-page 192 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 18-1: bit 4 SPIxCON: SPI CONTROL REGISTER (CONTINUED) DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) bit 3-2 bit 1-0 Note 1: 2: 3: 4: When using the 1:1 PBCLK divisor, the user software should not read or write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to `0' for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI module functions as if the CKP bit is equal to `1', regardless of the actual value of CKP. 2012-2017 Microchip Technology Inc. DS60001185G-page 193 PIC32MX330/350/370/430/450/470 REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- U-0 -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT -- -- FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R/W-0 U-0 AUDEN(1) -- -- -- AUDMONO(1,2) -- Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set SPITUREN IGNROV R/W-0 IGNTUR R/W-0 AUDMOD<1:0>(1,2) U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extened bit 14-13 Unimplemented: Read as `0' bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame Error overflow generates error events 0 = Frame Error does not generate error events bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun Generates Error Events 0 = Transmit Underrun Does Not Generates Error Events bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions) 1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data 0 = A ROV is a critical error which stop SPI operation bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error which stop SPI operation bit 7 AUDEN: Enable Audio CODEC Support bit(1) 1 = Audio protocol is enabled 0 = Audio protocol is disabled bit 6-5 Unimplemented: Read as `0' bit 3 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data is mono (Each data word is transmitted on both left and right channels) 0 = Audio data is stereo bit 2 Unimplemented: Read as `0' bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit(1,2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = I2S mode Note 1: 2: This bit can only be written when the ON bit = 0. This bit is only valid for AUDEN = 1. DS60001185G-page 194 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 18-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 -- -- -- U-0 U-0 U-0 R-0 R-0 RXBUFELM<4:0> R-0 R-0 R-0 -- -- -- U-0 U-0 U-0 R/C-0, HS R-0 TXBUFELM<4:0> U-0 U-0 R-0 -- -- -- FRMERR SPIBUSY -- -- SPITUR R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE -- SPITBE -- SPITBF SPIRBF Legend: C = Clearable bit HS = Set in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as `0' bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as `0' bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as `0' bit 12 FRMERR: SPI Frame Error status bit 1 = Frame error is detected 0 = No Frame error is detected This bit is only valid when FRMEN = 1. bit 11 SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle bit 10-9 Unimplemented: Read as `0' bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module, or writing a `0' to SPITUR. bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can bit only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module, or by writing a `0' to SPIROV. bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR SWPTR) bit 4 Unimplemented: Read as `0' 2012-2017 Microchip Technology Inc. DS60001185G-page 195 PIC32MX330/350/370/430/450/470 REGISTER 18-3: SPIxSTAT: SPI STATUS REGISTER (CONTINUED) bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. bit 2 Unimplemented: Read as `0' bit 1 SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode: Set when CWPTR + 1 = SRPTR; cleared otherwise bit 0 SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Set when SWPTR + 1 = CRPTR; cleared otherwise DS60001185G-page 196 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 19.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. "InterIntegrated Circuit (I2C)" (DS60001116), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/ pic32). 2012-2017 Microchip Technology Inc. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 19-1 illustrates the I2C module block diagram. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module offers the following key features: * I2C interface supporting both master and slave operation * I2C Slave mode supports 7-bit and 10-bit addressing * I2C Master mode supports 7-bit and 10-bit addressing * I2C port allows bidirectional transfers between master and slaves * Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) * I2C supports multi-master operation; detects bus collision and arbitrates accordingly * Provides support for address bit masking DS60001185G-page 197 PIC32MX330/350/370/430/450/470 FIGURE 19-1: I2C BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001185G-page 198 2012-2017 Microchip Technology Inc. Control Registers TABLE 19-1: I2C1 AND I2C2 REGISTER MAP 31/15 30/14 5040 I2C1BRG 31:16 15:0 -- -- -- -- 28/12 27/11 26/10 25/9 24/8 23/7 22/6 -- SIDL -- -- -- -- -- -- -- SCLREL -- -- -- -- -- -- -- STRICT -- -- -- -- -- -- -- A10M -- BCL -- -- -- -- -- DISSLW -- GCSTAT -- -- SMEN -- ADD10 -- -- GCEN -- IWCOL -- -- STREN -- I2COV -- -- -- -- -- -- -- -- -- -- -- -- -- -- 21/5 20/4 19/3 -- -- -- ACKDT ACKEN RCEN -- -- -- D_A P S -- -- -- Address Register -- -- -- Address Mask Register -- -- -- Baud Rate Generator Register -- 18/2 17/1 16/0 -- PEN -- R_W -- -- RSEN -- RBF -- -- SEN -- TBF -- -- -- -- -- -- -- 0000 BFFF 0000 0000 0000 0000 0000 0000 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 -- -- -- -- -- -- -- -- Transmit Register 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5060 I2C1RCV 15:0 -- -- -- -- -- -- -- -- Receive Register 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5100 I2C2CON 15:0 ON -- SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN BFFF 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5110 I2C2STAT 15:0 ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5120 I2C2ADD 15:0 -- -- -- -- -- -- Address Register 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5130 I2C2MSK 15:0 -- -- -- -- -- -- Address Mask Register 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5140 I2C2BRG 15:0 -- -- -- -- Baud Rate Generator Register 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5150 I2C2TRN 15:0 -- -- -- -- -- -- -- -- Transmit Register 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 5160 I2C2RCV 15:0 -- -- -- -- -- -- -- -- Receive Register 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 5050 I2C1TRN DS60001185G-page 199 PIC32MX330/350/370/430/450/470 31:16 -- -- 15:0 ON -- 31:16 -- -- 5010 I2C1STAT 15:0 ACKSTAT TRSTAT 31:16 -- -- 5020 I2C1ADD 15:0 -- -- 31:16 -- -- 5030 I2C1MSK 15:0 -- -- 5000 I2C1CON 29/13 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. 19.1 PIC32MX330/350/370/430/450/470 REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 -- SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN ON Legend: HC = Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: I2C Enable bit(1) 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write `1' to release clock). Hardware clear at beginning of slave transmission. bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C Reserved Address Rule is not enabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001185G-page 200 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 19-1: I2CXCON: I2C CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 201 PIC32MX330/350/370/430/450/470 REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF Legend: HS = Set in hardware HSC = Hardware set/cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as `0' bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as `0' bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. This condition can only be cleared by disabling (ON bit = 0) and re-enabling (ON bit = 1) the module. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. DS60001185G-page 202 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 19-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. 2012-2017 Microchip Technology Inc. DS60001185G-page 203 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 204 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The UART module is one of the serial I/O modules available in the PIC32MX330/350/370/430/450/470 family of devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. FIGURE 20-1: The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, Odd or No Parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 76 bps to 30 Mbps at 120 MHz 8-level deep First-In-First-Out (FIFO) transmit data buffer 8-level deep FIFO receive data buffer Parity, framing and buffer overrun error detection Support for interrupt-only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support * LIN Protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 20-1 illustrates a simplified block diagram of the UART. UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) Hardware Flow Control Note: UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information. 2012-2017 Microchip Technology Inc. DS60001185G-page 205 Control Registers U1STA(1) 6020 U1TXREG 6030 U1RXREG 6040 U1BRG(1) 6200 U2MODE(1) 6210 U2STA(1) 6220 U2TXREG 6230 U2RXREG 6240 U2BRG(1) 2012-2017 Microchip Technology Inc. 6400 U3MODE(1) 6410 U3STA(1) 6420 U3TXREG 6430 U3RXREG Bit Range Register Name Bits 6000 U1MODE(1) 6010 UART1 THROUGH UART5 REGISTER MAP 31/15 30/14 31:16 -- -- -- 15:0 ON -- SIDL 31:16 -- -- -- 15:0 UTXISEL<1:0> 29/13 28/12 27/11 26/10 25/9 24/8 -- -- -- -- -- IREN RTSMD -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 31:16 15:0 -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 21/5 20/4 19/3 18/2 17/1 -- -- -- -- -- -- -- WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> 16/0 -- 0000 STSEL 0000 ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- 31:16 15:0 -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 WAKE LPBACK ABAUD RXINV BRGH STSEL 0000 PDSEL<1:0> ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 WAKE LPBACK ABAUD RXINV BRGH STSEL 0000 Baud Rate Generator Prescaler -- 15:0 22/6 Baud Rate Generator Prescaler -- 15:0 23/7 All Resets Virtual Address (BF80_#) TABLE 20-1: 0000 0000 PDSEL<1:0> ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- Receive Register 0000 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 206 20.1 Register Name 6440 U3BRG(1) Bit Range Bits (1) 6600 U4MODE 6610 U4STA (1) U4BRG (1) 6800 U5MODE (1) 6830 U5RXREG U5BRG 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 WAKE LPBACK ABAUD RXINV BRGH STSEL 0000 15:0 Baud Rate Generator Prescaler 31:16 15:0 -- -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- (1) -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ON -- SIDL IREN RTSMD -- 31:16 -- -- -- -- -- -- -- ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UTXISEL<1:0> -- -- UEN<1:0> 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- TX8 31:16 -- -- -- -- -- -- -- -- 15:0 -- -- -- -- -- -- -- RX8 31:16 -- -- -- -- -- -- -- -- 15:0 PDSEL<1:0> ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 WAKE LPBACK ABAUD RXINV BRGH STSEL 0000 Baud Rate Generator Prescaler 31:16 15:0 15:0 6820 U5TXREG 6840 30/14 15:0 (1) U5STA 31/15 0000 PDSEL<1:0> ADDR<7:0> URXISEL<1:0> 0000 ADDEN RIDLE PERR FERR OERR URXDA FFFF -- -- -- -- -- 0000 -- -- -- -- -- -- -- -- -- -- -- -- Transmit Register -- -- 0000 Receive Register -- Baud Rate Generator Prescaler 0000 -- -- -- -- 0000 0000 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. DS60001185G-page 207 PIC32MX330/350/370/430/450/470 6630 U4RXREG 6810 31:16 15:0 6620 U4TXREG 6640 UART1 THROUGH UART5 REGISTER MAP (CONTINUED) All Resets Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. TABLE 20-1: PIC32MX330/350/370/430/450/470 REGISTER 20-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 -- SIDL IREN RTSMD -- R/W-0 ON R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH UEN<1:0> R/W-0 PDSEL<1:0> R/W-0 STSEL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: UARTx Enable bit(1) 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode bit 12 IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as `0' bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up is enabled 0 = Wake-up is disabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. DS60001185G-page 208 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode - 4x baud clock enabled 0 = Standard Speed mode - 16x baud clock enabled bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 209 PIC32MX330/350/370/430/450/470 REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXINV URXEN UTXBRK UTXEN UTXBF TRMT R/W-0 R-1 R-0 R-0 R/W-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as `0' bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR<7:0>: Automatic Address Mask bits When the ADM_EN bit is `1', this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is `0'): 1 = UxTX Idle state is `0' 0 = UxTX Idle state is `1' If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is `1'): 1 = IrDA encoded UxTX Idle state is `1' 0 = IrDA encoded UxTX Idle state is `0' bit 12 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by the port. bit 11 UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by the port. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written DS60001185G-page 210 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty 2012-2017 Microchip Technology Inc. DS60001185G-page 211 PIC32MX330/350/370/430/450/470 20.2 Timing Diagrams Figure 20-2 and Figure 20-3 illustrate typical receive and transmit timing for the UART module. FIGURE 20-2: UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Read to UxRXREG Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13 UxRX RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00 Cleared by Software UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 20-3: TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF Write to UxTXREG TSR Pull from Buffer BCLK/16 (Shift Clock) UxTX Start Bit 0 Bit 1 Stop Start Bit 1 UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS60001185G-page 212 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 21.0 PARALLEL MASTER PORT (PMP) Note: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS60001128), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. The following are key features of the PMP module: * * * * * * * * * * * * 8-bit,16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options - Individual read and write strobes, or - Read/write strobe with enable strobe Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait states Operate during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Freeze option for in-circuit debugging Note: FIGURE 21-1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Parallel Master Port Control Lines PMA<0> PMALL PMA<1> PMALH Flash EEPROM SRAM Up to 16-bit Address PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2 PMRD PMRD/PMWR PMWR PMENB PMD<7:0> PMD<15:8>(1) Note: Microcontroller LCD FIFO Buffer 8-bit/16-bit Data (with or without multiplexed addressing) On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes. 2012-2017 Microchip Technology Inc. DS60001185G-page 213 Control Registers PARALLEL MASTER PORT REGISTER MAP 31:16 15:0 31:16 7010 PMMODE 15:0 31:16 7020 PMADDR 15:0 7000 PMCON 31/15 -- ON -- BUSY -- CS2 30/14 29/13 -- -- -- SIDL -- -- IRQM<1:0> -- -- 28/12 27/11 -- -- ADRMUX<1:0> -- -- INCM<1:0> -- -- 26/10 25/9 -- -- -- PMPTTL PTWREN PTRDEN -- -- -- MODE16 MODE<1:0> -- -- -- CS1 PMAEN 31:16 15:0 23/7 22/6 -- -- CSF<1:0> -- -- WAITB<1:0> -- -- 21/5 -- ALP -- -- 20/4 19/3 -- -- CS2P CS1P -- -- WAITM<3:0> -- -- 18/2 -- -- -- -- 17/1 16/0 -- -- WRSP RDSP -- -- WAITE<1:0> -- -- ADDR<13:0> 31:16 7030 PMDOUT 15:0 31:16 7040 PMDIN 15:0 7050 24/8 0000 0000 0000 0000 DATAIN<31:0> -- -- -- -- -- -- -- -- PTEN<15:0> 0000 0000 0000 0000 0000 0000 DATAOUT<31:0> -- All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 21-1: -- -- -- -- -- -- -- 0000 0000 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 7060 PMSTAT 15:0 IBF IBOV -- -- IB3F IB2F IB1F IB0F OBE OBUF -- -- OB3E OB2E OB1E OB0E BFBF Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. PIC32MX330/350/370/430/450/470 DS60001185G-page 214 21.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 21-1: Bit Range 31:24 23:16 15:8 7:0 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- SIDL PMPTTL PTWREN PTRDEN R/W-0 R/W-0 (2) R/W-0 (2) U-0 R/W-0 R/W-0 -- WRSP RDSP ON CSF<1:0> Legend: R = Readable bit -n = Value at POR ALP ADRMUX<1:0> R/W-0 (2) CS2P W = Writable bit `1' = Bit is set R/W-0 (2) CS1P U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Parallel Master Port Enable bit(1) 1 = PMP is enabled 0 = PMP is disabled, no off-chip access performed bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower 8 bits of address are multiplexed on PMD<15:0> pins 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8> 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled bit 7-6 CSF<1:0>: Chip Select Function bits(2) 11 = Reserved 10 = PMCS1 and PMCS2 function as Chip Select 01 = PMCS1 functions as address bit 14; PMCS2 functions as Chip Select 00 = PMCS1 and PMCS2 function as address bits 14 and 15, respectively bit 5 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. 2012-2017 Microchip Technology Inc. DS60001185G-page 215 PIC32MX330/350/370/430/450/470 REGISTER 21-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 2 bit 1 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) Unimplemented: Read as `0' WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) bit 0 For Master mode 1 (MODE<1:0> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) bit 3 For Master mode 1 (MODE<1:0> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. DS60001185G-page 216 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 21-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 (1) R/W-0 WAITB<1:0> INCM<1:0> R/W-0 MODE16 R/W-0 (1) MODE<1:0> R/W-0 R/W-0 WAITM<3:0> R/W-0 (1) WAITE<1:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved, do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only) 10 = Decrement ADDR<15:0> by 1 every read/write cycle(2) 01 = Increment ADDR<15:0> by 1 every read/write cycle(2) 00 = No increment or decrement of address bit 10 MODE16: 8/16-bit Mode bit 1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer 0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>(3)) 10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>(3)) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPB cycle for a write operation; WAITB = 1 TPB cycle, WAITE = 0 TPB cycles for a read operation. 2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select CS2 and CS1. 3: These pins are active when MODE16 = 1 (16-bit mode). 2012-2017 Microchip Technology Inc. DS60001185G-page 217 PIC32MX330/350/370/430/450/470 REGISTER 21-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB * * * 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPB cycle for a write operation; WAITB = 1 TPB cycle, WAITE = 0 TPB cycles for a read operation. 2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select CS2 and CS1. 3: These pins are active when MODE16 = 1 (16-bit mode). DS60001185G-page 218 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 21-3: Bit Range 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) R/W-0 (3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 ADDR15 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 R/W-0 CS1 (2) ADDR<13:8> ADDR14(4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 CS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive bit 15 ADDR<15>: Destination Address bit 15(2) bit 14 CS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive bit 14 ADDR<14>: Destination Address bit 14(4) bit 13-0 ADDR<13:0>: Address bits Note 1: 2: 3: 4: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01. When the CSF<1:0> bits (PMCON<7:6>) = 00. When the CSF<1:0> bits (PMCON<7:6>) = 10. When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01. 2012-2017 Microchip Technology Inc. DS60001185G-page 219 PIC32MX330/350/370/430/450/470 REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<15:14>(1) R/W-0 R/W-0 PTEN<13:8> R/W-0 PTEN<1:0>(2) PTEN<7:2> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Write `0'; ignore read bit 15-14 PTEN<15:14>: PMCSx Address Port Enable bits 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1) 0 = PMA15 and PMA14 function as port I/O bit 13-2 PTEN<13:2>: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Address Port Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads function as port I/O Note 1: 2: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>). The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by the ADRMUX<1:0> bits in the PMCON register. DS60001185G-page 220 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV -- -- IB3F IB2F IB1F IB0F R-1 R/W-0, HS, SC U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF -- -- OB3E OB2E OB1E OB0E Legend: HS = Set by Hardware SC = Cleared by software R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as `0' bit 11-8 IBxF: Input Buffer `x' Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as `0' bit 3-0 OBxE: Output Buffer `x' Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted 2012-2017 Microchip Technology Inc. DS60001185G-page 221 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 222 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 22.0 Note: The following are key features of the RTCC module: REAL-TIME CLOCK AND CALENDAR (RTCC) * * * * This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS60001125), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). * * * * * * * * * The PIC32 RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. * * * * FIGURE 22-1: Time: hours, minutes and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year Alarm repeat with decrementing counter Alarm with indefinite repeat: Chime Year range: 2000 to 2099 Leap year correction BCD format for smaller firmware overhead Optimized for long-term battery operation Fractional second synchronization User calibration of the clock crystal frequency with auto-adjust Calibration range: 0.66 seconds error per month Calibrates up to 260 ppm of crystal error Requirements: External 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin RTCC BLOCK DIAGRAM CAL<9:0> 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers RTCTIME 0.5s HR, MIN, SEC RTCVAL RTCC Timer Alarm Event RTCDATE YEAR, MONTH, DAY, WDAY Comparator ALRMTIME Compare Registers with Masks HR, MIN, SEC ALRMVAL ALRMDATE MONTH, DAY, WDAY Repeat Counter Set RTCC Flag RTCC Interrupt Logic Alarm Pulse Seconds Pulse 0 1 RTCC RTSECSEL RTCOE 2012-2017 Microchip Technology Inc. DS60001185G-page 223 Control Registers Virtual Address (BF80_#) Register Name(1) TABLE 22-1: 0200 RTCCON RTCC REGISTER MAP 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 31:16 -- 15:0 ON 31:16 -- 15:0 ALRMEN 31:16 15:0 31:16 15:0 31:16 15:0 30/14 29/13 -- -- -- SIDL -- -- CHIME PIV HR10<3:0> SEC10<3:0> YEAR10<3:0> DAY10<3:0> HR10<3:0> SEC10<3:0> 28/12 27/11 -- -- -- ALRMSYNC -- -- -- 26/10 25/9 -- -- -- -- -- AMASK<3:0> HR01<3:0> SEC01<3:0> YEAR01<3:0> DAY01<3:0> HR01<3:0> SEC01<3:0> 24/8 -- -- 23/7 22/6 -- -- 20/4 19/3 18/2 17/1 16/0 CAL<9:0> -- -- RTCWREN RTCSYNC HALFSEC RTCOE -- -- -- -- -- -- ARPT<7:0> MIN10<3:0> MIN01<3:0> -- -- -- -- -- -- -- MONTH10<3:0> MONTH01<3:0> -- -- -- WDAY01<3:0> MIN10<3:0> MIN01<3:0> -- -- -- -- -- -- -- RTSECSEL RTCCLKON -- -- -- 21/5 All Resets 31/15 0000 0000 0000 0000 xxxx xx00 xxxx xx00 xxxx xx00 31:16 -- -- -- -- -- -- -- -- MONTH10<3:0> MONTH01<3:0> 00xx 15:0 DAY10<3:0> DAY01<3:0> -- -- -- -- WDAY01<3:0> xx0x x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 0250 ALRMDATE Legend: Note 1: Bit Range Bits PIC32MX330/350/370/430/450/470 DS60001185G-page 224 22.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 22-1: Bit Range 31:24 23:16 Bit 30/22/14/6 Bit Bit 29/21/13/5 28/20/12/4 U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CAL<9:8> CAL<7:0> 15:8 7:0 RTCCON: RTC CONTROL REGISTER Bit 31/23/15/7 R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 ON(1,2) -- SIDL -- -- -- -- -- R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 -- -- RTSECSEL(3) RTCCLKON Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set RTCWREN(4) RTCSYNC HALFSEC(5) RTCOE U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as `0' bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute * * * 0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute * * * bit 15 bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5-4 Note 1: 2: 3: 4: 5: Note: 1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute ON: RTCC On bit(1,2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as `0' SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode 0 = Continue normal operation in Idle mode Unimplemented: Read as `0' RTSECSEL: RTCC Seconds Clock Output Select bit(3) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin RTCCLKON: RTCC Clock Enable Status bit 1 = RTCC Clock is actively running 0 = RTCC Clock is not running Unimplemented: Read as `0' The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Requires RTCOE = 1 (RTCCON<0>) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to `0' on a write to the seconds bit fields (RTCTIME<14:8>). This register is reset only on a Power-on Reset (POR). 2012-2017 Microchip Technology Inc. DS60001185G-page 225 PIC32MX330/350/370/430/450/470 REGISTER 22-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid 0 = RTC Value registers can be read without concern about a rollover ripple HALFSEC: Half-Second Status bit(5) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output is enabled - clock presented onto an I/O 0 = RTCC clock output is disabled bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: 4: 5: Note: The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Requires RTCOE = 1 (RTCCON<0>) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to `0' on a write to the seconds bit fields (RTCTIME<14:8>). This register is reset only on a Power-on Reset (POR). DS60001185G-page 226 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 22-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (3) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIV ALRMSYNC(3) R/W-0 AMASK<3:0> R/W-0 ARPT<7:0>(3) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ALRMEN: Alarm Enable bit(1,2) 1 = Alarm is enabled 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit(2) 1 = Chime is enabled - ARPT<7:0> is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled - ARPT<7:0> stops once it reaches 0x00 bit 13 PIV: Alarm Pulse Initial Value bit(2) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. bit 12 ALRMSYNC: Alarm Sync bit(3) 1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain 0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC clocks away from a half-second rollover bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(3) 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved; do not use 1011 = Reserved; do not use 11xx = Reserved; do not use Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = `1' (RTCCON<15>) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. This register is reset only on a Power-on Reset (POR). 2012-2017 Microchip Technology Inc. DS60001185G-page 227 PIC32MX330/350/370/430/450/470 REGISTER 22-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(3) 11111111 = Alarm will trigger 256 times bit 7-0 * * * 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = `1' (RTCCON<15>) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. This register is reset only on a Power-on Reset (POR). DS60001185G-page 228 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 22-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x R/W-x MIN01<3:0> SEC10<3:0> R/W-x R/W-x SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10s place digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1s place digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10s place digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1s place digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10s place digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1s place digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as `0' Note: This register is only writable when RTCWREN = 1 (RTCCON<3>). 2012-2017 Microchip Technology Inc. DS60001185G-page 229 PIC32MX330/350/370/430/450/470 REGISTER 22-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x R/W-x R/W-x YEAR01<3:0> R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x DAY10<3:0> R/W-x R/W-x DAY01<3:0> U-0 U-0 U-0 U-0 -- -- -- -- R/W-x R/W-x R/W-x R/W-x WDAY01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10s place digits bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1s place digit bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10s place digits; contains a value of 0 or 1 bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1s place digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10s place digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1s place digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as `0' bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1s place digit; contains a value from 0 to 6 Note: This register is only writable when RTCWREN = 1 (RTCCON<3>). DS60001185G-page 230 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 22-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> R/W-x R/W-x R/W-x R/W-x HR01<3:0> R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MIN10<3:0> R/W-x R/W-x R/W-x MIN01<3:0> SEC10<3:0> R/W-x R/W-x SEC01<3:0> U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10s place digits; contains a value from 0 to 2 bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1s place digit; contains a value from 0 to 9 bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10s place digits; contains a value from 0 to 5 bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1s place digit; contains a value from 0 to 9 bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10s place digits; contains a value from 0 to 5 bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1s place digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as `0' 2012-2017 Microchip Technology Inc. DS60001185G-page 231 PIC32MX330/350/370/430/450/470 REGISTER 22-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-x R/W-x R/W-x R/W-x R/W-x MONTH10<3:0> R/W-x R/W-x R/W-x Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x DAY10<1:0> R/W-x R/W-x DAY01<3:0> U-0 U-0 U-0 U-0 -- -- -- -- R/W-x R/W-x R/W-x R/W-x WDAY01<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10s place digits; contains a value of 0 or 1 bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1s place digit; contains a value from 0 to 9 bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10s place digits; contains a value from 0 to 3 bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1s place digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as `0' bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1s place digit; contains a value from 0 to 6 DS60001185G-page 232 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 23.0 Note: 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The 10-bit Analog-to-Digital Converter (ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 1 Msps conversion speed * Up to 28 analog input pins * External voltage reference input pins * One unipolar, differential Sample and Hold Amplifier (SHA) * Automatic Channel Scan mode * Selectable conversion trigger source * 16-word conversion result buffer * Selectable buffer fill modes * Eight conversion result format options * Operation during CPU Sleep and Idle modes A block diagram of the 10-bit ADC is illustrated in Figure 23-1. The 10-bit ADC has up to 28 analog input pins, designated AN0-AN27. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. FIGURE 23-1: ADC1 MODULE BLOCK DIAGRAM CTMUI(3) VREF+(1) AVDD VREF-(1) AVSS AN0 AN27 VCFG<2:0> IVREF(3) ADC1BUF0 CTMUT(2) ADC1BUF1 Open(4) S&H Channel Scan VREFH VREFL ADC1BUF2 + CH0SB<4:0> CH0SA<4:0> - SAR ADC CSCNA AN1 ADC1BUFE VREFL ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs. 2: Connected to the CTMU module. See Section 26.0 "Charge Time Measurement Unit (CTMU)" for more information. 3: See Section 25.0 "Comparator Voltage Reference (CVREF)" for more information. 4: This selection is only used with CTMU capacitive and time measurement. 2012-2017 Microchip Technology Inc. DS60001185G-page 233 PIC32MX330/350/370/430/450/470 FIGURE 23-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC(1) Div 2 1 TAD ADCS<7:0> 0 8 TPB ADC Conversion Clock Multiplier (2) 2, 4,..., 512 Note 1: 2: See Section 31.0 "Electrical Characteristics" for the exact FRC clock value. Refer to Figure 8-1 in Section 8.0 "Oscillator Configuration" for more information. DS60001185G-page 234 2012-2017 Microchip Technology Inc. Control Registers TABLE 23-1: Register Name 9010 AD1CON2(1) AD1CON3(1) 9050 AD1CSSL (1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 DS60001185G-page 235 90F0 ADC1BUF8 9100 ADC1BUF9 30/14 31:16 -- 15:0 ON 31:16 -- 15:0 29/13 28/12 27/11 26/10 -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- OFFCAL -- CSCNA -- -- BUFS -- -- -- -- -- -- -- -- VCFG<2:0> 25/9 24/8 23/7 -- -- -- FORM<2:0> 31:16 -- -- -- 15:0 ADRC -- -- SAMC<4:0> 31:16 CH0NB -- -- CH0SB<4:0> 15:0 -- -- -- -- -- -- -- 31:16 -- CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 22/6 21/5 -- -- SSRC<2:0> -- 20/4 19/3 18/2 16/0 -- -- -- -- -- 0000 CLRASAM -- ASAM SAMP DONE 0000 -- -- -- -- -- 0000 BUFM ALTS 0000 -- -- 0000 SMPI<3:0> -- 17/1 -- -- -- ADCS<7:0> 0000 CH0NA -- -- -- -- -- -- -- -- -- -- CSSL25 CSSL24 CSSL23 CSSL22 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16 0000 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) CH0SA<4:0> 0000 -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for details. PIC32MX330/350/370/430/450/470 9040 AD1CHS(1) 31/15 All Resets Bits 9000 AD1CON1(1) 9020 ADC REGISTER MAP Bit Range Virtual Address (BF80_#) 2012-2017 Microchip Technology Inc. 23.1 Register Name 9110 ADC1BUFA 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range Virtual Address (BF80_#) ADC REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for details. PIC32MX330/350/370/430/450/470 DS60001185G-page 236 TABLE 23-1: 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 (1) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- SIDL -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CLRASAM -- ASAM ON SSRC<2:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set FORM<2:0> R/W-0, HSC (2) SAMP R/C-0, HSC (3) DONE U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: ADC Operating Mode bit(1) 1 = ADC module is operating 0 = ADC module is not operating bit 14 Unimplemented: Read as `0' bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as `0' bit 10-8 FORM<2:0>: Data Output Format bits 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Note 1: 2: 3: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. If ASAM = 0, software can write a `1' to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a `0' to end sampling and start conversion. If SSRC 0, this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when ADC is complete. Software can write a `0' to clear this bit (a write of `1' is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. 2012-2017 Microchip Technology Inc. DS60001185G-page 237 PIC32MX330/350/370/430/450/470 REGISTER 23-1: bit 4 AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence Unimplemented: Read as `0' ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit(2) 1 = The ADC sample and hold amplifier is sampling 0 = The ADC sample/hold amplifier is holding When ASAM = 0, writing `1' to this bit starts sampling. When SSRC = 000, writing `0' to this bit will end sampling and start conversion. DONE: Analog-to-Digital Conversion Status bit(3) 1 = Analog-to-digital conversion is done 0 = Analog-to-digital conversion is not done or has not started Clearing this bit will not affect any operation in progress. bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. If ASAM = 0, software can write a `1' to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a `0' to end sampling and start conversion. If SSRC 0, this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when ADC is complete. Software can write a `0' to clear this bit (a write of `1' is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. DS60001185G-page 238 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 23-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL -- CSCNA -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS -- R/W-0 SMPI<3:0> Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits 000 001 010 011 1xx bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5-2 VREFH VREFL AVDD External VREF+ pin AVDD External VREF+ pin AVDD AVss AVSS External VREF- pin External VREF- pin AVSS OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode Positive and negative inputs of the sample and hold amplifier are connected to VREFL 0 = Disable Offset Calibration mode The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL Unimplemented: Read as `0' CSCNA: Input Scan Select bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as `0' BUFS: Buffer Fill Status bit Only valid when BUFM = 1. 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as `0' SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence * * * bit 1 bit 0 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples 0 = Always use Sample A input multiplexer settings 2012-2017 Microchip Technology Inc. DS60001185G-page 239 PIC32MX330/350/370/430/450/470 REGISTER 23-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC -- -- R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 (2) R/W-0 ADCS<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ADRC: ADC Conversion Clock Source bit 1 = Clock derived from FRC 0 = Clock derived from Peripheral Bus Clock (PBCLK) bit 14-13 Unimplemented: Read as `0' bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1) 11111 = 31 TAD * * * 00001 = 1 TAD 00000 = 0 TAD (Not allowed) bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 =TPB * 2 * (ADCS<7:0> + 1) = 512 * TPB = TAD * * * 00000001 =TPB * 2 * (ADCS<7:0> + 1) = 4 * TPB = TAD 00000000 =TPB * 2 * (ADCS<7:0> + 1) = 2 * TPB = TAD Note 1: 2: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111. This bit is not used if the ADRC bit (AD1CON3<15>) = 1. DS60001185G-page 240 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 23-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 U-0 U-0 CH0NB -- -- Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CH0SB<4:0> R/W-0 U-0 U-0 CH0NA(3) -- -- R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- CH0SA<4:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31 CH0NB: Negative Input Select bit for Sample B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 30-29 Unimplemented: Read as `0' bit 28-24 CH0SB<4:0>: Positive Input Select bits for Sample B 11110 = Channel 0 positive input is Open(1) 11101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(2) 11100 = Channel 0 positive input is IVREF(3) 11011 = Channel 0 positive input is AN27 * * * 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(3) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL bit 22-21 Unimplemented: Read as `0' bit 20-16 CH0SA<4:0>: Positive Input Select bits for Sample A Multiplexer Setting 11110 = Channel 0 positive input is Open(1) 11101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(2) 11100 = Channel 0 positive input is IVREF(3) 11011 = Channel 0 positive input is AN27 * * * 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 15-0 Unimplemented: Read as `0' Note 1: 2: 3: This selection is only used with CTMU capacitive and time measurement. See Section 26.0 "Charge Time Measurement Unit (CTMU)" for more information. See Section 25.0 "Comparator Voltage Reference (CVREF)" for more information. 2012-2017 Microchip Technology Inc. DS60001185G-page 241 PIC32MX330/350/370/430/450/470 REGISTER 23-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- CSSL30 CSSL29 CSSL28 CSSL27 CSSL26 CSSL25 CSSL24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL23 CSSL21 CSSL21 CSSL20 CSSL19 CSSL18 CSSL17 CSSL16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15-0 CSSL<30:0>: ADC Input Pin Scan Selection bits(1,2) 1 = Select ANx for input scan 0 = Skip ANx for input scan Note 1: CSSL = ANx, where x = 0-27; CSSL30 selects Vss for scan; CSSL29 selects CTMU input for scan; CSSL28 selects IVREF for scan. On devices with less than 28 analog inputs, all CSSLx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to VREFL. 2: DS60001185G-page 242 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 24.0 The Analog Comparator module contains two comparators that can be configured in a variety of ways. COMPARATOR Note: This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. "Comparator" (DS60001110), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The following are key features of the Comparator module: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be Inverted * Selectable interrupt generation A block diagram of the comparator module is provided in Figure 24-1. FIGURE 24-1: COMPARATOR BLOCK DIAGRAM CCH<1:0> C1INB C1INC COE C1IND CMP1 C1OUT CREF CMSTAT<C1OUT> CM1CON<COUT> CPOL C1INA CCH<1:0> C2INB To CTMU module (Pulse Generator) C2INC COE C2IND CMP2 C2OUT CREF CPOL C2INA CMSTAT<C2OUT> CM2CON<COUT> CVREF(1) IVREF (1.2V) Note 1: Internally connected. See Section 25.0 "Comparator Voltage Reference (CVREF)" for more information. 2012-2017 Microchip Technology Inc. DS60001185G-page 243 Control Registers COMPARATOR REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 24-1: 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON COE CPOL -- -- -- -- COUT EVPOL<1:0> -- CREF -- -- CCH<1:0> E1C3 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 A010 CM2CON 15:0 ON COE CPOL -- -- -- -- COUT EVPOL<1:0> -- CREF -- -- CCH<1:0> E1C3 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 A060 CMSTAT 15:0 -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- C2OUT C1OUT 0000 Legend: x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. A000 CM1CON PIC32MX330/350/370/430/450/470 DS60001185G-page 244 24.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 CMxCON: COMPARATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- R/W-0 (1) R/W-0 ON COE R/W-1 R/W-1 EVPOL<1:0> Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 -- R/W-0 (2) CPOL Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 -- -- -- -- U-0 U-0 U-0 U-0 -- -- -- -- -- U-0 U-0 U-0 U-0 R-0 COUT -- -- -- -- U-0 R/W-0 U-0 U-0 R/W-1 -- CREF -- -- W = Writable bit `1' = Bit is set R/W-1 CCH<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Comparator ON bit(1) 1 = Module is enabled. Setting this bit does not affect the other bits in this register 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register bit 14 COE: Comparator Output Enable bit 1 = Comparator output is driven on the output CxOUT pin 0 = Comparator output is not driven on the output CxOUT pin bit 13 CPOL: Comparator Output Inversion bit(2) 1 = Output is inverted 0 = Output is not inverted bit 12-9 Unimplemented: Read as `0' bit 8 COUT: Comparator Output bit 1 = Output of the Comparator is a `1' 0 = Output of the Comparator is a `0' bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled bit 5 Unimplemented: Read as `0' bit 4 CREF: Comparator Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the CXINA pin bit 3-2 Unimplemented: Read as `0' bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the CxIND pin 01 = Comparator inverting input is connected to the CxINC pin 00 = Comparator inverting input is connected to the CxINB pin Note 1: 2: When using the 1:1 PBCLK divisor, the user's software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>. 2012-2017 Microchip Technology Inc. DS60001185G-page 245 PIC32MX330/350/370/430/450/470 REGISTER 24-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 -- -- SIDL -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 -- -- -- -- -- -- C2OUT C1OUT Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as `0' bit 13 SIDL: Stop in IDLE Control bit 1 = All Comparator modules are disabled in IDLE mode 0 = All Comparator modules continue to operate in the IDLE mode bit 12-2 Unimplemented: Read as `0' bit 1 C2OUT: Comparator Output bit 1 = Output of Comparator 2 is a `1' 0 = Output of Comparator 2 is a `0' bit 0 C1OUT: Comparator Output bit 1 = Output of Comparator 1 is a `1' 0 = Output of Comparator 1 is a `0' DS60001185G-page 246 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 25.0 Note: A block diagram of the module is illustrated in Figure 25-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. COMPARATOR VOLTAGE REFERENCE (CVREF) This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. "Comparator Voltage Reference (CVREF)" (DS60001109), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The CVREF module has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. FIGURE 25-1: VREF+ AVDD COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVRSRC 8R CVRSS = 0 CVR<3:0> CVREF R CVREN R R 16-to-1 MUX R 16 Steps R CVREFOUT CVRCON<CVROE> R R CVRR VREFAVSS 2012-2017 Microchip Technology Inc. 8R CVRSS = 1 CVRSS = 0 DS60001185G-page 247 Control Register COMPARATOR VOLTAGE REFERENCE REGISTER MAP 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 15:0 ON -- -- -- -- -- -- -- -- CVROE CVRR CVRSS CVR<3:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. 9800 CVRCON Legend: Note 1: 31/15 All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 25-1: PIC32MX330/350/370/430/450/470 DS60001185G-page 248 25.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 25-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ON(1) -- -- -- -- -- -- -- U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- CVROE CVRR CVRSS CVR<3:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as `0' bit 15 ON: Comparator Voltage Reference On bit(1) 1 = Module is enabled Setting this bit does not affect other bits in the register. 0 = Module is disabled and does not consume current Clearing this bit does not affect the other bits in the register. bit 14-7 Unimplemented: Read as `0' bit 6 CVROE: CVREFOUT Enable bit 1 = Voltage level is output on CVREFOUT pin 0 = Voltage level is disconnected from CVREFOUT pin bit 5 CVRR: CVREF Range Selection bit 1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size bit 4 CVRSS: CVREF Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator voltage reference source, CVRSRC = AVDD - AVSS bit 3-0 CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits When CVRR = 1: CVREF = (CVR<3:0>/24) (CVRSRC) When CVRR = 0: CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC) Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripheral's SFRs in the SYSCLK cycle immediately following the instruction that clears the module's ON bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 249 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 250 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 26.0 The CTMU module includes the following key features: CHARGE TIME MEASUREMENT UNIT (CTMU) * Up to 13 channels available for capacitive or time measurement input * On-chip precision current source * 16-edge input trigger sources * Selection of edge or level-sensitive inputs * Polarity control for each edge source * Control of edge sequence * Control of response to edges * High precision time measurement * Time delay of external or internal signal asynchronous to system clock * Integrated temperature sensing diode * Control of current source during auto-sampling * Four current source ranges * Time measurement resolution of one nanosecond This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 37. "Charge Time Measurement Unit (CTMU)" (DS60001167), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). Note: The Charge Time Measurement Unit (CTMU) is a flexible analog module that has a configurable current source with a digital configuration circuit built around it. The CTMU can be used for differential time measurement between pulse sources and can be used for generating an asynchronous pulse. By working with other on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. FIGURE 26-1: A block diagram of the CTMU is shown in Figure 26-1. CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUICON ITRIM<5:0> IRNG<1:0> Current Source CTED1 * * * Edge Control Logic CTED13 Timer1 OC1 IC1-IC3 CMP1-CMP2 PBCLK EDG1STAT EDG2STAT TGEN Current Control CTMUP CTMUT (To ADC) Temperature Sensor CTMU Control Logic ADC Trigger Pulse Generator CTPLS CTMUI (To ADC S&H capacitor) C2INB CDelay Comparator 2 External capacitor for pulse generation TGEN EDG1STAT, EDG2STAT CTMUT Current Control Selection 0 EDG1STAT = EDG2STAT CTMUI 0 EDG1STAT EDG2STAT CTMUP 1 EDG1STAT EDG2STAT No Connect 1 EDG1STAT = EDG2STAT 2012-2017 Microchip Technology Inc. DS60001185G-page 251 Control Register 30/14 31:16 EDG1MOD EDG1POL 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range 31/15 EDG2STAT EDG1STAT EDG2MOD EDG2POL 0000 EDG1SEL<3:0> EDG2SEL<3:0> -- -- 15:0 ON -- CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information. A200 CTMUCON Legend: Note 1: CTMU REGISTER MAP Bits Register Name(1) Virtual Address (BF80_#) TABLE 26-1: PIC32MX330/350/370/430/450/470 DS60001185G-page 252 26.1 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 CTMUCON: CTMU CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 EDG1MOD EDG1POL R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 EDG1SEL<3:0> R/W-0 R/W-0 EDG2MOD EDG2POL R/W-0 U-0 R/W-0 R/W-0 R/W-0 ON -- CTMUSIDL TGEN(1) EDGEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W = Writable bit `1' = Bit is set R/W-0 R/W-0 U-0 R/W-0 U-0 -- -- R/W-0 R/W-0 EDGSEQEN IDISSEN(2) ITRIM<5:0> Legend: R = Readable bit -n = Value at POR Bit 24/16/8/0 EDG2STAT EDG1STAT EDG2SEL<3:0> R/W-0 Bit 25/17/9/1 R/W-0 CTTRIG R/W-0 IRNG<1:0> U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 EDG1MOD: Edge 1 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 30 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits 1111 = Reserved 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = IC3 Capture Event is selected 1011 = IC2 Capture Event is selected 1010 = IC1 Capture Event is selected 1001 = CTED8 pin is selected 1000 = CTED7 pin is selected 0111 = CTED6 pin is selected 0110 = CTED5 pin is selected 0101 = CTED4 pin is selected 0100 = CTED3 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 25 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control edge source 1 = Edge 2 has occurred 0 = Edge 2 has not occurred Note 1: 2: 3: 4: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to `1110' to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 31-42) in Section 31.0 "Electrical Characteristics" for current values. This bit setting is not available for the CTMU temperature diode. 2012-2017 Microchip Technology Inc. DS60001185G-page 253 PIC32MX330/350/370/430/450/470 REGISTER 26-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 24 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control edge source 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 23 EDG2MOD: Edge 2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 22 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Reserved 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = PBCLK clock is selected 1011 = IC3 Capture Event is selected 1010 = IC2 Capture Event is selected 1001 = IC1 Capture Event is selected 1000 = CTED13 pin is selected 0111 = CTED12 pin is selected 0110 = CTED11 pin is selected 0101 = CTED10 pin is selected 0100 = CTED9 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 17-16 Unimplemented: Read as `0' bit 15 ON: ON Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as `0' bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked Note 1: 2: 3: 4: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to `1110' to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 31-42) in Section 31.0 "Electrical Characteristics" for current values. This bit setting is not available for the CTMU temperature diode. DS60001185G-page 254 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 26-1: bit 10 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 must occur before Edge 2 can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 bit 9 bit 8 bit 7-2 * * * 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current * * * 100010 100001 = Maximum negative change from nominal current IRNG<1:0>: Current Range Select bits(3) 11 = 100 times base current 10 = 10 times base current 01 = Base current level 00 = 1000 times base current(4) bit 1-0 Note 1: 2: 3: 4: When this bit is set for Pulse Delay Generation, the EDG2SEL<3:0> bits must be set to `1110' to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to `1', performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 31-42) in Section 31.0 "Electrical Characteristics" for current values. This bit setting is not available for the CTMU temperature diode. 2012-2017 Microchip Technology Inc. DS60001185G-page 255 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 256 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 27.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "PowerSaving Features" (DS60001130), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). This section describes power-saving features for the PIC32MX330/350/370/430/450/470 family of devices. These PIC32 devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-saving is controlled by software. 27.1 Power Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK and by individually disabling modules. These methods are grouped into the following categories: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. In addition, the Peripheral Bus Scaling mode is available where peripherals are clocked at the programmable fraction of the CPU clock (SYSCLK). 27.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which Halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. * SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. * LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock 2012-2017 Microchip Technology Inc. running. * Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. 27.3 Power-Saving Operation Peripherals and the CPU can be Halted or disabled to further reduce power consumption. 27.3.1 SLEEP MODE Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are Halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics: * The CPU is Halted. * The system clock source is typically shutdown. See Section 27.3.3 "Peripheral Bus Scaling Method" for specific information. * There can be a wake-up delay based on the oscillator selection. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit remains operative during Sleep mode. * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. * Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture). * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. * The USB module can override the disabling of the Posc or FRC. Refer to the USB section for specific details. * Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption. DS60001185G-page 257 PIC32MX330/350/370/430/450/470 The processor will exit, or `wake-up', from Sleep on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset * On a WDT time-out If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. 27.3.2 IDLE MODE In Idle mode, the CPU is Halted but the System Clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted. Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. Note 1: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in the PB divisor ratio. 2: Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator startup delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator start-up/lock delays would be applied. DS60001185G-page 258 The device enters Idle mode when the SLPEN bit (OSCCON<4>) is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode. * On any form of device Reset * On a WDT time-out interrupt 27.3.3 PERIPHERAL BUS SCALING METHOD Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as the USB, Interrupt Controller, DMA, and the bus matrix are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes. Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power, the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 27.4 To disable a peripheral, the associated PMDx bit must be set to `1'. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 27-1 for more information. Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. TABLE 27-1: Note: Disabling a peripheral module while it's ON bit is set, may result in undefined behavior. The ON bit for the associated peripheral module must be cleared prior to disable a module via the PMDx bits. PERIPHERAL MODULE DISABLE BITS AND LOCATIONS Peripheral(1) PMDx bit Name(1) Register Name and Bit Location ADC1 AD1MD PMD1<0> CTMU CTMUMD PMD1<8> CVRMD PMD1<12> Comparator Voltage Reference Comparator 1 CMP1MD PMD2<0> Comparator 2 CMP2MD PMD2<1> Input Capture 1 IC1MD PMD3<0> Input Capture 2 IC2MD PMD3<1> Input Capture 3 IC3MD PMD3<2> Input Capture 4 IC4MD PMD3<3> Input Capture 5 IC5MD PMD3<4> Output Compare 1 OC1MD PMD3<16> Output Compare 2 OC2MD PMD3<17> Output Compare 3 OC3MD PMD3<18> Output Compare 4 OC4MD PMD3<19> Output Compare 5 OC5MD PMD3<20> Timer1 T1MD PMD4<0> Timer2 T2MD PMD4<1> Timer3 T3MD PMD4<2> Timer4 T4MD PMD4<3> Timer5 T5MD PMD4<4> UART1 U1MD PMD5<0> UART2 U2MD PMD5<1> UART3 U3MD PMD5<2> UART4 U4MD PMD5<3> UART5 U5MD PMD5<4> SPI1 SPI1MD PMD5<8> SPI2 SPI2MD PMD5<9> I2C1 I2C1MD PMD5<16> I2C2 I2C2MD PMD5<17> (2) USBMD PMD5<24> RTCC RTCCMD PMD6<0> Reference Clock Output REFOMD PMD6<1> PMPMD PMD6<16> USB PMP Note 1: 2: Not all modules and associated PMDx bits are available on all devices. See TABLE 1: "PIC32MX330/ 350/370/430/450/470 Controller Family Features" for the lists of available peripherals. Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit. 2012-2017 Microchip Technology Inc. DS60001185G-page 259 PIC32MX330/350/370/430/450/470 27.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals: * Control register lock sequence * Configuration bit select lock 27.4.1.1 Control Register Lock Under normal operation, writes to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the PMDLOCK Configuration bit (CFGCON<12>). Setting PMDLOCK prevents writes to the control registers; clearing PMDLOCK allows writes. To set or clear PMDLOCK, an unlock sequence must be executed. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. 27.4.1.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the PMDx registers. The PMDL1WAY Configuration bit (DEVCFG3<28>) blocks the PMDLOCK bit from being cleared after it has been set once. If PMDLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable PMD functionality is to perform a device Reset. DS60001185G-page 260 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 28.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX330/350/370/430/450/470 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 32. "Configuration" (DS60001124) and Section 33. "Programming and Diagnostics" (DS60001129), which are available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). 28.1 Configuration Bits The Configuration bits can be programmed using the following registers to select various device configurations. * * * * * DEVCFG0: Device Configuration Word 0 DEVCFG1: Device Configuration Word 1 DEVCFG2: Device Configuration Word 2 DEVCFG3: Device Configuration Word 3 CFGCON: Configuration Control Register In addition, the DEVID register (Register 28-6) provides device and revision information. The PIC32MX330/350/370/430/450/470 family of devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are: * Flexible device configuration * Joint Test Action Group (JTAG) interface * In-Circuit Serial ProgrammingTM (ICSPTM) 2012-2017 Microchip Technology Inc. DS60001185G-page 261 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 -- -- -- -- -- -- -- 31:16 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY 15:0 USERID<15:0> 31:16 -- -- -- -- -- -- -- -- -- -- -- 2FF4 DEVCFG2 15:0 UPLLEN(1) -- -- -- -- UPLLIDIV<2:0>(1) -- FPLLMUL<2:0> 31:16 -- -- -- -- -- -- FWDTWINSZ<1:0> FWDTEN WINDIS -- 2FF8 DEVCFG1 15:0 FCKSM<1:0> FPBDIV<1:0> -- OSCIOFNC POSCMOD<1:0> IESO -- FSOSCEN 31:16 -- -- -- CP -- -- -- BWP -- -- -- 2FFC DEVCFG0 15:0 PWP<3:0> -- -- -- -- -- -- -- Legend: x = unknown value on Reset; -- = reserved, write as `1'. Reset values are shown in hexadecimal. Note 1: This bit is only available on devices with a USB module. 20/4 19/3 -- -- -- -- -- 2FF0 DEVCFG3 F200 CFGCON F220 17/1 16/0 FSRSSEL<2:0> FPLLODIV<2:0> FPLLIDIV<2:0> WDTPS<4:0> FNOSC<2:0> PWP<7:4> JTAGEN DEBUG<1:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx DEVICE ID, REVISION, AND CONFIGURATION SUMMARY DEVID 30/14 31:16 -- -- 15:0 -- -- 31:16 15:0 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IOLOCK PMDLOCK VER<3:0> DEVID<27:16> DEVID<15:0> 19/3 16/0 All Resets 31/15 31:16 SYSKEY<31:0> 15:0 x = unknown value on Reset; -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. F230 SYSKEY 2012-2017 Microchip Technology Inc. Legend: Note 1: Bit Range Bits Register Name Virtual Address (BF80_#) TABLE 28-2: -- -- -- ICESEL<1:0> 18/2 All Resets Bit Range Bits Register Name Virtual Address (BFC0_#) DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 18/2 17/1 -- -- -- -- 0000 JTAGEN TROEN -- TDOEN 000B xxxx(1) xxxx(1) 0000 0000 PIC32MX330/350/370/430/450/470 DS60001185G-page 262 TABLE 28-1: PIC32MX330/350/370/430/450/470 REGISTER 28-1: Bit Range 31:24 23:16 15:8 7:0 DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P -- -- -- CP -- -- -- BWP R/P R/P R/P R/P r-1 r-1 r-1 r-1 -- -- -- -- R/P R/P R/P R/P PWP<3:0> r-1 r-1 r-1 -- -- -- Legend: R = Readable bit -n = Value at POR r = Reserved bit W = Writable bit `1' = Bit is set R/P PWP<7:4> r-1 r-1 r-1 r-1 -- -- -- -- R/P R/P R/P R/P ICESEL<1:0> JTAGEN(1) DEBUG<1:0> P = Programmable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 Reserved: Write `0' bit 30-29 Reserved: Write `1' bit 28 CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection is disabled 0 = Protection is enabled bit 27-25 Reserved: Write `1' bit 24 BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 23-20 Reserved: Write `1' bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF . . . 01111111 = 0xBD07_FFFF Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register. 2012-2017 Microchip Technology Inc. DS60001185G-page 263 PIC32MX330/350/370/430/450/470 REGISTER 28-1: bit 11-5 bit 4-3 bit 2 bit 1-0 Note 1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) Reserved: Write `1' ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits 11 = PGEC1/PGED1 pair is used 10 = PGEC2/PGED2 pair is used 01 = PGEC3/PGED3 pair is used 00 = Reserved JTAGEN: JTAG Enable bit(1) 1 = JTAG is enabled 0 = JTAG is disabled DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 1x = Debugger is disabled 0x = Debugger is enabled This bit sets the value for the JTAGEN bit in the CFGCON register. DS60001185G-page 264 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 28-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- R/P R/P r-1 R/P R/P R/P FWDTEN WINDIS -- R/P R/P R/P R/P r-1 R/P -- OSCIOFNC R/P FCKSM<1:0> Bit 25/17/9/1 Bit 24/16/8/0 R/P R/P FWDTWINSZ<1:0> R/P R/P R/P R/P WDTPS<4:0> FPBDIV<1:0> R/P r-1 R/P r-1 r-1 IESO -- FSOSCEN -- -- POSCMOD<1:0> R/P R/P FNOSC<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-26 Reserved: Write `1' bit 25-24 FWDTWINSZ<1:0>: Watchdog Timer Window Size bits 11 = Window size is 25% 10 = Window size is 37.5% 01 = Window size is 50% 00 = Window size is 75% bit 23 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled and cannot be disabled by software 0 = Watchdog Timer is not enabled; it can be enabled in software bit 22 WINDIS: Watchdog Timer Window Enable bit 1 = Watchdog Timer is in non-Window mode 0 = Watchdog Timer is in Window mode bit 21 Reserved: Write `1' bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. 2012-2017 Microchip Technology Inc. DS60001185G-page 265 PIC32MX330/350/370/430/450/470 REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write `1' bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output is disabled 0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00) bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = External Clock mode is selected bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) bit 6 Reserved: Write `1' bit 5 FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 4-3 Reserved: Write `1' bit 2-0 FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. DS60001185G-page 266 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 28-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 -- -- -- -- -- -- -- -- r-1 r-1 r-1 r-1 r-1 R/P R/P R/P -- -- -- -- -- R/P r-1 r-1 r-1 r-1 UPLLEN(1) -- -- -- -- r-1 R/P-1 R/P R/P-1 r-1 -- FPLLMUL<2:0> FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0>(1) R/P -- R/P R/P FPLLIDIV<2:0> Legend: r = Reserved bit P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-19 Reserved: Write `1' bit 18-16 FPLLODIV<2:0>: Default PLL Output Divisor bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit(1) 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write `1' bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits(1) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write `1' bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write `1' Note 1: This bit is available on PIC32MX4XX devices only. 2012-2017 Microchip Technology Inc. DS60001185G-page 267 PIC32MX330/350/370/430/450/470 REGISTER 28-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Note 1: This bit is available on PIC32MX4XX devices only. DS60001185G-page 268 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 28-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/P R/P R/P R/P U-0 U-0 U-0 FVBUSONIO FUSBIDIO IOL1WAY PMDL1WAY -- -- -- -- U-0 U-0 U-0 U-0 U-0 R/P R/P R/P -- -- -- -- -- R/P R/P R/P R/P R/P FSRSSEL<2:0> R/P R/P R/P R/P R/P R/P USERID<15:8> R/P R/P Legend: R = Readable bit -n = Value at POR R/P R/P R/P USERID<7:0> r = Reserved bit W = Writable bit `1' = Bit is set P = Programmable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 31 FVBUSONIO: USB VBUS_ON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function bit 30 FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function bit 29 IOL1WAY: Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 28 PMDL1WAY: Peripheral Module Disable Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 27-19 Unimplemented: Read as `0' bit 18-16 FSRSSEL<2:0>: Shadow Register Set Priority Select bit These bits assign an interrupt priority to a shadow register. 111 = Shadow register set used with interrupt priority 7 110 = Shadow register set used with interrupt priority 6 101 = Shadow register set used with interrupt priority 5 100 = Shadow register set used with interrupt priority 4 011 = Shadow register set used with interrupt priority 3 010 = Shadow register set used with interrupt priority 2 001 = Shadow register set used with interrupt priority 1 000 = Shadow register set used with interrupt priority 0 bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSPTM and JTAG 2012-2017 Microchip Technology Inc. DS60001185G-page 269 PIC32MX330/350/370/430/450/470 REGISTER 28-5: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 -- -- -- -- JTAGEN TROEN -- TDOEN IOLOCK(1) PMDLOCK(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as `0' bit 13 IOLOCK: Peripheral Pin Select Lock bit(1) 1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed 0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed bit 12 PMDLOCK: Peripheral Module Disable bit(1) 1 = Peripheral module is locked. Writes to PMD registers is not allowed 0 = Peripheral module is not locked. Writes to PMD registers is allowed bit 11-4 Unimplemented: Read as `0' bit 3 JTAGEN: JTAG Port Enable bit 1 = Enable the JTAG port 0 = Disable the JTAG port bit 2 TROEN: Trace Output Enable bit 1 = Enable trace outputs and start trace clock (trace probe must be present) 0 = Disable trace outputs and stop trace clock bit 1 Unimplemented: Read as `0' bit 0 TDOEN: TDO Enable for 2-Wire JTAG 1 = 2-wire JTAG protocol uses TDO 0 = 2-wire JTAG protocol does not use TDO Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 6. "Oscillator" (DS60001112) in the "PIC32 Family Reference Manual" for details. DS60001185G-page 270 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 REGISTER 28-6: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R R R R R VER<3:0>(1) R R R R R R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R DEVID<27:24>(1) R R (1) DEVID<23:16> R R R R R R R R R R R DEVID<15:8>(1) R R R R R (1) DEVID<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 DEVID<27:0>: Device ID(1) Note 1: See the "PIC32 Flash Programming Specification" (DS60001145) for a list of Revision and Device ID values. 2012-2017 Microchip Technology Inc. DS60001185G-page 271 PIC32MX330/350/370/430/450/470 28.2 On-Chip Voltage Regulator All PIC32MX330/350/370/430/450/470 devices' core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX330/350/370/430/450/470 family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 28-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 31.1 "DC Characteristics". It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. Note: 28.2.1 HIGH VOLTAGE DETECT (HVD) The HVD module monitors the core voltage at the VCAP pin. If a voltage above the required level is detected on VCAP, the I/O pins are disabled and the device is held in Reset as long as the HVD condition persists. See parameter HV10 (VHVD) in Table 31-11 in Section 31.1 "DC Characteristics" for more information. 28.2.2 ON-CHIP REGULATOR AND POR It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. 28.2.3 28.3 Programming and Diagnostics PIC32MX330/350/370/430/450/470 devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire In-Circuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. FIGURE 28-2: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS PGEC1 PGED1 ICSPTM Controller PGEC3 PGED3 ON-CHIP REGULATOR AND BOR PIC32MX330/350/370/430/450/470 devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 31.1 "DC Characteristics". FIGURE 28-1: ICESEL TDI TDO TCK JTAG Controller Core TMS JTAGEN CONNECTIONS FOR THE ON-CHIP REGULATOR DEBUG<1:0> TRCLK 3.3V(1) PIC32 VDD TRD0 TRD1 Instruction Trace Controller TRD2 VCAP CEFC(2,3) (10 F typ) TRD3 VSS DEBUG<1:0> Note 1: 2: 3: These are typical operating voltages. Refer to Section 31.1 "DC Characteristics" for the full operating ranges of VDD. It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. The typical voltage on the VCAP pin is 1.8V. DS60001185G-page 272 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 29.0 INSTRUCTION SET The PIC32MX330/350/370/430/450/470 family instruction set complies with the MIPS32(R) Release 2 instruction set architecture. The PIC32 device family does not support the following features: * Core extend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions Note: Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.imgtec.com for more information. 2012-2017 Microchip Technology Inc. DS60001185G-page 273 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 274 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 30.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers (MCU) and dsPIC(R) digital signal controllers (DSC) are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) X IDE Software * Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB X SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkitTM 3 * Device Programmers - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits * Third-party development tools 30.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows(R), Linux and Mac OS(R) X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: * Color syntax highlighting * Smart code completion makes suggestions and provides hints as you type * Automatic code formatting based on user-defined rules * Live parsing User-Friendly, Customizable Interface: * Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. * Call graph window Project-Based Workspaces: * * * * Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: * Local file history feature * Built-in support for Bugzilla issue tracker 2012-2017 Microchip Technology Inc. DS60001185G-page 275 PIC32MX330/350/370/430/450/470 30.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip's 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 30.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 30.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility * Integration into MPLAB X IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multipurpose source files * Directives that allow complete control over the assembly process DS60001185G-page 276 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 30.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 30.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 2012-2017 Microchip Technology Inc. 30.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 30.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer's PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM (ICSPTM). 30.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS60001185G-page 277 PIC32MX330/350/370/430/450/470 30.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 30.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. * Device Programmers and Gang Programmers from companies, such as SoftLog and CCS * Software Tools from companies, such as Gimpel and Trace Systems * Protocol Analyzers from companies, such as Saleae and Total Phase * Demonstration Boards from companies, such as MikroElektronika, Digilent(R) and Olimex * Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika(R) The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS60001185G-page 278 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 31.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX330/350/370/430/450/470 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX330/350/370/430/450/470 devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings (See Note 1) Ambient temperature under bias.............................................................................................................-40C to +105C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +6.0V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB3V3 .................................................................... -0.3V to (VUSB3V3 + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................200 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................200 mA Maximum output current sourced/sunk by any 4x I/O pin .......................................................................................15 mA Maximum output current sourced/sunk by any 8x I/O pin .......................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................150 mA Maximum current sourced by all ports (Note 2)....................................................................................................150 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: See the "Device Pin Tables" section for the 5V tolerant pins. 2012-2017 Microchip Technology Inc. DS60001185G-page 279 PIC32MX330/350/370/430/450/470 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) Characteristic DC5 2.3-3.6V DC5b PIC32MX330/350/370/430/450/470 (1) -40C to +85C 100 MHz (1) -40C to +105C 80 MHz (1) 0C to +70C 120 MHz 2.3-3.6V DC5c 2.3-3.6V Note 1: Max. Frequency Temp. Range (in C) Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for VBORMIN values. TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min. Typical Max. Unit Operating Junction Temperature Range TJ Operating Ambient Temperature Range TA 0 0 -- -- +115 +70 C C Industrial Temperature Devices Operating Junction Temperature Range TJ Operating Ambient Temperature Range TA -40 -40 -- -- +125 +85 C C -40 -40 -- -- +140 +105 C C Commercial Temperature Devices V-temp Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) I/O Pin Power Dissipation: I/O = S (({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation TABLE 31-3: TJ TA PD PINT + PI/O W PDMAX (TJ - TA)/JA W THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical Max. Unit Notes Package Thermal Resistance, 64-pin QFN (9x9x0.9 mm) JA 28 -- C/W 1 Package Thermal Resistance, 64-pin TQFP (10x10x1 mm) JA 47 -- C/W 1 Package Thermal Resistance, 100-pin TQFP (12x12x1 mm) JA 43 -- C/W 1 Package Thermal Resistance, 100-pin TQFP (14x14x1 mm) JA 43 -- C/W 1 Package Thermal Resistance, 124-pin VTLA JA 21 -- C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS60001185G-page 280 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions Operating Voltage DC10 VDD Supply Voltage 2.3 -- 3.6 V -- DC12 VDR RAM Data Retention Voltage (Note 1) 1.75 -- -- V -- DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal 1.75 -- 2.1 V -- DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal 0.00005 -- 0.115 V/s -- Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2012-2017 Microchip Technology Inc. DS60001185G-page 281 PIC32MX330/350/370/430/450/470 TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Parameter No. Typical(3) Maximum Units Conditions Operating Current (IDD)(1,2) DC20 2.5 4 mA 4 MHz DC21 6 9 mA 10 MHz (Note 4) DC22 11 17 mA 20 MHz (Note 4) DC23 21 32 mA 40 MHz (Note 4) DC24 30 45 mA 60 MHz (Note 4) DC25 40 60 mA 80 MHz DC25a 50 75 mA 100 MHz, -40C TA +85C DC25c 72 84 mA 120 MHz, 0C TA +70C 100 -- A DC26 Note 1: 2: 3: 4: +25C, 3.3V LPRC (31 kHz) (Note 4) A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating (ON bit = 0), but the associated PMD bit is clear * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * CPU executing while(1) statement from Flash * RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. DS60001185G-page 282 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Parameter No. Typical(2) Maximum Units Conditions Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) DC30a 1 2.2 mA 4 MHz DC31a 3 5 mA 10 MHz (Note 3) DC32a 5 7 mA 20 MHz (Note 3) DC33a 8 13 mA 40 MHz (Note 3) DC34a 11 18 mA 60 MHz (Note 3) DC34b 15 24 mA 80 MHz DC34c 19 29 mA 100 MHz, -40C TA +85C 120 MHz, 0C TA +70C DC34d 25 34 mA DC37a 100 -- A -40C DC37b 250 -- A +25C DC37c 380 -- A +85C Note 1: 2: 3: 3.3V LPRC (31 kHz) (Note 3) The test conditions for IIDLE measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Idle mode (CPU core is halted), program Flash memory Wait states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. 2012-2017 Microchip Technology Inc. DS60001185G-page 283 PIC32MX330/350/370/430/450/470 TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Param. No. Typ.(2) Units Max. Conditions PIC32MX330 Devices Only Power-Down Current (IPD) (Note 1) DC40k 20 55 A DC40l 38 55 A DC40n 128 167 A DC40m 261 419 A -40C +25C +85C +105C Base Power-Down Current -40C +25C +85C +105C Base Power-Down Current -40C +25C +85C +105C Base Power-Down Current PIC32MX430 Devices Only Power-Down Current (IPD) (Note 1) DC40k 12 28 A DC40l 21 28 A DC40n 128 167 A DC40m 261 419 A PIC32MX350F128 Devices Only Power-Down Current (IPD) (Note 1) DC40k 31 70 A DC40l 45 70 A DC40n 175 280 A DC40m 415 600 A PIC32MX450F128 Devices Only Power-Down Current (IPD) (Note 1) DC40k 19 35 A -40C DC40l 28 35 A +25C Base Power-Down Current DC40n 175 280 A +85C DC40m 415 600 A +105C Note 1: The test conditions for IPD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, program Flash memory Wait states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled * Voltage regulator is off during Sleep mode (VREGS bit in the RCON register = 0) 2: Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: 120 MHz commercial devices only (0C to +70C). DS60001185G-page 284 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Param. No. Typ.(2) Units Max. Conditions PIC32MX350F256 Devices Only Power-Down Current (IPD) (Note 1) DC40k 38 80 A DC40l 57 80 A DC40n 220 352 A DC40m 513 749 A PIC32MX450F256 Devices Only -40C +25C +85C +105C Base Power-Down Current Power-Down Current (IPD) (Note 1) DC40k 26 42 A -40C DC40o 26 42 A 0C(5) DC40l 26 42 A +25C Base Power-Down Current DC40p 250 352 A +70C(5) DC40n 250 352 A +85C DC40m 513 749 A +105C Note 1: The test conditions for IPD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, program Flash memory Wait states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled * Voltage regulator is off during Sleep mode (VREGS bit in the RCON register = 0) 2: Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: 120 MHz commercial devices only (0C to +70C). 2012-2017 Microchip Technology Inc. DS60001185G-page 285 PIC32MX330/350/370/430/450/470 TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Param. No. Typ.(2) Units Max. Conditions PIC32MX370 Devices Only Power-Down Current (IPD) (Note 1) DC40k 55 95 A DC40l 81 95 A DC40n 281 450 A DC40m 559 895 A PIC32MX470 Devices Only -40C +25C +85C +105C Base Power-Down Current Power-Down Current (IPD) (Note 1) DC40k 33 78 A -40C DC40o 33 78 A 0C(5) DC40l 49 78 A +25C Base Power-Down Current DC40p 281 450 A +70C(5) DC40n 281 450 A +85C DC40m 559 895 A +105C PIC32MX330/350/370/430/450/470 Devices Module Differential Current DC41e 6.7 20 A 3V Watchdog Timer Current: IWDT (Note 3) DC42e 29.1 50 A 3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) DC43d 1000 1200 A 3V ADC: IADC (Notes 3,4) Note 1: The test conditions for IPD measurements are as follows: * Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required) * OSC2/CLKO is configured as an I/O input pin * USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8 * CPU is in Sleep mode, program Flash memory Wait states = 7, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1 * No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set * WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled * All I/O pins are configured as inputs and pulled to VSS * MCLR = VDD * RTCC and JTAG are disabled * Voltage regulator is off during Sleep mode (VREGS bit in the RCON register = 0) 2: Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: 120 MHz commercial devices only (0C to +70C). DS60001185G-page 286 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symb. No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typ.(1) Max. Units DI18 Input Low Voltage I/O Pins with PMP I/O Pins SDAx, SCLx VSS VSS VSS -- -- -- 0.15 VDD 0.2 VDD 0.3 VDD V V V DI19 SDAx, SCLx VSS -- 0.8 V 0.65 VDD 0.25 VDD + 0.8V -- -- VDD 5.5 V V 0.65 VDD 0.65 VDD -- -- 5.5 5.5 V V 2.1 -- 5.5 V DI10 VIL Characteristics DI28 Input High Voltage I/O Pins not 5V-tolerant(5) I/O Pins 5V-tolerant with PMP(5) I/O Pins 5V-tolerant(5) SDAx, SCLx DI29 SDAx, SCLx DI20 VIH Conditions SMBus disabled (Note 4) SMBus enabled (Note 4) (Note 4,6) (Note 4,6) SMBus disabled (Note 4,6) SMBus enabled, 2.3V VPIN 5.5 (Note 4,6) VDD = 3.3V, VPIN = VSS (Note 3,6) VDD = 3.3V, VPIN = VDD Change Notification -- -- -50 A Pull-up Current DI31 ICNPD Change Notification -- 50 -- A Pull-down Current(4) Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the "Device Pin Tables" section for the 5V tolerant pins. 6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32 device are guaranteed to be recognized only as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the minimum value of ICNPU. For External "input" logic inputs that require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the PIC32 device. 7: VIL source < (VSS - 0.3). Characterized but not tested. 8: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any "positive" input injection current. 10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)). 11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0. DI30 ICNPU 2012-2017 Microchip Technology Inc. DS60001185G-page 287 PIC32MX330/350/370/430/450/470 TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param. Symb. No. DI50 DI51 IIL Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typ.(1) Max. Units Input Leakage Current (Note 3) I/O Ports -- -- +1 A Analog Input Pins -- -- +1 A Characteristics Conditions VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes Pins with Analog functions. Exceptions: [N/A] = 0 mA max Digital 5V tolerant desigInput Low Injection 0 -- -5(7,10) mA nated pins. Exceptions: DI60a IICL Current [N/A] = 0 mA max Digital non-5V tolerant designated pins. Exceptions: [N/A] = 0 mA max Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the "Device Pin Tables" section for the 5V tolerant pins. 6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32 device are guaranteed to be recognized only as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the minimum value of ICNPU. For External "input" logic inputs that require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the PIC32 device. 7: VIL source < (VSS - 0.3). Characterized but not tested. 8: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any "positive" input injection current. 10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)). 11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0. DI55 DI56 MCLR(2) OSC1 DS60001185G-page 288 -- -- -- -- +1 +1 A A 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param. Symb. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typ.(1) Max. Units Conditions Pins with Analog functions. Exceptions: [SOSCI, SOSCO, OSC1, D+, D-] = 0 mA max. Digital 5V tolerant desigInput High Injection 0 -- +5(8,9,10) mA nated pins (VIH < 5.5V)(9). DI60b IICH Current Exceptions: [All] = 0 mA max. Digital non-5V tolerant designated pins. Exceptions: [N/A] = 0 mA max. DI60c IICT Total Input Injection -20(11) -- +20(11) mA Absolute instantaneous sum Current (sum of all I/O of all input injection curand control pins) rents from all I/O pins ( | IICL + | IICH | ) IICT Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: This parameter is characterized, but not tested in manufacturing. 5: See the "Device Pin Tables" section for the 5V tolerant pins. 6: The VIH specifications are only in relation to externally applied inputs, and not with respect to the userselectable internal pull-ups. External open drain input signals utilizing the internal pull-ups of the PIC32 device are guaranteed to be recognized only as a logic "high" internally to the PIC32 device, provided that the external load does not exceed the minimum value of ICNPU. For External "input" logic inputs that require a pull-up source, to guarantee the minimum VIH of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the PIC32 device. 7: VIL source < (VSS - 0.3). Characterized but not tested. 8: VIH source > (VDD + 0.3) for non-5V tolerant pins only. 9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any "positive" input injection current. 10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD + 0.3) or VIL source < (VSS - 0.3)). 11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the "absolute instantaneous" sum of the input injection currents from all pins do not exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDD + 0.3), injection current = 0. 2012-2017 Microchip Technology Inc. DS60001185G-page 289 PIC32MX330/350/370/430/450/470 TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH DO20A VOH1 Note 1: Characteristic Output Low Voltage I/O Pins: 4x Sink Driver Pins - All I/O output pins not defined as 8x Sink Driver pins Output Low Voltage I/O Pins: 8x Sink Driver Pins - RC15, RD2, RD10, RF6, RG6 Output High Voltage I/O Pins: 4x Source Driver Pins - All I/O output pins not defined as 8x Source Driver pins Output High Voltage I/O Pins: 8x Source Driver Pins - RC15, RD2, RD10, RF6, RG6 Output High Voltage I/O Pins: 4x Source Driver Pins - All I/O output pins not defined as 8x Sink Driver pins Output High Voltage I/O Pins: 8x Source Driver Pins - RC15, RD2, RD10, RF6, RG6 Min. Typ. Max. Units Conditions -- -- 0.4 V IOL 9 mA, VDD = 3.3V -- -- 0.4 V IOL 15 mA, VDD = 3.3V 2.4 -- -- V IOH -10 mA, VDD = 3.3V 2.4 -- -- V IOH -15 mA, VDD = 3.3V 1.5(1) -- -- 2.0(1) -- -- (1) -- -- IOH -7 mA, VDD = 3.3V 1.5(1) -- -- IOH -22 mA, VDD = 3.3V 2.0(1) -- -- 3.0(1) -- -- 3.0 IOH -14 mA, VDD = 3.3V V V IOH -12 mA, VDD = 3.3V IOH -18 mA, VDD = 3.3V IOH -10 mA, VDD = 3.3V Parameters are characterized, but not tested. DS60001185G-page 290 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. BO10 Note 1: VBOR Characteristics BOR Event on VDD transition high-to-low Min.(1) Typical 2.0 -- Max. Units Conditions 2.3 V -- Parameters are for design guidance only and are not tested in manufacturing. TABLE 31-11: ELECTRICAL CHARACTERISTICS: HVD Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No.(1) HV10 Note 1: VHVD Characteristics High Voltage Detect on VCAP pin Min. Typical Max. Units Conditions -- 2.5 -- V -- Parameters are for design guidance only and are not tested in manufacturing. 2012-2017 Microchip Technology Inc. DS60001185G-page 291 PIC32MX330/350/370/430/450/470 TABLE 31-12: DC CHARACTERISTICS: PROGRAM MEMORY(3) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. D130 Characteristics EP Cell Endurance Min. Typical(1) Max. Units Conditions 20,000 -- -- E/W -- D131 VPR VDD for Read 2.3 -- 3.6 V -- D132 VPEW VDD for Erase or Write 2.3 -- 3.6 V -- D134 TRETD Characteristic Retention 20 -- -- Year Provided no other specifications are violated D135 IDDP Supply Current during Programming -- 10 -- mA -- D138 TWW Word Write Cycle Time(4) 44 -- 59 s -- D136 TRW Row Write Cycle Time(2,4) 2.8 3.3 3.8 ms -- D137 TPE Page Erase Cycle Time(4) 22 -- 29 ms -- D139 TCE Chip Erase Cycle Time(4) 86 -- 116 ms -- Note 1: 2: 3: 4: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 8 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to the "PIC32 Flash Programming Specification" (DS60001145) for operating conditions during programming and erase cycles. This parameter depends on the FRC accuracy (see Table 31-20) and the FRC tuning values (see Register 8-2). TABLE 31-13: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATE DC CHARACTERISTICS Required Flash Wait States 0 Wait State 1 Wait State 2 Wait States 3 Wait States DS60001185G-page 292 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp SYSCLK Units Conditions 0-40 MHz -40C to +85C 0-30 MHz -40C to +105C 41-80 MHz -40C to +85C 31-60 MHz -40C to +105C 81-100 MHz -40C to +85C 61-80 MHz -40C to +105C 101-120 MHz 0C to +70C 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-14: COMPARATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage -- 7.5 25 mV AVDD = VDD, AVSS = VSS D301 VICM Input Common Mode Voltage 0 -- VDD V AVDD = VDD, AVSS = VSS (Note 2) D302 CMRR Common Mode Rejection Ratio 55 -- -- dB Max VICM = (VDD - 1)V (Note 2) D303 TRESP Response Time -- 150 400 ns AVDD = VDD, AVSS = VSS (Notes 1,2) D304 ON2OV Comparator Enabled to Output Valid -- -- 10 s Comparator module is configured before setting the comparator ON bit (Note 2) D305 IVREF Internal Voltage Reference 1.14 1.2 1.26 V -- Note 1: 2: 3: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested. Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing. 2012-2017 Microchip Technology Inc. DS60001185G-page 293 PIC32MX330/350/370/430/450/470 TABLE 31-15: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typ. Max. Units -- -- 10 s See Note 1 AVSS -- AVDD V CVRSRC with CVRSS = 0 VREF- -- VREF+ V CVRSRC with CVRSS = 1 0 -- 0.625 x DACREFH V 0 to 0.625 DACREFH with DACREFH/24 step size 0.25 x DACREFH -- 0.719 x DACREFH V 0.25 x DACREFH to 0.719 DACREFH with DACREFH/ 32 step size -- DACREFH/24 Internal 4-bit DAC Comparator Reference Settling time. D312 TSET D313 DACREFH CVREF Input Voltage Reference Range D314 DVREF CVREF Programmable Output Range Comments D315 DACRES Resolution -- -- -- DACREFH/32 D316 DACACC Absolute Accuracy(2) -- -- 1/4 LSB DACREFH/24, CVRCON<CVRR> = 1 -- -- 1/2 LSB DACREFH/32, CVRCON<CVRR> = 0 Note 1: 2: CVRCON<CVRR> = 1 CVRCON<CVRR> = 0 Settling time was measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. This parameter is characterized, but is not tested in manufacturing. These parameters are characterized but not tested. TABLE 31-16: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp DC CHARACTERISTICS Param. No. D321 Symbol CEFC Characteristics Min. Typical Max. Units Comments External Filter Capacitor Value 8 10 -- F Capacitor must be low series resistance (3 ohm). Typical voltage on the VCAP pin is 1.8V. DS60001185G-page 294 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 31.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX330/350/370/430/450/470 AC characteristics and timing parameters. FIGURE 31-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) VSS TABLE 31-17: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Param. Symbol No. Min. Typical(1) Max. Units Characteristics Conditions DO50 COSCO OSC2 pin -- -- 15 pF In XT and HS modes when an external crystal is used to drive OSC1 DO56 CIO All I/O pins and OSC2 -- -- 50 pF EC mode DO58 CB SCLx, SDAx -- -- 400 pF In I2C mode Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 31-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 2012-2017 Microchip Technology Inc. OS31 DS60001185G-page 295 PIC32MX330/350/370/430/450/470 TABLE 31-18: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. OS10 FOSC OS11 Min. Typical(1) Max. Units Conditions External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) DC 4 -- -- 50 50 MHz MHz EC (Note 4) ECPLL (Note 3) Oscillator Crystal Frequency Characteristics 3 -- 10 MHz XT (Note 4) OS12 4 -- 10 MHz XTPLL (Notes 3,4) OS13 10 -- 25 MHz HS (Note 4) OS14 10 -- 25 MHz HSPLL (Notes 3,4) OS15 32 32.768 100 kHz SOSC (Note 4) -- -- -- -- See parameter OS10 for FOSC value OS20 TOSC TOSC = 1/FOSC = TCY (Note 2) OS30 TOSL, TOSH External Clock In (OSC1) High or Low Time 0.45 x TOSC -- -- ns EC (Note 4) OS31 TOSR, TOSF External Clock In (OSC1) Rise or Fall Time -- -- 0.05 x TOSC ns EC (Note 4) OS40 TOST Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) -- 1024 -- OS41 TFSCM Primary Clock Fail Safe Time-out Period -- 2 -- OS42 GM External Oscillator Transconductance (Primary Oscillator only) -- 12 -- Note 1: 2: 3: 4: TOSC (Note 4) ms (Note 4) mA/V VDD = 3.3V, TA = +25C (Note 4) Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing. DS60001185G-page 296 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-19: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. 3.92 OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range OS51a FSYS On-Chip VCO System Frequency OS51b OS51c OS52 OS53 Note 1: 2: TLOCK DCLK PLL Start-up Time (Lock Time) Stability(2) CLKO (Period Jitter or Cumulative) Typical Max. -- 5 Units MHz Conditions ECPLL, HSPLL, XTPLL, FRCPLL modes 60 -- 120 MHz Commercial devices 60 -- 100 MHz Industrial devices 60 -- 80 MHz V-temp devices -- -- 2 ms -0.25 -- +0.25 % -- Measured over 100 ms period These parameters are characterized, but not tested in manufacturing. This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D CLK EffectiveJitter = -------------------------------------------------------------SYSCLK ---------------------------------------------------------CommunicationClock For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: D CLK D CLK EffectiveJitter = ------------- = ------------1.41 40 -----20 TABLE 31-20: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param. No. Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical Max. Units Conditions -- +0.9 % -- Internal FRC Accuracy @ 8.00 MHz(1) F20b Note 1: FRC -0.9 Frequency calibrated at 25C and 3.3V. The TUN bits can be used to compensate for temperature drift. 2012-2017 Microchip Technology Inc. DS60001185G-page 297 PIC32MX330/350/370/430/450/470 TABLE 31-21: INTERNAL LPRC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Characteristics Min. Typical Max. Units Conditions -15 -- +15 % -- LPRC @ 31.25 kHz(1) F21 LPRC Note 1: Change of LPRC frequency as VDD changes. FIGURE 31-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 31-1 for load conditions. DO31 DO32 TABLE 31-22: I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Characteristics(2) Symbol Min. Typical(1) Max. Units 5 15 ns Conditions DO31 TIOR Port Output Rise Time -- -- 5 10 ns VDD > 2.5V DO32 TIOF Port Output Fall Time -- 5 15 ns VDD < 2.5V -- 5 10 ns VDD > 2.5V DI35 TINP INTx Pin High or Low Time 10 -- -- ns -- DI40 TRBP CNx High or Low Time (input) 2 -- -- TSYSCLK -- Note 1: 2: VDD < 2.5V Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing. DS60001185G-page 298 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). Includes interval voltage regulator stabilization delay. 2012-2017 Microchip Technology Inc. DS60001185G-page 299 PIC32MX330/350/370/430/450/470 FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 31-23: RESETS TIMING Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions SY00 TPU Power-up Period Internal Voltage Regulator Enabled -- 400 600 s -- SY02 TSYSDLY System Delay Period: Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched. -- s + 8 SYSCLK cycles -- -- -- SY20 TMCLR MCLR Pulse Width (low) 2 -- -- s -- SY30 TBOR BOR Pulse Width (low) -- 1 -- s -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested. DS60001185G-page 300 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 31-1 for load conditions. TABLE 31-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristics(2) TxCK High Time TxCK Low Time Typical Max. Units Conditions Synchronous, with prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- -- ns Must also meet parameter TA15 Asynchronous, with prescaler 10 -- -- ns -- Synchronous, with prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- -- ns Must also meet parameter TA15 Asynchronous, with prescaler 10 -- -- ns -- [(Greater of 25 ns or 2 TPB)/N] + 30 ns -- -- ns VDD > 2.7V [(Greater of 25 ns or 2 TPB)/N] + 50 ns -- -- ns VDD < 2.7V 20 -- -- ns VDD > 2.7V (Note 3) 50 -- -- ns VDD < 2.7V (Note 3) 32 -- 100 kHz -- 1 TPB -- TxCK Synchronous, Input Period with prescaler Asynchronous, with prescaler OS60 F T1 TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: 2: 3: Min. SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) -- Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. N = Prescale Value (1, 8, 64, 256). 2012-2017 Microchip Technology Inc. DS60001185G-page 301 PIC32MX330/350/370/430/450/470 TABLE 31-25: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units Conditions TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet N = prescale parameter value TB15 (1, 2, 4, 8, Must also meet 16, 32, 64, 256) parameter TB11 TTXL TxCK Synchronous, with Low Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns -- ns TB15 TTXP TxCK Input Period [(Greater of [(25 ns or 2 TPB)/N] + 30 ns -- ns VDD > 2.7V [(Greater of [(25 ns or 2 TPB)/N] + 50 ns -- ns VDD < 2.7V -- 1 TPB TB15 TB20 Synchronous, with prescaler TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: -- These parameters are characterized, but not tested in manufacturing. FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 31-1 for load conditions. TABLE 31-26: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet parameter IC15. IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPB)/N] + 25 ns -- ns Must also meet parameter IC15. IC15 TCCP ICx Input Period [(25 ns or 2 TPB)/N] + 50 ns -- ns Note 1: These parameters are characterized, but not tested in manufacturing. DS60001185G-page 302 N = prescale value (1, 4, 16) -- 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM mode) OC10 OC11 Note: Refer to Figure 31-1 for load conditions. TABLE 31-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical(2) Max. Units Conditions OC10 TCCF OCx Output Fall Time -- -- -- ns See parameter DO32 OC11 TCCR OCx Output Rise Time -- -- -- ns See parameter DO31 Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 31-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure 31-1 for load conditions. TABLE 31-28: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param No. Symbol Characteristics(1) Min Typical(2) Max Units Conditions OC15 TFD Fault Input to PWM I/O Change -- -- 50 ns -- OC20 TFLT Fault Input Pulse Width 50 -- -- ns -- Note 1: 2: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2012-2017 Microchip Technology Inc. DS60001185G-page 303 PIC32MX330/350/370/430/450/470 FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-29: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 -- -- ns -- SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 -- -- ns -- SP20 TSCF SCKx Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP21 TSCR SCKx Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 ns VDD > 2.7V -- -- 20 ns VDD < 2.7V SP40 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 10 -- -- ns -- SP41 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 10 -- -- ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS60001185G-page 304 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 Bit 14 - - - - - -1 MSb SDOX LSb SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-30: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions -- -- ns -- SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 -- -- ns -- SP20 TSCF SCKx Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP21 TSCR SCKx Output Rise Time (Note 4) -- -- -- ns See parameter DO32 SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 15 ns VDD > 2.7V -- -- 20 ns VDD < 2.7V SP36 TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge 15 -- -- ns SP40 TDIV2SCH, Setup Time of SDIx Data Input to TDIV2SCL SCKx Edge 15 -- -- ns 20 -- -- ns VDD < 2.7V SP41 TSCH2DIL, TSCL2DIL 15 -- -- ns VDD > 2.7V 20 -- -- ns VDD < 2.7V Note 1: 2: 3: 4: Hold Time of SDIx Data Input to SCKx Edge -- VDD > 2.7V These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. 2012-2017 Microchip Technology Inc. DS60001185G-page 305 PIC32MX330/350/370/430/450/470 FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 Characteristics(1) Symbol TSCL TSCH TSCF TSCR TDOF SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time TDOR (Note 4) TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL Min. Typ.(2) Max. Units Conditions TSCK/2 TSCK/2 -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- See parameter DO32 See parameter DO31 See parameter DO32 -- -- -- ns See parameter DO31 -- -- 10 -- -- -- 15 20 -- ns ns ns VDD > 2.7V VDD < 2.7V 10 -- -- ns -- 175 -- -- ns -- -- 5 -- 25 ns -- TSSH2DOZ SSx to SDOx Output High-Impedance (Note 3) Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins. SP51 DS60001185G-page 306 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. SP52 Note 1: 2: 3: 4: Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions TSCH2SSH SSx after SCKx Edge TSCK + -- -- ns -- 20 TSCL2SSH These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins. 2012-2017 Microchip Technology Inc. DS60001185G-page 307 PIC32MX330/350/370/430/450/470 FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-32: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Characteristics(1) Symbol Min. Typical(2) Max. Units Conditions -- ns -- SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 -- SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 -- -- ns -- SP72 TSCF SCKx Input Fall Time -- 5 10 ns -- SP73 TSCR SCKx Input Rise Time -- 5 10 ns -- SP30 TDOF SDOx Data Output Fall Time (Note 4) -- -- -- ns See parameter DO32 SP31 TDOR SDOx Data Output Rise Time (Note 4) -- -- -- ns See parameter DO31 SP35 TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge -- -- 20 ns VDD > 2.7V -- -- 30 ns VDD < 2.7V SP40 TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge 10 -- -- ns -- SP41 TSCH2DIL, Hold Time of SDIx Data Input TSCL2DIL to SCKx Edge 10 -- -- ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins. DS60001185G-page 308 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-32: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions 175 -- -- ns -- SP50 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL SP51 TSSH2DOZ SSx to SDOX Output High-Impedance (Note 4) 5 -- 25 ns -- SP52 TSCH2SSH SSx after SCKx Edge TSCL2SSH TSCK + 20 -- -- ns -- SP60 TSSL2DOV SDOx Data Output Valid after SSx Edge -- -- 25 ns -- Note 1: 2: 3: 4: These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins. 2012-2017 Microchip Technology Inc. DS60001185G-page 309 PIC32MX330/350/370/430/450/470 FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 31-1 for load conditions. DS60001185G-page 310 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. IM10 IM11 IM20 Min.(1) Max. Units Conditions TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode (Note 2) TPB * (BRG + 2) -- s -- Clock High Time 100 kHz mode TPB * (BRG + 2) -- s -- 400 kHz mode TPB * (BRG + 2) -- s -- 1 MHz mode (Note 2) TPB * (BRG + 2) -- s -- -- 300 ns 20 + 0.1 CB 300 ns -- 100 ns -- 1000 ns 20 + 0.1 CB 300 ns -- 300 ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode (Note 2) 100 -- ns THI:SCL TF:SCL Characteristics SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode (Note 2) IM21 TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode (Note 2) IM25 IM26 IM30 IM31 IM33 Note 1: 2: 3: TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time 100 kHz mode 0 -- s 400 kHz mode 0 0.9 s 1 MHz mode (Note 2) 0 0.3 s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s 100 kHz mode TPB * (BRG + 2) -- s 400 kHz mode TPB * (BRG + 2) -- s 1 MHz mode (Note 2) TPB * (BRG + 2) -- s CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF -- -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- BRG is the value of the I2C Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. 2012-2017 Microchip Technology Inc. DS60001185G-page 311 PIC32MX330/350/370/430/450/470 TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. IM34 THD:STO Stop Condition Hold Time IM40 IM45 Min.(1) Max. Units Conditions 100 kHz mode TPB * (BRG + 2) -- ns -- 400 kHz mode TPB * (BRG + 2) -- ns 1 MHz mode (Note 2) TPB * (BRG + 2) -- ns 100 kHz mode -- 3500 ns -- 400 kHz mode -- 1000 ns -- 1 MHz mode (Note 2) -- 350 ns -- 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode (Note 2) 0.5 -- s The amount of time the bus must be free before a new transmission can start Characteristics TAA:SCL Output Valid from Clock TBF:SDA Bus Free Time IM50 CB Bus Capacitive Loading -- 400 pF -- IM51 TPGD Pulse Gobbler Delay 52 312 ns See Note 3 Note 1: 2: 3: BRG is the value of the I2C Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. DS60001185G-page 312 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 31-1 for load conditions. 2012-2017 Microchip Technology Inc. DS60001185G-page 313 PIC32MX330/350/370/430/450/470 TABLE 31-34: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. IS10 IS11 IS20 Symbol TLO:SCL THI:SCL TF:SCL Characteristics Clock Low Time Clock High Time SDAx and SCLx Fall Time Min. Max. Units 100 kHz mode 4.7 -- s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 1.3 -- s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode (Note 1) 0.5 -- s 100 kHz mode 4.0 -- s PBCLK must operate at a minimum of 800 kHz 400 kHz mode 0.6 -- s PBCLK must operate at a minimum of 3.2 MHz 1 MHz mode (Note 1) 0.5 -- s 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1 CB 300 ns -- 100 ns 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns -- 300 ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode (Note 1) 100 -- ns 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s 1 MHz mode (Note 1) 0 0.3 s 100 kHz mode 4700 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 250 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 250 -- ns 100 kHz mode 4000 -- ns 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 600 -- ns 1 MHz mode (Note 1) IS21 TR:SCL SDAx and SCLx Rise Time 1 MHz mode (Note 1) IS25 IS26 IS30 IS31 IS33 Note 1: TSU:DAT THD:DAT TSU:STA THD:STA TSU:STO Data Input Setup Time Data Input Hold Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Conditions -- -- CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF -- -- Only relevant for Repeated Start condition After this period, the first clock pulse is generated -- Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS60001185G-page 314 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-34: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. IS34 IS40 Symbol THD:STO TAA:SCL Characteristics Stop Condition Hold Time Min. Max. Units Conditions 100 kHz mode 4000 -- ns -- 400 kHz mode 600 -- ns 1 MHz mode (Note 1) 250 Output Valid from 100 kHz mode Clock 400 kHz mode 0 3500 ns 0 1000 ns 0 350 ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s 1 MHz mode (Note 1) 0.5 -- s -- 400 pF 1 MHz mode (Note 1) IS45 IS50 Note 1: TBF:SDA CB Bus Free Time ns Bus Capacitive Loading -- The amount of time the bus must be free before a new transmission can start -- Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 2012-2017 Microchip Technology Inc. DS60001185G-page 315 PIC32MX330/350/370/430/450/470 TABLE 31-35: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS(5) Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical Max. Units Conditions Greater of VDD - 0.3 or 2.5 -- Lesser of VDD + 0.3 or 3.6 V VSS -- VSS + 0.3 V AVDD V (Note 1) Device Supply AD01 AD02 AVDD AVSS Module VDD Supply Module VSS Supply -- -- Reference Inputs VREFH Reference Voltage High AVSS + 2.0 -- 2.5 -- 3.6 V VREFH = AVDD (Note 3) AD06 VREFL Reference Voltage Low AVSS -- VREFH - 2.0 V (Note 1) AD07 VREF Absolute Reference Voltage (VREFH - VREFL) 2.0 -- AVDD V (Note 3) AD08 IREF Current Drain -- 250 -- 400 3 A A ADC operating ADC off AD05 AD05a Analog Input AD12 VINH-VINL Full-Scale Input Span AD13 VINL AD14 VIN AD15 AD17 RIN VREFL -- VREFH V -- Absolute VINL Input Voltage AVSS - 0.3 -- AVDD/2 V -- Absolute Input Voltage AVSS - 0.3 -- AVDD + 0.3 V -- Leakage Current -- +/- 0.001 +/-0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 k Recommended Impedance of Analog Voltage Source -- -- 5K (Note 1) ADC Accuracy - Measurements with External VREF+/VREFAD20c Nr Resolution AD21c INL Integral Nonlinearity > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD22c DNL Differential Nonlinearity > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) AD23c GERR Gain Error > -1 -- <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V AD24n EOFF Offset Error > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 3.3V AD25c Monotonicity -- -- -- Note 1: 2: 3: 4: 5: -- 10 data bits bits -- -- Guaranteed These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sine wave. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for VBORMIN values. DS60001185G-page 316 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-35: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS(5) Param. No. Symbol Characteristics Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typical Max. Units Conditions ADC Accuracy - Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD22d DNL Differential Nonlinearity > -1 -- <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) AD23d GERR Gain Error > -4 -- <4 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD24d EOFF Offset Error > -2 -- <2 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) AD25d Monotonicity -- -- -- -- Guaranteed -- 10 data bits bits (Note 3) Dynamic Performance AD31b SINAD Signal to Noise and Distortion 55 58 -- dB (Notes 3,4) AD34b ENOB Effective Number of Bits 9 9.5 -- bits (Notes 3,4) Note 1: 2: 3: 4: 5: These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with a 1 kHz sine wave. Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to parameter BO10 in Table 31-10 for VBORMIN values. 2012-2017 Microchip Technology Inc. DS60001185G-page 317 PIC32MX330/350/370/430/450/470 TABLE 31-36: 10-BIT CONVERSION RATE PARAMETERS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS(2) ADC Input ADC Speed AN0-AN14 1 Msps to 400 ksps(1) TAD Min. Sampling Time Min. 65 ns 132 ns RS Max. VDD ADC Channels Configuration 500 3.0V to 3.6V VREF- VREF+ CHX ANx Up to 400 ksps 200 ns 200 ns SHA 5.0 k 2.5V to 3.6V ADC VREF- VREF+ or or AVSS AVDD CHX ANx SHA ADC ANx or VREF- AN15-AN27 400 ksps(1) 154 ns 1000 ns 500 3.0V to 3.6V VREF- VREF+ ANx Note 1: 2: CHX SHA ADC External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing. DS60001185G-page 318 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-37: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max. Units ADC Clock Period(2) 65 -- -- ns Characteristics Conditions Clock Parameters AD50 TAD See Table 31-36 Conversion Rate AD55 TCONV Conversion Time -- 12 TAD -- -- AD56 FCNV Throughput Rate (Sampling Speed)(4) -- -- 1000 ksps AVDD = 3.0V to 3.6V -- -- 400 ksps AVDD = 2.5V to 3.6V 2 TAD -- -- -- -- 1.0 TAD -- -- 0.5 TAD -- 1.5 TAD -- -- AD57 TSAMP Sample Time -- -- Timing Parameters AD60 TPCS Conversion Start from Sample Trigger(3) AD61 TPSS Sample Start from Setting Sample (SAMP) bit AD62 TCSS Conversion Completion to Sample Start (ASAM = 1)(3) -- 0.5 TAD -- -- -- AD63 TDPU Time to Stabilize Analog Stage from ADC Off to ADC On(3) -- -- 2 s -- Note 1: 2: 3: 4: Auto-Convert Trigger (SSRC<2:0> = 111) not selected These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested. Refer to Table 31-36 for detailed conditions. 2012-2017 Microchip Technology Inc. DS60001185G-page 319 PIC32MX330/350/370/430/450/470 FIGURE 31-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) in the "PIC32 Family Reference Manual". 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion. DS60001185G-page 320 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 - Software sets ADxCON. ADON to start AD operation. 5 - Convert bit 0. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS60001104) in the "PIC32 Family Reference Manual" 6 - One TAD for end of conversion. 3 - Convert bit 9. 7 - Begin conversion of next channel. 8 - Sample for time specified by SAMC<4:0>. 4 - Convert bit 8. 2012-2017 Microchip Technology Inc. DS60001185G-page 321 PIC32MX330/350/370/430/450/470 FIGURE 31-20: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 31-38: PARALLEL SLAVE PORT REQUIREMENTS AC CHARACTERISTICS Para Symbol m.No. Characteristics(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typ. Max. Units Conditions PS1 TdtV2wr Data In Valid before WR or CS H Inactive (setup time) 20 -- -- ns -- PS2 TwrH2dt WR or CS Inactive to Data-In Invalid (hold time) I 40 -- -- ns -- PS3 TrdL2dt RD and CS Active to Data-Out Valid V -- -- 60 ns -- PS4 TrdH2dtI RD Activeor CS Inactive to Data-Out Invalid 0 -- 10 ns -- PS5 Tcs CS Active Time TPB + 40 -- -- ns -- PS6 TWR WR Active Time TPB + 25 -- -- ns -- PS7 TRD RD Active Time TPB + 25 -- -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. DS60001185G-page 322 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-21: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<x:8> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-39: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max. Units Conditions PM1 TLAT PMALL/PMALH Pulse Width -- 1 TPB -- -- -- PM2 TADSU Address Out Valid to PMALL/ PMALH Invalid (address setup time) -- 2 TPB -- -- -- PM3 TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) -- 1 TPB -- -- -- PM4 TAHOLD PMRD Inactive to Address Out Invalid (address hold time) 5 -- -- ns -- PM5 TRD PMRD Pulse Width -- 1 TPB -- -- -- PM6 TDSU PMRD or PMENB Active to Data In Valid (data setup time) 15 -- -- ns -- PM7 TDHOLD PMRD or PMENB Inactive to Data In Invalid (data hold time) 1 TPB -- -- -- PMP Clock Note 1: These parameters are characterized, but not tested in manufacturing. 2012-2017 Microchip Technology Inc. DS60001185G-page 323 PIC32MX330/350/370/430/450/470 FIGURE 31-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<x:8> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-40: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max. Units Conditions PM11 TWR PMWR Pulse Width -- 1 TPB -- -- -- PM12 TDVSU Data Out Valid before PMWR or PMENB goes Inactive (data setup time) -- 2 TPB -- -- -- PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time) -- 1 TPB -- -- -- Note 1: These parameters are characterized, but not tested in manufacturing. DS60001185G-page 324 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 TABLE 31-41: OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typ. Max. Units USB313 VUSB3V3 USB Voltage 3.0 -- 3.6 V USB315 VILUSB Input Low Voltage for USB Buffer -- -- 0.8 V USB316 VIHUSB Input High Voltage for USB Buffer 2.0 -- -- V -- USB318 VDIFS Differential Input Sensitivity -- -- 0.2 V The difference between D+ and Dmust exceed this value while VCM is met USB319 VCM Differential Common Mode Range 0.8 -- 2.5 V -- USB320 ZOUT Driver Output Impedance 28.0 -- 44.0 -- USB321 VOL Voltage Output Low 0.0 -- 0.3 V 1.425 k load connected to VUSB3V3 USB322 VOH Voltage Output High 2.8 -- 3.6 V 14.25 k load connected to ground Note 1: Conditions Voltage on VUSB3V3 must be in this range for proper USB operation -- These parameters are characterized, but not tested in manufacturing. 2012-2017 Microchip Technology Inc. DS60001185G-page 325 PIC32MX330/350/370/430/450/470 TABLE 31-42: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp Min. Typ. Max. Units Conditions -- 0.55 -- A CTMUICON<9:8> = 01 -- 5.5 -- A CTMUICON<9:8> = 10 -- 55 -- A CTMUICON<9:8> = 11 CTMU CURRENT SOURCE CTMUI1 IOUT1 Base Range(1) (1) CTMUI2 IOUT2 10x Range CTMUI3 IOUT3 100x Range(1) CTMUI4 IOUT4 CTMUFV1 VF CTMUFV2 VFVR Note 1: 2: (1) -- 550 -- A CTMUICON<9:8> = 00 Temperature Diode Forward Voltage(1,2) -- 0.598 -- V TA = +25C, CTMUICON<9:8> = 01 -- 0.658 -- V TA = +25C, CTMUICON<9:8> = 10 -- 0.721 -- V TA = +25C, CTMUICON<9:8> = 11 -- -1.92 -- mV/C CTMUICON<9:8> = 01 -- -1.74 -- mV/C CTMUICON<9:8> = 10 -- -1.56 -- mV/C CTMUICON<9:8> = 11 1000x Range Temperature Diode Rate of Change(1,2) Nominal value at center point of current trim range (CTMUICON<15:10> = 000000). Parameters are characterized but not tested in manufacturing. Measurements taken with the following conditions: * VREF+ = AVDD = 3.3V * ADC module configured for conversion speed of 500 ksps * All PMD bits are cleared (PMDx = 0) * Executing a while(1) statement * Device operating from the FRC with no PLL DS60001185G-page 326 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 FIGURE 31-23: EJTAG TIMING CHARACTERISTICS TTCKcyc TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TTRST*low TTDOout TRST* TTDOzstate Defined Trf Undefined TABLE 31-43: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature 0C TA +70C for Commercial -40C TA +85C for Industrial -40C TA +105C for V-temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max. Units Conditions EJ1 TTCKCYC TCK Cycle Time 25 -- ns -- EJ2 TTCKHIGH TCK High Time 10 -- ns -- EJ3 TTCKLOW TCK Low Time 10 -- ns -- EJ4 TTSETUP TAP Signals Setup Time Before Rising TCK 5 -- ns -- EJ5 TTHOLD TAP Signals Hold Time After Rising TCK 3 -- ns -- EJ6 TTDOOUT TDO Output Delay Time from Falling TCK -- 5 ns -- EJ7 TTDOZSTATE TDO 3-State Delay Time from Falling TCK -- 5 ns -- EJ8 TTRSTLOW TRST Low Time 25 -- ns -- EJ9 TRF TAP Signals Rise/Fall Time, All Input and Output -- -- ns -- Note 1: These parameters are characterized, but not tested in manufacturing. 2012-2017 Microchip Technology Inc. DS60001185G-page 327 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 328 2012-2017 Microchip Technology Inc. DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 32-1: VOH - 4x DRIVER PINS FIGURE 32-3: 40.00 45.000 3.3V 35.00 40.000 3.3V 35.000 30.00 25.00 Current(mA) Current(mA) VOL - 4x DRIVER PINS 20.00 15.00 Absolute Maximum 30.000 25.000 20.000 15.000 10.00 10.000 5.00 5.000 0.00 0.000 0.000 0.0 FIGURE 32-2: 0.5 1.0 1.5 Voltage(V) 2.0 2.5 3.0 0.500 1.000 1.500 2.000 2.500 3.000 Voltage(V) FIGURE 32-4: VOH - 8x DRIVER PINS Absolute Maximum VOL - 8x DRIVER PINS 80.000 70.00 70.000 60.00 3.3V 3.3V 60.000 Current(mA) DS60001185G-page 329 Current(mA) 50.00 40.00 30.00 Absolute Maximum 20.00 40.000 30.000 Absolute Maximum 20.000 10.000 10.00 0.00 50.000 0.0 0.5 1.0 1.5 2.0 Voltage(V) 2.5 3.0 0.000 0.000 0.500 1.000 1.500 2.000 Voltage(V) 2.500 3.000 PIC32MX330/350/370/430/450/470 2012-2017 Microchip Technology Inc. 32.0 TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 32-7: PIC32MX350/450 DEVICES PIC32MX330/430 DEVICES 400 350 IPD (A) IPD (A) 300 250 200 150 100 50 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 600 550 500 450 400 350 300 250 200 150 100 50 0 40 30 20 10 0 Temperature(Celsius) FIGURE 32-6: TYPICAL IPD CURRENT @ VDD = 3.3V TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 32-8: TYPICAL IIDLE CURRENT @ VDD = 3.3V PIC32MX330/430 DEVICES PIC32MX350/450 DEVICES 20 450 18 400 16 IPD (A) 2012-2017 Microchip Technology Inc. IIDLECURRENT(mA) 500 350 300 250 200 150 10 20 30 40 50 60 70 80 90 100 110 Temperature(Celsius) 14 12 10 8 6 4 100 2 50 0 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature(Celsius) 0 10 20 30 40 50 MIPS 60 70 80 90 100 PIC32MX330/350/370/430/450/470 DS60001185G-page 330 FIGURE 32-5: TYPICAL IIDLE CURRENT @ VDD = 3.3V FIGURE 32-11: TYPICAL IDD CURRENT @ VDD = 3.3V PIC32MX330/430 DEVICES PIC32MX350/450 DEVICES 20 60 18 50 14 40 12 IDD (mA) IIDLE CURRENT(mA) 16 10 8 30 20 6 4 10 2 0 0 10 20 30 40 50 60 70 80 90 0 100 0 10 20 30 40 MIPS FIGURE 32-10: TYPICAL IIDLE CURRENT @ VDD = 3.3V FIGURE 32-12: PIC32MX370/470 DEVICES 60 70 80 90 100 TYPICAL IDD CURRENT @ VDD = 3.3V PIC32MX350/450 DEVICES 60 20 18 50 16 DS60001185G-page 331 14 40 12 IDD (mA) IIDLE CURRENT(mA) 50 MIPS 10 8 30 20 6 4 10 2 0 0 10 20 30 40 50 MIPS 60 70 80 90 100 0 0 10 20 30 40 50 MIPS 60 70 80 90 100 PIC32MX330/350/370/430/450/470 2012-2017 Microchip Technology Inc. FIGURE 32-9: TYPICAL IDD CURRENT @ VDD = 3.3V FIGURE 32-15: PIC32MX370/470 DEVICES TYPICAL LPRC FREQUENCY @ VDD = 3.3V 33 60 LPRC Frequency (kHz) 50 IDD (mA) 40 30 20 32 31 10 0 0 10 20 30 40 50 60 70 80 90 100 30 -40 -30 -20 -10 0 10 MIPS FIGURE 32-14: 20 30 40 50 60 70 80 90 100 Temperature (Celsius) TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-16: TYPICAL CTMU TEMPERATURE DIODE FORWARD VOLTAGE 7990 0.850 7980 0.800 7970 0.750 Forward Voltage (V) 2012-2017 Microchip Technology Inc. FRC Frequency (kHz) 8000 7960 7950 7940 7930 7920 0.700 VF = 0.721 0.650 VF = 0.658 0.600 55 A , VFV R = -1.5 6 mV 5.5 A, V VF = 0.598 FVR 0.55 0.550 0 500 0.500 /C = -1. 74 m A, V/C VFV R = -1 .92 0.450 7910 mV/ C 0.400 7900 0.350 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (Celsius) 60 70 80 90 100 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (Celsius) 60 70 80 90 100 110 PIC32MX330/350/370/430/450/470 DS60001185G-page 332 FIGURE 32-13: PIC32MX330/350/370/430/450/470 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX330F 064H-I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: Example Example PIC32MX330F 064L-I/PF e3 0510017 Example PIC32MX330F 064L-I/PT e3 0510017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e) 3 can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012-2017 Microchip Technology Inc. DS60001185G-page 333 PIC32MX330/350/370/430/450/470 33.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) with 5.40x5.40 Exposed Pad XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX330F 128H-I/MR e3 0510017 64-Lead QFN (9x9x0.9 mm) with 4.7x4.7 Exposed Pad XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: DS60001185G-page 334 Example PIC32MX330F 064H-I/RG e3 0510017 124-Lead VTLA (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Example Example PIC32MX430F 064L-I/TL e3 0510017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e) 3 can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 33.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2012-2017 Microchip Technology Inc. DS60001185G-page 335 PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185G-page 336 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 /HDG3ODVWLF7KLQ4XDG)ODWSDFN 3) [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E1 E b N NOTE 1 1 23 A NOTE 2 c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2012-2017 Microchip Technology Inc. DS60001185G-page 337 PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185G-page 338 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 c A L A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2012-2017 Microchip Technology Inc. DS60001185G-page 339 PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185G-page 340 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2017 Microchip Technology Inc. DS60001185G-page 341 PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001185G-page 342 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2017 Microchip Technology Inc. DS60001185G-page 343 PIC32MX330/350/370/430/450/470 64-Terminal Plastic Quad Flat Pack, No Lead (RG) 9x9x0.9 mm Body [QFN] Saw Singulated Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N 1 2 NOTE 1 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C DETAIL A 0.10 C C SEATING PLANE (A3) A SIDE VIEW 0.10 D2 C A B 0.10 C A B E2 e 2 NOTE 1 64X (K) 2 1 N 64X L e BOTTOM VIEW 64X b 0.10 0.05 C A B C Microchip Technology Drawing C04-260A Sheet 1 of 2 DS60001185G-page 344 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 64-Terminal Plastic Quad Flat Pack, No Lead (RG) 9x9x0.9 mm Body [QFN] Saw Singulated Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C A1 SEATING PLANE 64X 0.08 C DETAIL A Units Dimension Limits N Number of Terminals e Pitch A Overall Height Standoff A1 Standoff A3 E Overall Width E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width L Terminal Length K Terminal-to-Exposed-Pad MIN 0.80 0.00 4.60 4.60 0.15 0.30 MILLIMETERS NOM 64 0.50 BSC 0.85 0.02 0.20 REF 9.00 BSC 4.70 9.00 BSC 4.70 0.20 0.40 1.755 REF MAX 0.90 0.05 4.80 4.80 0.25 0.50 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-260A Sheet 2 of 2 2012-2017 Microchip Technology Inc. DS60001185G-page 345 PIC32MX330/350/370/430/450/470 64-Lead Very Thin Plastic Quad Flat, No Lead Package (RG) - 9x9x1.0 mm Body [QFN] 4.7x4.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 C2 Y2 (G1) Y1 Y1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X64) X1 Contact Pad Length (X64) Y1 Contact Pad to Center Pad (X64) G1 MIN MILLIMETERS NOM 0.50 BSC MAX 4.80 4.80 8.90 8.90 0.25 0.85 1.625 REF Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2260A DS60001185G-page 346 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 2012-2017 Microchip Technology Inc. DS60001185G-page 347 PIC32MX330/350/370/430/450/470 DS60001185G-page 348 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 124-Very Thin Leadless Array Package (TL) - 9x9x0.9 mm Body [VTLA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E/2 G4 X1 X2 G3 E T2 C2 G1 G5 X4 G2 SILK SCREEN W3 W2 C1 RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Pad Clearance G1 Pad Clearance G2 Pad Clearance G3 Pad Clearance G4 Contact to Center Pad Clearance (X4) G5 Optional Center Pad Width T2 Optional Center Pad Length W2 W3 Optional Center Pad Chamfer (X4) Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X124) X1 Contact Pad Length (X124) X2 MIN MILLIMETERS NOM 0.50 BSC MAX 0.20 0.20 0.20 0.20 0.30 6.60 6.60 0.10 8.50 8.50 0.30 0.30 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2193A 2012-2017 Microchip Technology Inc. DS60001185G-page 349 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 350 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 APPENDIX A: REVISION HISTORY Revision A (July 2012) This is the initial released version of the document. Revision B (April 2013) Note: The status of this data sheet was updated to Preliminary; however, any electrical specifications listed for PIC32MX370/470 devices is to be considered Advance Information and is marked accordingly. This revision includes the following updates, as shown in Table A-1. TABLE A-1: MAJOR SECTION UPDATES Section "32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog" Update Description SRAM was changed from 32 KB to 64 KB. Data Memory (KB) was changed from 32 to 64 for the following devices (see Table 1): * PIC32MX350F256H * PIC32MX350F256L * PIC32MX450F256H * PIC32MX450F256L The following devices were added: * * * * 4.0 "Memory Organization" PIC32MX370F512H PIC32MX370F512L PIC32MX470F512H PIC32MX470F512L The Memory Map for Devices with 256 KB of Program Memory was updated (see Figure 4-3). The Memory Map for Devices with 512 KB of Program Memory was added (see Figure 4-4). 7.0 "Interrupt Controller" Updated the Interrupt IRQ, Vector and Bit Locations (see Table 7-1). 20.0 "Parallel Master Port (PMP)" Added the CS2 bit and updated the ADDR bits in the Parallel Port Address register (see Register 20-3). 27.0 "Special Features" Updated the PWP bit in the Device Configuration Word 3 register (see Register 27-4). 30.0 "Electrical Characteristics" Note 2 in the DC Characteristics: Operating Current (IDD) were updated (see Table 30-5). Note 1 in the DC Characteristics: Idle Current (IIDLE) were updated (see Table 30-6). Note 1 in the DC Characteristics: Power-down Current (IPD) were updated (see Table 30-7). Updated Program Memory values for parameters D135 (TWW), D136 (TRW), and D137 (TPE and TCE) (see Table 30-12). 31.0 "DC and AC Device Characteristics Graphs" 2012-2017 Microchip Technology Inc. New IDD, IIDLE, and IPD current graphs were added for PIC32MX330/430 devices and PIC32MX350/450 devices. DS60001185G-page 351 PIC32MX330/350/370/430/450/470 Revision C (October 2013) This revision includes the following updates, as listed in Table A-2. TABLE A-2: MAJOR SECTION UPDATES Section Update Description "32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/Touch (HMI), USB, and Advanced Analog" The Operating Conditions and Core sections were updated in support of 100 MHz (-40C to +85C) devices. 2.0 "Guidelines for Getting Started with 32-bit MCUs" Updated the recommended minimum connection (see Figure 2-1). 20.0 "Parallel Master Port (PMP)" Updated the Parallel Port Control register, PMCON (see Register 20-1). Added Notes 2 and 3 regarding the conductive thermal pad to the 124-pin VTLA pin diagrams. Added 2.10 "SOSC Design Recommendation". Updated the Parallel Port Mode register, PMMODE (see Register 20-2). Updated the Parallel Port Pin Enable register, PMAEN (see Register 20-4). 30.0 "Electrical Characteristics" Removed Note 4 from the Absolute Maximum Ratings. The maximum frequency for parameter DC5 In Operating MIPS vs. Voltage was changed to 100 MHz (see Table 30-1). Parameter DC25a was added to DC Characteristics: Operating Current (IDD) (see Table 30-5). Parameter DC34c was added to DC Characteristics: Idle Current (IIDLE) (see Table 30-5). Added parameters for PIC32MX370/470 devices and removed Note 5 from DC Characteristics: Power-Down Current (IPD) (see Table 30-7). Updated the Minimum, Typical, and Maximum values and added a reference to Note 3 for parameter DI30 (ICNPU) in DC Characteristics: I/O Pin Input Specifications (see Table 30-8). The SYSCLK values for all required Flash Wait states were updated (see Table 30-13). Added parameter DO50A (CSOSC) to the Capacitive Loading Requirements on Output Pins (see Table 30-16). Updated the maximum values for parameter OS10, and the Characteristics definition of parameter OS42 (GM) in the External Clock Timing Characteristics (see Table 30-17). 31.0 "DC and AC Device Characteristics Graphs" DS60001185G-page 352 Updated the IPD, IIDLE, and IDD graphs, and added new graphs for the PIC32MX370/470 devices (see Figure 31-5 through Figure 31-13). 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Revision D (March 2015) This revision includes the following updates, as listed in Table A-3. TABLE A-3: MAJOR SECTION UPDATES Section Update Description "32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/Graphics/ Touch (HMI), USB, and Advanced Analog" 100 MHz and 120 MHz operation information was added. 2.0 "Guidelines for Getting Started with 32-bit MCUs" Added 2.8.1 "Crystal Oscillator Design Consideration". 12.0 "I/O Ports" The Block Diagram of a Typical Multiplexed Port Structure was updated (see Figure 12-1). 21.0 "Parallel Master Port (PMP)" The PMADDR: Parallel Port Address Register was updated (see Register 21-3). 31.0 "Electrical Characteristics" Specifications for 120 MHz operation were added to the following tables: Pins 59 through 63 of the 64-pin QFN and TQFP pin diagrams were updated. * Table 31-1: "Operating MIPS vs. Voltage" * Table 31-5: "DC Characteristics: Operating Current (IDD)" * Table 31-6: "DC Characteristics: Idle Current (IIDLE)" * Table 31-7: "DC Characteristics: Idle Current (IPD)" * Table 31-13: "DC Characteristics: Program Flash Memory Wait State" * Table 31-18: "External Clock Timing Requirements" The unit of measure for IIDLE Current parameters DC37a, DC37b, and DC37c were updated (see Table 31-6). Parameter D312 (TSET) was removed from the Comparator Specifications (see Table 31-14). Comparator Voltage Reference Specifications were added (see Table 31-15). Parameter OS10 (FOSC) in the External Clock Timing Requirements was updated (see Table 31-18). Parameter USB321 (VOL) in the OTG Electrical Specifications was updated (see Table 31-41). 32.0 "Packaging Information" The 64-lead QFN package marking information was updated. The 124-lead VTLA package land pattern information was added. "Product Identification System" The Speed category was removed. The Example was updated. The MR package was updated. The RG package was added. 2012-2017 Microchip Technology Inc. DS60001185G-page 353 PIC32MX330/350/370/430/450/470 Revision E (October 2015) This revision includes the following updates, as listed in Table A-4. TABLE A-4: MAJOR SECTION UPDATES Section Update Description 2.0 "Guidelines for Getting Started with 32-bit MCUs" Section 2.10 "Sosc Design Recommendations" was removed. 31.0 "Electrical Characteristics" The Power-Down Current (IPD) DC Characteristics were updated (see Table 31-7). Revision F (September 2016) This revision includes the following updates, as listed in Table A-5. TABLE A-5: MAJOR SECTION UPDATES Section Update Description "32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Audio/ Graphics/Touch (HMI), USB, and Advanced Analog" The PIC32MX450F128HB and PIC32MX470F512LB devices and Note 4 were added to the family features table (see Table 1). Note 2 in the 64-pin device pin table was updated (see Table 2). Note 2 in the 64-pin device pin table was updated and Note 4 was removed (see Table 3). Note 2 and Note 3 in the 100-pin device pin table was updated (see Table 4). Note 3 in the 124-pin device pin table was updated (see Table 6). Note 2 in the 124-pin device pin table was updated (see Table 7). RPF3 was removed from USB devices (see Table 3, Table 5, and Table 7). 1.0 "Device Overview" The Pinout I/O Descriptions for pins U5CTS, U5RTS, U5RX, and U5TX in 64-pin QFN/TQFP packages were updated (see Table 1-1). 2.0 "Guidelines for Getting Started with 32-bit MCUs" 2.10 "EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression Considerations" was added. 8.0 "Oscillator Configuration" The Clock Diagram was updated (see Figure 8-1). 12.0 "I/O Ports" Note references in the Input Pin Selection table were updated (see Table 12-1). The Center Frequency values in the TUN<5:0> bits (OSCTUN<5:0>) were updated (see Register 8-2). Note references in the Output Pin Selection table were updated (see Table 12-2). PORTF Register Maps were updated (see Table 12-11 and Table 12-3). Note 1 was added to the Peripheral Pin Select Input Register Map (see Table 12-17). 31.0 "Electrical Characteristics" The conditions for parameter DI60b (IICH) were updated (see Table 31-8). Parameter DO50a (CSOSC) was removed. The maximum value for parameter OS10 (FOSC) was updated (see Table 31-18). Parameter PM7 (TDHOLD) was updated (see Table 31-39). Note 1 was added to the DC Characteristics: Program Memory (see Table 31-12). 33.0 "Packaging Information" The Land Pattern for 64-pin QFN packages was updated. "Product Identification System" The Software Targeting category was added. DS60001185G-page 354 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 Revision G (October 2017) This revision includes the following updates, as listed in Table A-6. TABLE A-6: MAJOR SECTION UPDATES Section Update Description "32-bit Microcontrollers (up The PIC32MX450F128HB and PIC32MX470F512LB devices and Note 4 were to 512 KB Flash and 128 KB removed (see Table 1). SRAM) with Audio/ Graphics/Touch (HMI), USB, and Advanced Analog" "Product Identification System" The Software Targeting category was removed. 2012-2017 Microchip Technology Inc. DS60001185G-page 355 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 356 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 INDEX A AC Characteristics ............................................................ 295 10-Bit Conversion Rate Parameters ......................... 318 ADC Specifications ................................................... 316 Analog-to-Digital Conversion Requirements............. 319 EJTAG Timing Requirements ................................... 327 Internal FRC Accuracy.............................................. 297 Internal RC Accuracy ................................................ 298 OTG Electrical Specifications ................................... 325 Parallel Master Port Read Requirements ................. 323 Parallel Master Port Write ......................................... 324 Parallel Master Port Write Requirements.................. 324 Parallel Slave Port Requirements ............................. 322 PLL Clock Timing...................................................... 297 Analog-to-Digital Converter (ADC).................................... 233 Assembler MPASM Assembler................................................... 276 B Block Diagrams ADC Module.............................................................. 233 Comparator I/O Operating Modes............................. 243 Comparator Voltage Reference ................................ 247 Connections for On-Chip Voltage Regulator............. 272 CPU ............................................................................ 35 CTMU Configurations Time Measurement ........................................... 251 DMA ............................................................................ 93 I2C Circuit ................................................................. 198 Input Capture ............................................................ 181 Interrupt Controller ...................................................... 63 JTAG Programming, Debugging and Trace Ports .... 272 Output Compare Module........................................... 185 PMP Pinout and Connections to External Devices ... 213 Prefetch Module.......................................................... 83 Reset System.............................................................. 59 RTCC ........................................................................ 223 SPI Module ............................................................... 189 Timer1....................................................................... 167 Timer2/3/4/5 (16-Bit) ................................................. 171 Typical Multiplexed Port Structure .................... 137, 353 UART ........................................................................ 205 WDT and Power-up Timer ........................................ 177 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 272 C C Compilers MPLAB C18 .............................................................. 276 Charge Time Measurement Unit. See CTMU. Clock Diagram .................................................................... 74 Comparator Specifications.................................................... 293, 294 Comparator Module .......................................................... 243 Comparator Voltage Reference (CVref ............................. 247 Configuration Bit ............................................................... 261 Configuring Analog Port Pins ............................................ 138 CPU Architecture Overview................................................. 36 Coprocessor 0 Registers ............................................ 37 Core Exception Types................................................. 38 EJTAG Debug Support ............................................... 38 Power Management.................................................... 38 2012-2017 Microchip Technology Inc. CPU Module ................................................................. 27, 35 CTMU Registers .................................................................. 253 Customer Change Notification Service............................. 361 Customer Notification Service .......................................... 361 Customer Support............................................................. 361 D DC and AC Characteristics Graphs and Tables ................................................... 329 DC Characteristics............................................................ 280 I/O Pin Input Specifications ...................................... 287 I/O Pin Output Specifications.................................... 290 Idle Current (IIDLE) .................................................... 283 Power-Down Current (IPD)........................................ 284 Program Memory ...................................................... 292 Temperature and Voltage Specifications.................. 281 Development Support ....................................................... 275 Direct Memory Access (DMA) Controller............................ 93 E Electrical Characteristics .................................................. 279 AC............................................................................. 295 Errata .................................................................................. 14 External Clock Timer1 Timing Requirements ................................... 301 Timer2, 3, 4, 5 Timing Requirements ....................... 302 Timing Requirements ............................................... 296 F Flash Program Memory ...................................................... 53 RTSP Operation ......................................................... 53 H High Voltage Detect (HVD)................................. 61, 272, 291 I I/O Ports............................................................................ 137 Parallel I/O (PIO) ...................................................... 138 Write/Read Timing .................................................... 138 Input Change Notification ................................................. 138 Instruction Set................................................................... 273 Inter-Integrated Circuit (I2C .............................................. 197 Internal Voltage Reference Specifications........................ 294 Internet Address ............................................................... 361 Interrupt Controller.............................................................. 63 IRG, Vector and Bit Location ...................................... 64 M Memory Maps Devices with 128 KB of Program Memory .................. 41 Devices with 256 KB of Program Memory .................. 42 Devices with 512 KB of Program Memory .................. 43 Devices with 64 KB of Program Memory .................... 40 Memory Organization ......................................................... 39 Layout ......................................................................... 39 Microchip Internet Web Site.............................................. 361 MPLAB ASM30 Assembler, Linker, Librarian ................... 276 MPLAB Integrated Development Environment Software.. 275 MPLAB PM3 Device Programmer .................................... 277 MPLAB REAL ICE In-Circuit Emulator System ................ 277 MPLINK Object Linker/MPLIB Object Librarian ................ 276 DS60001185G-page 357 PIC32MX330/350/370/430/450/470 O Oscillator Configuration....................................................... 73 Output Compare................................................................ 185 P Packaging ......................................................................... 333 Details ....................................................................... 335 Marking ..................................................................... 333 Parallel Master Port (PMP) ............................................... 213 PIC32 Family USB Interface Diagram............................... 114 Pinout I/O Descriptions (table) ............................................ 18 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 272 Power-Saving Features..................................................... 257 CPU Halted Methods ................................................ 257 Operation .................................................................. 257 with CPU Running..................................................... 257 Prefetch Cache ................................................................... 83 R Real-Time Clock and Calendar (RTCC)............................ 223 Register Map ADC .......................................................................... 235 Bus Matrix ................................................................... 45 Comparator ............................................................... 244 Comparator Voltage Reference ................................ 248 CTMU........................................................................ 252 Device and Revision ID Summary ............................ 262 Device Configuration Word Summary....................... 262 DMA Channel 0-3 ....................................................... 95 DMA CRC ................................................................... 94 DMA Global................................................................. 94 Flash Controller........................................................... 54 I2C1 and I2C2 ........................................................... 199 Interrupt....................................................................... 66 Output Compare1-5 .................................................. 186 Parallel Master Port .................................................. 214 Peripheral Pin Select Input ....................................... 159 Peripheral Pin Select Output..................................... 161 PORTA...................................................................... 145 PORTB...................................................................... 146 PORTC ............................................................. 147, 148 PORTD ............................................................. 149, 150 PORTE.............................................................. 151, 152 PORTF .............................................. 153, 154, 155, 156 PORTG ............................................................. 157, 158 Prefetch....................................................................... 84 RTCC ........................................................................ 224 SPI1 and SPI2 .......................................................... 190 System Control ..................................................... 60, 75 Timer1-5............................................................ 168, 173 UART1-5 ................................................................... 206 USB........................................................................... 115 Registers [pin name]R (Peripheral Pin Select Input)................. 165 AD1CHS (ADC Input Select)..................................... 241 AD1CON1 (A/D Control 1) ........................................ 232 AD1CON1 (ADC Control 1)............................... 232, 237 AD1CON2 (ADC Control 2)....................................... 239 AD1CON3 (ADC Control 3)....................................... 240 AD1CSSL (ADC Input Scan Select).......................... 242 ALRMDATE (Alarm Date Value) ............................... 232 ALRMDATECLR (ALRMDATE Clear)....................... 232 ALRMDATESET (ALRMDATE Set) .......................... 232 ALRMTIME (Alarm Time Value)................................ 231 DS60001185G-page 358 ALRMTIMECLR (ALRMTIME Clear) ........................ 232 ALRMTIMEINV (ALRMTIME Invert) ......................... 232 ALRMTIMESET (ALRMTIME Set)............................ 232 BMXBOOTSZ (Boot Flash (IFM) Size ........................ 51 BMXCON (Bus Matrix Configuration) ......................... 46 BMXDKPBA (Data RAM Kernel Program Base Address) .................................................... 47 BMXDRMSZ (Data RAM Size Register)..................... 50 BMXDUDBA (Data RAM User Data Base Address)... 48 BMXDUPBA (Data RAM User Program Base Address) .................................................... 49 BMXPFMSZ (Program Flash (PFM) Size).................. 51 BMXPUPBA (Program Flash (PFM) User Program Base Address) .................................................... 50 CHEACC (Cache Access) .......................................... 86 CHECON (Cache Control).......................................... 85 CHEHIT (Cache Hit Statistics).................................... 91 CHELRU (Cache LRU) ............................................... 90 CHEMIS (Cache Miss Statistics) ................................ 91 CHEMSK (Cache TAG Mask)..................................... 88 CHETAG (Cache TAG)............................................... 87 CHEW0 (Cache Word 0) ............................................ 88 CHEW1 (Cache Word 1) ............................................ 89 CHEW2 (Cache Word 2) ............................................ 89 CHEW3 (Cache Word 3) ............................................ 90 CM1CON (Comparator 1 Control) ............................ 245 CMSTAT (Comparator Control Register).................. 246 CNCONx (Change Notice Control for PORTx) ......... 166 CTMUCON (CTMU Control) ..................................... 253 CVRCON (Comparator Voltage Reference Control) 249 DCHxCON (DMA Channel x Control) ....................... 103 DCHxCPTR (DMA Channel x Cell Pointer) .............. 110 DCHxCSIZ (DMA Channel x Cell-Size) .................... 110 DCHxDAT (DMA Channel x Pattern Data) ............... 111 DCHxDPTR (Channel x Destination Pointer) ........... 109 DCHxDSA (DMA Channel x Destination Start Address)................................................... 107 DCHxDSIZ (DMA Channel x Destination Size) ........ 108 DCHxECON (DMA Channel x Event Control) .......... 104 DCHxINT (DMA Channel x Interrupt Control)........... 105 DCHxSPTR (DMA Channel x Source Pointer) ......... 109 DCHxSSA (DMA Channel x Source Start Address) . 107 DCHxSSIZ (DMA Channel x Source Size) ............... 108 DCRCCON (DMA CRC Control)............................... 100 DCRCDATA (DMA CRC Data) ................................. 102 DCRCXOR (DMA CRCXOR Enable) ....................... 102 DEVCFG0 (Device Configuration Word 0................. 263 DEVCFG1 (Device Configuration Word 1................. 265 DEVCFG2 (Device Configuration Word 2................. 267 DEVCFG3 (Device Configuration Word 3................. 269 DEVID (Device and Revision ID) .............................. 271 DMAADDR (DMA Address) ........................................ 99 DMAADDR (DMR Address)........................................ 99 DMACON (DMA Controller Control) ........................... 98 DMASTAT (DMA Status) ............................................ 99 I2CxCON (I2C Control)............................................. 200 I2CxSTAT (I2C Status) ............................................. 202 ICxCON (Input Capture x Control)............................ 182 IFSx (Interrupt Flag Status) ........................................ 70 INTCON (Interrupt Control)......................................... 68 INTSTAT (Interrupt Status)......................................... 69 IPCx (Interrupt Priority Control) .................................. 71 IPTMR Interrupt Proximity Timer) ............................... 69 NVMADDR (Flash Address) ....................................... 56 NVMCON (Programming Control) .............................. 55 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 NVMDATA (Flash Program Data)............................... 57 NVMKEY (Programming Unlock)................................ 56 NVMSRCADDR (Source Data Address)..................... 57 OCxCON (Output Compare x Control) ..................... 187 OSCCON (Oscillator Control) ..................................... 76 PFABT (Prefetch Cache Abort Statistics) ................... 92 PMADDR (Parallel Port Address) ............................. 219 PMAEN (Parallel Port Pin Enable)............................ 220 PMCON (Parallel Port Control) ................................. 215 PMMODE (Parallel Port Mode)................................. 217 PMSTAT (Parallel Port Status (Slave Modes Only).. 221 REFOCON (Reference Oscillator Control) ................. 80 REFOTRIM (Reference Oscillator Trim) ..................... 82 RPnR (Peripheral Pin Select Output)........................ 165 RSWRST (Software Reset) ........................................ 62 RTCCON (RTC Control) ........................................... 225 RTCDATE (RTC Date Value) ................................... 230 RTCTIME (RTC Time Value) .................................... 229 SPIxCON (SPI Control)............................................. 191 SPIxCON2 (SPI Control 2)........................................ 194 SPIxSTAT (SPI Status)............................................. 195 T1CON (Type A Timer Control) ................................ 169 TxCON (Type B Timer Control) ................................ 174 U1ADDR (USB Address) .......................................... 131 U1BDTP1 (USB BDT Page 1) .................................. 133 U1BDTP2 (USB BDT Page 2) .................................. 134 U1BDTP3 (USB BDT Page 3) .................................. 134 U1CNFG1 (USB Configuration 1) ............................. 135 U1CON (USB Control) .............................................. 129 U1EIE (USB Error Interrupt Enable) ......................... 127 U1EIR (USB Error Interrupt Status) .......................... 125 U1EP0-U1EP15 (USB Endpoint Control) ................. 136 U1FRMH (USB Frame Number High)....................... 132 U1FRML (USB Frame Number Low) ........................ 131 U1IE (USB Interrupt Enable)..................................... 124 U1IR (USB Interrupt)................................................. 123 U1OTGCON (USB OTG Control) ............................. 121 U1OTGIE (USB OTG Interrupt Enable) .................... 119 U1OTGIR (USB OTG Interrupt Status)..................... 118 U1OTGSTAT (USB OTG Status).............................. 120 U1PWRC (USB Power Control)................................ 122 U1SOF (USB SOF Threshold).................................. 133 U1STAT (USB Status) .............................................. 128 U1TOK (USB Token) ................................................ 132 WDTCON (Watchdog Timer Control) ....................... 179 Resets ................................................................................. 59 Revision History ................................................................ 351 RTCALRM (RTC ALARM Control) .................................... 227 T S W Serial Peripheral Interface (SPI) ....................................... 189 Software Simulator (MPLAB SIM)..................................... 277 Special Features ............................................................... 261 WWW Address ................................................................. 361 WWW, On-Line Support ..................................................... 14 2012-2017 Microchip Technology Inc. Timer1 Module.................................................................. 167 Timer2/3, Timer4/5 Modules............................................. 171 Timing Diagrams 10-Bit Analog-to-Digital Conversion (ASAM = 0, SSRC<2:0> = 000)........................ 320 10-Bit Analog-to-Digital Conversion (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 321 EJTAG ...................................................................... 327 External Clock .......................................................... 295 I/O Characteristics .................................................... 298 I2Cx Bus Data (Master Mode) .................................. 310 I2Cx Bus Data (Slave Mode) .................................... 313 I2Cx Bus Start/Stop Bits (Master Mode)................... 310 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 313 Input Capture (CAPx) ............................................... 302 OCx/PWM................................................................. 303 Output Compare (OCx) ............................................ 303 Parallel Master Port Read ........................................ 323 Parallel Master Port Write......................................... 324 Parallel Slave Port .................................................... 322 SPIx Master Mode (CKE = 0) ................................... 304 SPIx Master Mode (CKE = 1) ................................... 305 SPIx Slave Mode (CKE = 0) ..................................... 306 SPIx Slave Mode (CKE = 1) ..................................... 308 Timer1, 2, 3, 4, 5 External Clock .............................. 301 UART Reception....................................................... 212 UART Transmission (8-bit or 9-bit Data) .................. 212 Timing Requirements CLKO and I/O ........................................................... 298 Timing Specifications I2Cx Bus Data Requirements (Master Mode)........... 311 I2Cx Bus Data Requirements (Slave Mode)............. 314 Input Capture Requirements .................................... 302 Output Compare Requirements................................ 303 Simple OCx/PWM Mode Requirements ................... 303 SPIx Master Mode (CKE = 0) Requirements............ 304 SPIx Master Mode (CKE = 1) Requirements............ 305 SPIx Slave Mode (CKE = 1) Requirements.............. 308 SPIx Slave Mode Requirements (CKE = 0).............. 306 U UART ................................................................................ 205 USB On-The-Go (OTG) .................................................... 113 V VCAP pin............................................................................ 272 Voltage Regulator (On-Chip) ............................................ 272 DS60001185G-page 359 PIC32MX330/350/370/430/450/470 NOTES: DS60001185G-page 360 2012-2017 Microchip Technology Inc. PIC32MX330/350/370/430/450/470 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2012-2017 Microchip Technology Inc. DS60001185G-page 361 PIC32MX330/350/370/430/450/470 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 3XX F 064 H T - XXX I / PT - XXX Example: PIC32MX330F064H-I/PT: General purpose PIC32, 32-bit RISC MCU, 64 KB program memory, 64-pin, Industrial temperature, TQFP package. Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Flash Memory Family Architecture MX = 32-bit RISC MCU core Product Groups 3XX = General purpose microcontroller family 4XX = General purpose with USB microcontroller family Flash Memory Family F = Flash program memory Program Memory Size 064 128 256 512 = 6 4KB = 128KB = 256KB = 512KB Pin Count H L = 64-pin = 100-pin Speed blank = up to 100 MHz 120 = up to 120 MHz Temperature Range blank = 0C to +70C (Commercial) I = -40C to +85C (Industrial) V = -40C to +105C (V-Temp) Package Pattern MR RG PT PT PF TL = 64-Lead (9x9x0.9 mm) QFN with 5.40x5.40 Exposed Pad (Plastic Quad Flat) = 64-Lead (9x9x0.9 mm) QFN with 4.7x4.7 Exposed Pad (Plastic Quad Flat) = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) = 124-Lead (9x9x0.9 mm) VTLA (Very Thin Leadless Array) Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample 2012-2017 Microchip Technology Inc. DS60001185G-page 362 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2012-2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-2247-1 2012-2017 Microchip Technology Inc. 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