10-Bit, 65/80/105 MSPS
Dual A/D Converter
AD9216
Rev. A
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Integrated dual 10-bit ADC
Single 3 V supply operation
SNR = 57.6 dBc (to Nyquist, AD9216-105)
SFDR = 74 dBc (to Nyquist, AD9216-105)
Low power: 150 mW/ch at 105 MSPS
Differential input with 300 MHz 3 dB bandwidth
Exceptional crosstalk immunity < -80 dB
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
3G, radio point-to-point, LMDS, MMDS
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital
converter (ADC). It features dual high performance sample-
and-hold amplifiers (SHAs) and an integrated voltage reference.
The AD9216 uses a multistage differential pipelined archi-
tecture with output error correction logic to provide 10-bit
accuracy and guarantee no missing codes over the full
operating temperature range at up to 105 MSPS data rates.
The wide bandwidth, differential SHA allows for a variety of
user selectable input ranges and offsets, including single-ended
applications. The AD9216 is suitable for various applications,
including multiplexed systems that switch full-scale voltage
levels in successive channels and for sampling inputs at
frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9216 and can compensate for wide variations in the clock
duty cycle, allowing the converters to maintain excellent
performance. The digital output data is presented in either
straight binary or twos complement format.
FUNCTIONAL BLOCK DIAGRAM
VIN+_A
VIN–_A
REFT_A
REFB_A
VREF
SENSE
AGND
REFT_B
REFB_B
VIN+_B
VIN–_B
D9_A–D0_A
OEB_A
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
D9_B–D0_B
OEB_B
AVDD AGND
DRVDD DRGND
10
AD9216
10
0.5V
OUTPUT
MUX/
BUFFERS
10
10 OUTPUT
MUX/
BUFFERS
CLOCK
DUTY CYCLE
STABILIZER
MODE
CONTROL
ADC
ADC
SHA
SHA
04775-001
Figure 1.
Fabricated on an advanced CMOS process, the AD9216 is avail-
able in a space saving, Pb-free, 64-lead LFCSP (9 mm × 9 mm) and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/
65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/
65 MSPS ADC.
2. 105 MSPS capability allows for demanding, high frequency
applications.
3. Low power consumption: AD9216–105: 105 MSPS = 300 mW.
4. The patented SHA input maintains excellent performance for
input frequencies up to 200 MHz and can be configured for
single-ended or differential operation.
5. Typical channel crosstalk of < −80 dB at fIN up to 70 MHz.
6. The clock duty cycle stabilizer maintains performance over a
wide range of clock duty cycles.
AD9216
Rev. A | Page 2 of 40
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
AC Specifications.............................................................................. 4
Logic Specifications.......................................................................... 5
Switching Specifications .................................................................. 6
Timing Diagram ............................................................................... 7
Absolute Maximum Ratings............................................................ 8
Explanation of Test Levels........................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Ter m in olo g y .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 20
Analog Input ............................................................................... 20
Clock Input and Considerations .............................................. 22
Power Dissipation and Standby Mode..................................... 22
Digital Outputs ........................................................................... 22
Output Coding............................................................................ 23
Timing ......................................................................................... 23
Data Format ................................................................................ 23
Voltage Reference....................................................................... 24
Dual ADC LFCSP PCB.................................................................. 26
Power Connector........................................................................ 26
Analog Inputs ............................................................................. 26
Optional Operational Amplifier .............................................. 26
Clock ............................................................................................ 26
Voltage Reference ....................................................................... 26
Data Outputs............................................................................... 26
LFCSP Evaluation Board Bill of Materials (BOM) ................ 27
LFCSP PCB Schematics............................................................. 28
LFCSP PCB Layers..................................................................... 31
Thermal Considerations............................................................ 37
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Added 65 and 80 Speed Grades ........................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 4............................................................................ 6
Changes to Table 7............................................................................ 9
Added Figure 8................................................................................ 13
Added Figure 11, Figure 13, and Figure 14................................. 14
Changes to Figure 36...................................................................... 18
Changes to Table 12........................................................................ 27
Changes to Figure 51...................................................................... 28
Changes to Figure 52...................................................................... 29
Changes to Figure 53...................................................................... 30
Changes to Figure 54...................................................................... 31
Changes to Figure 55...................................................................... 32
Changes to Figure 56...................................................................... 33
Changes to Figure 57...................................................................... 34
Changes to Figure 58...................................................................... 35
Changes to Figure 59...................................................................... 36
Changes to Ordering Guide .......................................................... 38
10/04—Revision 0: Initial Version
AD9216
Rev. A | Page 3 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Temp Test AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105
Parameter Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 10 10 10 Bits
ACCURACY
No Missing Codes Full VI Guaranteed Guaranteed Guaranteed
Offset Error Full VI -1.9 ±0.3 +1.9 -1.9 ±0.3 +1.9 −2.2 ±0.3 +2.2 % FSR
Gain Error125°C VI -1.6 ±0.4 +1.6 -1.6 ±0.4 +1.6 −1.6 ±0.4 +1.6 % FSR
Differential Nonlinearity (DNL)2Full IV -1.0 ±0.3 +1.0 -1.0 ±0.4 +1.0 −1.0 ±0.5 +1.0 LSB
25°C I -0.9 ±0.3 +0.9 -0.9 ±0.4 +0.9 −1.0 ±0.5 +1.0 LSB
Integral Nonlinearity (INL)2 Full IV -1.4 ±0.5 +1.4 -1.6 ±0.5 +1.6 −2.5 ±1.0 +2.5 LSB
25°C I -1.0 ±0.5 +1.0 -1.1 ±0.5 +1.1 −1.5 ±1.0 +1.5 LSB
TEMPERATURE DRIFT
Offset Error Full V ±10 ±10 ±10 µV/°C
Gain Error1 Full V ±75 ±75 ±75 ppm/°C
Reference Voltage Full V ±15 ±15 ±15 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error Full VI ±2 ±35 ±2 ±35 ±2 ±35 mV
Load Regulation @ 1.0 mA 25°C V 1.0 1.0 1.0 mV
INPUT REFERRED NOISE
Input Span = 2.0 V 25°C V 0.5 0.5 0.5 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p
Input Capacitance325°C V 2 2 2 pF
REFERENCE INPUT RESISTANCE 25°C V 7 7 7 kΩ
POWER SUPPLIES
Supply Voltages
AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 2.7 3.0 3.3 V
DRVDD Full IV 2.25 2.5 3.3 2.25 2.5 3.3 2.25 2.5 3.3 V
Supply Current
IAVDD4Full VI 72 80 78 85 100 110 mA
IDRVDD4 Full VI 15 18 24 mA
PSRR 25°C V ±0.1 ±0.1 ±0.1 % FSR
POWER CONSUMPTION
PAVDD4 25°C I 216 240 234 255 300 330 mW
PDRVDD4 25°C V 38 45 60 mW
Standby Power525°C V 3.0 3.0 3.0 mW
MATCHING CHARACTERISTICS
Offset Matching Error625°C I -2.6 ±0.2 +2.6 -2.6 ±0.2 +2.6 −3.5 ±0.3 +3.5 % FSR
Gain Matching Error (Shared Reference
Mode)
25°C I -0.4 ±0.1 +0.4 -0.4 ±0.1 +0.4 −0.6 ±0.1 +0.6 % FSR
Gain Matching Error (Nonshared
Reference Mode)
25°C I -1.6 ±0.1 +1.6 -1.6 ±0.1 +1.6 −1.6 ±0.3 +1.6 % FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured with low frequency ramp at maximum clock rate.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 37
4 Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
6 Both shared reference mode and nonshared reference mode.
AD9216
Rev. A | Page 4 of 40
AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 2.
Parameter Temp Test
Level
Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz 25°C V 58.6 58.5 58.0 dB
fINPUT = Nyquist1Full IV 56.6 58.4 55.9 58.1 54.8 57.6 dB
25°C I 57.2 58.4 56.4 58.5 56.4 57.6 dB
fINPUT = 69 MHz 25°C V 58.0 58.0 57.4 dB
fINPUT = 100 MHz 25°C V 57.5 57.5 57.3 dB
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
fINPUT = 2.4 MHz 25°C V 58.5 58.2 57.8 dB
fINPUT = Nyquist1 Full IV 56.4 58.3 55.4 58.0 53.4 57.4 dB
25°C I 57.0 58.3 56.2 58.0 56.1 57.4 dB
fINPUT = 69 MHz 25°C V 57.5 57.5 56.8 dB
fINPUT = 100 MHz 25°C V 57.0 57.0 56.7 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz 25°C V 9.4 9.4 9.3 Bits
fINPUT = Nyquist1 Full IV 9.1 9.4 8.9 9.3 8.6 9.3 Bits
25°C I 9.2 9.4 9.0 9.3 9.1 9.3 Bits
fINPUT = 69 MHz 25°C V 9.3 9.3 9.2 Bits
fINPUT = 100 MHz 25°C V 9.3 9.3 9.2 Bits
WORST HARMONIC (SECOND OR
THIRD)
fINPUT = 2.4 MHz Full IV −82.0 −81.0 −76.0 dBc
fINPUT = Nyquist1 Full IV −79.5 -65.1 −77.0 -64.1 −74.0 −60.0 dBc
25°C I −79.5 -67.8 −77.0 -67.2 −74.0 −66.5 dBc
fINPUT = 69 MHz 25°C V −79.0 −76.5 −74.0 dBc
fINPUT = 100 MHz 25°C V −78.5 −76.0 −74.0 dBc
WORST OTHER (EXCLUDING
SECOND OR THIRD)
fINPUT = 2.4 MHz Full IV −82.5 −81.5 −76.5 dBc
fINPUT = Nyquist1 Full IV −80.5 -65.8 −78.0 -64.5 −75.0 −62.0 dBc
25°C I −80.5 -68.7 −78.0 -67.8 −75.0 −67.5 dBc
fINPUT = 69 MHz 25°C V −80.0 −77.5 −75.0 dBc
fINPUT = 100 MHz 25°C V −79.5 −77.0 −75.0 dBc
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
fINPUT = 2.4 MHz Full IV 82.0 81.0 76.0 dBc
fINPUT = Nyquist1 Full IV 65.1 79.5 64.1 77.0 60.0 74.0 dBc
25°C I 67.8 79.5 67.2 77.0 66.5 74.0 dBc
fINPUT = 69 MHz 25°C V 79.0 76.5 74.0 dBc
fINPUT = 100 MHz 25°C V 78.5 76.0 74.0 dBc
TWO-TONE SFDR (AIN = −7 dBFS)
fIN1 = 69.1 MHz, fIN2 = 70.1 MHz 25°C V 71.0 70.0 70.0 dBc
fIN1 = 100.1 MHz, fIN2 = 101.1 MHz 25°C V 70.0 69.0 69.0 dBc
ANALOG BANDWIDTH 25°C V 300 300 300 MHz
CROSSTALK 25°C V −80.0 −80.0 −80.0 dB
1 Nyquist = approximately 32 MHz, 40MHz, 50MHz for the −65, −80, and −105 grades respectively
AD9216
Rev. A | Page 5 of 40
LOGIC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105
Parameter Temp Test
Level
Min Typ Max Min Typ Max Min Typ Max Unit
LOGIC INPUTS
High Level Input
Voltage
Full IV 2.0 2.0 2.0 V
Low Level Input
Voltage
Full IV 0.8 0.8 0.8 V
High Level Input
Current
Full IV −10 +10 −10 +10 −10 +10 µA
Low Level Input
Current
Full IV −10 +10 −10 +10 −10 +10 µA
Input Capacitance Full IV 2 2 2 pF
LOGIC OUTPUTS1
DRVDD = 2.5 V
High Level Output
Voltage
Full IV 2.45 2.45 2.45 V
Low Level Output
Voltage
Full IV 0.05 0.05 0.05 V
1 Output voltage levels measured with 5 pF load on each output.
AD9216
Rev. A | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
AD9216BCPZ-65 AD9216BCPZ-80 AD9216BCPZ-105
Parameter Temp Test Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 65 80 105 MSPS
Minimum Conversion Rate Full IV 10 10 10 MSPS
CLK Period Full VI 15.4 12.5 9.5 nS
CLK Pulse Width High Full VI 4.6 4.4 3.8 nS
CLK Pulse Width Low Full VI 4.6 4.4 3.8 nS
OUTPUT PARAMETERS1
Output Propagation Delay2 (tPD) 25°C I 4.5 6.4 4.5 6.4 4.5 6.4 nS
Valid Time3 (tV) 25°C I 2.0 2.0 2.0
Output Rise Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS
Output Fall Time (10% to 90%) 25°C V 1.0 1.0 1.0 nS
Output Enable Time4Full IV 1 1 1 Cycle
Output Disable Time4 Full IV 1 1 1 Cycle
Pipeline Delay (Latency) Full IV 6 6 6 Cycle
APERTURE
Aperture Delay (tA) 25°C V 1.5 1.5 1.5 nS
Aperture Uncertainty (tJ) 25°C V 0.5 0.5 0.5 pS
rms
Wake-Up Time525°C V 7 7 7 ms
OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycle
1 CLOAD equals 5 pF maximum for all output switching parameters.
2 Output delay is measured from clock 50% transition to data 50% transition.
3 Valid time is approximately equal to the minimum output propagation delay.
4 Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective
channel outputs going into high impedance.
5 Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.
AD9216
Rev. A | Page 7 of 40
TIMING DIAGRAM
t
A
N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1
N–1
NN+1
N+2
N+3
N+4
N+5 N+6
N+7
N+8
t
PD
ANALOG
INPUT
CLK
DATA
OUT
04775-002
Figure 2.
AD9216
Rev. A | Page 8 of 40
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter To Rating
ELECTRICAL
AVDD AGND
−0.3 V to
+3.9 V
DRVDD DRGND
−0.3 V to
+3.9 V
AGND DRGND
−0.3 V to
+0.3 V
AVDD DRVDD
−0.3 V to
+3.9 V
Digital Outputs DRGND −0.3 V to
DRVDD +
0.3 V
CLK_A, CLK_B, DCS, DFS, MUX_SELECT,
OEB_A, OEB_B, SHARED_REF,
PDWN_A, PDWN_B
AGND −0.3 V to
AVDD +
0.3 V
VIN−_A, VIN+_A, VIN−_B, VIN+_B AGND −0.3 V to
AVDD +
0.3 V
REFT_A, REFB_A,VREF, REFT_B, REFB_B,
SENSE
AGND −0.3 V to
AVDD +
0.3 V
ENVIRONMENTAL1
Operating Temperature −40°C to
+85°C
Junction Temperature 150°C
Lead Temperature (10 sec) 300°C
Storage Temperature −65°C to
+150°C
1 Typical thermal impedances (64-lead LFCSP); θJA = 26.4°C/W. These
measurements were taken on a 4-layer board (with thermal via array) in still
air, in accordance with EIA/JESD51-7.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 6.
Test Level Description
I 100% production tested.
II 100% production tested at 25°C and sample
tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and
characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by
design and characterization testing for industrial
temperature range; 100% production tested at
temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD9216
Rev. A | Page 9 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
CLK_B
DCS
DFS
PDWN_B
OEB_B
DNC
DNC
DNC
DNC
D0_B (LSB)
DRGND
DRVDD
D1_B
D2_B
D3_B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
CLK_A
SHARED_REF
MUX_SELECT
PDWN_A
OEB_A
DNC
D9_A (MSB)
D8_A
D7_A
D6_A
DRGND
DRVDD
D5_A
D4_A
D3_A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AGND
VIN+_A
VIN–_A
AGND
AVDD
REFT_A
REFB_
A
VREF
SENSE
REFB_B
REFT_B
AVDD
AGND
VIN–_B
VIN+_B
AGND
D2_A
D1_A
D0_A (LSB)
DNC
DNC
DNC
DNC
DRVDD
DRGND
DNC
D9_B (MSB)
D8_B
D7_B
D6_B
D5_B
D4_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9216
TOP VIEW
(Not to Scale)
04775-003
DNC =
DO NOT CONNECT
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 13, 16 AGND1Analog Ground.
2 VIN+_A Analog Input Pin (+) for Channel A.
3 VIN−_A Analog Input Pin (−) for Channel A.
5, 12, 17, 64 AVDD Analog Power Supply.
6 REFT_A Differential Reference (+) for Channel A.
7 REFB_A Differential Reference (−) for Channel A.
8 VREF Voltage Reference Input/Output.
9 SENSE Reference Mode Selection.
10 REFB_B Differential Reference (−) for Channel B.
11 REFT_B Differential Reference (+) for Channel B.
14 VIN−_B Analog Input Pin (−) for Channel B.
15 VIN+_B Analog Input Pin (+) for Channel B.
18 CLK_B Clock Input Pin for Channel B.
19 DCS Duty Cycle Stabilizer (DCS) Mode Pin (Active High).
20 DFS Data Output Format Select Pin. Low for offset binary; high for twos complement.
21 PDWN_B Power-Down Function Selection for Channel B.
Logic 0 enables Channel B.
Logic 1 powers down Channel B. (Outputs static, not High-Z.)
22 OEB_B Output Enable for Channel B.
Logic 0 enables Data Bus B.
Logic 1 sets outputs to High-Z.
23 to 26, 39,
42 to 45, 58
DNC Do Not Connect Pins. Should be left floating.
27, 30 to 38 D0_B (LSB) to
D9_B (MSB)
Channel B Data Output Bits.
28, 40, 53 DRGND Digital Output Ground.
29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.
Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.
AD9216
Rev. A | Page 10 of 40
Pin No. Mnemonic Description
46 to 51,
54 to 57
D0_A (LSB) to
D9_A (MSB)
Channel A Data Output Bits.
59 OEB_A Output Enable for Channel A.
Logic 0 enables Data Bus A.
Logic 1 sets outputs to High-Z.
60 PDWN_A Power-Down Function Selection for Channel A.
Logic 0 enables Channel A.
Logic 1 powers down Channel A. (Outputs static, not High-Z.)
61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable.)
62 SHARED_REF Shared Reference Control Bit. Low for independent reference mode; high for shared reference mode.
63 CLK_A Clock Input Pin for Channel A.
1 It is recommended that all ground pins (AGND and DRGND) be tied to a common ground plane.
AD9216
Rev. A | Page 11 of 40
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Pulse-width high is the minimum amount of time that the
clock pulse should be left in a Logic 1 state to achieve rated
performance; pulse-width low is the minimum time clock pulse
should be left in a low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Crosstalk
Coupling onto one channel being driven by a low level (−40
dBFS) signal when the adjacent interfering channel is driven by
a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input
Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and by taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
The ENOB is calculated from the measured SINAD based on
the equation (assuming full-scale input)
6.02
dB1.76−
=MEASURED
SINAD
ENOB
Full-Scale Input Power
Expressed in dBm and computed using the following equation.
⎟
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎜
⎝
⎛
=0.001
V
log10
2
INPUT
SCALEFULL
SCALEFULL
Z
rms
Power
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaran-
teed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a 50% crossing of the CLK rising edge and
the time when all output data bits are within valid logic levels.
AD9216
Rev. A | Page 12 of 40
Noise (for Any Range within the ADC)
This value includes both thermal and quantization noise.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−−
××= 10
10.0010 dBFSdBcdBm SignalSNRFS
ZVnoise
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale.
Power Supply Rejection Ratio
The specification shows the maximum change in full scale
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below
full scale) to the rms value of the sum of all other spectral
components, excluding the first seven harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of
the peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (that is, degrades as signal level is lowered)
or dBFS (that is, always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product, in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious
component may or may not be an IMD product. It also may be
reported in dBc (that is, degrades as signal level is lowered) or
in dBFS (that is, always relates back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic), reported in dBc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
AD9216
Rev. A | Page 13 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, T = 25°C, AIN differential drive, internal reference, DCS on, unless otherwise noted.
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
20 30010 4050
FREQUENCY (MHz)
04775-018
SNR = 57.8dB
SINAD = 57.8dB
H2 = –92.7dBc
H3 = –80.3dBc
SFDR = 78.2dBc
Figure 4. FFT: fS = 105 MSPS, AIN = 10.3 MHz at −0.5 dBFS (−105 Grade)
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
20 30010 4050
FREQUENCY (MHz)
04775-019
SNR = 56.9dB
SINAD = 56.8dB
H2 = –78.5dBc
H3 = –80dBc
SFDR = 78.3dBc
Figure 5. FFT: fS = 105 MSPS, AIN = 70 MHz at −0.5 dBFS (−105 Grade)
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
20 30010 4050
FREQUENCY (MHz)
04775-020
SNR = 56.8dB
SINAD = 56.7dB
H2 = –74dBc
H3 = –84.3dBc
SFDR = 74dBc
Figure 6. FFT: fS = 105 MSPS, AIN = 100 MHz at −0.5 dBFS (−105 Grade)
04775-021
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
27 28 29
(76) 30 31 32 33 34 35
(70) 36
FREQUENCY (MHz)
AMPLITUDE (dBFS)
70MHz ON CHANNEL A ACTIVE
76MHz CROSSTALK FROM
CHANNEL B
Figure 7. FFT: fS = 105 MSPS, AIN =70 MHz, 76 MHz (−105 Grade)
(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)
0
–120
04775-048
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
SNR = 57.6dB
SINAD = 57.4dB
H2 = –84.1dBc
H3 = –77.2dBc
SFDR = 74dBc
040
FREQUENCY (MHz)
5 101520253035
70MHz ON
CHANNEL A
ACTIVE
76MHz
CROSSTALK
FROM
CHANNEL B
Figure 8. FFT: fS = 80 MSPS, AIN =70 MHz, 76 MHz (−80 Grade)
(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)
0
–120
04775-049
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
SNR = 57.5dB
SINAD = 57.3dB
H2 = –85.9dBc
H3 = –74.4dBc
SFDR = 72.4dBc
70MHz ON
CHANNEL A
ACTIVE
76MHz
CROSSTALK
FROM
CHANNEL B
0FREQUENCY (MHz)
5 1015202530
Figure 9. FFT: fS = 65 MSPS, AIN =70 MHz, 76 MHz (−65 Grade)
(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)
AD9216
Rev. A | Page 14 of 40
04775-022
50
60
70
80
90
100
0 20 40 60 80 100 120
CLOCK FREQUENCY (MHz)
dB
SNR
SINAD
H2
SFDR
H3
Figure 10. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency
AIN = 70 MHz at −0.5 dBFS (−105 Grade)
50
60
70
80
90
100
010
04775-050
CLOCK FREQUENCY (MHz)
dB
H2 H3
SNR
20 30 40 50 60 70 80 90 100
SFDR
SINAD
Figure 11. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency,
AIN = 70 MHz at −0.5 dBFS (−65/80 Grade)
04775-023
50
60
70
80
90
100
0 50 100 150 200 250 300
ANALOG INPUT FREQUENCY (MHz)
dB
H2
H3
SINAD
SFDR
SNR
Figure 12. Analog Input Frequency Sweep, AIN = −0.5 dBFS,
fS = 105 MSPS (−105 Grade)
50
60
70
80
90
100
0
04775-051
ANALOG INPUT FREQUENCY (MHz)
dB
H2
H3
SNR
SINAD
50 100 150 200 250 300
SFDR
Figure 13. Analog Input Frequency Sweep, AIN = −0.5 dBFS,
fS = 80 MSPS (−80 Grade)
50
60
70
80
90
100
0
04775-052
ANALOG INPUT FREQUENCY (MHz)
dB
H2
H3
SNR
SINAD
50 100 150 200 250 300
SFDR
Figure 14. Analog Input Frequency Sweep, AIN = −0.5 dBFS,
fS = 65 MSPS (−65 Grade)
–40
04775-053
INPUT LEVEL (dBFS)
dB
0
10
20
30
40
50
60
70
80
90
–60–50 –30–20–10 0
SNR dB
SFDR dBc
SFDR dBFS
65dB REF. LINE
Figure 15. SFDR vs. Analog Input Level,
AIN = 70 MHz, fS = 105 MSPS (−105 Grade)
AD9216
Rev. A | Page 15 of 40
0
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0
INPUT LEVEL (dBFS)
dB
SFDR dBc
65dB REF. LINE
SNR dB
SFDR dBFS
04775-063
Figure 16. SFDR vs. Analog Input Level,
AIN = 70 MHz, fS = 80 MSPS (−80 Grade)
0
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0
INPUT LEVEL (dBFS)
SFDR dBFS
SFDR dBc
SNR dB
65dB REF. LINE
04775-054
dB
Figure 17. SFDR vs. Analog Input Level,
AIN = 70 MHz, fS = 65 MSPS (−65 Grade )
AMPLITUDE (dBFS)
20 30010 4050
INPUT FREQUENCY (MHz)
04775-025
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
IMD = –69.9dBc
Figure 18. Two-Tone IMD Performance
F1, F2 = 69.1 MHz, 70.1 MHz at −7 dBFS, 105 MSPS (−105 Grade)
04775-026
–60 –50 –40 –30 –20 –10 0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
dB
0
10
20
30
40
50
60
70
80
90
70dB REF LINE
TWO-TONE SFDR dBc
TWO-TONE SFDR dBFS
Figure 19. Two-Tone IMD Performance vs. Input Drive Level
(69.1 MHz and 70.1 MHz; fS = 105 MSPS (−105 Grade); F1, F2 Levels Equal)
0
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
04775-055
dB
SFDR dBFS
SFDR dBc
75dB REF. LINE
–70
Figure 20. Two-Tone IMD Performance vs. Input Drive Level
(69.1 MHz and 70.1 MHz; fS = 80 MSPS (−80 Grade); F1, F2 Levels Equal)
0
10
20
30
40
50
60
70
80
90
–60 –50 –40 –30 –20 –10 0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
04775-056
dB
–70
SFDR dBFS
SFDR dBc
75dB REF. LINE
Figure 21. Two-Tone IMD Performance vs. Input Drive Level
(69.1 MHz and 70.1 MHz; fS = 65 MSPS (−65 Grade); F1, F2 Levels Equal)
AD9216
Rev. A | Page 16 of 40
04775-027
–60 –50 –40 –30 –20 –10 0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
dB
0
10
20
30
40
50
60
70
80
90
100
70dB REF LINE
TWO-TONE SFDR dBc
TWO-TONE SFDR dBFS
Figure 22. Two-Tone IMD Performance vs. Input Drive Level
(100.1 MHz and 101.1 MHz; fS = 105 MSPS (−105 Grade); F1, F2 Levels Equal)
04775-028
10 20 40 60 80 90 100
SAMPLE CLOCK RATE (MSPS)
CURRENT (mA)
0
10
20
30
40
50
60
70
80
90
100
AVDD CURRENT (–105 GRADE)
AVDD CURRENT (–65/80 GRADE)
30 50 70
DRVDD CURRENT (ALL GRADES)
Figure 23. IAVDD, IDRVDD vs. Sample Clock Frequency,
CLOAD = 5 pF, AIN = 70 MHz @ −0.5 dBFS
04775-029
POSITIVE DUTY CYCLE (%)
dB
20
30
40
50
60
70
80
25 30 35 40 45 50 55 60 65 70 75
SFDR DCS ON
SFDR DCS
OFF
SNR DCS OFF
SNR DCS ON
Figure 24. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled;
AIN = 70 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)
04775-030
VREF (V)
dB
0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25
40
45
50
55
60
65
70
75
80
SNR
SFDR
Figure 25. SNR, SFDR vs. External VREF (Full Scale = 2 × VREF)
AIN = 70.3 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)
04775-031
–40–20020406080
TEMPERATURE (°C)
GAIN ERROR (% Full Scale)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
INTERNAL REFERENCE MODE
EXTERNAL REFERENCE MODE
Figure 26. Typical Gain Error Variation vs. Temperature, (−105 Grade)
AIN = 70 MHz at 0.5 dBFS, 105 MSPS (Normalized to 25°C)
04775-032
–40–20020406080
TEMPERATURE (°C)
dB
55
60
65
70
75
80
SFDR
SNR
SINAD
Figure 27. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)
AIN = 70 MHz at −0.5 dBFS, 105 MSPS, Internal Reference Mode
AD9216
Rev. A | Page 17 of 40
04775-033
–40–20020406080
TEMPERATURE (°C)
dB
55
60
65
70
75
80
SFDR
SNR
SINAD
Figure 28. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)
AIN = 70 MHz at −0.5 dBFS, 105 MSPS , External Reference Mode
55
60
65
70
75
80
–20 0 20 40 60 80
TEMPERATURE (°C)
04775-057
dB
–40
SNR
SINAD
SFDR
Figure 29. SNR, SINAD, SFDR vs. Temperature, (-80 Grade)
AIN = 70 MHz at −0.5 dBFS, 80 MSPS, Internal Reference Mode
55
60
65
70
75
85
–20 0 20 40 60 80
TEMPERATURE (°C)
04775-058
dB
–40
SNR
SINAD
SFDR
80
Figure 30. SNR, SINAD, SFDR vs. Temperature, (-65 Grade)
AIN = 70 MHz at −0.5 dBFS, 65 MSPS,, Internal Reference Mode
55
60
65
70
75
80
2.8 2.9 3.0 3.1 3.2 3.3
AVDD (V)
04775-059
dB
2.7
SFDR
SINAD
SNR
Figure 31. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz at −0.5 dBFS, 105 MSPS
(−105 Grade)
55
60
65
70
75
80
2.8 2.9 3.0 3.1 3.2 3.3
AVDD (V)
04775-062
dB
2.7
SFDR
SNR
SINAD
Figure 32. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz at −0.5 dBFS, 80 MSPS
(−80 Grade)
55
60
65
70
75
85
2.8 2.9 3.0 3.1 3.2 3.3
AVDD (V)
04775-060
dB
2.7
SFDR
SINAD
SNR
80
Figure 33. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz at −0.5 dBFS, 65MSPS
(−65 Grade)
AD9216
Rev. A | Page 18 of 40
04775-035
CODE
LSB
0 200 400 600 800 1000
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
Figure 34. Typical DNL Plot, AIN = 10.3 MHz at −0.5 dBFS, 105 MSPS
(−105 Grade)
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0 200 400 600 800 1000
CODE
LSB
04775-036
Figure 35. Typical INL Plot, AIN = 10.3 MHz at −0.5 dBFS, 105 MSPS
(−105 Grade)
4.0
4.2
4.4
4.6
4.8
5.0
5.2
–40–200 20406080
TEMPERATURE (°C)
TPD (ns)
04775-061
Figure 36. Typical Propagation Delay vs. Temperature ( All Speed Grades)
AD9216
Rev. A | Page 19 of 40
EQUIVALENT CIRCUITS
AVDD
VIN+_A, VIN–_A,
VIN+_B, VIN–_B
04775-004
Figure 37. Equivalent Analog Input
AVDD
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT,
SHARED_REF
04775-005
Figure 38. Equivalent Clock, Digital Inputs Circuit
AVDD
30kΩ
PDWN
04775-006
Figure 39. Power-Down Input
DRVDD
04775-007
Figure 40. Digital Outputs
AD9216
Rev. A | Page 20 of 40
THEORY OF OPERATION
The AD9216 consists of two high performance ADCs that are
based on the AD9215 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined, switched-capacitor ADC.
The pipelined ADC is divided into three sections, consisting of
a sample-and-hold amplifier, followed by seven 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined through the digital
correction logic block into a final 10-bit result. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the respec-
tive clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9216 is a differential switched-
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended
to maintain optimal performance.
The SHA input is a differential switched-capacitor circuit.
In Figure 41, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependant on the
application. In IF under-sampling applications, any shunt
capacitors should be removed. In combination with the driv-
ing source impedance, they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, so the common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
H
H
VIN+
VIN
–
C
PAR
C
PAR
T
T
0.5pF T
T
04775-008
0.5pF
Figure 41. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common-mode
of the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = 1/2 (AV D D + VREF)
REFB = 1/2 (AV D D − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage and,
by definition, the input span is twice the value of the VREF voltage.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as
VCMMIN = VREF/2
VCMMAX = (AV DD + VREF)/2
The minimum common-mode input level allows the AD9216
to accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN−. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference.
AD9216
Rev. A | Page 21 of 40
For example, a 2 V p-p signal may be applied to VIN+, while a
1 V reference is applied to VIN−. The AD9216 then accepts an
input signal varying between 2 V and 0 V. In the single-ended
configuration, distortion performance may degrade signifi-
cantly as compared to the differential case. However, the effect
is less noticeable at lower input frequencies.
04775-009
40
45
50
55
60
65
70
75
80
85
0.25 0.75 1.25 1.75 2.25 2.75
dB
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2V p-p SFDR
2V p-p SNR
Figure 42. Input Common-Mode Voltage Sensitivity
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9216 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9216. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 43.
AD9216
VIN_A
VIN_B
AVDD
AGND
2
V p-p
50Ω
50Ω
10pF
10pF
49.9Ω
1kΩ
1kΩ
0.1µF
04775-010
Figure 43. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
For dc-coupled applications, the AD8138, AD8139, or
AD8351 can serve as a convenient ADC driver, depending on
requirements. Figure 44 shows an example with the AD8138.
The AD9216 PCB has an optional AD8139 on board, as shown
in Figure 53. Note the AD8351 typically yields better perform-
ance for frequencies greater than 30 MHz to 40 MHz.
04775-011
AD9216
AD8138
VIN+
AVDD
AGND
0.1µF
20pF
33Ω
33ΩVIN–
49.9Ω
1kΩ
1kΩ
499Ω
499Ω
523Ω
499Ω
Figure 44. Driving the ADC with the AD8138
FULL
SCALE/2
SENSE = GROUND
VIN+
VIN–
DIGITAL OUT = ALL ONES DIGITAL OUT = ALL ZEROES
04775-012
AVDD/2 AVDD/2
Figure 45. Analog Input Full Scale (Full Scale = 2 V)
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
AD9216
Rev. A | Page 22 of 40
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels asyn-
chronously may degrade performance significantly. In some
applications, it is desirable to skew the clock timing of adjacent
channels. The AD9216’s separate clock inputs allow for clock
timing skew (typically ±1 ns) between the channels without
significant performance degradation.
The AD9216 contains two clock duty cycle stabilizers, one for
each converter, that retime the nonsampling edge, providing an
internal clock with a nominal 50% duty cycle. Faster input clock
rates, where it becomes difficult to maintain 50% duty cycles,
can benefit from using DCS, as a wide range of input clock duty
cycles can be accommodated. Maintaining a 50% duty cycle
clock is particularly important in high speed applications, when
proper track-and-hold times for the converter are required to
maintain high performance. The DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 µs to 3 µs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated by
SNR degradation = 2 × log 10[1/2 × p × fINPUT × tJ]
In the equation, the rms aperture jitter, tJ, represents the root-
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. Under-
sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aper-
ture jitter may affect the dynamic range of the AD9216, it
is important to minimize input clock jitter. The clock input
circuitry should use stable references; for example, use analog
power and ground planes to generate the valid high and low
digital levels for the AD9216 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9216 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers
and the load on each output bit. The digital drive current can
be calculated by
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased, so each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases with clock frequency.
Either channel of the AD9216 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
Time to go into or come out of standby mode is 5 cycles maxi-
mum when only one channel is being powered down. When both
channels are powered down, VREF goes to ground, resulting in a
wake-up time of ~7 ms dependent on decoupling capacitor
values.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 3 mW for the ADC.
If the clock inputs remain active while in total standby mode,
typical power dissipation of 10 mW results.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B
= HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down.
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
DIGITAL OUTPUTS
The AD9216 output drivers can interface directly with 3 V
logic families. Applications requiring the ADC to drive large
capacitive loads or large fanouts may require external buffers
or latches because large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
The data format can be selected for either offset binary or twos
complement. This is discussed in the Data Format section.
AD9216
Rev. A | Page 23 of 40
OUTPUT CODING
Table 8.
Code (VIN+) − (VIN−) Offset Binary Twos Complement
1023 > +0.998 V 11 1111 1111 01 1111 1111
1023 +0.998 V 11 1111 1111 01 1111 1111
1022 +0.996 V 11 1111 1110 01 1111 1110
• • • •
• • • •
513 +0.002 V 10 0000 0001 00 0000 0001
512 +0.0 V 10 0000 0000 00 0000 0000
511 −0.002 V 01 1111 1111 11 1111 1111
• • • •
• • • •
1 −0.998 V 00 0000 0001 10 0000 0001
0 −1.000 V 00 0000 0000 10 0000 0000
0 < −1.000 V 00 0000 0000 10 0000 0000
TIMING
The AD9216 provides latched data outputs with a pipeline delay
of six clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest conversion rate of the AD9216 is
10 MSPS. At clock rates below 10 MSPS, dynamic perform-
ance may degrade.
DATA FORMAT
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
data format select pin (DFS). Connecting DFS to AGND
produces offset binary output data. Conversely, connecting
DFS to AVDD formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single, 10-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel
data is reversed; that is, the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to
the Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade ac perform-
ance. It is recommended to keep the clock skew < 100 pHs.
After the MUX_SELECT rising edge, either data port has
the data for its respective channel; after the falling edge, the
alternate channel’s data is placed on the bus. Typically, the
other unused bus is disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 46 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel’s power-
down pin must remain low.
B
–7
A
–6
B
–6
A
–5
B
–5
A
–4
B
–4
A
–3
B
–3
A
–2
B
–2
A
–1
B
–1
A
0
B
0
A
1
B
1
A
–1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
B
–1
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
CLK_A = CLK_B =
MUX_SELECT
D0_A
–D11_A
04775-013
Figure 46. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
AD9216
Rev. A | Page 24 of 40
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into
the AD9216. The input range can be adjusted by varying the
reference voltage applied to the AD9216, using either the inter-
nal reference with different external resistor configurations or
an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly.
Internal Reference Connection
A comparator within the AD9216 detects the potential at the
SENSE pin and configures the reference into three possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 47), setting VREF to 1 V. If a resistor divider
is connected, as shown in Figure 48, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
VREF = 0.5 × (1 + R2/R1)
Note: The optimum performance is obtained with VREF =
1.0 V; performance degrades as VREF (and full scale) reduces
(see Figure 25). In all reference configurations, REFT and REFB
drive the ADC core and establish its input span. The input
range of the ADC always equals twice the voltage at the refer-
ence pin for either an internal or an external reference.
VIN+
VIN–
10µF
10µF
0.1µF
0.1µF
REFT
ADC
CORE
SELECT
LOGIC
SENSE
0.1µF0.5V
AD9216
REFB
0.1µF
VREF
04775-014
Figure 47. Internal Reference Configuration (One Channel Shown)
Table 9. Reference Configuration Summary
Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)
External Reference AVDD N/A 2 × External Reference
Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (see Figure 48)
Internal Fixed Reference AGND to 0.2 V 1.0 2.0
AD9216
Rev. A | Page 25 of 40
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 49 shows the typical drift
characteristics of the internal reference.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V. If the internal reference of the AD9216 is
used to drive multiple converters to improve gain matching,
the loading of the reference by the other converters must be
considered. Figure 50 depicts how the internal reference
voltage is affected by loading.
VIN+
VIN–
V
REF
REFT
SENSE
0.5V
AD9216
REFB
R1
R2
10µF10µF
0.1µF
0.1µF10µF
ADC
CORE
SELECT
LOGIC
0.1µF
04775-015
Figure 48. Programmable Reference Configuration (one channel shown)
04775-016
TEMPERATURE (°C)
VREF ERROR (%)
0.4
0.5
0.6
0.3
0.2
0.1
0
–40–20020406080
VREF = 1.0V
Figure 49. Typical VREF Drift
04775-017
I
LOAD
(mA)
VREF ERROR (%)
0
0.05
–0.25
–0.20
–0.15
–0.10
–0.05
0 0.5 1.0 1.5 2.0 2.5 3.0
VREF = 1.0V
Figure 50. VREF Accuracy vs. Load
Shared Reference Mode
The shared reference mode allows the user to connect
the references from the dual ADCs together externally for
superior gain and offset matching performance. If the ADCs
are to function independently, the reference decoupling can
be treated independently and can provide superior isolation
between the dual channels. To enable shared reference mode,
the SHARED_REF pin must be tied high, and the external
differential references must be externally shorted. (REFT_A
must be externally shorted to REFT_B, and REFB_A must
be shorted to REFB_B.)
AD9216
Rev. A | Page 26 of 40
DUAL ADC LFCSP PCB
The PCB requires a low jitter clock source, analog sources,
and power supplies. The PCB interfaces directly with ADI’s
standard dual-channel data capture board (HSC-ADC-EVAL-
DC), which together with ADI’s ADC Analyzer™ software
allows for quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable
4-lead power strips.
Table 10. Power Connector
Terminal Comments
VCC1 3.0 V Analog supply for ADC
VDD1 2.5 V Output supply for ADC
VDL1 2.5 V Buffer supply
VCLK 3.0 V Supply for XOR Gates
+5 V Optional op amp supply
−5 V Optional op amp supply
1VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
primary side transformer. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can
be low-pass filtered at the secondary transformer to reduce
high frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution
for dc-coupled applications. To use the AD8139 op amp,
remove C14, R4, R5, C13, R37, and R36, and place R22, R23,
R30, and R24.
CLOCK
The single-clock input is at J5; the input clock is buffered and
drives both channel input clocks from Pin 3 at U8 through R79,
R40, and R85. Jumper E11 to E19 allows for inverting the input
clock. U8 also provides CLKA and CLKB outputs, which are
buffered by U6 and U5, which drive the DRA and DRB signals
(these are the data-ready clocks going off card). DRA and DRB
can also be inverted at their respective jumpers.
Table 11. Jumpers
Terminal Comments
OEB A Output Enable for A Side
PWDN A Power-Down A
MUX Mux Input
SHARED REF Shared Reference Input
DRA Invert DRA
LATA Invert A Latch Clock
ENC A Invert Encode A
OEB B Output Enable for B Side
PWDN B Power-Down B
DFS Data Format Select
SHARED REF Shared Reference Input
DRB Invert DRB
LATB Invert B Latch Clock
ENC B Invert Encode B
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are buffered on the PCB at U2, U4. The ADC
outputs have the recommended series resistors in line to limit
switching transient effects on ADC performance.
AD9216
Rev. A | Page 27 of 40
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 12. Dual CSP PCB Rev. B
No. Quan. Reference Designator Device Package Value
1 2 C1, C3 Capacitors 0201 20 pF
2 7 C2, C5, C7, C9, C10, C22, C36 Capacitors 0805 10 µF
3 44 C4, C6, C8, C11 to C15, C20, C21, C24 to C27, C29 to
C35, C39 to C66
Capacitors 0402 0.1 µF, (C59, C61 NP1)
4 7 C16 to C19, C37, C38,C67 Capacitors TAJD 10 µF
5 2 C23, C28 Capacitors 0201 0.1 µF
6 40 E1 to E7, E9 to E22, E24 to E27, E29 to E31, E33 to
E38, E40 to E43, E49, E61
Jumpers
7 6 J1 to J6 SMA
8 3 P1, P4, P11 Power Connector Posts Z5.531.3425.0 Wieland
9 3 P1, P4, P11 Detachable Connectors 25.602.5453.0 Wieland
10 1 P3, P8 (implemented as one 80 pin connector) Connector TSW-140-08-
L-D-RA
Samtec
11 4 R1, R2, R32, R34 Resistors 0402 36 Ω (All NP1)
12 6 R3, R7, R11, R14, R51, R61 Resistors 0402 50 Ω, (R11, R51 NP1)
13 4 R6, R8, R33, R42 Resistors 0402 100 Ω, (All NP1)
14 4 R4, R5, R36, R37 Resistors 0402 33 Ω
15 10 R9, R12, R20, R35, R40, R43, R50, R53, R84, R85 Resistors 0402 Zero Ω (R9, R12, R35,
R43, R50, R84 NP1)
16 6 R15, R16, R18, R26, R29, R31 Resistors 0402 499 Ω (R16, R29 NP1)
17 2 R17, R25 Resistors 0402 525 Ω
18 34 R19, R21, R27, R28, R39, R41, R44, R46 to R49, R52,
R54, R55, R57 to R60, R62 to R73, R75, R77, R78, R81
to R83
Resistors 0402
1 kΩ (R64, R78, R81, R82,
R83 NP1)
19 4 R22 to R24, R30 Resistors 0402 40 Ω (R22, R23, R24, R30
NP1)
20 2 R45, R56 Resistors 0402 10 kΩ (R45, R56 NP1)
21 7 R10, R13, R38, R74, R76, R79, R80 Resistor 0402 22 Ω
22 8 RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ9, RZ10 Resistor Pack CTS
742C163470J
47 Ω
24 2 T1, T2 Transformers T1-1WT
Minicircuits
25 1 U1 AD9216/AD9238/AD9248 LFCSP-64
26 2 U2, U4 Transparent Latch/Buffer TSSOP-48 SN74LVCH16373ADGGR
27 2 U3, U7 Inverter SC-70 SN74LVC1G04DCKT
(U3, U7 NP1)
28 3 U5, U6, U8 XOR SO-14 SN74VCX86
29 2 U11, U12 Amp SO-8/EP
AD8139
30 14 P2, P5 to P7, P9, P10, P12 to P18, P21 Solder Bridge
1 Not Populated.
AD9216
Rev. A | Page 28 of 40
LFCSP PCB SCHEMATICS
D7_A D7A
49
D8_A D8A
50
D9_A D9A
DRVDD2 52
DRGND2 53
D10_A D10A
54
D11_A D11A
55
D12_A D12A
56
D13_A D13A
57
OTR_A OTRA
58
OEB_A 59
PWDN_A 60
MUX_SEL 61
SH_REF 62
CLK_A 63
AVDD5
VD
64
EPAD 65
D7B D7_B
32
D6B 31
D5_B
30
DRVDD
29
DRGND
28
D4B D4_B
27
D3B D3_B
26
D2B D2_B
25
D1B 24
23
22
21
20
DCS
19
ENCB
D6_B
D1_B
D0_B
OEB_B
PDWN_B
DFS
CLK_B
D6_A D6A
48
D5_A D5A
47
D4_A D4A
46
D3_A D3A
45
D2_A D2A
44
D1_A D1A
43
D0_A D0A
42
DRVDD1 41
DRGND1 40
OTR_B OTRB
39
D13_B D13B
38
D12_B D12B
37
D11_B D11B
36
D10_B D10B
35
D9_B D9B
34
D8_B D8B
33
1AGND
2VIN_A
3VIN_AB
4AGND1
VD 5AVDD1
6REFT_A
7REFB_A
VREF
8VREF
SENSE
9SENSE
10 REFB_B
11 REFT_B
VD 12 AVDD2
13 AGND2
14 VIN_BB
15 VIN_B
16 AGND3
VCC 14
4B 13
4A 12
4Y 11
3B 10
3A 9
3Y 8
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
GND 7
2Y 6
2B 5
2A 4
1Y 3
1B 2
1A 1
3Y
3A
3B
4Y
4A
4B
VCC
8
9
10
11
12
13
14
18
VD
AVDD3
17
D0B
D5B
+
+ + + ++
ENCA
VREF
C30
0.1
µ
F
C66
0.1
µ
F
R45
NP_10k
Ω
R56
NP_10k
Ω
E2
E1
E27 E30
E41
E25
VD
C11
0.1
µ
F
SENSE
EXT_VREF C2
10
µ
F
VREF AND SENSE CIRCUIT
C4
0.1
µ
F
VDD
VDD C6
0.1
µ
F
E22
E24
VD
R67
1k
Ω
R68
1k
Ω
R70
1k
Ω
R69
1k
Ω
E21
E40
VD
E26
E29
VD E31
E33
VD
PADS TO SHORT
REFERENCES TOGETHER
P15
P16
P18
P17
REFTA
REFTB
REFBA
REFBB
REFB_B
REFT_B
REFT_A
REFB_A
AMPOUTB
R36
33
Ω
R37
33
Ω
AMPOUTBB
C3
20pF
C28
0.1µF
C7
10µF
C54
0.1µF
C23
0.1µF
C5
10µF
C55
0.1µF
C24
0.1µF
C26
0.1µF
C29
0.1µF
C27
0.1µF
4123 4123 4123
P5
P6
P7
VD
VDD
VDL
P21 VCLK
C37
10µF
C38
10µF
C16
10µF
C17
10µF
C18
10µF
C19
10µF
+
C67
10µFC39
0.1µF
C43
0
.
1µF
C44
0
.
1µF
C45
0
.
1µF
+5V –5VVCLKVDLVDD
VD
P11 P4 P1
E34 E16VD
VD
R55
1k
Ω
E37E38
R48
1k
Ω
NP_0
Ω
R12
22
Ω
R13
E35
E36VD
R49
1kΩ
C41
0.1
µ
F
VD
VCLK
J2
CLOCK B
R51
NP_50Ω
C42
0.1µF
R54
1kΩ
R52
1kΩ
P2 P9
U3
P13
ENCB
VD
VCLK
C22
10µF
C57
0.1µF
R6
NP_100
Ω
R8
NP_100
Ω
TIEB
1
2
3
5
4
SN74LVC1G04
NC
A
GND
VCC
Y
1
2
3
5
4
SN74LVC1G04
NC
A
GND
VCC
Y
P10 P12
C36
10µF
C58
0.1µF
ENCA
VCLK
VD R33
NP_100
Ω
R42
NP_100
Ω
R38
22
Ω
R50
NP_0
Ω
R74
22
Ω
R43
NP_0
Ω
U1
E13 E12VD
VD
R47
1k
Ω
E15
E14
R46
1k
Ω
NP_0
Ω
R9
22
Ω
R10
CLKLATB
DRB
DRA
CLKLATA
J6
R61
50
Ω
C56
0.1
µ
F
VCLK
J3
CLOCK A
R11
NP_50Ω
C40
0.1µF
R41
1kΩ
TIEA
R39
1kΩ
VCLK
C25
0.1µF
E3
E4
VD
R44
1kΩ
P14
E6
E5
VD
E20
E18
VD
E9
E7
VD
R66
1k
Ω
R65
1kΩ
R64
NP_1k
Ω
E10
E17
R63
1k
Ω
R62
1k
Ω
VD
VDD
C8
0.1µF
MUX
DUT CLOCK SELECTABLE
TO BE DIRECT OR BUFFERED
74VCX86
74LCX86
R4
33
Ω
J1
AIN B
C13
0.1
µ
F
R59
1k
Ω
R7
50
Ω
AMPINB
C10
10
µ
F
C12
0.1
µ
F
E43
E42
C9
10
µ
F
C31
0.1
µ
F
R57
1k
Ω
1
2
3
6
5
4
CTAPB
R5
33
Ω
1
2
3
6
5
4
CTAPA
AMPOUTAB
AMPOUTA
C14
0.1
µ
F
AMPINA
R3
50
Ω
R1
NP_36
Ω
R2
NP_36
Ω
J4
C1
20pF
C62
0.1µF
VD
–5V +5V VD VDD VDL EXT_VREF VCLK
CTAPA
R58
1k
Ω
VD
VD
R60
1k
Ω
CTAPB
T1
T2
SEE
BELOW
DUT CLOCK SELECTABLE
TO BE DIRECT OR
BUFFERED
J2, J3, OPTIONAL CLOCK PATHING
U5
U6
U7
AIN A
04775-038
NOTE
14-BIT PINOUT SHOWN
FOR 14-BIT: LSB = PIN 42, PI N 23
FOR 12-BIT: LSB = PIN 44, PI N 25
FOR 10-BIT: LSB = PIN 46, PI N 27
R34
NP_36
Ω
R32
NP_36
Ω
C63
0.1
µ
F
51
Figure 51. PCB Schematic (1 of 3)
AD9216
Rev. A | Page 29 of 40
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
47Ω
47Ω
47Ω
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
47Ω
SN74LVCH16373A
U2
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GND
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GND
GND
GND GND
GND
GND
GND
47Ω
R8
R7
R6
R5
R4
R3
R1
R2
47Ω
47Ω
47Ω
SN74LVCH16373A
U4
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GND
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GND
GND
GND GND
GND
GND
GND
Q = OUTPUT
D = INPUT
47
46
44
43
41
40
38
37
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
4
10
15
21
45
39
34
28
48
25
7
18
42
31
1
24
CLKLATB
CLKLATA
VDL
VDL
VDL
RZ6
RSO16ISO
RZ5
RSO16ISO
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ4
RSO16ISO
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ3
RSO16ISO
47
46
44
43
41
40
38
37
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
4
10
15
21
45
39
34
28
48
25
7
18
42
31
1
24
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ1
RSO16ISO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P3
RZ9
RSO16ISO
RZ10
RSO16ISO
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D8A
D9A
D2A
D3A
D4A
D5A
D6A
D7A
D0A
D1A
GND
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D0P
GND
DRA
DRB
OTRA
D13A
D12A
D11A
D10A
D7B
D9B
D8B
OTRB
D13B
D12B
D11B
D10B
DORP
D13P
D12P
D11P
D10P
DORQ
D13Q
D12Q
D11Q
D10Q
D9Q
D0Q
D8Q
D1Q
D2Q
D6Q
D7Q
D3Q
D4Q
D5Q
D13P
D12P
D11P
D10P
D0P
DORP
D13Q
D12Q
D11Q
D10Q
D0Q
DORQ
VDL
VDL VDL
VDL
CLKLATA
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ2
RSO16ISO
D5B
D6B
D4B
D3B
D2B
D1B
D0B
R8
R83
NP_1kΩR82
NP_1kΩ
R7
R6
R5
R4
R3
R1
R2
R8
R7
R6
R5
R4
R3
R1
R2
R8
R7
R6
R5
R4
R3
R1
R2
Q = OUTPUT
D = INPUT
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P8
VDL
C49
0.1µF
C48
0.1µF
C47
0.1µF
C46
0.1µF
C53
0.1µF
C52
0.1µF
C51
0.1µF
C50
0.1µF
39 39
VDL
04775-039
CLKLATB
R81
NP_1kΩR78
NP_1kΩ
Figure 52. PCB Schematic (2 of 3)
AD9216
Rev. A | Page 30 of 40
+IN
+OUT
–IN
–OUT
EPAD
NC V+
V– VOCM
AD8139
C20
0.1µF
8
4
1
5
9
736 2
U12
C35
0.1µF
R29
NP_499Ω
R30
NP_40Ω
R25
525Ω
AMPOUTB AMPOUTBB
+5V
–5V
AMPINB
C34
0.1µF
R28
1kΩ
R27
1kΩ
VD
R24
NP_40Ω
+IN
+OUT
–IN
–OUT
EPAD
NC V+
V– VOCM
AD8139
C21
0.1µF
8
4
1
5
9
736 2
U11
C32
0.1µF
R17
525Ω
R22
NP_40Ω
R16
NP_499Ω
AMPOUTAB AMPOUTA
+5V
–5V
AMPINA
C33
0.1µF
R19
1kΩ
R21
1kΩ
VD
R23
NP_40Ω
OP AMP INPUT OFF PIN ONE OF TRANSFORMER
04775-040
R31
499Ω
C61
NP_0.1µF
R26
499ΩC15
NP_0.1µFR15
499Ω
C60
NP_0.1µFR18
499Ω
C59
0.1µF
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
74VCX86 1
2
3
4
5
6
7
14
13
12
11
10
9
8
U8
E19 VD
ENCB
ENCA
J5 C64
1µF
R77
1kΩ
R72
1kΩ
R71
1kΩ
R14
50ΩR73
1kΩ
E11
R80
22Ω
R76
22ΩR79
22Ω
R75
1kΩ
R85
0Ω
R40
0Ω
C65
0.1µF
VCLK
CLKB
VCLK
CLKA
SCLK
CLOCK A/B
SINGLE CLOCK PATH
SINGLE CLOCK CIRCUIT
TO TIE CLOCKS TOGETHER
E49
E61
TIEACLKA
R20
0Ω
TIEBCLKB
R53
0Ω
MUXMUX1
R35
NP_0Ω
R84
NP_0Ω
SCLK MUX1
Figure 53. PCB Schematic (3 of 3)
AD9216
Rev. A | Page 31 of 40
LFCSP PCB LAYERS
04775–041
Figure 54. PCB Top-Side Silkscreen
AD9216
Rev. A | Page 32 of 40
04775–042
Figure 55. PCB Top-Side Copper Routing
AD9216
Rev. A | Page 33 of 40
04775–043
Figure 56. PCB Ground Layer
AD9216
Rev. A | Page 34 of 40
04775–044
Figure 57. PCB Split Power Plane
AD9216
Rev. A | Page 35 of 40
04775–045
Figure 58. PCB Bottom-Side Copper Routing
AD9216
Rev. A | Page 36 of 40
04775–046
Figure 59. PCB Bottom-Side Silkscreen
AD9216
Rev. A | Page 37 of 40
THERMAL CONSIDERATIONS
The AD9216 LFCSP package has an integrated heat slug that
improves the thermal and electrical properties of the package
when locally attached to a ground plane at the PCB. A thermal
(filled) via array to a ground plane beneath the part provides
a path for heat to escape the package, lowering junction
temperature. Improved electrical performance also results
from the reduction in package parasitics due to proximity
of the ground plane. Recommended array is 0.3 mm vias
on 1.2 mm pitch. θJA = 26.4°C/W with this recommended
configuration. Soldering the slug to the PCB is a require-
ment for this package.
04775-047
Figure 60. Thermal Via Array
AD9216
Rev. A | Page 38 of 40
OUTLINE DIMENSIONS
PIN 1
INDICATOR
TOP
VIEW 8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.45
0.40
0.35
0.50 BSC 0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
*4.85
4.70 SQ
4.55
SEATING
PLANE
PIN 1
INDICATOR
EXPOSED PAD
(BOTTOM VIEW)
0.30
0.25
0.18
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 × 9 mm Body, Very Thin Quad (CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9216BCPZ-651−40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1
AD9216BCPZRL7-651 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1
AD9216BCPZ-801 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1
AD9216BCPZRL7-801 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1
AD9216BCPZ-1051 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1
AD9216BCPZRL7-1051 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP-VQ) CP-64-1
AD9216-80PCB2 Evaluation Board with AD9216BCPZ-80
AD9216-105PCB Evaluation Board with AD9216BCPZ-105
1 Z = Pb-free part.
2 Supports AD9216-65 and AD9216-80 Evaluation.
AD9216
Rev. A | Page 39 of 40
NOTES
AD9216
Rev. A | Page 40 of 40
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04775–0–6/05(A)
