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OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage,
Low Input Bias Current Op Amp with e-trim™
1 Features 3 Description
The OPAx192 family (OPA192, OPA2192, and
1 Low Offset Voltage: ±5 µV OPA4192) is a new generation of 36-V, e-trim
Low Offset Voltage Drift: ±0.2 µV/°C operational amplifiers.
Low Noise: 5.5 nV/Hz at 1 kHz These devices offer outstanding dc precision and ac
High Common-Mode Rejection: 140 dB performance, including rail-to-rail input/output, low
Low Bias Current: ±5 pA offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ),
and 10-MHz bandwidth.
Rail-to-Rail Input and Output
Wide Bandwidth: 10 MHz GBW Unique features such as differential input-voltage
range to the supply rail, high output current (±65 mA),
High Slew Rate: 20 V/µs high capacitive load drive of up to 1 nF, and high
Low Quiescent Current: 1 mA per Amplifier slew rate (20 V/µs) make the OPA192 a robust, high-
Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V performance operational amplifier for high-voltage
industrial applications.
EMI/RFI Filtered Inputs
Differential Input Voltage Range to Supply Rail The OPA192 family of op amps is available in
standard packages and is specified from –40°C to
High Capacitive Load Drive Capability: 1 nF +125°C.
Industry Standard Packages:
Single in SOIC-8, SOT-23-5, and VSSOP-8 Device Information(1)
Dual in SOIC-8 and VSSOP-8 PART NUMBER PACKAGE BODY SIZE (NOM)
Quad in SOIC-14 and TSSOP-14 SOIC (8) 4.90 mm × 3.90 mm
OPA192 SOT-23 (5) 2.90 mm × 1.60 mm
2 Applications VSSOP (8) 3.00 mm × 3.00 mm
SOIC (8) 4.90 mm × 3.90 mm
Multiplexed Data-Acquisition Systems OPA2192 VSSOP (8) 3.00 mm × 3.00 mm
Test and Measurement Equipment SOIC (14) 8.65 mm x 3.90 mm
High-Resolution ADC Driver Amplifiers OPA4192 TSSOP (14) 5.00 mm x 4.40 mm
SAR ADC Reference Buffers (1) For all available packages, see the package option addendum
Programmable Logic Controllers at the end of the data sheet.
High-Side and Low-Side Current Sensing
High Precision Comparator
OPA192 in a High-Voltage, Multiplexed, Data-Acquisition System
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA192
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,
OPA4192
SBOS620E DECEMBER 2013REVISED NOVEMBER 2015
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Table of Contents
8.1 Overview................................................................. 23
1 Features.................................................................. 18.2 Functional Block Diagram....................................... 23
2 Applications ........................................................... 18.3 Feature Description................................................. 24
3 Description............................................................. 18.4 Device Functional Modes........................................ 30
4 Revision History..................................................... 29 Application and Implementation ........................ 31
5 Pin Configuration and Functions......................... 49.1 Application Information............................................ 31
6 Specifications......................................................... 69.2 Typical Applications ................................................ 31
6.1 Absolute Maximum Ratings ..................................... 610 Power-Supply Recommendations..................... 35
6.2 ESD Ratings.............................................................. 611 Layout................................................................... 35
6.3 Recommended Operating Conditions....................... 611.1 Layout Guidelines ................................................. 35
6.4 Thermal Information: OPA192 .................................. 711.2 Layout Example .................................................... 36
6.5 Thermal Information: OPA2192 ................................ 712 Device and Documentation Support................. 37
6.6 Thermal Information: OPA4192 ................................ 712.1 Device Support...................................................... 37
6.7 Electrical Characteristics: VS= ±4 V to ±18 V (VS=
+8 V to +36 V)............................................................ 812.2 Documentation Support ........................................ 37
6.8 Electrical Characteristics: VS= ±2.25 V to ±4 V (VS=12.3 Related Links ........................................................ 37
+4.5 V to +8 V)......................................................... 10 12.4 Community Resources.......................................... 37
6.9 Typical Characteristics............................................ 12 12.5 Trademarks........................................................... 38
6.10 Typical Characteristics.......................................... 13 12.6 Electrostatic Discharge Caution............................ 38
7 Parameter Measurement Information ................ 21 12.7 Glossary................................................................ 38
7.1 Input Offset Voltage Drift......................................... 21 13 Mechanical, Packaging, and Orderable
8 Detailed Description............................................ 23 Information........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2015) to Revision E Page
Changed PW package from product preview to production data........................................................................................... 1
Added PW package to test condition for input offset voltage drift.......................................................................................... 8
Added PW package to test condition for input offset voltage drift........................................................................................ 10
Added PW package condition to Figure 8 ........................................................................................................................... 13
Added PW package condition to Figure 10 ......................................................................................................................... 13
Added PW package condition to Figure 52 ......................................................................................................................... 22
Changed Figure 70 to fix typos ............................................................................................................................................ 36
Changes from Revision C (March 2015) to Revision D Page
Changed device status to Production Data; OPA4192 released to Production .................................................................... 1
Deleted footnote 2 from Device Information table ................................................................................................................. 1
Deleted footnote 2 from Pin Configuration and Functions section......................................................................................... 4
Changed ESD Ratings table: added correct OPA4192 CDM specifications ......................................................................... 6
Added Frequency Response, Crosstalk parameter to Electrical Characteristics: VS= ±4 V to ±18 V table ......................... 9
Added Frequency Response, Crosstalk parameter to Electrical Characteristics: VS= ±2.25 V to ±4 V table .................... 11
Changed Typical Characteristics to current standards (split curves and table of graphs into separate sections to be
SDS compliant) .................................................................................................................................................................... 12
Added Crosstalk vs Frequency row to Table 1 ................................................................................................................... 12
Added Figure 48 .................................................................................................................................................................. 20
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Changes from Revision B (March 2014) to Revision C Page
Added CDM row for OPA2192, OPA4192 in ESD Ratings table........................................................................................... 6
Changed input offset voltage values for VCM (V+) 1.5 V test condition............................................................................ 8
Changed Input offset voltage parameter typical specs for VCM = (V+) 1.5 V test conditions ............................................. 8
Changed test conditions for dVOS/dT parameter.................................................................................................................... 8
Changed input offset voltage max values and test conditions for VCM = (V+) 3 V test condition...................................... 10
Changed input offset voltage values and test conditions for VCM = (V+) 1.5 V test condition .......................................... 10
Changed Input offset voltage parameter typical specs for VCM = (V+) 1.5 V test conditions............................................ 10
Changed test conditions for dVOS/dT parameter ................................................................................................................. 10
Added text to last bullet of Layout Guidelines section.......................................................................................................... 35
Changes from Revision A (January 2014) to Revision B Page
Added ESD Ratings and Recommended Operating Conditions tables, and Parameter Measurement Information,
Application and Implementation,Power-Supply Recommendations, and Device and Documentation Support
sections, and moved existing sections................................................................................................................................... 1
Changed all OPA192 and OPA2192 packages to production data........................................................................................ 1
Changed package names to latest standard; changed all MSOP to VSSOP, SO to SOIC, and SOT23 to SOT ................. 1
Deleted DCK package pin configuration................................................................................................................................. 4
Added thermal information for OPA192 DBV and DGK packages......................................................................................... 7
Added OPA2192 and OPA4192 Thermal Information tables ................................................................................................ 7
Added rows with additional test conditions to input offset voltage parameter........................................................................ 8
Changed Input offset voltage drift parameter ........................................................................................................................ 8
Changed CMRR test conditions ............................................................................................................................................ 8
Added rows with additional test conditions to input offset voltage parameter...................................................................... 10
Changed Input offset voltage drift parameter....................................................................................................................... 10
Changed PSSR parameter .................................................................................................................................................. 10
Changed CMRR test conditions .......................................................................................................................................... 10
Added Output section........................................................................................................................................................... 11
Added typical characteristic curves to Table 1 .................................................................................................................... 12
Added TA= 25°C to Typical Characteristics condition line .................................................................................................. 12
Added nine new histogram plots from Figure 2 to Figure 10............................................................................................... 13
Changed Figure 11 to show more units ............................................................................................................................... 13
Changed Figure 19 .............................................................................................................................................................. 15
Added text to Application Information section...................................................................................................................... 31
Changed text in Layout Guidelines section.......................................................................................................................... 35
Changes from Original (December 2013) to Revision A Page
Changed first paragraph of 16-Bit Precision Multiplexed Data-Acquisition System section ................................................ 31
Changed Figure 66 and title................................................................................................................................................. 31
Changed TIDU181 reference design title............................................................................................................................. 32
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1
2
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14
13
12
11
OUTD
-IND
+IND
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-INA
+INA
V+
5
6
7
10
9
8
+INC
-INC
OUTC
+INB
-INB
OUTB
1
2
3
4
8
7
6
5
NC(1)
V+
OUT
NC(1)
NC(1)
-IN
+IN
V-
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
1
2
3
5
4
V+
-IN
OUT
V-
+IN
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5 Pin Configuration and Functions
DBV Package: OPA192 D and DGK Packages: OPA2192
5-Pin SOT 8-Pin SOIC and VSSOP
Top View Top View
D and DGK Packages: OPA192
8-Pin SOIC and VSSOP
Top View D and PW Packages: OPA4192
14-Pin SOIC and TSSOP
Top View
(1) NC = No internal connection.
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Pin Functions: OPA192
PIN
OPA192 I/O DESCRIPTION
NAME D (SOIC), DBV (SOT)
DGK (VSSOP)
+IN 3 3 I Noninverting input
–IN 2 4 I Inverting input
NC 1, 5, 8 No internal connection (can be left floating)
OUT 6 1 O Output
V+ 7 5 Positive (highest) power supply
V– 4 2 Negative (lowest) power supply
Pin Functions: OPA2192 and OPA4192
PIN
OPA2192 OPA4192 I/O DESCRIPTION
NAME D (SOIC), D (SOIC),
DGK (VSSOP) PW (TSSOP)
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
+IN C 10 I Noninverting input, channel C
+IN D 12 I Noninverting input, channel D
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
–IN C 9 I Inverting input,,channel C
–IN D 13 I Inverting input, channel D
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V+ 8 4 Positive (highest) power supply
V– 4 11 Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
±20
Supply voltage, VS= (V+) (V–) V
(40, single supply)
Common-mode (V–) 0.5 (V+) + 0.5
Voltage V
Signal input pins Differential (V+) (V–) + 0.2
Current ±10 mA
Output short circuit(2) Continuous
Operating range –55 150
Temperature Junction 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
OPA192
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
OPA2192
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 V
OPA4192
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Supply voltage, VS= (V+) (V–) 4.5 (±2.25) 36 (±18) V
Specified temperature –40 +125 °C
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6.4 Thermal Information: OPA192 OPA192
THERMAL METRIC(1) D (SOIC) DBV (SOT) DGK (VSSOP) UNIT
8 PINS 5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 115.8 158.8 180.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 60.1 60.7 67.9 °C/W
RθJB Junction-to-board thermal resistance 56.4 44.8 102.1 °C/W
ψJT Junction-to-top characterization parameter 12.8 1.6 10.4 °C/W
ψJB Junction-to-board characterization parameter 55.9 4.2 100.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2192 OPA2192
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 107.9 158 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 53.9 48.6 °C/W
RθJB Junction-to-board thermal resistance 48.9 78.7 °C/W
ψJT Junction-to-top characterization parameter 6.6 3.9 °C/W
ψJB Junction-to-board characterization parameter 48.3 77.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information: OPA4192 OPA4192
THERMAL METRIC(1) D (SOIC) PW (TSSOP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 86.4 92.6 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 46.3 27.5 °C/W
RθJB Junction-to-board thermal resistance 41.0 33.6 °C/W
ψJT Junction-to-top characterization parameter 11.3 1.9 °C/W
ψJB Junction-to-board characterization parameter 40.7 33.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.7 Electrical Characteristics: VS= ±4 V to ±18 V (VS= +8 V to +36 V)
At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
±5 ±25
TA= 0°C to 85°C ±8 ±50
TA= –40°C to +125°C ±10 ±75
VOS Input offset voltage µV
±10 ±40
VCM = (V+) 1.5 V TA= 0°C to 85°C ±25 ±150
TA= –40°C to +125°C ±50 ±250
TA= 0°C to 85°C ±0.1 ±0.5
D packages only TA= –40°C to +125°C ±0.15 ±0.8
dVOS/dT Input offset voltage drift µV/°C
TA= 0°C to 85°C ±0.1 ±0.8
DBV, DGK, and PW packages only TA= –40°C to +125°C ±0.2 ±1.0
Power-supply rejection
PSRR TA= –40°C to +125°C ±0.3 ±1.0 µV/V
ratio
INPUT BIAS CURRENT
±5 ±20 pA
IBInput bias current TA= –40°C to +125°C ±5 nA
±2 ±20 pA
IOS Input offset current TA= –40°C to +125°C ±2 nA
NOISE
(V–) 0.1 V < VCM < (V+) 3 V f = 0.1 Hz to 10 Hz 1.30
EnInput voltage noise µVPP
(V+) 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 4
f = 100 Hz 10.5
(V–) 0.1 V < VCM < (V+) 3 V f = 1 kHz 5.5
Input voltage noise
ennV/Hz
density f = 100 Hz 32
(V+) 1.5 V < VCM < (V+) + 0.1 V f = 1 kHz 12.5
NOISE (continued)
Input current noise
inf = 1 kHz 1.5 fA/Hz
density
INPUT VOLTAGE
Common-mode voltage
VCM (V–) 0.1 (V+) + 0.1 V
range
120 140
(V–) 0.1 V < VCM < (V+) 3 V TA= –40°C to +125°C 114 126 dB
Common-mode
CMRR 100 120
rejection ratio (V+) 1.5 V < VCM < (V+) TA= –40°C to +125°C 86 100
(V+) 3 V < VCM < (V+) 1.5 V See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 100 || 1.6 MΩ|| pF
1013Ω||
ZIC Common-mode 1 || 6.4 pF
OPEN-LOOP GAIN
120 134
(V–) + 0.6 V < VO< (V+) 0.6 V,
RLOAD = 2 kΩTA= –40°C to +125°C 114 126
AOL Open-loop voltage gain dB
126 140
(V–) + 0.3 V < VO< (V+) 0.3 V,
RLOAD = 10 kΩTA= –40°C to +125°C 120 134
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Electrical Characteristics: VS= ±4 V to ±18 V (VS= +8 V to +36 V) (continued)
At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE
GBW Unity gain bandwidth 10 MHz
SR Slew rate G = 1, 10-V step 20 V/µs
VS= ±18 V, G = 1, 10-V step 1.4
To 0.01% VS= ±18 V, G = 1, 5-V step 0.9
tsSettling time µs
VS= ±18 V, G = 1, 10-V step 2.1
To 0.001% VS= ±18 V, G = 1, 5-V step 1.8
tOR Overload recovery time VIN × G = VS200 ns
Total harmonic
THD+N G = 1, f = 1 kHz, VO= 3.5 VRMS 0.00008%
distortion + noise
OPA2192 and OPA4192, at dc 150
Crosstalk dB
OPA2192 and OPA4192, f = 100 kHz 130
OUTPUT
No load 5 15
Positive rail RLOAD = 10 kΩ95 110
RLOAD = 2 kΩ430 500
Voltage output swing
VOmV
from rail No load 5 15
Negative rail RLOAD = 10 kΩ95 110
RLOAD = 2 kΩ430 500
ISC Short-circuit current ±65 mA
CLOAD Capacitive load drive See Typical Characteristics
Open-loop output
ZOf = 1 MHz, IO= 0 A, see Figure 31 375 Ω
impedance
POWER SUPPLY
IO= 0 A 1 1.2
Quiescent current per
IQmA
amplifier TA= –40°C to +125°C, IO= 0 A 1.5
TEMPERATURE
Thermal protection(1) 140 °C
(1) For a detailed description of thermal protection, see the Thermal Protection section.
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6.8 Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= +4.5 V to +8 V)
At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
±5 ±25
VCM = (V+) 3 V TA= 0°C to 85°C ±8 ±50 µV
TA= –40°C to +125°C ±10 ±75
VOS Input offset voltage (V+) 3.5 V < VCM < (V+) 1.5 V See Common-Mode Voltage Range section
±10 ±40
VCM = (V+) 1.5 V TA= 0°C to 85°C ±25 ±150 µV
TA= –40°C to +125°C ±50 ±250
TA= 0°C to 85°C ±0.1 ±0.5
VCM = (V+) 3 V,
D packages only TA= –40°C to +125°C ±0.15 ±0.8
dVOS/dT Input offset voltage drift TA= 0°C to 85°C ±0.1 ±0.8 µV/°C
VCM = (V+) 3 V,
DBV, DGK, and PW packages only TA= –40°C to +125°C ±0.2 ±1.1
VCM = (V+) 1.5 V, TA= –40°C to +125°C ±0.5 ±3
Power-supply rejection
PSRR TA= –40°C to +125°C, VCM = VS/ 2 0.75 V ±1 µV/V
ratio
INPUT BIAS CURRENT
±5 ±20 pA
IBInput bias current TA= –40°C to +125°C ±5 nA
±2 ±20 pA
IOS Input offset current TA= –40°C to +125°C ±2 nA
NOISE
(V–) 0.1 V < VCM < (V+) 3 V, f = 0.1 Hz to 10 Hz 1.30
EnInput voltage noise µVPP
(V+) 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz 4
f = 100 Hz 10.5
(V–) 0.1 V < VCM < (V+) 3 V f = 1 kHz 5.5
enInput voltage noise density nV/Hz
f = 100 Hz 32
(V+) 1.5 V < VCM < (V+) + 0.1 V f = 1 kHz 12.5
inInput current noise density f = 1 kHz 1.5 fA/Hz
INPUT VOLTAGE
Common-mode voltage
VCM (V–) 0.1 (V+) + 0.1 V
range
94 110
(V–) 0.1 V < VCM < (V+) 3 V TA= –40°C to +125°C 90 104 dB
Common-mode rejection
CMRR 100 120
ratio (V+) 1.5 V < VCM < (V+) TA= –40°C to +125°C 84 100
(V+) 3 V < VCM < (V+) 1.5 V See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 100 || 1.6 MΩ|| pF
1013Ω||
ZIC Common-mode 1 || 6.4 pF
OPEN-LOOP GAIN
110 120
(V–) + 0.6 V < VO< (V+) 0.6 V,
RLOAD = 2 kΩTA= –40°C to +125°C 100 114
AOL Open-loop voltage gain dB
110 126
(V–) + 0.3 V < VO< (V+) 0.3 V,
RLOAD = 10 kΩTA= –40°C to +125°C 110 120
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Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= +4.5 V to +8 V) (continued)
At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE
GBW Unity gain bandwidth 10 MHz
SR Slew rate G = 1, 10-V step 20 V/µs
tsSettling time To 0.01% VS= ±3 V, G = 1, 5-V step 1 µs
tOR Overload recovery time VIN× G = VS200 ns
OPA2192 and OPA4192, at dc 150
Crosstalk dB
OPA2192 and OPA4192, f = 100 kHz 130
OUTPUT
No load 5 15
Positive rail RLOAD = 10 kΩ95 110
RLOAD = 2 kΩ430 500
Voltage output swing from
VOmV
rail No load 5 15
Negative rail RLOAD = 10 kΩ95 110
RLOAD = 2 kΩ430 500
ISC Short-circuit current ±65 mA
CLOAD Capacitive load drive See Typical Characteristics
Open-loop output
ZOf = 1 MHz, IO= 0 A, see Figure 31 375 Ω
impedance
POWER SUPPLY
1 1.2
Quiescent current per
IQIO= 0 A mA
amplifier TA= –40°C to +125°C 1.5
TEMPERATURE
Thermal protection(1) 140 °C
(1) For a detailed description of thermal protection, see the Thermal Protection section.
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Product Folder Links: OPA192 OPA2192 OPA4192
OPA192
,
OPA2192
,
OPA4192
SBOS620E DECEMBER 2013REVISED NOVEMBER 2015
www.ti.com
6.9 Typical Characteristics Table 1. Table of Graphs
DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1 to Figure 6
Offset Voltage Drift Distribution Figure 7 to Figure 10
Offset Voltage vs Temperature Figure 11
Offset Voltage vs Common-Mode Voltage Figure 12 to Figure 14
Offset Voltage vs Power Supply Figure 15
Open-Loop Gain and Phase vs Frequency Figure 16
Closed-Loop Gain and Phase vs Frequency Figure 17
Input Bias Current vs Common-Mode Voltage Figure 18
Input Bias Current vs Temperature Figure 19
Output Voltage Swing vs Output Current (maximum supply) Figure 20
CMRR and PSRR vs Frequency Figure 21
CMRR vs Temperature Figure 22
PSRR vs Temperature Figure 23
0.1-Hz to 10-Hz Noise Figure 24
Input Voltage Noise Spectral Density vs Frequency Figure 25
THD+N Ratio vs Frequency Figure 26
THD+N vs Output Amplitude Figure 27
Quiescent Current vs Supply Voltage Figure 28
Quiescent Current vs Temperature Figure 29
Open Loop Gain vs Temperature Figure 30
Open Loop Output Impedance vs Frequency Figure 31
Small Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 32,Figure 33
No Phase Reversal Figure 34
Positive Overload Recovery Figure 35
Negative Overload Recovery Figure 36
Small-Signal Step Response (100 mV) Figure 37,Figure 38
Large-Signal Step Response Figure 39
Settling Time Figure 40 to Figure 43
Short-Circuit Current vs Temperature Figure 44
Maximum Output Voltage vs Frequency Figure 45
Propagation Delay Rising Edge Figure 46
Propagation Delay Falling Edge Figure 47
Crosstalk vs Frequency Figure 48
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-75
-50
-25
0
25
50
75
Amplifiers (%)
Offset Voltage (µV)
C013
Distribution Taken From 190 Amplifiers
TA = -25ƒC
-75
-50
-25
0
25
50
75
Amplifiers (%)
Offset Voltage (µV)
C013
Distribution Taken From 190 Amplifiers
TA = -40ƒC
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Amplifiers (%)
Offset Voltage (µV)
C013
Distribution Taken From 190 Amplifiers
TA = 85ƒC
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Amplifiers (%)
Offset Voltage (µV)
C013
Distribution Taken From 190 Amplifiers
TA = 0ƒC
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
Percentage of Amplifiers (%)
Offset Voltage (V)
C032
Distribution Taken From 4715 Amplifiers
-75
-50
-25
0
25
50
75
Amplifiers (%)
Offset Voltage (µV)
C013
Distribution Taken From 190 Amplifiers
TA = 125 ƒC
OPA192
,
OPA2192
,
OPA4192
www.ti.com
SBOS620E DECEMBER 2013REVISED NOVEMBER 2015
6.10 Typical Characteristics
At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.
Figure 1. Offset Voltage Production Distribution at 25°C Figure 2. Offset Voltage Production Distribution at 125°C
Figure 3. Offset Voltage Production Distribution at 85°C Figure 4. Offset Voltage Production Distribution at 0°C
Figure 5. Offset Voltage Production Distribution at –25°C Figure 6. Offset Voltage Production Distribution at 40°C
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VOS (V)
VCM (V)
C001
5 Typical Units Shown
VCM = -18.1 V
±100
±75
±50
±25
0
25
50
75
100
±75 ±50 ±25 0 25 50 75 100 125 150
VOS (V)
Temperature (ƒC)
C001
190 Typical Units Shown
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Amplifiers (%)
Offset Voltage Drift (µV/ƒC)
C013
Distribution Taken From 120 Amplifiers
SOIC, TA = 0ƒC to 85ƒC
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Amplifiers (%)
Offset Voltage Drift (µV/ƒC)
C013
Distribution Taken From 75 Amplifiers
SOT and VSSOP, TA = 0ƒC to 85ƒC
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Amplifiers (%)
Offset Voltage Drift (µV/ƒC)
C013
Distribution Taken From 120 Amplifiers
SOIC, TA = -40ƒC to +125ƒC
-1.1
-0.9
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
Amplifiers (%)
Offset Voltage Drift (µV/ƒC)
C013
Distribution Taken From 75 Amplifiers
SOT and VSSOP, TA = -40ƒC to +125ƒC
OPA192
,
OPA2192
,
OPA4192
SBOS620E DECEMBER 2013REVISED NOVEMBER 2015
www.ti.com
Typical Characteristics (continued)
At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.
OPA192ID and OPA2192ID OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW
Figure 7. Offset Voltage Drift Distribution Figure 8. Offset Voltage Drift Distribution
from –40°C to +125°C from –40°C to +125°C
OPA192ID and OPA2192ID OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW
Figure 9. Offset Voltage Drift Distribution Figure 10. Offset Voltage Drift Distribution
from 0°C to 85°C from 0°C to 85°C
Figure 11. Offset Voltage vs Temperature Figure 12. Offset Voltage vs Common-Mode Voltage
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