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OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage,

Low Input Bias Current Op Amp with e-trim™

1 Features 3 Description

The OPAx192 family (OPA192, OPA2192, and

1• Low Offset Voltage: ±5 µV OPA4192) is a new generation of 36-V, e-trim

• Low Offset Voltage Drift: ±0.2 µV/°C operational amplifiers.

• Low Noise: 5.5 nV/√Hz at 1 kHz These devices offer outstanding dc precision and ac

• High Common-Mode Rejection: 140 dB performance, including rail-to-rail input/output, low

• Low Bias Current: ±5 pA offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ),

and 10-MHz bandwidth.

• Rail-to-Rail Input and Output

• Wide Bandwidth: 10 MHz GBW Unique features such as differential input-voltage

range to the supply rail, high output current (±65 mA),

• High Slew Rate: 20 V/µs high capacitive load drive of up to 1 nF, and high

• Low Quiescent Current: 1 mA per Amplifier slew rate (20 V/µs) make the OPA192 a robust, high-

• Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V performance operational amplifier for high-voltage

industrial applications.

• EMI/RFI Filtered Inputs

• Differential Input Voltage Range to Supply Rail The OPA192 family of op amps is available in

standard packages and is specified from –40°C to

• High Capacitive Load Drive Capability: 1 nF +125°C.

• Industry Standard Packages:

– Single in SOIC-8, SOT-23-5, and VSSOP-8 Device Information(1)

– Dual in SOIC-8 and VSSOP-8 PART NUMBER PACKAGE BODY SIZE (NOM)

– Quad in SOIC-14 and TSSOP-14 SOIC (8) 4.90 mm × 3.90 mm

OPA192 SOT-23 (5) 2.90 mm × 1.60 mm

2 Applications VSSOP (8) 3.00 mm × 3.00 mm

SOIC (8) 4.90 mm × 3.90 mm

• Multiplexed Data-Acquisition Systems OPA2192 VSSOP (8) 3.00 mm × 3.00 mm

• Test and Measurement Equipment SOIC (14) 8.65 mm x 3.90 mm

• High-Resolution ADC Driver Amplifiers OPA4192 TSSOP (14) 5.00 mm x 4.40 mm

• SAR ADC Reference Buffers (1) For all available packages, see the package option addendum

• Programmable Logic Controllers at the end of the data sheet.

• High-Side and Low-Side Current Sensing

• High Precision Comparator

OPA192 in a High-Voltage, Multiplexed, Data-Acquisition System

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

Table of Contents

8.1 Overview................................................................. 23

1 Features.................................................................. 18.2 Functional Block Diagram....................................... 23

2 Applications ........................................................... 18.3 Feature Description................................................. 24

3 Description............................................................. 18.4 Device Functional Modes........................................ 30

4 Revision History..................................................... 29 Application and Implementation ........................ 31

5 Pin Configuration and Functions......................... 49.1 Application Information............................................ 31

6 Specifications......................................................... 69.2 Typical Applications ................................................ 31

6.1 Absolute Maximum Ratings ..................................... 610 Power-Supply Recommendations..................... 35

6.2 ESD Ratings.............................................................. 611 Layout................................................................... 35

6.3 Recommended Operating Conditions....................... 611.1 Layout Guidelines ................................................. 35

6.4 Thermal Information: OPA192 .................................. 711.2 Layout Example .................................................... 36

6.5 Thermal Information: OPA2192 ................................ 712 Device and Documentation Support................. 37

6.6 Thermal Information: OPA4192 ................................ 712.1 Device Support...................................................... 37

6.7 Electrical Characteristics: VS= ±4 V to ±18 V (VS=

+8 V to +36 V)............................................................ 812.2 Documentation Support ........................................ 37

6.8 Electrical Characteristics: VS= ±2.25 V to ±4 V (VS=12.3 Related Links ........................................................ 37

+4.5 V to +8 V)......................................................... 10 12.4 Community Resources.......................................... 37

6.9 Typical Characteristics............................................ 12 12.5 Trademarks........................................................... 38

6.10 Typical Characteristics.......................................... 13 12.6 Electrostatic Discharge Caution............................ 38

7 Parameter Measurement Information ................ 21 12.7 Glossary................................................................ 38

7.1 Input Offset Voltage Drift......................................... 21 13 Mechanical, Packaging, and Orderable

8 Detailed Description............................................ 23 Information........................................................... 38

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (September 2015) to Revision E Page

• Changed PW package from product preview to production data........................................................................................... 1

• Added PW package to test condition for input offset voltage drift.......................................................................................... 8

• Added PW package to test condition for input offset voltage drift........................................................................................ 10

• Added PW package condition to Figure 8 ........................................................................................................................... 13

• Added PW package condition to Figure 10 ......................................................................................................................... 13

• Added PW package condition to Figure 52 ......................................................................................................................... 22

• Changed Figure 70 to fix typos ............................................................................................................................................ 36

Changes from Revision C (March 2015) to Revision D Page

• Changed device status to Production Data; OPA4192 released to Production .................................................................... 1

• Deleted footnote 2 from Device Information table ................................................................................................................. 1

• Deleted footnote 2 from Pin Configuration and Functions section......................................................................................... 4

• Changed ESD Ratings table: added correct OPA4192 CDM specifications ......................................................................... 6

• Added Frequency Response, Crosstalk parameter to Electrical Characteristics: VS= ±4 V to ±18 V table ......................... 9

• Added Frequency Response, Crosstalk parameter to Electrical Characteristics: VS= ±2.25 V to ±4 V table .................... 11

• Changed Typical Characteristics to current standards (split curves and table of graphs into separate sections to be

SDS compliant) .................................................................................................................................................................... 12

• Added Crosstalk vs Frequency row to Table 1 ................................................................................................................... 12

• Added Figure 48 .................................................................................................................................................................. 20

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Changes from Revision B (March 2014) to Revision C Page

• Added CDM row for OPA2192, OPA4192 in ESD Ratings table........................................................................................... 6

• Changed input offset voltage values for VCM ≥(V+) – 1.5 V test condition............................................................................ 8

• Changed Input offset voltage parameter typical specs for VCM = (V+) – 1.5 V test conditions ............................................. 8

• Changed test conditions for dVOS/dT parameter.................................................................................................................... 8

• Changed input offset voltage max values and test conditions for VCM = (V+) – 3 V test condition...................................... 10

• Changed input offset voltage values and test conditions for VCM = (V+) – 1.5 V test condition .......................................... 10

• Changed Input offset voltage parameter typical specs for VCM = (V+) – 1.5 V test conditions............................................ 10

• Changed test conditions for dVOS/dT parameter ................................................................................................................. 10

• Added text to last bullet of Layout Guidelines section.......................................................................................................... 35

Changes from Revision A (January 2014) to Revision B Page

• Added ESD Ratings and Recommended Operating Conditions tables, and Parameter Measurement Information,

Application and Implementation,Power-Supply Recommendations, and Device and Documentation Support

sections, and moved existing sections................................................................................................................................... 1

• Changed all OPA192 and OPA2192 packages to production data........................................................................................ 1

• Changed package names to latest standard; changed all MSOP to VSSOP, SO to SOIC, and SOT23 to SOT ................. 1

• Deleted DCK package pin configuration................................................................................................................................. 4

• Added thermal information for OPA192 DBV and DGK packages......................................................................................... 7

• Added OPA2192 and OPA4192 Thermal Information tables ................................................................................................ 7

• Added rows with additional test conditions to input offset voltage parameter........................................................................ 8

• Changed Input offset voltage drift parameter ........................................................................................................................ 8

• Changed CMRR test conditions ............................................................................................................................................ 8

• Added rows with additional test conditions to input offset voltage parameter...................................................................... 10

• Changed Input offset voltage drift parameter....................................................................................................................... 10

• Changed PSSR parameter .................................................................................................................................................. 10

• Changed CMRR test conditions .......................................................................................................................................... 10

• Added Output section........................................................................................................................................................... 11

• Added typical characteristic curves to Table 1 .................................................................................................................... 12

• Added TA= 25°C to Typical Characteristics condition line .................................................................................................. 12

• Added nine new histogram plots from Figure 2 to Figure 10............................................................................................... 13

• Changed Figure 11 to show more units ............................................................................................................................... 13

• Changed Figure 19 .............................................................................................................................................................. 15

• Added text to Application Information section...................................................................................................................... 31

• Changed text in Layout Guidelines section.......................................................................................................................... 35

Changes from Original (December 2013) to Revision A Page

• Changed first paragraph of 16-Bit Precision Multiplexed Data-Acquisition System section ................................................ 31

• Changed Figure 66 and title................................................................................................................................................. 31

• Changed TIDU181 reference design title............................................................................................................................. 32

Product Folder Links: OPA192 OPA2192 OPA4192

OUTD

-IND

+IND

V-

OUTA

-INA

+INA

V+

+INC

-INC

OUTC

+INB

-INB

OUTB

NC(1)

V+

OUT

NC(1)

-IN

+IN

V-

V+

OUTB

-INB

+INB

OUTA

-INA

+INA

V-

V+

-IN

OUT

V-

+IN

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

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5 Pin Configuration and Functions

DBV Package: OPA192 D and DGK Packages: OPA2192

5-Pin SOT 8-Pin SOIC and VSSOP

Top View Top View

D and DGK Packages: OPA192

8-Pin SOIC and VSSOP

Top View D and PW Packages: OPA4192

14-Pin SOIC and TSSOP

Top View

(1) NC = No internal connection.

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Pin Functions: OPA192

OPA192 I/O DESCRIPTION

NAME D (SOIC), DBV (SOT)

DGK (VSSOP)

+IN 3 3 I Noninverting input

–IN 2 4 I Inverting input

NC 1, 5, 8 — — No internal connection (can be left floating)

OUT 6 1 O Output

V+ 7 5 — Positive (highest) power supply

V– 4 2 — Negative (lowest) power supply

Pin Functions: OPA2192 and OPA4192

OPA2192 OPA4192 I/O DESCRIPTION

NAME D (SOIC), D (SOIC),

DGK (VSSOP) PW (TSSOP)

+IN A 3 3 I Noninverting input, channel A

+IN B 5 5 I Noninverting input, channel B

+IN C — 10 I Noninverting input, channel C

+IN D — 12 I Noninverting input, channel D

–IN A 2 2 I Inverting input, channel A

–IN B 6 6 I Inverting input, channel B

–IN C — 9 I Inverting input,,channel C

–IN D — 13 I Inverting input, channel D

OUT A 1 1 O Output, channel A

OUT B 7 7 O Output, channel B

OUT C — 8 O Output, channel C

OUT D — 14 O Output, channel D

V+ 8 4 — Positive (highest) power supply

V– 4 11 — Negative (lowest) power supply

Product Folder Links: OPA192 OPA2192 OPA4192

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OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

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6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

±20

Supply voltage, VS= (V+) – (V–) V

(40, single supply)

Common-mode (V–) – 0.5 (V+) + 0.5

Voltage V

Signal input pins Differential (V+) – (V–) + 0.2

Current ±10 mA

Output short circuit(2) Continuous

Operating range –55 150

Temperature Junction 150 °C

Storage, Tstg –65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V

OPA192

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V

OPA2192

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750 V

OPA4192

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Supply voltage, VS= (V+) – (V–) 4.5 (±2.25) 36 (±18) V

Specified temperature –40 +125 °C

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

6.4 Thermal Information: OPA192 OPA192

THERMAL METRIC(1) D (SOIC) DBV (SOT) DGK (VSSOP) UNIT

8 PINS 5 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 115.8 158.8 180.4 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 60.1 60.7 67.9 °C/W

RθJB Junction-to-board thermal resistance 56.4 44.8 102.1 °C/W

ψJT Junction-to-top characterization parameter 12.8 1.6 10.4 °C/W

ψJB Junction-to-board characterization parameter 55.9 4.2 100.3 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Thermal Information: OPA2192 OPA2192

THERMAL METRIC(1) D (SOIC) DGK (VSSOP) UNIT

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 107.9 158 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 53.9 48.6 °C/W

RθJB Junction-to-board thermal resistance 48.9 78.7 °C/W

ψJT Junction-to-top characterization parameter 6.6 3.9 °C/W

ψJB Junction-to-board characterization parameter 48.3 77.3 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.6 Thermal Information: OPA4192 OPA4192

THERMAL METRIC(1) D (SOIC) PW (TSSOP) UNIT

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 86.4 92.6 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 46.3 27.5 °C/W

RθJB Junction-to-board thermal resistance 41.0 33.6 °C/W

ψJT Junction-to-top characterization parameter 11.3 1.9 °C/W

ψJB Junction-to-board characterization parameter 40.7 33.1 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

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6.7 Electrical Characteristics: VS= ±4 V to ±18 V (VS= +8 V to +36 V)

At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

±5 ±25

TA= 0°C to 85°C ±8 ±50

TA= –40°C to +125°C ±10 ±75

VOS Input offset voltage µV

±10 ±40

VCM = (V+) – 1.5 V TA= 0°C to 85°C ±25 ±150

TA= –40°C to +125°C ±50 ±250

TA= 0°C to 85°C ±0.1 ±0.5

D packages only TA= –40°C to +125°C ±0.15 ±0.8

dVOS/dT Input offset voltage drift µV/°C

TA= 0°C to 85°C ±0.1 ±0.8

DBV, DGK, and PW packages only TA= –40°C to +125°C ±0.2 ±1.0

Power-supply rejection

PSRR TA= –40°C to +125°C ±0.3 ±1.0 µV/V

ratio

INPUT BIAS CURRENT

±5 ±20 pA

IBInput bias current TA= –40°C to +125°C ±5 nA

±2 ±20 pA

IOS Input offset current TA= –40°C to +125°C ±2 nA

NOISE

(V–) – 0.1 V < VCM < (V+) – 3 V f = 0.1 Hz to 10 Hz 1.30

EnInput voltage noise µVPP

(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 4

f = 100 Hz 10.5

(V–) – 0.1 V < VCM < (V+) – 3 V f = 1 kHz 5.5

Input voltage noise

ennV/√Hz

density f = 100 Hz 32

(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 1 kHz 12.5

NOISE (continued)

Input current noise

inf = 1 kHz 1.5 fA/√Hz

density

INPUT VOLTAGE

Common-mode voltage

VCM (V–) – 0.1 (V+) + 0.1 V

range

120 140

(V–) – 0.1 V < VCM < (V+) – 3 V TA= –40°C to +125°C 114 126 dB

Common-mode

CMRR 100 120

rejection ratio (V+) – 1.5 V < VCM < (V+) TA= –40°C to +125°C 86 100

(V+) – 3 V < VCM < (V+) – 1.5 V See Typical Characteristics

INPUT IMPEDANCE

ZID Differential 100 || 1.6 MΩ|| pF

1013Ω||

ZIC Common-mode 1 || 6.4 pF

OPEN-LOOP GAIN

120 134

(V–) + 0.6 V < VO< (V+) – 0.6 V,

RLOAD = 2 kΩTA= –40°C to +125°C 114 126

AOL Open-loop voltage gain dB

126 140

(V–) + 0.3 V < VO< (V+) – 0.3 V,

RLOAD = 10 kΩTA= –40°C to +125°C 120 134

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Electrical Characteristics: VS= ±4 V to ±18 V (VS= +8 V to +36 V) (continued)

At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FREQUENCY RESPONSE

GBW Unity gain bandwidth 10 MHz

SR Slew rate G = 1, 10-V step 20 V/µs

VS= ±18 V, G = 1, 10-V step 1.4

To 0.01% VS= ±18 V, G = 1, 5-V step 0.9

tsSettling time µs

VS= ±18 V, G = 1, 10-V step 2.1

To 0.001% VS= ±18 V, G = 1, 5-V step 1.8

tOR Overload recovery time VIN × G = VS200 ns

Total harmonic

THD+N G = 1, f = 1 kHz, VO= 3.5 VRMS 0.00008%

distortion + noise

OPA2192 and OPA4192, at dc 150

Crosstalk dB

OPA2192 and OPA4192, f = 100 kHz 130

OUTPUT

No load 5 15

Positive rail RLOAD = 10 kΩ95 110

RLOAD = 2 kΩ430 500

Voltage output swing

VOmV

from rail No load 5 15

Negative rail RLOAD = 10 kΩ95 110

RLOAD = 2 kΩ430 500

ISC Short-circuit current ±65 mA

CLOAD Capacitive load drive See Typical Characteristics

Open-loop output

ZOf = 1 MHz, IO= 0 A, see Figure 31 375 Ω

impedance

POWER SUPPLY

IO= 0 A 1 1.2

Quiescent current per

IQmA

amplifier TA= –40°C to +125°C, IO= 0 A 1.5

TEMPERATURE

Thermal protection(1) 140 °C

(1) For a detailed description of thermal protection, see the Thermal Protection section.

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6.8 Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= +4.5 V to +8 V)

At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

±5 ±25

VCM = (V+) – 3 V TA= 0°C to 85°C ±8 ±50 µV

TA= –40°C to +125°C ±10 ±75

VOS Input offset voltage (V+) – 3.5 V < VCM < (V+) – 1.5 V See Common-Mode Voltage Range section

±10 ±40

VCM = (V+) – 1.5 V TA= 0°C to 85°C ±25 ±150 µV

TA= –40°C to +125°C ±50 ±250

TA= 0°C to 85°C ±0.1 ±0.5

VCM = (V+) – 3 V,

D packages only TA= –40°C to +125°C ±0.15 ±0.8

dVOS/dT Input offset voltage drift TA= 0°C to 85°C ±0.1 ±0.8 µV/°C

VCM = (V+) – 3 V,

DBV, DGK, and PW packages only TA= –40°C to +125°C ±0.2 ±1.1

VCM = (V+) – 1.5 V, TA= –40°C to +125°C ±0.5 ±3

Power-supply rejection

PSRR TA= –40°C to +125°C, VCM = VS/ 2 – 0.75 V ±1 µV/V

ratio

INPUT BIAS CURRENT

±5 ±20 pA

IBInput bias current TA= –40°C to +125°C ±5 nA

±2 ±20 pA

IOS Input offset current TA= –40°C to +125°C ±2 nA

NOISE

(V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz 1.30

EnInput voltage noise µVPP

(V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz 4

f = 100 Hz 10.5

(V–) – 0.1 V < VCM < (V+) – 3 V f = 1 kHz 5.5

enInput voltage noise density nV/√Hz

f = 100 Hz 32

(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 1 kHz 12.5

inInput current noise density f = 1 kHz 1.5 fA/√Hz

INPUT VOLTAGE

Common-mode voltage

VCM (V–) – 0.1 (V+) + 0.1 V

range

94 110

(V–) – 0.1 V < VCM < (V+) – 3 V TA= –40°C to +125°C 90 104 dB

Common-mode rejection

CMRR 100 120

ratio (V+) – 1.5 V < VCM < (V+) TA= –40°C to +125°C 84 100

(V+) – 3 V < VCM < (V+) – 1.5 V See Typical Characteristics

INPUT IMPEDANCE

ZID Differential 100 || 1.6 MΩ|| pF

1013Ω||

ZIC Common-mode 1 || 6.4 pF

OPEN-LOOP GAIN

110 120

(V–) + 0.6 V < VO< (V+) – 0.6 V,

RLOAD = 2 kΩTA= –40°C to +125°C 100 114

AOL Open-loop voltage gain dB

110 126

(V–) + 0.3 V < VO< (V+) – 0.3 V,

RLOAD = 10 kΩTA= –40°C to +125°C 110 120

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Electrical Characteristics: VS= ±2.25 V to ±4 V (VS= +4.5 V to +8 V) (continued)

At TA= +25°C, VCM = VOUT = VS/ 2, and RLOAD = 10 kΩconnected to VS/ 2, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FREQUENCY RESPONSE

GBW Unity gain bandwidth 10 MHz

SR Slew rate G = 1, 10-V step 20 V/µs

tsSettling time To 0.01% VS= ±3 V, G = 1, 5-V step 1 µs

tOR Overload recovery time VIN× G = VS200 ns

OPA2192 and OPA4192, at dc 150

Crosstalk dB

OPA2192 and OPA4192, f = 100 kHz 130

OUTPUT

No load 5 15

Positive rail RLOAD = 10 kΩ95 110

RLOAD = 2 kΩ430 500

Voltage output swing from

VOmV

rail No load 5 15

Negative rail RLOAD = 10 kΩ95 110

RLOAD = 2 kΩ430 500

ISC Short-circuit current ±65 mA

CLOAD Capacitive load drive See Typical Characteristics

Open-loop output

ZOf = 1 MHz, IO= 0 A, see Figure 31 375 Ω

impedance

POWER SUPPLY

1 1.2

Quiescent current per

IQIO= 0 A mA

amplifier TA= –40°C to +125°C 1.5

TEMPERATURE

Thermal protection(1) 140 °C

(1) For a detailed description of thermal protection, see the Thermal Protection section.

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6.9 Typical Characteristics Table 1. Table of Graphs

DESCRIPTION FIGURE

Offset Voltage Production Distribution Figure 1 to Figure 6

Offset Voltage Drift Distribution Figure 7 to Figure 10

Offset Voltage vs Temperature Figure 11

Offset Voltage vs Common-Mode Voltage Figure 12 to Figure 14

Offset Voltage vs Power Supply Figure 15

Open-Loop Gain and Phase vs Frequency Figure 16

Closed-Loop Gain and Phase vs Frequency Figure 17

Input Bias Current vs Common-Mode Voltage Figure 18

Input Bias Current vs Temperature Figure 19

Output Voltage Swing vs Output Current (maximum supply) Figure 20

CMRR and PSRR vs Frequency Figure 21

CMRR vs Temperature Figure 22

PSRR vs Temperature Figure 23

0.1-Hz to 10-Hz Noise Figure 24

Input Voltage Noise Spectral Density vs Frequency Figure 25

THD+N Ratio vs Frequency Figure 26

THD+N vs Output Amplitude Figure 27

Quiescent Current vs Supply Voltage Figure 28

Quiescent Current vs Temperature Figure 29

Open Loop Gain vs Temperature Figure 30

Open Loop Output Impedance vs Frequency Figure 31

Small Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 32,Figure 33

No Phase Reversal Figure 34

Positive Overload Recovery Figure 35

Negative Overload Recovery Figure 36

Small-Signal Step Response (100 mV) Figure 37,Figure 38

Large-Signal Step Response Figure 39

Settling Time Figure 40 to Figure 43

Short-Circuit Current vs Temperature Figure 44

Maximum Output Voltage vs Frequency Figure 45

Propagation Delay Rising Edge Figure 46

Propagation Delay Falling Edge Figure 47

Crosstalk vs Frequency Figure 48

Product Folder Links: OPA192 OPA2192 OPA4192

-75

-50

-25

Amplifiers (%)

Offset Voltage (µV)

C013

Distribution Taken From 190 Amplifiers

TA = -25ƒC

-75

-50

-25

Amplifiers (%)

Offset Voltage (µV)

C013

Distribution Taken From 190 Amplifiers

TA = -40ƒC

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

Amplifiers (%)

Offset Voltage (µV)

C013

Distribution Taken From 190 Amplifiers

TA = 85ƒC

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

Amplifiers (%)

Offset Voltage (µV)

C013

Distribution Taken From 190 Amplifiers

TA = 0ƒC

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

Percentage of Amplifiers (%)

Offset Voltage (V)

C032

Distribution Taken From 4715 Amplifiers

-75

-50

-25

Amplifiers (%)

Offset Voltage (µV)

C013

Distribution Taken From 190 Amplifiers

TA = 125 ƒC

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

6.10 Typical Characteristics

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 1. Offset Voltage Production Distribution at 25°C Figure 2. Offset Voltage Production Distribution at 125°C

Figure 3. Offset Voltage Production Distribution at 85°C Figure 4. Offset Voltage Production Distribution at 0°C

Figure 5. Offset Voltage Production Distribution at –25°C Figure 6. Offset Voltage Production Distribution at –40°C

Product Folder Links: OPA192 OPA2192 OPA4192

±50

±25

±20 ±15 ±10 ±5 0 5 10 15 20

VOS (V)

VCM (V)

C001

5 Typical Units Shown

VCM = -18.1 V

±100

±75

±50

±25

100

±75 ±50 ±25 0 25 50 75 100 125 150

VOS (V)

Temperature (ƒC)

C001

190 Typical Units Shown

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

Amplifiers (%)

Offset Voltage Drift (µV/ƒC)

C013

Distribution Taken From 120 Amplifiers

SOIC, TA = 0ƒC to 85ƒC

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Amplifiers (%)

Offset Voltage Drift (µV/ƒC)

C013

Distribution Taken From 75 Amplifiers

SOT and VSSOP, TA = 0ƒC to 85ƒC

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Amplifiers (%)

Offset Voltage Drift (µV/ƒC)

C013

Distribution Taken From 120 Amplifiers

SOIC, TA = -40ƒC to +125ƒC

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

0.1

0.3

0.5

0.7

0.9

1.1

Amplifiers (%)

Offset Voltage Drift (µV/ƒC)

C013

Distribution Taken From 75 Amplifiers

SOT and VSSOP, TA = -40ƒC to +125ƒC

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

OPA192ID and OPA2192ID OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW

Figure 7. Offset Voltage Drift Distribution Figure 8. Offset Voltage Drift Distribution

from –40°C to +125°C from –40°C to +125°C

OPA192ID and OPA2192ID OPA192IDBV, OPA192IDGK, OPA2192IDGK, and OPA4192IPW

Figure 9. Offset Voltage Drift Distribution Figure 10. Offset Voltage Drift Distribution

from 0°C to 85°C from 0°C to 85°C

Figure 11. Offset Voltage vs Temperature Figure 12. Offset Voltage vs Common-Mode Voltage

Product Folder Links: OPA192 OPA2192 OPA4192

±20.0

0.0

20.0

40.0

60.0

1000 10k 100k 1M 10M

Gain (dB)

Frequency (Hz)

G = -100

G = +1

G = -1

G = -10

C003

±20

±15

±10

±5

±18.0 ±9.0 0.0 9.0 18.0

Input Bias Current (pA)

VCM (V)

C001

IB+

IB-

135

180

±20.0

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

1 10 100 1k 10k 100k 1M 10M 100M

Phase (ƒ)

Gain (dB)

Frequency (Hz)

C004

Phase

Open-loop Gain

CLOAD = 15 pF

±50

±40

±30

±20

±10

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0

VOS (V)

VSUPPLY (V)

C001

10 Typical Units Shown

VS = ±2.25 V to “18 V

±200

±150

±100

±50

100

150

200

±2.5 ±2.0 ±1.5 ±1.0 ±0.5 0.0 0.5 1.0 1.5 2.0 2.5

VOS (V)

VCM (V)

C001

5 Typical Units Shown

VS = ±2.25 V

VCM = +2.35 V

VCM = -2.35 V

P-Channel

Transition

N-Channel

±100

±75

±50

±25

100

12.5 13.5 14.5 15.5 16.5 17.5 18.5

VOS (V)

VCM (V)

C001

5 Typical Units Shown

VCM = +18.1 V

N-Channel

P-Channel

Transition

VCM = -18.1 V

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 13. Offset Voltage vs Common-Mode Voltage Figure 14. Offset Voltage vs Common-Mode Voltage

Figure 15. Offset Voltage vs Power Supply Figure 16. Open-Loop Gain and Phase vs Frequency

Figure 17. Closed-Loop Gain and Phase vs Frequency Figure 18. Input Bias Current vs Common-Mode Voltage

Product Folder Links: OPA192 OPA2192 OPA4192

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

±75 ±50 ±25 0 25 50 75 100 125 150

Power-Supply Rejection Ratio (µV/V)

Temperature (ƒC)

C001

400 nV/div

Time (1 s/div)

C001

Peak-to-Peak Noise = VRMS × 6.6 = 1.30 Vpp

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

1 10 100 1k 10k 100k 1M

Common-Mode Rejection Ratio (dB),

Power-Supply Rejection Ratio (dB)

Frequency (Hz)

+PSRR

CMRR

-PSRR

C012

±10

±8

±6

±4

±2

±75 ±50 ±25 0 25 50 75 100 125 150

Common-Mode Rejection Ratio (µV/V)

Temperature (ƒC)

C001

VS = ±18 V, VCM = 0 V

VS = ±2.25 V, VCM = V+ - 3 V

(V-) - 1

(V-)

(V-) + 1

(V-) + 2

(V-) + 3

(V-) + 4

(V-) + 5

0 10 20 30 40 50 60 70 80

Vout (V)

Iout (mA)

C001

-40°C

+125°C

±1000

1000

2000

3000

4000

5000

6000

±75 ±50 ±25 0 25 50 75 100 125 150 175

Input Bias Current (pA)

Temperature (ƒC)

C001

IB+

IB -

Ios

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 19. Input Bias Current vs Temperature Figure 20. Output Voltage Swing vs Output Current

(Maximum Supply)

Figure 21. CMRR and PSRR vs Frequency Figure 22. CMRR vs Temperature

Figure 23. PSRR vs Temperature Figure 24. 0.1-Hz to 10-Hz Noise

Product Folder Links: OPA192 OPA2192 OPA4192

0.8

0.9

1.1

1.2

±75 ±50 ±25 0 25 50 75 100 125 150

IQ (mA)

Temperature (ƒC)

C001

Vs = ±18 V

Vs = ±2.25 V

±3.0

±2.0

±1.0

0.0

1.0

2.0

3.0

±75 ±50 ±25 0 25 50 75 100 125 150

AOL (µV/V)

Temperature (ƒC)

C001

Vs = 4.5 V

Vs = 36 V

RL = 10 kŸ

0.8

0.9

1.0

1.1

1.2

0 4 8 12 16 20 24 28 32 36

IQ (mA)

Supply Voltage (V)

C001

-140

-120

-100

-80

-60

0.00001

0.0001

0.001

0.01

0.1

0.01 0.1 1 10

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

Output Amplitude (VRMS)

G = +1 V/V, RL = 10 k

G = +1 V/V, RL = 2 k

G = -1 V/V, RL = 10 k

G = -1 V/V, RL = 2 k

C008

f = 1 kHz

BW = 80 kHz

100

1000

0.1 1 10 100 1k 10k 100k

Voltage Noise Density (nV/rtHz)

Frequency (Hz)

C002

= V+ - 100 mV

N-Channel Input

= 0 V

P-Channel Input

-140

-120

-100

-80

-60

0.00001

0.0001

0.001

0.01

0.1

10 100 1k 10k

Total Harmonic Distortion + Noise (dB)

Total Harmonic Distortion + Noise (%)

Frequency (Hz)

G = +1 V/V, RL = 10 k

G = +1 V/V, RL = 2 k

G = -1 V/V, RL = 10 k

G = -1 V/V, RL = 2 k

C007

VOUT = 3.5 VRMS

BW = 80 kHz

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 26. THD+N Ratio vs Frequency

Figure 25. Input Voltage Noise Spectral Density

vs Frequency

Figure 27. THD+N vs Output Amplitude Figure 28. Quiescent Current vs Supply Voltage

Figure 30. Open-Loop Gain vs Temperature

Figure 29. Quiescent Current vs Temperature

Product Folder Links: OPA192 OPA2192 OPA4192

5 V/div

Time (200 ns/div)

C009

VOUT

VIN

RF= 10 kORI= 1 kO

VOUT

VIN

+ 18 V

±18 V

OPA192

G = -10

RI NŸ RF NŸ

5 V/div

Time (200 ns/div)

C010

VOUT

VIN

RF= 10 kORI= 1 kO

VOUT

VIN

+ 18 V

±18 V

OPA192

G = -10

RI NŸ RF NŸ

10p 100p 1n

Overshoot (%)

Capacitive Load (F)

C013

RISO = 0 

RISO = 25 

RISO = 50 

VIN

+ 18 V

±18 V

OPA192

RISO

G = +1

5 V/div

Time (200 s/div)

C011

VIN

VOUT

37 VPP

Sine Wave

(±18.5V)

+VOUT

+ 18 V

±18 V

OPA192

100

10k

0 1 10 100 1k 10k 100k 1M 10M

Output Impedance ()

Frequency (Hz)

C016

10p 100p 1n

Overshoot (%)

Capacitive Load (F)

RI= 1 kO

VIN

+ 18 V

±18 V

OPA192

RF= 1 kO

RISO

G = -1

C013

RISO = 0 

RISO = 25 

RISO = 50 

RI NŸ RF NŸ

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 31. Open-Loop Output Impedance vs Frequency Figure 32. Small-Signal Overshoot vs Capacitive Load

(100-mV Output Step)

Figure 33. Small-Signal Overshoot vs Capacitive Load Figure 34. No Phase Reversal

(100-mV Output Step)

Figure 35. Positive Overload Recovery Figure 36. Negative Overload Recovery

Product Folder Links: OPA192 OPA2192 OPA4192

-4

-3

-2

-1

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Output Delta from Final Value (mV)

Time (s)

C034

0.01% Settling = ±500 V

G = +1

Step Applied at t = 0

-4

-3

-2

-1

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Output Delta from Final Value (mV)

Time (s)

C034

0.01% Settling = ±1 mV

G = +1

Step Applied at t = 0

2 V/div

Time (300 ns/div)

C005

= 1 kŸ

CL = 10 pF

RI= 1 kO

VIN

+ 18 V

±18 V

OPA192

RF= 1 kO G = -1

RI NŸ RF NŸ

-4

-3

-2

-1

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

Output Delta from Final Value (mV)

Time (s)

C034

0.01% Settling = ±1 mV

G = +1

Step Applied at t = 0

20 mV/div

Time (100 ns/div)

C015

VIN

+ 18 V

±18 V

OPA192

G = +1

CL = 10 pF

20 mV/div

Time (120 ns/div)

C006

RI= 1 kO

VIN

+ 18 V

±18 V

OPA192

RF= 1 kO G = -1

RI NŸ RF NŸ

= 1 kŸ

CL = 10 pF

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 38. Small-Signal Step Response (100 mV)

Figure 37. Small-Signal Step Response (100 mV)

Figure 40. Settling Time (10-V Positive Step)

Figure 39. Large-Signal Step Response

Figure 41. Settling Time (5-V Positive Step) Figure 42. Settling Time (10-V Negative Step)

Product Folder Links: OPA192 OPA2192 OPA4192

Frequency (Hz)

Crosstalk (db)

-180

-160

-140

-120

-100

-80

1k 10k 100k 1M

Output Voltage (1 V/div)

Time (200 ns/div)

C026

VOUT Voltage

Overdrive = 100 mV

tpLH = 1.1 s

10k 100k 1M 10M

Output Voltage (VPP)

Frequency (Hz)

C033

VS = ±2.25 V

VS = ±5 V

VS = ±15 V

Maximum output voltage without

slew-rate induced distortion.

Output Voltage (5 V/div)

Time (200 ns/div)

C025

VOUT Voltage

Overdrive = 100 mV

tpLH = 0.97 s

-4

-3

-2

-1

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Output Delta from Final Value (mV)

Time (s)

C034

0.01% Settling = ±500 V

G = +1

Step Applied at t = 0

±75 ±50 ±25 0 25 50 75 100 125 150

ISC (mA)

Temperature (ƒC)

C001

ISC, Source

ISC, Sink

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

Typical Characteristics (continued)

At TA= 25°C, VS= ±18 V, VCM = VS/ 2, RLOAD = 10 kΩconnected to VS/ 2, and CL= 100 pF, unless otherwise noted.

Figure 43. Settling Time (5-V Negative Step) Figure 44. Short-Circuit Current vs Temperature

Figure 45. Maximum Output Voltage vs Frequency Figure 46. Propagation Delay Rising Edge

Figure 47. Propagation Delay Falling Edge Figure 48. Crosstalk vs Frequency

Product Folder Links: OPA192 OPA2192 OPA4192

Temperature (qC)

Offset Voltage (PV)

Offset Voltage vs Temperature

-50 -25 0 25 50 75 100 125 150

-100

-75

-50

-25

100

Temperature

Input Offset Voltage

VOS Before e-trim

VOS After e-trim

Linear component of drift

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

7 Parameter Measurement Information

7.1 Input Offset Voltage Drift

The OPAx192 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier input

offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with

input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of trimming

internal device parameters during either wafer probing or final testing. When trimming input offset voltage drift the

systematic or linear drift error on each device is trimmed to zero. This results in the remaining errors associated

with input offset drift are minimal and are the result from only nonlinear error sources. Figure 49 illustrates this

concept.

Figure 49. Input Offset Before and After Drift Trim

A common method of specifying input offset voltage drift is the box method. The box method estimates a

maximum input offset drift by bounding the offset voltage versus temperature curve with a box and using the

corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the

box corresponds to the input offset voltage drift. Figure 50 shows the box method concept. The box method

works particularly well when the input offset drift is dominated by the linear component of drift, but because the

OPA192 family uses TI’s e-trim technology to remove the linear component input offset voltage drift, the box

method is not a particularly useful method of accurately performing an error analysis. Figure 50 shows 30 typical

units of the OPAx192 with the box method superimposed for illustrative purposes. The boundaries of the box are

determined by the specified temperature range along the x-axis and the maximum specified input offset voltage

across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift

of 0.9 µV/°C. As shown in Figure 50, the slopes of the actual input offset voltage versus temperature are much

less than that predicted by the box method. The box method predicts a pessimistic value for the maximum input

offset voltage drift and is not recommended when performing an error analysis.

Figure 50. The Box Method

Product Folder Links: OPA192 OPA2192 OPA4192

±75

±50

±25

±75 ±50 ±25 0 25 50 75 100 125 150

VOS (V)

Temperature (ƒC)

C001

6 Typical Units Shown

3 1

-3 1

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

±75 ±50 ±25 0 25 50 75 100 125 150

Input Offset Voltage Drift (V/ƒC)

Temperature (ƒC)

C001

+3 1

-3 1

- 1

+ 1

SOIC

-1.1

-0.9

-0.7

-0.5

-0.3

-0.1

0.1

0.3

0.5

0.7

0.9

1.1

±75 ±50 ±25 0 25 50 75 100 125 150

Input Offset Voltage Drift (V/ƒC)

Temperature (ƒC)

C001

+3 1

-3 1

- 1

+ 1

SOT and VSSOP

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

Input Offset Voltage Drift (continued)

Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input

offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along

the input offset voltage versus temperature curve. The results for the OPAx192 family are shown in Figure 51

and Figure 52.

Figure 51. Input Offset Voltage Drift vs Temperature Figure 52. Input Offset Voltage Drift vs Temperature

(OPA192ID and OPA2192ID) (OPA192IDBV, OPA192IDGK, OPA2192IDGK, and

OPA4192IPW)

As shown in Figure 51, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to

+125°C. When performing an error analysis over the full specified temperature range, use the typical and

maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced

temperature range is applicable, use the information shown in Figure 51 or Figure 52 when performing an error

analysis. To determine the change in input offset voltage, use Equation 1:

ΔVOS =ΔT × dVOS/dT

where

•ΔVOS = Change in input offset voltage

•ΔT = Change in temperature

• dVOS/dT = Input offset voltage drift (1)

For example, determine the amount of OPA192ID input offset voltage change over the temperature range of

25°C to 75°C for 1 σ(68%) of the units. As shown in Figure 51, the input offset drift is typically 0.15 µV/°C. This

input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.15 µV/°C = 7.5 µV .

For 3 σ(99.7%) of the units, Figure 51 shows a typical input offset drift of 0.4 µV/°C. This input offset drift results

in a typical input offset voltage change of (75°C – 25°C) × 0.4 µV/°C = 20 µV.

Figure 53 shows six typical units.

Figure 53. Input Offset Voltage Drift vs Temperature for Six Typical Units

Product Folder Links: OPA192 OPA2192 OPA4192





36-V

Differential

Front End Slew

Boost

High

Capacitive Load

Compensation

e-trim

Package Level Trim

IN+

IN

VOUT

OPAx192





NCH Input

Stage

PCH Input

Stage

Output

Stage

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

8 Detailed Description

8.1 Overview

The OPAx192 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset

temperature drift implemented during the final steps of manufacturing after the plastic molding process. This

method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package

molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are

set, further communication to the trim structure is permanently disabled. The Functional Block Diagram section

shows the simplified diagram of the OPA192 with e-trim.

Unlike previous e-trim op amps, the OPAx192 uses a patented two-temperature trim architecture to achieve a

very low offset voltage of 25 µV (max) and low voltage offset drift of 0.5 µV/°C (max) over the full specified

temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for

high-impedance industrial sensors, filters, and high-voltage data acquisition.

8.2 Functional Block Diagram

Product Folder Links: OPA192 OPA2192 OPA4192

±100

±80

±60

±40

±20

100

0 5 10 15 20 25 30 35 40 45 50 55 60

Output Delta From Final Value (mV)

Time (s)

C040

Standard Input Diode Structure

Extends Settling Time

OPA192 Input Structure

Offers Fast Settling

0.1% Settling = ±10 mV

Input Low Pass Filter

Ron_mux

Sn+1

Simplified Mux Model

RFILT

CFILT

Vn = +10 V

Vn+1 = ±10 V

+10 V

±10 V

Buffer Amplifier

Idiode_transient

+10 V ~±9.3 V

Vin+

Vin±

~0.7 V Vout

±10 V

Ron_mux

OPA192

36 V ~0.7 V

VOUT

V+

VConventional Input Protection

Limits Differential Input Range

OPA192 Provides Full 36-V

Differential Input Range

VIN+

VIN

VOUT

V+

V

VIN+

VIN

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

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8.3 Feature Description

8.3.1 Input Protection Circuitry

The OPAx192 uses a unique input architecture to eliminate the need for input protection diodes but still provides

robust input protection under transient conditions. Conventional input diode protection schemes shown in

Figure 54 can be activated by fast transient step responses and can introduce signal distortion and settling time

delays because of alternate current paths, as shown in Figure 55. For low-gain circuits, these fast-ramping input

signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling

time, as shown in Figure 56.

Figure 54. OPA192 Input Protection Does Not Limit Differential Input Capability

Figure 55. Back-to-Back Diodes Create Settling Issues

Figure 56. OPA192 Protection Circuit Maintains Fast-Settling Transient Response

Product Folder Links: OPA192 OPA2192 OPA4192

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

10M 100M 1G 10G

EMIRR IN+ (dB)

Frequency (Hz)

C017

PRF = -10 dBm

VSUPPLY = ±18 V

VCM = 0 V

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Feature Description (continued)

The OPAx192 family of operational amplifiers provides a true high-impedance differential input capability for high-

voltage applications. This patented input protection architecture does not introduce additional signal distortion or

delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.

The OPA192 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the

op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping

input signals such as multiplexed data-acquisition systems; see Figure 66.

8.3.2 EMI Rejection

The OPAx192 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the OPAx192 benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.

Figure 57 shows the results of this testing on the OPA192. Table 2 shows the EMIRR IN+ values for the OPA192

at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be

centered on or operated near the particular frequency shown. Detailed information can also be found in the

application report EMI Rejection Ratio of Operational Amplifiers,SBOA128, available for download from

www.ti.com.

Figure 57. EMIRR Testing

Table 2. OPA192 EMIRR IN+ For Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

400 MHz 44.1 dB

applications

Global system for mobile communications (GSM) applications, radio communication, navigation,

900 MHz 52.8 dB

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.0 dB

802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and

2.4 GHz 69.5 dB

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

5.0 GHz 105.5 dB

operation, C-band (4 GHz to 8 GHz)

Product Folder Links: OPA192 OPA2192 OPA4192

VOUT

140ºC

3 V

0 V

Temperature

Normal

Operation

Output

High-Z

150°C

+30 V

100 Ÿ





VIN

3 V

IOUT = 30 mA

OPA192

TA = 65°C

PD = 0.81W

JA = 116°C/W

TJ = 116°C/W × 0.81W + 65°C

TJ = 159°C (expected)

5 V/div

Time (200 s/div)

C011

VIN

VOUT

37 VPP

Sine Wave

(±18.5V)

+VOUT

+ 18 V

±18 V

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

8.3.3 Phase Reversal Protection

The OPAx192 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The OPAx192 is a rail-to-rail input op amp; therefore, the common-mode range can

extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into

the appropriate rail. This performance is shown in Figure 58.

Figure 58. No Phase Reversal

8.3.4 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This

phenomenon is called self heating. The absolute maximum junction temperature of the OPAx192 is 150°C.

Exceeding this temperature causes damage to the device. The OPAx192 has a thermal protection feature that

prevents damage from self heating. The protection works by monitoring the temperature of the device and

turning off the op amp output drive for temperatures above 140°C. Figure 59 shows an application example for

the OPA192 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal

calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C.

The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 59 shows

how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the

output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal

protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.

Figure 59. Thermal Protection

8.3.5 Capacitive Load and Stability

The OPAx192 features a patented output stage capable of driving large capacitive loads, and in a unity-gain

configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the

amplifier to drive greater capacitive loads; see Figure 60 and Figure 61. The particular op amp circuit

configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an

amplifier will be stable in operation.

Product Folder Links: OPA192 OPA2192 OPA4192

Cload

Vin

Vout

+Vs

Riso

-Vs

10p 100p 1n

Overshoot (%)

Capacitive Load (F)

RI= 1 kO

VIN

+ 18 V

±18 V

OPA192

RF= 1 kO

RISO

G = -1

C013

RISO = 0 

RISO = 25 

RISO = 50 

RI NŸ RF NŸ

10p 100p 1n

Overshoot (%)

Capacitive Load (F)

C013

RISO = 0 

RISO = 25 

RISO = 50 

VIN

+ 18 V

±18 V

OPA192

RISO

G = +1

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

Figure 60. Small-Signal Overshoot vs Capacitive Load Figure 61. Small-Signal Overshoot vs Capacitive Load

(100-mV Output Step) (100-mV Output Step)

For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small

(10 Ωto 20 Ω) resistor, RISO, in series with the output, as shown in Figure 62. This resistor significantly reduces

ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with

the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly

reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at

low output levels. A high capacitive load drive makes the OPA192 well suited for applications such as reference

buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 62 uses an isolation resistor,

RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase

margin, and results using the OPA192 are summarized in Table 3. For additional information on techniques to

optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation,

and test results.

Figure 62. Extending Capacitive Load Drive with the OPA192

Table 3. OPA192 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and

Measured Results

PARAMETER VALUE

Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF

Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60°

RISO (Ω)47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7

Measured 23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6

Overshoot (%)

Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2°

For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,

simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using

an Isolation Resistor .

Product Folder Links: OPA192 OPA2192 OPA4192

±15.0 ±14.0 «11.0 12.0 13.0 14.0 15.0

Common-Mode Voltage (V)

Input Offset Voltage (V)

200

100

±100

±200

±300

Input Offset Voltage vs Vcm

without e-Trim Input

Transition

Region

P-Channel

Region N-Channel

Region

±15.0 ±14.0 «11.0 12.0 13.0 14.0 15.0

Common-Mode Voltage (V)

Input Offset Voltage (V)

200

100

±100

±200

±300

Transition

Region

P-Channel

Region N-Channel

Region

OPA192 e-Trim

Input Offset Voltage vs Vcm

NCH3

PCH2

PCH1

IS1

NCH4

-Vsupply

+Vsupply

VIN+

VIN-

FUSE BANK

VOS TRIM VOS DRIFT TRIM

e-TrimTM

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

8.3.6 Common-Mode Voltage Range

The OPAx192 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that

extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel

and P-channel differential input pairs, as shown in Figure 63. The N-channel pair is active for input voltages

close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active

for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition

region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary

modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD

performance may be degraded compared to operation outside this region.

Figure 63. Rail-to-Rail Input Stage

To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when

possible. The OPAx192 uses a precision trim for both the N-channel and P-channel regions. This technique

enables significantly lower levels of offset than previous-generation devices, causing variance in the transition

region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in

Figure 64.

Figure 64. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers

Product Folder Links: OPA192 OPA2192 OPA4192

Power-Supply

ESD Cell

100 Ÿ

VSS

VDD

IN±

IN+

TVS

VIN

+VS

±VS

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

8.3.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the

output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. Figure 65 shows an illustration of the ESD circuits contained in the OPAx192 (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or

the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

Figure 65. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

Product Folder Links: OPA192 OPA2192 OPA4192

OPA192

OPA2192

OPA4192

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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event

is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit

ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).

During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled

ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

8.3.8 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a

linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the

rated operating voltage, either due to the high input voltage or the high gain. After the device enters the

saturation region, the charge carriers in the output devices require time to return back to the linear state. After

the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the

propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

The overload recovery time for the OPAx192 is approximately 200 ns.

8.4 Device Functional Modes

The OPAx192 has a single functional mode and is operational when the power-supply voltage is greater than

4.5 V (±2.25 V). The maximum power supply voltage for the OPAx192 is 36 V (±18 V).

Product Folder Links: OPA192 OPA2192 OPA4192

SAR

ADC

REFP

VINP

VINM

4:2

Mux

+Antialiasing

Filter

Gain

Network

Gain

Network

Gain

Network

High-Voltage Level Translation

VCM

High-Voltage Multiplexed Input

Reference Driver

2 4

Voltage

Reference RC Filter Buffer RC Filter

16 Bits

400 kSPS

Delay

Digital Counter For Multiplexer

CONV

Very Low Output Impedance

Input-Filter Bandwidth High-Impedance Inputs

No Differential Input Clamps

Fast Settling-Time Requirements

Attenuate High-Voltage Input Signal

Fast-Settling Time Requirements

Stability of the Input Driver

Attenuate ADC Kickback Noise

VREF Output: Value and Accuracy

Low Temp and Long-Term Drift

Fast logic transition

±20-V,

10-kHz

Sine Wave

±20-V,

10-kHz

Sine Wave

Shmidtt

Trigger

Counter

REF3240 Voltage

Divider OPA350

VCM Generation Circuit

CH0+

CH0-

CH3+

CH3-

OPA192

OPA140

OPA192

OPA192 Gain

Network

OPA192

OPA2192

OPA4192

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The OPAx192 family offers outstanding dc precision and ac performance. These devices operate up to 36-V

supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as

10-MHz bandwidth and high capacitive load drive. These features make the OPAx192 a robust, high-

performance operational amplifier for high-voltage industrial applications.

9.2 Typical Applications

9.2.1 16-Bit Precision Multiplexed Data-Acquisition System

Figure 66 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in

industrial applications that require low distortion and a high-voltage differential input. The circuit uses the

ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along

with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This

TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the

OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.

Figure 66. OPA192 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage

Inputs with Lowest Distortion

9.2.1.1 Design Requirements

The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest

distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.

The design requirements for this block design are:

Product Folder Links: OPA192 OPA2192 OPA4192

Integral Nonlinearity Error (LSB)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ADC Differential Input (V)

–20 –15 –10 –5 0 5 10 15 20

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

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Typical Applications (continued)

• System Supply Voltage: ±15 V

• ADC Supply Voltage: 3.3 V

• ADC Sampling Rate: 400 kSPS

• ADC Reference Voltage (REFP): 4.096 V

• System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency

(fIN) of 10 kHz are applied to each differential input of the mux.

9.2.1.2 Detailed Design Procedure

The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for

highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 66. The circuit

is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output

buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast

sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design

considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input

analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each

analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit

resolution and lowest distortion system. The diagram includes the most important specifications for each

individual analog block.

This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input

stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design

is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding

helps in the decision of an appropriate input filter and selection of a mux to meet the system settling

requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level

translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next

step is to design a digital interface to switch the mux input channels with minimum delay. The final design

challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage

with low offset, drift, and noise contributions.

9.2.1.3 Application Curve

Figure 67. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test

results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition

System for High Voltage Inputs with Lowest Distortion.

Product Folder Links: OPA192 OPA2192 OPA4192

VCC

VEE

1.6 MŸ

VOUT

V+

VIN

10 kŸ

1.69 kŸ

470 nF

Op Amp Gain Stage Slew Rate Limiter





OPA192

VCC

VEE

V+





OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

9.2.2 Slew Rate Limit for Input Protection

In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.

By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down

at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one

additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high

output current and slew rate of the OPAx192 make the device an optimal amplifier to achieve slew rate control

for both dual- and single-supply systems.Figure 68 shows the OPA192 in a slew-rate limit design.

Figure 68. Slew Rate Limiter Uses One Op Amp

For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test

results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.

Product Folder Links: OPA192 OPA2192 OPA4192

1 kŸ

10 µF

RISO

37.4 Ÿ

VREF

2.5 V

RFx

10 kŸ CF

39 nF

V+





OPA192 VOUT

VCC



OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

9.2.3 Precision Reference Buffer

The OPAx192 features high output current drive capability and low input offset voltage, making the device an

excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the

10-µF ceramic capacitor shown in Figure 69, RISO, a 37.4-Ωisolation resistor, provides separation of two

feedback paths for optimal stability. Feedback path number one is through RFand is directly at the output, VOUT.

Feedback path number two is through RFx and CFand is connected at the output of the op amp. The optimized

stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still

provides a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability

components: RF, RFx , CF, and RISO.

Figure 69. Precision Reference Buffer

Product Folder Links: OPA192 OPA2192 OPA4192

OPA192

OPA2192

OPA4192

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SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

10 Power-Supply Recommendations

The OPAx192 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from

–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or

temperature are presented in the Typical Characteristics.

CAUTION

Supply voltages larger than 40 V can permanently damage the device; see the

Absolute Maximum Ratings.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout

section.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically

separate digital and analog grounds paying attention to the flow of the ground current. For more detailed

information refer to Circuit Board Layout Techniques,SLOA089.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much

better as opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. As illustrated in Figure 70, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

• Cleaning the PCB following board assembly is recommended for best performance.

• Any precision integrated circuit may experience performance shifts due to moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is

recommended to remove moisture introduced into the device packaging during the cleaning process. A

low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

Product Folder Links: OPA192 OPA2192 OPA4192

N/C

±IN

+IN

V±

V+

OUTPUT

N/C

VS+

GND

VS±

GND Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Use low-ESR, ceramic

bypass capacitor

Place components

close to device and to

each other to reduce

parasitic errors

VIN VOUT

(Schematic Representation)

Use low-ESR,

ceramic bypass

capacitor

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

11.2 Layout Example

Figure 70. Operational Amplifier Board Layout for Noninverting Configuration

Product Folder Links: OPA192 OPA2192 OPA4192

OPA192

OPA2192

OPA4192

www.ti.com

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a

free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range

of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain

analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE

These files require that either the TINA software (from DesignSoft™) or TINA-TI software

be installed. Download the free TINA-TI software from the TINA-TI folder.

12.1.1.2 TI Precision Designs

The OPA192 is featured in several TI Precision Designs, available online at

http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s

precision analog applications experts and offer the theory of operation, component selection, simulation,

complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.

12.2 Documentation Support

12.2.1 Related Documentation

Circuit Board Layout Techniques,SLOA089.

Op Amps for Everyone,SLOD006.

12.3 Related Links

Table 4 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

OPA192 Click here Click here Click here Click here Click here

OPA2192 Click here Click here Click here Click here Click here

OPA4192 Click here Click here Click here Click here Click here

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

Product Folder Links: OPA192 OPA2192 OPA4192

OPA192

OPA2192

OPA4192

SBOS620E –DECEMBER 2013–REVISED NOVEMBER 2015

www.ti.com

12.5 Trademarks

e-trim, E2E are trademarks of Texas Instruments.

TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

TINA, DesignSoft are trademarks of DesignSoft, Inc.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: OPA192 OPA2192 OPA4192

PACKAGE OPTION ADDENDUM

www.ti.com 3-Dec-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

OPA192ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192

OPA192IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OUYS

OPA192IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OUYS

OPA192IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OUXS

OPA192IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OUXS

OPA192IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192

OPA2192ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2192

OPA2192IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OVLM

OPA2192IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OVLM

OPA2192IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2192

OPA4192ID ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4192

OPA4192IDR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4192

OPA4192IPW ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 OPA4192

OPA4192IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 OPA4192

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com 3-Dec-2015

Addendum-Page 2

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

OPA192IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

OPA192IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

OPA192IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA192IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA192IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA2192IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2192IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1

OPA2192IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

OPA4192IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

OPA4192IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA192IDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0

OPA192IDBVT SOT-23 DBV 5 250 223.0 270.0 35.0

OPA192IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0

OPA192IDGKT VSSOP DGK 8 250 223.0 270.0 35.0

OPA192IDR SOIC D 8 2500 367.0 367.0 35.0

OPA2192IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0

OPA2192IDGKT VSSOP DGK 8 250 223.0 270.0 35.0

OPA2192IDR SOIC D 8 2500 367.0 367.0 35.0

OPA4192IDR SOIC D 14 2500 367.0 367.0 38.0

OPA4192IPWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

www.ti.com

PACKAGE OUTLINE

TYP

0.22

0.08

0.25

3.0

2.6

2X 0.95

1.9

1.45 MAX

TYP

0.15

0.00

5X 0.5

0.3

TYP

0.6

0.3

TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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OPA2192IDR OPA2192ID OPA2192IDGKT OPA2192IDGKR