IRF1302PBF - International Rectifier

HEXFET® Power MOSFET

Description

Specifically designed for Automotive applications, this Stripe Planar

design of HEXFET® Power MOSFET utilizes the lastest processing

techniques to achieve extremely low on-resistance per silicon area.

Additional features of this design are a 175°C junction operating

temperature, fast switching speed and improved repetitive avalanche

rating. These benefits combine to make this design an extremely efficient

and reliable device for use in Automotive applications and a wide variety

of other applications.

VDSS = 20V

RDS(on) = 4.0mΩ

ID = 180A

10/31/02

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Benefits

●Advanced Process Technology

●Ultra Low On-Resistance

●Dynamic dv/dt Rating

●175°C Operating Temperature

●Fast Switching

●Repetitive Avalanche Allowed up to Tjmax

AUTOMOTIVE MOSFET

PD - 94591

IRF1302

TO-220AB

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 180

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 130A

IDM Pulsed Drain Current 700

PD @TC = 25°C Power Dissipation 230 W

Linear Derating Factor 1.5 W/°C

VGS Gate-to-Source Voltage ± 20 V

EAS Single Pulse Avalanche Energy350 mJ

IAR Avalanche CurrentSee Fig.12a, 12b, 15, 16 A

EAR Repetitive Avalanche EnergymJ

dv/dt Peak Diode Recovery dv/dt TBD V/ns

TJOperating Junction and -55 to + 175

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Absolute Maximum Ratings

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case ––– 0.65

RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W

RθJA Junction-to-Ambient (PCB mount)––– 62

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Parameter Min. Typ. Max. Units Conditions

V(BR)DSS Drain-to-Source Breakdown Voltage 20 ––– ––– V VGS = 0V, ID = 250µA

∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.021 ––– V/°C Reference to 25°C, ID = 1mA

RDS(on) Static Drain-to-Source On-Resistance ––– 3.3 4.0 mΩVGS = 10V, ID = 104A 

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA

gfs Forward Transconductance 59 ––– ––– S VDS = 15V, ID = 104A

––– ––– 20 µA VDS = 20V, VGS = 0V

––– ––– 250 VDS = 16V, VGS = 0V, TJ = 150°C

Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V

Gate-to-Source Reverse Leakage ––– ––– -200 nA VGS = -20V

QgTotal Gate Charge ––– 79 120 ID = 104A

Qgs Gate-to-Source Charge ––– 18 27 nC VDS = 16V

Qgd Gate-to-Drain ("Miller") Charge ––– 31 46 VGS = 10V

td(on) Turn-On Delay Time ––– 28 ––– VDD = 11V

trRise Time ––– 130 ––– ID = 104A

td(off) Turn-Off Delay Time ––– 47 ––– RG = 4.5Ω

tfFall Time ––– 16 ––– VGS = 10V 

Between lead,

––– ––– 6mm (0.25in.)

from package

and center of die contact

Ciss Input Capacitance ––– 3600 ––– VGS = 0V

Coss Output Capacitance ––– 2370 ––– pF VDS = 25V

Crss Reverse Transfer Capacitance ––– 520 ––– ƒ = 1.0MHz, See Fig. 5

Coss Output Capacitance ––– 5710 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

Coss Output Capacitance ––– 2370 ––– VGS = 0V, VDS = 16V, ƒ = 1.0MHz

Coss eff. Effective Output Capacitance ––– 3540 ––– VGS = 0V, VDS = 0V to 16V

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

LDInternal Drain Inductance

LSInternal Source Inductance ––– –––

IGSS

4.5

7.5

IDSS Drain-to-Source Leakage Current

Parameter Min. Typ. Max. Units Conditions

ISContinuous Source Current MOSFET symbol

(Body Diode) ––– ––– showing the

ISM Pulsed Source Current integral reverse

(Body Diode) ––– ––– p-n junction diode.

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 104A, VGS = 0V 

trr Reverse Recovery Time ––– 66 100 ns TJ = 25°C, IF = 104A

Qrr Reverse RecoveryCharge ––– 130 200 nC di/dt = 100A/µs 

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Source-Drain Ratings and Characteristics

180

700

IRF1302

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Fig 4. Normalized On-Resistance

Vs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

-60 -40 -20 020 40 60 80 100 120 140 160 180

0.0

0.5

1.0

1.5

2.0

T , Junction Temperature ( C)

R , Drain-to-Source On Resistance

(Normalized)

DS(on)

V =

I =

10V

174A

4.0 5.0 6.0 7.0

VGS, Gate-to-Source Voltage (V)

10.00

100.00

1000.00

ID, Drain-to-Source Current (Α)

TJ = 25°C

TJ = 175°C

VDS = 15V

20µs PULSE WIDTH

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

ID, Drain-to-Source Current (A)

4.5V

20µs PULSE WIDTH

Tj = 25°C

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

ID, Drain-to-Source Current (A)

4.5V

20µs PULSE WIDTH

Tj = 175°C

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

IRF1302

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

020 40 60 80 100

Q , Total Gate Charge (nC)

V , Gate-to-Source Voltage (V)

I =

D104A V = 16V

0.1

100

1000

0.2 0.7 1.2 1.7 2.2

V ,Source-to-Drain Voltage (V)

I , Reverse Drain Current (A)

V = 0 V

T = 175 C

J°

T = 25 C

J°

110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C, Capacitance(pF)

Coss

Crss

Ciss

VGS

= 0V, f = 1 MHZ

Ciss

= C

+ C

gd, C

ds SHORTED

Crss

= C

Coss

= C

+ C

1 10 100

VDS , Drain-toSource Voltage (V)

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY R DS(on)

100µsec

IRF1302

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Fig 9. Maximum Drain Current Vs.

Case Temperature

VDS

90%

10%

VGS

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 10a. Switching Time Test Circuit

Fig 10b. Switching Time Waveforms

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

25 50 75 100 125 150 175

100

150

200

I , Drain Current (A)

LIMITED BY PACKAGE

TC, Case Temperature (°C)

0.01

0.1

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

1 2

JDM thJC C

t , Rectangular Pulse Duration (sec)

Thermal Response (Z )

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

IRF1302

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QGS QGD

Charge

D.U.T. V

3mA

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

25 50 75 100 125 150 175

140

280

420

560

700

Starting Tj, Junction Temperature ( C)

E , Single Pulse Avalanche Energy (mJ)

TOP

BOTTOM

43A

74A

104A

Fig 14. Threshold Voltage Vs. Temperature

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

1.0

2.0

3.0

4.0

VGS(th) Gate threshold Voltage (V)

ID = 250µA

IRF1302

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Fig 15. Typical Avalanche Current Vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆∆

∆∆

∆T/ ZthJC

Iav = 2∆∆

∆∆

∆T/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

100

1000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses

0.01

25 50 75 100 125 150

Starting T J , Junction Temperature (°C)

110

160

210

260

310

360

410

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 10% Duty Cycle

ID = 104A

IRF1302

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Peak Diode Recovery dv/dt Test Circuit

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

=10V

Driver Gate Drive

D.U.T. I

Waveform

D.U.T. V

Waveform

Inductor Curent

D = P. W .

Period







VDD

• dv/dt controlled by RG

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T*Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer



* Reverse Polarity of D.U.T for P-Channel

VGS

[ ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

[ ] ***

Fig 17. For N-channel HEXFET® power MOSFETs

IRF1302

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LEAD ASSIGNMENTS

1 - GATE

2 - DRAIN

3 - SOURCE

4 - DRAIN

- B -

1.32 (.052)

1.22 (.048)

3X 0.55 (.022)

0.46 (.018)

2.92 (.115)

2.64 (.104)

4.69 (.185)

4.20 (.165)

3X 0.93 (.037)

0.69 (.027)

4.06 (.160)

3.55 (.140)

1.15 (.045)

MIN

6.47 (.255)

6.10 (.240)

3.78 (.149)

3.54 (.139)

- A -

10.54 (.415)

10.29 (.405)

2.87 (.113)

2.62 (.103)

15.24 (.600)

14.84 (.584)

14.09 (.555)

13.47 (.530)

3X 1.40 (.055)

1.15 (.045)

2.54 (.100)

0.36 (.014) M B A M

1 2 3

NOTES:

1 DIMENSIONING & TOLER ANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.

2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

TO-220AB Part Marking Information

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

EXAMPLE:THIS IS AN IRF1010

LOT CODE 1789

ASSEMBLED ON WW 19, 1997

IN THE ASSEMBLY

LINE "C"

INTERNATIONAL

RECTIFIER

LOGO

ASSEMBLY

LOT CODE

PART NUMBER

DATE CODE

YEAR 7 = 1997

WEEK 19

LINE C

TO-220 package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.10/02

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Starting TJ = 25°C, L = 0.063mH

RG = 25Ω, IAS = 104A. (See Figure 12).

ISD ≤ 104A, di/dt ≤ 100A/µs, VDD ≤ V(BR)DSS,

TJ ≤ 175°C.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

 Coss eff. is a fixed capacitance that gives the same charging

time as Coss while VDS is rising from 0 to 80% VDSS .

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 75A.

 Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

 This is applied to D2Pak, when mounted on 1" square PCB ( FR-

4 or G-10 Material ). For recommended footprint and soldering

techniques refer to application note #AN-994.