HDLx-2416 Series Four Character 5.0 mm (0.2 inch) Smart 5x7 Alphanumeric Displays Data Sheet Description Features These are 5.0 mm (0.2 inch) four character 5 x 7 dot matrix displays driven by an on-board CMOS IC. These displays are pin for pin compatible with the HPDL-2416. The IC stores and decodes 7 bit ASCII data and displays it using a 5 x 7 font. Multiplexing circuitry, and drivers are also part of the IC. The IC has fast setup and hold times which makes it easy to interface to a microprocessor. x Enhanced drop-in replacement to HPDL-2416 x Smart alphanumeric display Built-in RAM, ASCII decoder, and LED drive circuitry x CMOS IC for low power consumption x Software controlled dimming levels and blank x 128 ASCII character set x End-stackable x Categorized for luminous intensity; Yellow and Green categorized for color x Low power and sunlight viewable AlGaAs versions x Wide operating temperature range -40C to +85C x Excellent ESD protection x Wide viewing angle (50 typ.) Absolute Maximum Ratings Supply Voltage, VDD to Ground[1] -0.5 V to 7.0 V Input Voltage, Any Pin to Ground -0.5 V to VDD + 0.5 V Free Air Operating Temperature Range, TA -40C to +85C Storage Temperature, TS -40C to 100C CMOS IC Junction Temperature, TJ (IC) +150C Relative Humidity (non-condensing) at 65C 85% Soldering Temperature [1.59 mm (0.063 in.) Below Body] Solder Dipping Wave Soldering 260C for 5 secs 250C for 3 secs ESD Protection, R = 1.5 k, C = 100 pF VZ = 2 kV (each pin) Note: 1. Maximum Voltage is with no LEDs illuminated. Devices: AlGaAs Red High Efficiency Red Orange Yellow Green HDLS-2416 HDLO-2416 HDLA-2416 HDLY-2416 HDLG-2416 HDLU-2416 HDLO-2416-DE000 HDLG-2416-FG000 ESD WARNING: Standard CMOS handling precautions should be observed with the HDLX-2416. The address and data inputs can be directly connected to the microprocessor address and data buses. The HDLX-2416 has several enhancements over the HPDL2416. These features include an expanded character set, internal 8 level dimming control, external dimming capability, and individual digit blanking. Finally, the extended functions can be disabled which allows the HDLX-2416 to operate exactly like an HPDL-2416 by disabling all of the enhancements except the expanded character set. The difference between the sunlight viewable HDLS2416 and the low power HDLU-2416 occurs at power-on or at the default brightness level. Following power up, the HDLS-2416 operates at the 100% brightness level, while the HDLU-2416 operates at the 27% brightness level. Power on sets the internal brightness control (bits 3-5) in the control register to binary code (000). For the HDLS-2416 binary code (000) corresponds to a 100% brightness level, and for the HDLU-2416 binary code (000) corresponds to a 27% brightness level. The other seven brightness levels are identical for both parts. Package Dimensions 25.15 (0.990) 3.05 (0.120) 0.38 REF. (0.015) 0.25 0.13 TYP. (0.010 0.005) 6.35 TYP. (0.250) 10.03 (0.395) PIN 1 IDENTIFIER 15.24 (0.600) 10.16 REF. (0.400) 5.08 (0.200) 20.07 (0.790) IMAGE PLANE 1.52 REF. (0.060) 3.43 (0.135) 2.41 TYP. (0.095) DATE CODE (YEAR, WEEK) PART NUMBER LUMINOUS INTENSITY COLOR BIN (3) 6.60 (0.260) HDLX-2416 YYWW X Z 4.06 (0.160) REF. NOTES: 1. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON ALL DIMENSIONS IS 0.254 mm ( 0.010). 0.51 0.13 TYP. (0.020 0.005) 2.41 (0.095) Pin Numbering and Location CE1 CE2 CLR CUE CU WR A1 A0 VDD 2 2. ALL DIMENSIONS ARE IN MILLIMETERS (INCHES). 2.54 TYP. (0.100) 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 BL D4 D5 D6 D3 D2 D1 D0 GND 3. FOR YELLOW AND GREEN DISPLAYS ONLY. Pin No. Function Pin No. Function 1 10 CE1 Chip Enable GND 2 CE2 Chip Enable 11 D0 Data Input 3 CLR Cle ar 12 D1 Data Input 4 CUE Cursor Enable 13 D2 Data Input 5 CU Cursor Select 14 D3 Data Input 6 WR Write 15 D6 Data Input 7 A1 Address Input 16 D5 Data Input 8 A0 Address Input 17 D4 Data Input 9 VDD 18 BL Display Blank Character Set D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D4 HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F ASCII CODE D6 D5 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 NOTES: 1 = HIGH LEVEL 0 = LOW LEVEL 3 Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 4.5 5.0 5.5 V Electrical Characteristics over Operating Temperature Range 4.5 < VDD < 5.5 V (unless otherwise specified) All Devices 25C [1] Parameter Symbol IDD Blank IDD (blnk) Input Current II Input Voltage High Input Voltage Low Min. Typ. Max. Max. Units Test Conditions 4.0 mA All Digits Blanked -40 10 A VIN = 0 V to VDD VDD = 5.0 V VIH 2.0 VDD V VIL GND 0.8 V 1.0 HDLO/HDLA/HDLY/HDLG-2416 25C [1] Parameter Symbol IDD 4 digits 20 Dots/Character[2, 3] IDD Cursor All Dots ON @ 50% Min. Typ. Max. Max. Units Test Conditions IDD(#) 110 135 160 mA "#" ON in All Four Locations IDD (CU) 92 110 135 mA Cursor ON in All Four Locations HDLS/HDLU-2416 25C[1] Part Number Parameter Symbol Typ. Max. Max. Units Test Conditions HDLS-2416 IDD 4 digits IDD(#) 125 146 180 mA HDLU-2416 20 dots/character[2,3] 34 42 52 Four "#" ON in All Four Locations HDLS-2416 IDD Cursor all dots 105 124 154 mA HDLU-2416 ON @ 50% 29 36 45 Four Cursors ON in All Four Locations IDD(CU) Notes: 1. VDD = 5.0 V. 2. Average IDD measured at full brightness. Peak IDD = 28/15 x Average IDD(#). 3. IDD(#) max. = 135 mA for HDLO/HDLA/HDLY/HDLG-2416, 146 mA for HDLS-2416, and 42 mA for HDLU-2416 at default brightness, 150C IC junction temperature and VDD = 5.5 V. 4 Optical Characteristics at 25C [1] VDD = 5.0 V at Full Brightness HDLS/HDLU-2416 Part Number Parameter Symbol Min. Typ. Units Test Conditions HDLS-2416 Average Luminous Intensity per IV 4.0 12.7 mcd `'*'' Illuminated in All Four HDLU-2416 Digit, Character Average 1.2 3.1 mcd Digits, 19 Dots ON per Digit All Peak Wavelength OPEAK 645 nm Dominant Wavelength[2] Od 637 nm HDLO-2416 Parameter Symbol Min. Typ. Units Test Conditions Average Luminous Intensity per Digit, Character Average IV 1.2 3.5 mcd `'*'' Illuminated in All Four Digits. 19 Dots ON Peak Wavelength OPEAK 635 nm Dominant Wavelength[2] Od 626 nm HDLA-2416 Parameter Symbol Min. Typ. Units Test Conditions Average Luminous Intensity per Digit, Character Average IV 1.2 3.5 mcd `'*'' Illuminated in All Four Digits. 19 Dots ON Peak Wavelength OPEAK 600 nm Dominant Wavelength[2] Od 602 nm HDLY-2416 Parameter Symbol Min. Typ. Units Test Conditions Average Luminous Intensity per Digit, Character Average IV 1.2 3.7 mcd `'*'' Illuminated in All Four Digits. 19 Dots ON Peak Wavelength OPEAK 583 nm Dominant Wavelength[2] Od 585 nm HDLG-2416 Parameter Symbol Min. Typ. Units Test Conditions Average Luminous Intensity per Digit, Character Average IV 1.2 5.6 mcd `'*'' Illuminated in All Four Digits. 19 Dots ON Peak Wavelength OPEAK 568 nm Dominant Wavelength[2] Od 574 nm Notes: 1. Refers to the initial case temperature of the device immediately prior to the light measurement. 2. Dominant wavelength, Od, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the device. 5 AC Timing Characteristics over Operating Temperature Range at VDD = 4.5 V Parameter Symbol Min Units Address Setup tAS 10 ns Address Hold tAH 40 ns Data Setup tDS 50 ns Data Hold tDH 40 ns Chip Enable Setup tCES 0 ns Chip Enable Hold tCEH 0 ns Write Time tW 75 ns Clear tCLR 10 s Clear Disable tCLRD 1 s Timing Diagram Enlarged Character Font 2.0 V CE1 0.8 V CE2 tCES 3.43 (0.135) 0.80 (0.031) TYP. tCEH 2.0 V A0 - A1, CU 0.8 V tAS 5.08 (0.200) tAH 2.0 V WR 0.8 V 0.25 (0.010) TYP. tW 2.0 V D 0 - D6 0.8 V tDS tCLR tCLRD 2.0 V CLR 6 0.8 V tDH 0.80 (0.031) TYP. NOTES: 1. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON ALL DIMENSIONS IS 0.254 mm (0.010"). 2. DIMENSIONS ARE IN mm (INCHES). Electrical Description Pin Function Description Chip Enable (CE1 and CE1 and CE2 must be a logic 0 to write to the display. CE2, pins 1 and 2) Clear (CLR, pin 3) When CLR is a logic 0 the ASCII RAM is reset to 20hex (space) and the Control Register/Attribute RAM is reset to 00hex. Cursor Enable CUE determines whether the IC displays the ASCII or (CUE pin 4) the Cursor memory. (1 = Cursor, 0 = ASCII). Cursor Select CU determines whether data is stored in the ASCII RAM (CU, pin 5) or the Attribute RAM/Control Register. (1 = ASCII, 0 = Attribute RAM/Control Register). Write (WR, pin 6) WR must be a logic 0 to store data in the display. Address Inputs A0-A1 selects a specific location in the display memory. (A1 and A0, Address 00 accesses the far right display location. Pins 8 and 7) Address 11 accesses the far left location. Data Inputs D0-D6 are used to specify the input data for the (D0-D6, Pins 11-17) display. VDD (pin 9) VDD is the positive power supply input. GND (pin 10) Blanking Input (BL, pin 18) GND is the display ground. BL is used to flash the display, blank the display or to dim the display. Display Internal Block Diagram Figure 1 shows the HDLX-2416 display internal block diagram. The CMOS IC consists of a 4 x 7 Character RAM, a 2 x 4 Attribute RAM, a 5 bit Control Register, a 128 character ASCII decoder and the refresh circuitry necessary to synchronize the decoding and driving of four 5 x 7 dot matrix displays. Four 7 bit ASCII words are stored in the Character RAM. The IC reads the ASCII data and decodes it via the 128 character ASCII decoder. The ASCII decoder includes the 64 character set of the HPDL-2416, 32 lower case ASCII symbols, and 32 foreign language symbols. A 5 bit word is stored in the Control Register. Three fields within the Control Register provide an 8 level brightness control, master blank, and extended functions disable. 7 For each display digit location, two bits are stored in the Attribute RAM. One bit is used to enable a cursor character at each digit location. A second bit is used to individually disable the blanking features at each digit location. The display is blanked and dimmed through an internal blanking input on the row drivers. Logic within the IC allows the user to dim the display either through the BL input or through the brightness control in the control register. Similarly the display can be blanked through the BL input, the Master Blank in the Control Register, or the Digit Blank Disable in the Attribute RAM. CHARACTER RAM A0 - A1 CE1 D0 - D6 2 7 CE2 DATA OUT WRITE ADDRESS CHARACTER/CURSOR MULTIPLEXER ASCII DECODER 7 CHARACTER SELECT COLUMN DATA DATA IN 5 0 CHARACTER/ CURSOR MULTIPLEXER WRITE WR (4 x 7) CU 2 READ ADDRESS 3 ROW SELECT CURSOR CHARACTER 5 1 CLR SELECT CLR ATTRIBUTE RAM CUE D0 DIGIT CURSOR D1 DIGIT BLANK DISABLE A0 - A1 DCn WRITE ADDRESS WRITE 2 (2 x 4) READ ADDRESS CLR CLR CONTROL REGISTER ROW DRIVERS MB EFD MASTER BLANK D2 COLUMN DRIVERS BL ROW SELECT DBDn D3 - D5 3 D6 CE1 BRIGHTNESS LEVELS BLANK EFD EFD EXTENDED FUNCTIONS DISPLAY 1x5 CE2 3 WRITE WR CLR CU CLR 3 DIGITAL DUTY CONTROL 4 (LSBs) OSC + 32 2 (MSBs) Figure 1. Internal block diagram. 8 +7 DISPLAY Display Clear Cursor Data stored in the Character RAM, Control Register, and Attribute RAM will be cleared if the clear (CLR) is held low for a minimum of 10 s. Note that the display will be cleared regardless of the state of the chip enables (CE1, CE2). After the display is cleared, the ASCII code for a space (20hex) is loaded into all character RAM locations and 00hex is loaded into all Attribute RAM/Control Register memory locations. When cursor enable (CUE) is a logic 1, a cursor will be displayed in all digit locations where a logic 1 has been stored in the Digit Cursor memory in the Attribute RAM. The cursor consists of all 35 dots ON at half brightness. A flashing cursor can be displayed by pulsing CUE. When CUE is a logic 0, the ASCII data stored in the Character RAM will be displayed regardless of the Digit Cursor bits. Blanking Data Entry Blanking of the display is controlled through the BL input, the Control Register and Attribute RAM. The user can achieve a variety of functions by using these controls in different combinations, such as full hardware display blank, software blank, blanking of individual characters, and synchronized flashing of individual characters or entire display (by strobing the blank input). All of these blanking modes affect only the output drivers, maintaining the contents and write capability of the internal RAMs and Control Register, so that normal loading of RAMs and Control Register can take place even with the display blanked. Figure 2 shows a truth table for the HDLX-2416 display. Setting the chip enables (CE1, CE2) to logic 0 and the cursor select (CU) to logic 1 will enable ASCII data loading. When cursor select (CU) is set to logic 0, data will be loaded into the Control Register and Attribute RAM. Address inputs A0-A1 are used to select the digit location in the display. Data inputs D0-D6 are used to load information into the display. Data will be latched into the display on the rising edge of the WR signal. D0-D6, A0-A1, CE1, CE2, and CU must be held stable during the write cycle to ensure that correct data is stored into the display. Data can be loaded into the display in any order. Note that when A0 and A1 are logic 0, data is stored in the right most display location. CUE BL CLR 0 1 1 1 1 1 CE1 CE2 WR CU A1 A0 D6 D4 D3 D2 D1 D0 Function Display ASCII Display Stored Cursor X X X X X X X X X X X X X X X 0 Reset RAMs X 0 1 Blank Display but do not reset RAMS and Control Register X X 1 0 0 0 0 0 Extended Functions Disable Intensity Control Master Blank Digit Blank Disable 0 Digit Cursor 0 Write to Attribute RAM and Control Register 0 0 1 0= Enable D1-D5 0= Display ON Digit Blank Disable 1 Digit Cursor 1 DBDn = 0, Allows Digit n to be blanked 0 1= Disable D1-D5 000 = 100%* 001 = 60% 010 = 40% 011 = 27% 100 = 17% 101 = 10% 110 = 7% 111 = 3% 1= Display Blanked Digit Blank Disable 2 Digit Cursor 2 D0 Always Enabled Digiit Blank Disable 3 Digit Cursor 3 0 0 X X X X 1 1 0 0 1 0 1 1 1 0 0 Digit 0 ASCII Data (Right Most Character) 1 0 1 Digit 1 ASCII Data 1 1 0 Digit 2 ASCII Data 1 1 1 Digit 3 ASCII Data (Left Most Character) X X X 0 1 X X X 1 X X X 1 Figure 2. Display truth table. DBDn = 1 Prevents Digit n from being blanked. DCn = 0 Removes cursor from Digit n DCn = 1 Stores cursor at Digit n Write to Character RAM X 0 = Logic 0; 1 = Logic 1; X = Do Not Care; * 000 = 27% for HDLU-2416 9 D5 X X X X X X No Change Figure 3 shows how the Extended Function Disable (bit D6 of the Control Register), Master Blank (bit D2 of the Control Register), Digit Blank Disable (bit D1 of the Attribute RAM), and BL input can be used to blank the display. Dimming Dimming of the display is controlled through either the BL input or the Control Register. A pulse width modulated signal can be applied to the BL input to dim the display. A three bit word in the Control Register generates an internal pulse width modulated signal to dim the display. The internal dimming feature is enabled only if the Extended Function Disable is a logic 0. When the Extended Function Disable is a logic 1, the display can be blanked only with the BL input. When the Extended Function Disable is a logic 0, the display can be blanked through the BL input, the Master Blank, and the Digit Blank Disable. The entire display will be blanked if either the BL input is logic 0 or the Master Blank is logic 1, providing all Digit Blank Disable bits are logic 0. Those digits with Digit Blank Disable bits a logic 1 will ignore both blank signals and remain ON. The Digit Blank Disable bits allow individual characters to be blanked or flashed in synchronization with the BL input. Bits 3-5 in the Control Register provide internal brightness control. These bits are interpreted as a three bit binary code, with code (000) corresponding to the maximum brightness and code (111) to the minimum brightness. In addition to varying the display brightness, bits 3-5 also vary the average value of IDD. IDD can be specified at any brightness level as shown in Table 1. EFD MB DBDn BL 0 0 0 0 Display Blanked by BL 0 0 X 1 Display ON 0 X 1 0 Display Blanked by BL. Individual characters "ON" based on "1" being stored in DBDn 0 1 0 X Display Blanked by MB 0 1 1 1 Display Blanked by MB. Individual characters "ON" based on "1" being stored in DBDn 1 X X 0 Display Blanked by BL 1 X X 1 Display ON Figure 3. Display blanking truth table. Table 1. Current Requirements at Different Brightness Levels Symbol D5 D4 D3 Brightness 25C Typ. 25C Max. Max. over Temp. Units IDD(#) 0 0 0 100% 110 130 160 mA 0 0 1 60% 66 79 98 mA 0 1 0 40% 45 53 66 mA 0 1 1 27% 30 37 46 mA 1 0 0 17% 20 24 31 mA 1 0 1 10% 12 15 20 mA 1 1 0 7% 9 11 15 mA 1 1 1 3% 4 6 9 mA 10 + VDD 1k 4 8 3 7 1k 1N914 555 BL (PIN 18) 10 kHz OUTPUT 6 250 k LOG 2 1 400 pF Figure 4. Intensity modulation control using an astable multivibrator (reprinted with permission from Electronics magazine, Sept. 19, 1974, VNU Business pub. Inc.) Figure 4 shows a circuit designed to dim the display from 98% to 2% by pulse width modulating the BL input. A logarithmic or a linear potentiometer may be used to adjust the display intensity. However, a logarithmic potentiometer matches the response of the human eye and therefore provides better resolution at low intensities. The circuit frequency should be designed to operate at 10 kHz or higher. Lower frequencies may cause the display to flicker. Extended Function Disable Extended Function Disable (bit D6 of the Control Register) disables the extended blanking and dimming functions in the HDLX-2416. If the Extended Function Disable is a logic 1, the internal brightness control, Master Blank, and Digit Blank Disable bits are ignored. However the BL input and Cursor control are still active. This allows downward compatibility to the HPDL-2416. Mechanical and Electrical Considerations The HDLX-2416 is an 18 pin DIP package that can be stacked horizontally and vertically to create arrays of any size. The HDLX-2416 is designed to operate continuously from -40C to +85C for all possible input conditions. The HDLX-2416 is assembled by die attaching and wire bonding 140 LEDs and a CMOS IC to a high temperature printed circuit board. A polycarbonate lens is placed over the PC board creating an air gap environment for the LED wire bonds. Backfill epoxy environmentally seals the display package. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering. The inputs to the CMOS IC are protected against static discharge and input current latchup. However, for best results standard CMOS handling precautions should be used. Prior to use, the HDLX-2416 should be stored in anti-static tubes or conductive material. During assembly a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static charge build-up. Input current latchup is caused when the CMOS inputs are subjected either to a voltage below ground (Vin < ground) or to a voltage higher than VDD (Vin > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display. Transient input voltages should be eliminated. Soldering and Post Solder Cleaning Instructions for the HDLX-2416 The HDLX-2416 may be hand soldered or wave soldered with SN63 solder. When hand soldering it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245C 5C (473F 9F), and dwell in the wave should be set between 1 1/2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 110C (230F) as measured on the solder side of the PC board. For further information on soldering and post solder cleaning, see Application Note 1027, Soldering LED Components. Contrast Enhancement The objective of contrast enhancement is to provide good readability in the end user's ambient lighting conditions. The concept is to employ both luminance and chrominance contrast techniques. These enhance readability by having the OFF-dots blend into the display background and the ON-dots vividly stand out against the same background. For additional information on contrast enhancement, see Application Note 1015. Intensity Bin Limits for HDLS-2416 Bin Intensity Range (mcd) Min. Max. E 3.97 F 5.55 G Intensity Bin Limits for HDLX-2416 Color Bin Limits Bin Intensity Range (mcd) Min. Max. Color 6.79 A 1.20 1.77 Yellow 3 581.5 585.0 9.50 B 1.25 2.47 4 584.0 587.5 7.78 13.30 C 2.02 3.46 5 586.5 590.0 H 10.88 18.62 D 2.83 4.85 6 589.0 592.5 I 15.24 26.07 E 3.97 6.79 1 576.0 580.0 J 21.33 36.49 F 5.55 9.50 2 573.0 577.0 G 7.78 13.30 3 570.0 574.0 4 567.0 571.5 Green Note: Test conditions as specified in Optical Characteristic table. Bin Color Range (nm) Min. Max. Note: Test conditions as specified in Optical Characteristic table. For product information and a complete list of distributors, please go to our website: Note: Test conditions as specified in Optical Characteristic table. www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright (c) 2005-2009 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3190EN AV02-0662EN - December 22, 2009