CYF0018V
CYF0036V
CYF0072V
18/36/72-Mbit Programmable FIFOs
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-53687 Rev. *N Revised July 26, 2013
18/36/72-Mbit Progr a mma ble FIFO s
Features
■Memory organization
❐Industry’s largest first in first out (FIFO) memory densities:
18-Mbit, 36-Mbit, and 72-Mbit
❐Selectable memory organization: × 9, × 12, × 16, × 18, × 20,
× 24, × 32, × 36
■Up to 133-MHz clock operation
■Unidirectional operation
■Independent read and write ports
❐Supports simultaneous read and write operations
❐Reads and writes operate on independent clocks, upto a
maximum ratio of two, enabling data buffering across clock
domains.
❐Supports multiple I/O voltage standard: low voltage
complementary metal oxide semiconductor (LVCMOS) 3.3 V
and 1.8 V voltage standards.
■Input and output enable control for write mask and read skip
operations
■Mark and retransmit: resets read pointer to user marked
position
■Empty, full, half-full, and programmable almost-empty and
almost-full status flags with configured offsets
■Flow-through mailbox register to send data from input to output
port, bypassing the FIFO seque nce
■Configure programmable fl ags and registers throug h serial or
parallel modes
■Separate serial clock (SCLK) input for serial programming
■Master reset to clear entire FIFO
■Partial reset to clear data but retain programmable settings
■Joint test action group (JT AG) port provided for boundary scan
function
■Industrial temperature range: –40 °C to +85 °C
Functional Description
The Cypress programmable FIFO family offers the industry’s
highest-density programmable FIFO memory device. It has
independent read and write ports, which can be clocked up to
133 MHz. User can configure input and output bus sizes. The
maximum bus size of 36 bits enables a maximum data
throughput of 4.8 Gbps. The user-programmable registers
enable user to configure the device operation as desired. The
device also offers a simple and e asy-to-use interface to re duce
implementation and debugging efforts, improve time-to-market,
and reduce engineering costs. This makes it an ideal memory
choice for a wide range of applications including multiprocessor
interfaces, video and image processing, networking and
telecommunications, high-speed data acquisition, or any system
that needs buffering at high speeds across different clock
domains.
As implied by the name, the functionality of the FIFO is such that
the data is read out of the read port in the same sequence in
which it was written into the write port. If writes and inputs are
enabled (WEN & IE), data on the write port gets written into the
device at the rising edge of write clock. Enabling reads and
outputs (REN & OE) fetches data on the read port at every rising
edge of read clock. Both reads and writes can occur
simultaneously at different speeds provided the ratio between
read and write clock is in the range of 0.5 to 2. Appropriate flags
are set whenever the FIFO is empty, almost-empty, half-full,
almost-full or full.
The device also supports mark and retransmit of data, and a
flow-through mailbox register.
All product features and specs are common to all densities
(CYF0072V, CYF0036V, and CYF0018V). All descriptions are
given assuming the 72Mbit (CYF0072V) device is operated in
× 36 mode. They are valid for other densities (CYF 0036V, and
CYF0018V) and all port sizes × 9, × 12, × 16, × 18, × 20, × 24
and × 32 unless otherwise specif ied. T he only difference will be
in the input and output bus width. Table 1 on page 7 shows the
part of bus with valid data from D[35:0] and Q[35:0] in × 9, × 12,
× 16, × 18, × 20, × 24, × 32 and × 36 modes.
Errata: For information on silicon errata, see Errata on p age 31. Details include trigger conditions, devices affected and proposed workaround.
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 2 of 35
Logic Block Diagram
WRITE POINTER
WRITE
CONTROL LOGIC
RESET POINTER
JTAG CONTROL
Memory Array
18 Mbit
36 Mbit
72 Mbit
OUTPUT
REGISTER
INPUT
REGISTER CONFIGURATION
REGISTERS/MAILBOX
FLAG LOGIC
READ POINTER
READ CONTROL
LOGIC
MEMORY LOGIC
ORGANIZATION
PORTSZ[2:0]
Q[35:0]
OE
RCLK
REN
MARK, RT
HF
DVal
PAE
EF
PAF
FF
MB
SPI_SI
LD SPI_SEN SPI_SCLK
D[35:0]
IE WEN WCLK
MRS
PRS
TCK
TRST
TMS
TDO
TDI
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 3 of 35
Contents
Pin Diagram for CYF0XXXVXXL [1] .................................4
Pin Definitions ..................................................................5
Architecture ......................................................................7
Reset Logic ................................................ .................7
Selecting Word Sizes ..................................................7
Memory Organization for Different Port Sizes .............7
Data Valid Signal (DVal) ..............................................8
Write Mask and Read Skip Operation .........................8
Flow-through Mailbox Register ....................................8
Flag Operation ........................ ... ............................ ......8
Retransmit from Mark Operation .................................9
Programming Flag Offsets and
Configuration Registers ......................................................9
Width Expansion Configuration .................................13
Power Up ............ ... ....................................................13
Read/Write Clock Requirements ...............................13
JTAG Operation ........................................................14
Maximum Ratings ...........................................................15
Operating Range ..................... .. ............................ ..........15
Recommended DC Operating Conditions ....................15
Electrical Characteristics ...............................................15
I/O Characteristics ..........................................................16
Latency Table ..................................................................16
Switching Characteris tics ..............................................18
Switching Waveforms ....................................................19
Ordering Information ......................................................28
Ordering Code Definitions .........................................28
Package Diagram ............................................................29
Acronyms ........................................................................ 30
Document Conventions ..................... ... .........................30
Units of Measure ..... .. ... ............................ ... ..............30
Errata ............................................................................... 31
Part Numbers Affected ..............................................31
18-Mbit, 36-Mbit, and
72-Mbit Programmable FIFO Qualification Status ............31
18-Mbit, 36-Mbit, and
72-Mbit Programmable FIFO Errata Summary .................31
Document History Page ......................................... ........32
Sales, Solutions, and Legal Information ......................35
Worldwide Sales and Design Support .......................35
Products .................................................................... 35
PSoC® Solutions ......................................................35
Cypress Developer Community ...................... ... ........35
Technical Support .....................................................35
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 4 of 35
Pin Diagram for CYF0XXXVXXL [1]
Figure 1. 209-ball FBGA pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11
AFF D0 D1 DNU PORTSZ0 PORTSZ1 DNU DNU RT Q0 Q1
BEF D2 D3 DNU DNU PORTSZ2 DNU DNU REN Q2 Q3
CD4 D5 WEN DNU VCC1 DNU VCC1 DNU RCLK Q4 Q5
DD6 D7 V
SS VCC1 DNU LD DNU VCC1 Vss Q6 Q7
ED8 D9 V
CC2 VCC2 VCCIO VCCIO VCCIO VCC2 VCC2 Q8 Q9
FD10 D11 V
SS VSS VSS DNU VSS VSS VSS Q10 Q11
GD12 D13 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q12 Q13
HD14 D15 V
SS VSS VSS VCC1 VSS VSS VSS Q14 Q15
JD16 D17 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q16 Q17
K DNU DNU WCLK DNU VSS IE VSS DNU VCCIO VCCIO VCCIO
LD18 D19 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q18 Q19
MD20 D21 V
SS VSS VSS VCC1 VSS VSS VSS Q20 Q21
ND22 D23 V
CC2 VCC2 VCCIO VCC1 VCCIO VCC2 VCC2 Q22 Q23
PD24 D25 V
SS VSS VSS SPI_SEN VSS VSS VSS Q24 Q25
RD26 D27 V
CC2 VCC2 VCCIO VCCIO VCCIO VCC2 VCC2 Q26 Q27
TD28 D29 V
SS VCC1 VCC1 SPI_SI VCC1 VCC1 VSS Q28 Q29
UDVal DNU D30 D31 PRS DNU [2] SPI_SCLK VREF OE Q30 Q31
VPAF PAE D32 D33 DNU MRS MB DNU MARK Q32 Q33
W TDO HF D34 D35 TDI TRST TMS TCK DNU Q34 Q35
Notes
1. Pin Diagram for 18-Mbit, 36-Mbit & 72-Mbit; 1.8V & 3.3V IO voltage options.
2. This pin should be tied to VSS pre ferably or can be left floating to ensure normal operatio n.
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 5 of 35
Pin Definitions
Pin Name I/O Pin Description
MRS Input Master reset: MRS initializes the internal read an d write pointers to zero, resets all flags and sets the
output register to all zeroes. Duri ng Master Reset, the configuration registers are set to default values.
PRS Input Partial reset: PRS initializes the internal read and write pointers to zero, resets all flags and sets the
output register to all zeroes. Duri ng Partial Reset, the configuration register settings are retained.
PORTSZ [2:0] Input Port word size select: Port word width select pins (common for read and write ports).
WCLK Input Write clock: The rising edge clocks data into the FIFO when writes are enabled (WEN asserted). Data
is written into the FIFO memory when LD is high and into configuration registers when LD is low.
LD Input Load: When LD is LOW, D[7:0] (Q[7:0]) are written (read) into (from) the configur ation registers. Whe n
LD is HIGH, D[35:0] (Q[35:0]) are written (read) into (from) the FIFO memory.
WEN Input Write enable: Control signal to enable writes to the device. When WEN is low data present on the inputs
is written to the FIFO memory or configuration registers on every rising edge of WCLK.
IE Input Input enable: IE is the data input enable signal that controls the enabling and disabling of the 36-bit data
input pins. If it is enabled, data on the D[35:0] pins is written into the FIF O. The internal write ad dress
pointer is always incremented at rising edge of WCLK if WEN is enabled, regardless of the IE level. This
is used for 'write masking' or incrementing the write pointer without writing into a location.
D[35:0] Input Data inputs: Data inputs for a 36-bit bus.
RCLK Input Read clock: The rising edge initiates a read from the FIFO when reads are enabled (REN asserted).
Data is read from the FIFO memory when LD is high & from the configuration registers if LD is low.
REN Input Read enable: Control si gnal to enable reads from the device . When REN is low data is read from the
FIFO memory or configuration registers on every rising edge of RCLK.
OE Input Output enable: When OE is LOW , FIFO data outputs are enabled; when OE is HIGH, the FIFO’s outputs
are in High Z (high impedance) state.
Q[35:0] Output Data outputs: Data outputs for a 36-bit bus.
DVal Output Data valid: Active low data valid signal to indicate valid data on Q[35:0].
MARK Input Mark for retransmit: When this pin is asserted the memory l ocation corresponding to the data present
on the output bus is marked. Any subsequent retransmit operation resets the read pointer to this location.
RT Input Retransmit: A HIGH pulse on R T resets the internal read pointer to a physical location of the FIFO which
is marked by the user (using MARK pin). With every valid read cycle after retransmit, previously accessed
data is read until the FIFO is empty.
MB Input Mailbox: When asserted the reads and writes happen to flow-through mailbox register.
EF Output Empty flag: When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
PAE Output Programmable almost-empty: When P AE is LOW , the FIFO is almost empty based on the almost-empty
offset value programmed into the FIFO. It is synchronized to RCLK.
HF Output Hal f-full flag: When HF is LOW, half of the FIFO is full. HF is synchronized to WCLK.
PAF Output Programmable almost-full: When PAF is LOW, the FIFO is almost full based on the almost-full offset
value programmed into the FIFO. It is synchroni zed to WCLK.
FF Output Full flag: When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
SPI_SCLK Input Serial clock: A rising edge on SPI_SCLK clocks the serial data present on the SPI_SI input into the offset
registers if SPI_SEN is enabled.
SPI_SI Input Serial input: Serial input data in SPI mode.
SPI_SEN Input S erial enable: Enables serial loading of programmable flag offsets and configuration registers.
TCK Input Test clock (TCK) pin for JTAG.
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 6 of 35
TRST Input Reset pin for JTAG.
TMS Input Test mode select (TMS) pin for JTAG.
TDI Input Test data in (TDI) pin for JTAG.
TDO Output Test data out (TDO) pin for JTAG.
VREF Input
Reference Reference voltage: Reference voltage (regardless of I/O standard used)
VCC1 Power
Supply Core voltage supply 1: 1.8 V supply voltage
VCC2 Power
Supply Core voltage supply 2: 1.5 V supply voltage
VCCIO Power
Supply Supply for I/Os
VSS Ground Ground
DNU – Do not use: These pins need to be left floating.
Pin Definitions (continued)
Pin Name I/O Pin Description
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 7 of 35
Architecture
The CYF0072V, CYF0036V, and CYF0018V are memory arrays
of 72-Mbit, 36-Mbit, and 18-Mbit respectively. The memory
organization is user configurable and word sizes can be selected
as × 9, × 12, × 16, × 18, × 20, × 24, × 32, or × 36. The logic blocks
to implement the FIFO functionality and the associated features
are built around these memory arrays.
The input and output data buses have a maximum width of
36 bits. The input data bus goes to an input register and the data
flow from the input register to the memory is controlled by the
write control logic. The inputs to the write logic block are WCLK,
WEN and IE. When the write s are enabled through W EN and if
the inputs are enabled by IE, then the data on the input bus is
written into the memory a rray at the rising edge of WCL K. This
also increments the write pointer. Enabling writes but disabling
the data input pins through IE only increments the write pointer
without doing a ny writes or altering th e contents of the memory
location.
Similarly, the output register is connected to the data output bus.
Transfer of contents from the memory to the output register is
controlled by the read control logic. The inputs to the read control
logic include RCLK, REN, OE, RT and MARK. When reads are
enabled by REN and outputs are enabled using OE, the data
from the memory pointed by the read pointer is transferred to the
output data bus at the rising edge of RCLK along with active low
DVal. If the outputs are disabled but the reads enabled, the
outputs are in high impedance state, but internally the read
pointer is incremented.
During write operation, the number of writes performed is always
an even number (i.e., minimum write burst length is two and
number of writes always a multiple of two). Whereas during read
operation, the number of reads performed can be even or odd
(i.e., minimum read burst length is one).
The MARK signal is us ed to ‘mark’ the location from which data
is retransmitted when requested and RT is asserted to retransmit
the data from the marked location.
Reset Logic
The FIFO can be reset in two ways: Master Reset (MRS) and
Partial Reset (PRS). The MRS initializes the read and write
pointers to zero and sets the output register to all zeroes. It also
resets all flags & the configuration registers to their default
values. The word size is configured th rough pins; values of the
three PORTSZ pins are latched during MRS. A Master Reset is
required after power-up before accessing the FIFO.
PRS resets the read pointer, write pointer and mark location to
the first physical location in the memory array. It also resets all
flags to their default values. PRS does not affect the
programmed configuration register values. Any changes to
configuration registers during device operation mandates a PRS
cycle to guarantee accurate flag operation.
Selecting Word Sizes
The word sizes are configured ba sed on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of op eration and these pins are ignored. Table 1.
explains the pins of D[35:0] and Q[35:0] that will have valid data
in modes where the word size is less than × 36. If word size is
less than × 36, the unused output pins are tri-stated by the device
and unused input p ins will be ignored by the internal logic. The
pins with valid data input D[N:0] and output Q[N:0] is given in
Table 1.
Memory Organization for Different Port Sizes
The 72-Mbit memory has different organization for different port
sizes. Table 1 shows the depth of the FIFO for all port sizes.
Note that for all port sizes, four to eight locations are not available
for writing the data and are used to safeguard against false
synchronization of empty and full flags.
Table 1. Word Size Selection
PORTSZ[2:0] Word Siz e FIFO Depth [3] Memory Size [3] Active Input Data Pins D[N:0] Active Output Data Pins Q[N:0]
000 × 9 8 Meg 72-Mbit D[8:0] Q[8:0]
001 × 12 4 Meg 48-Mbit D[11:0] Q[11:0]
010 × 16 4 Meg 64-Mbit D[15:0 ] Q[15:0]
011 × 18 4 Meg 72-Mbit D[17:0] Q[17:0]
100 × 20 2 Meg 40-Mbit D[19:0 ] Q[19:0]
101 × 24 2 Meg 48-Mbit D[23:0 ] Q[23:0]
110 × 32 2 Meg 64-Mbit D[31 :0] Q[31:0]
111 × 36 2 Meg 72-Mbit D[35:0] Q[35:0]
Note
3. For all port sizes, four to eight locations are not available for writing the data.
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 8 of 35
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal , synchronized to RCLK
and is provided to check for valid data on the output bus. When
a read operation is performed, the DVal signal goes low along
with output data. This helps user to capture the data without
keeping track of REN to data output latency. This signal also
helps when write and read operations are performed
continuously at different frequencies by indicating when valid
data is availabl e at the output port Q[35:0].
Write Mask and Read Skip Operation
As mentioned in Architecture on page 7, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
This feature is called Write Mask and allows user to move the
write pointer w ithout actually writ ing to the locations. This “write
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
Similarly, du ri ng a rea d o peratio n, if the outputs are disable d by
keeping the OE high, the read data does not appear on the
output bus; however, the read pointer is incremented. This
feature is referred to as a Read Skip Operation.
Flow-through Mailbox Register
This feature transfers data from input to output directly bypassing
the FIFO sequence. When MB signal is asserted the data
present in D[35:0] will be available at Q[35:0] after two WCLK
cycles. Normal read and write operations are not allowed during
flow-through mailbox operation. Before starting Flow-through
mailbox operation FIFO read should be completed to make data
valid DVal high in order to avoid data loss from FIFO. The width
of flow-through mailbox register always corresponds to port size.
Flag Operation
This device provides five flag pins to indicate the condition of the
FIFO.
Full Flag
The Full Flag (FF) operates on double word (burst length of two)
boundaries and goes LOW when the device is full. Write
operations are inhibited whene ver FF i s LOW regardless o f the
state of WEN. FF is synchronized to WCLK, that is, it is
exclusively updated by each rising edge of WCLK. The worst
case assertion latency for Full Flag is four. As the user cannot
know that the FIFO is full for four clock cycles, it is possible that
user continues writing data during this time. In this case, the four
data words written will be stored to prevent data loss and these
words have to be read back in order for full flag to get
de-asserted. The minimum number of reads required to
de-assert full-flag is two and the maximum number of reads
required to de-assert full flag is six. The assertion and
de-assertion of Full flag with associated latencies is explained in
Latency Table on page 14.
Half-Full Flag
The Half-Full (HF) flag goes LOW when half of the memory array
is written. HF is synchronized to WCLK. The assertion and
de-assertion of Half-Full flag with associated latencies is
explained in Latency Table on page 16.
Empty Flag
The Empty Flag (EF) deassertion depe nds on burst writes and
goes LOW when the device is empty. Read operations are
inhibited whenever EF is LOW, regardless of the state of REN.
EF is synchronized to RCLK, that is, it is exclusively updated by
each rising edge of RCLK. The assertion and de-assertion of
Empty flag with associated latencies is explained in Latency
Table on page 16.
Programmable Almost-Empty and Almost-Full Flags
The CYF0072V includes programmable Almost-Empty and
Almost-Full flags. Each flag operates on word boundaries and is
programmed (see Programming Flag Offsets and Configuration
Registers on page 9) a specific distance from the corresponding
boundary flags (Empty or Full). (offset can range from 16 to
1023) When the FIFO contains the number of words for which
the flags are programmed, the P AF or P AE is asserted, signifying
that the FIFO is either almost-full or almost-empty. The default
flag offset for both PAE and PAF is 12 7 words. These pro gram-
mable flag boundaries have thresholds associated with them.
Table 2 give s the assertion and de-assertion conditi ons fo r PA E
& PAF flags based on thes e thresholds assuming default offset
values.
The PAF flag signal transition is caused by the rising edge of
WCLK and the PAE flag transition is caused by the rising edge
of RCLK. The assertion and de-assertion of these flags with
associated latencies is explained in Latency Table on page 16.
Table 2. Programmable Flag Assertion/De-assertion Thresholds
Operation PAE offset Numb e r of FIF O wo rds - PAE PAF offset Number of FIFO words - PAF
Assertion 127 # FIFO words <= (PAE offset + 2)
i.e. # FIFO words <= 129 127 # FIFO words >= FIFO depth - (offset + 1)
i.e. # FIFO words >= 2M - 128
Deassertion 127 # FIFO words > (of f set)
i.e. # FIFO words > 127 127 # FIFO words < FIFO depth - (offset)
i.e. # FIFO words < 2M - 127
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 9 of 35
Retransmit from Mark Operation
The retransmit feature is useful fo r transferring packets of data
repeatedly. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. Initiation of a
retransmit operation (using RT pin) resets the internal read
pointer to a physical l ocation of the FIFO that is marked by the
user (using the MARK pin). With every valid read cycle after
retransmit, data is read out starting from the marked location and
the read pointer is incremented until the FIFO is empty. Data
written to FIFO after initiation of a retransmit operation are also
transmitted. The full depth of the FIFO can be repeatedly
retransmitted.
Flags are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Refer to the
latency table for the associated flag update latencies after
initiation of a retransmit cycle [4].
Asserting RT initiates a retransmit operation. The retransmit
feature can be used when two or more data words have been
written to the FIFO. When the MARK pin is asserted, the memory
location corresponding to the d ata present on the output bus is
marked. A mark operation is mandated prior to initiating a
Retransmit operation.
A retransmit operation should not be initiated when reads or
writes are in progress. User should wait for four RCLK cycles
after disabling reads before RT is asserted to ensure that the
reads are completed.
On initiation of RT the ‘marked’ location becomes the new Full
Boundary. If user con tinues to write the data after initiation of a
retransmit operation, FF will be asserted wh en this boundary is
reached i.e. FF is asserted once the write pointer reaches the
marked location.This prevents overwriting and data-loss. During
RT reads the full boundary remains frozen to the marked location
and is released when the FIFO becomes empty. i.e. FF remains
LOW until the entire FIFO is read. Full flag is released
LFF_RELEASE clocks after the EF is asserted. Full boundary is
also released on a reset operation (MRS or PRS) [4].
Refer to Latency Table on page 16 for more details.
Programming Flag Offs ets and Configuration
Registers
The CYF0072V has ten 8-bit user configurable registers. These
registers contain the almost-full (M) and almost-empty (N) offset
values which decide when the PAF and PAE flags are asserted.
These registers can be programmed in one of two ways: serial
loading or parallel loading method. The loading method is
selected using the SPI_SEN (Serial Enable) pin. A low on the
SPI_SEN selects the serial method for writing into the registers.
For serial programming, there i s a separate SCLK and a Serial
Input (SI). In parallel mode, a LOW on the load (LD ) pin causes
the write and read operation to these registers. The write and
read operation happens from the first location (0x1) to the last
location (0xA) in a seq uence. If LD is HIGH , the w rites occur to
the FIFO.
Register values can be read through the parallel output port
regardless of the programming mode selected (serial or parallel).
Register values cannot be read serially. The registers may be
programmed (and reprogrammed) any time after master reset,
regardless of whether serial or parallel programming is selected.
Any changes to configurati on registers during device operation
mandates a PRS cycle to guarantee accurate flag operation.
See Table 4 on page 11 and Table 5 on page 12 for access to
configuration registers in serial and parallel modes.
In parallel mode, the read an d write operations loop back when
the maximum address location of the configuration registers is
reached. Simultaneous read and write operations should be
avoided on the configuration registers. Any change in
configuration registers will take effect after eight write clock
cycles (WCLK) cycles.
Note
4. Errata: Refer to Errata on page 31 for details on flag operation and full bound ary freezing during Mark and Retransmit operation.
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 10 of 35
Table 3. Configuration Registers
ADDR Configuration Register Default Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]
0x1 Reserved 0x00 X X X X X X X X
0x2 Reserved 0x00 X X X X X X X X
0x3 Reserved 0x00 X X X X X X X X
0x4 Almost-Empty Flag generation
address - (LSB) (N) 0x7F D7 D6 D5 D4 D3 D2 D1 D0
0x5 Almost-Empty Flag generation
address - (MSB) (N) 0x00 X X X X X X D9 D8
0x6 Reserved 0x00 X X X X X X X X
0x7 Almost-Full Flag generation
address - (LSB) (M) 0x7F D7 D6 D5 D4 D3 D2 D1 D0
0x8 Almost-Full Flag generation
address - (MSB) (M) 0x00 X X X X X X D9 D8
0x9 Reserved 0x00 X X X X X X X X
0xA Fast CLK Bit Register 1XXXXXXXb Fast CLK
bit XX X X X X X
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 11 of 35
Table 4. Writing and Reading Configuration Registers in Parallel Mode
SPI_SEN LD WEN REN WCLK RCLK SPI_SCLK Operation
1001 First rising edge
because both LD and
WEN are low
X X Parallel write to first register
1001 Second rising edge X X Parallel write to second register
1001 Third rising edge X X Parallel write to third register
1001 Fourth rising edge X X Parallel write to fourth register
1001 XX
1001 XX
1001 XX
1001 Tenth rising edge X X Parallel write to tenth register
1001 Eleventh rising edge X X Paral lel write to first register
(roll back)
1010 X First rising edge since
both LD and REN are
low
X Parallel read from first register
1010 X Second rising edge X Parallel read from second
register
1010 X Third rising edge X Parallel read from third register
1010 X Fourth rising edge X Parallel read from fourth
register
1010 X X
1010 X X
1010 X X
1010 X Tenth rising edge X Parallel read from tenth
register
1010 X Eleventh rising edge X Parallel read from first register
(roll back)
1 X 1 1 X X X No operation
X10X Rising edge X X Write to FIFO memory
X1X0 X Rising edge X Read from FIFO memory
0 0 X 1 X X X Illegal operation
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Document Number: 001-53687 Rev. *N Page 12 of 35
Table 5. Writing into Configuration Registers in Serial Mode
SPI_SEN LD WEN REN WCLK RCLK SCLK Operation
01XX X X Rising edge Each rising of the SCLK clocks
in one bit from the SI (Serial
In). Any of the 10 registers can
be addressed and written to,
followin g th e SPI protocol .
X10X Rising edge X X Parallel write to FIFO memory .
X1X0 X Rising edge X Parallel read from FIFO
memory.
1 0 1 1 X X X This corresponds to parallel
mode (refer to T able 4 on page
11).
Figure 2. Serial WR ITE to Configuration Register
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 13 of 35
Width Expansion Configuration
The width of CYFX072V can be expanded to provide word widths greater than 36 bits. During width expansion mode, all control line
inputs are common and all flags are available. Empty (Full) flags are created by ANDing the Empty (Full) flags of every FIFO; the PAE
and PAF flags can be detected from any one device. This technique avoids reading data from or writing data to the FIFO that is
“staggered” by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 3 demonstrates an example of
72 bit-word width by using two 36-bit word CYFX072Vs.
Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and
VREF attain minimum stable voltage required as given in
Recommended DC Operating Conditions on page 15. The
device can be accessed tPU time after these supplies attain the
minimum required level (see Switch ing Characteristics on page
18). There is no specific power sequencing required for the
device.
Read/Write Clock Requirements
The read and write clocks must satisfy the following
requirements:
■Both read (RCLK) and write (WCLK) clocks should be
free-running.
■The clock frequency for both clocks should be between the
minimum and maximum range given in Electrical
Characteristics on page 15.
■The WCLK to RCLK ratio should be in the range of 0.5 to 2.
For proper FIFO operation, the device must determine which of
the input clocks – RCLK or WCLK – is faster. T his is evaluated
using counters after the MRS cycle. The device uses two 9-bit
counters (one running on RCLK and other on WCLK), which
count 256 cycles of read and write clocks after MRS. The clock
of the counter which reaches its terminal count first is used as
master clock inside the FIFO.
When there is change in the relative frequency of RCLK and
WCLK during normal operation of FIFO, user can specify it by
using “Fast CLK bit” in the configuration register (0xA).
“1” - indicates freq (WCLK) > freq (RCLK)
“0” - indicates freq (WCLK) < freq (RCLK)
The result of counter evaluated frequency is available in this
register bit. User can override the counter evaluated frequency
for faster clock by changing this bit.
Whenever there is a change in this bit value, user must wait tPLL
time before issuing the next read or write to FIFO.
Figure 3. Using Two CYFX072V for Width Expansion
FF
FF EF EF
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
PAE
HF
FF
CYFX072V CYFX072V
3672
DATAIN (D) 36 READCLOCK(RCLK)
READENABLE(REN)
OUTPUTENABLE(OE)
36
DATAOUT(Q)
36 72
PAF
EF
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CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 14 of 35
JTAG Operation
CYFX072V has two devices connected internally in a JTAG chain as shown in Figure 4
Figure 4. Device Connection in a JTAG Chain
Table 6 shows the IR register length and device ID
device1
TDI TDO
device2
TDI TDO
TMS
TCK
TMS
TCK
TMS
TCK
TDI
TDO
TRST
TRST
Table 6. JTAG IDCODES
IR Register Length Device ID (HEX) Bypass Register Length
Device-1 3 “Ignore” 1
Device-2 8 1E3261CF 1
Table 7. JTAG Instructions for Device-1
Device-1 Opcode (Binary)
BYPASS 111
Table 8. JTAG Instructions for Device-2
Device-2 Opcode (HEX)
EXTEST 00
HIGHZ 07
SAMPLE/PRELOAD 01
BYPASS FF
IDCODE 0F
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Document Number: 001-53687 Rev. *N Page 15 of 35
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature (without bias) ........ –65 C to +150 C
Ambient temperature with
power applied .........................................–55 C to +125 C
Core supply vol tage 1 (VCC1) to
ground potential .............................................–0.3 V to 2.5 V
Core supply vol tage 2 (VCC2) to
ground potential .................. ... ... ...................–0.3 V to 1.65 V
Latch up curre nt ................................................ >100 mA
I/O port supply voltage (VCCIO) ......................–0.3 V to 3.7 V
Voltage applied to I/O pins ...........................–0.3 V to 3.75 V
Output current into outputs (L OW) .............................24 mA
Static discharge voltage
(per MIL–STD–883, Method 3015) .........................> 2001 V
Operating Range
Range Ambient Temperature
Industrial –40 C to +85 C
Recommended DC Operating Conditions
Parameter [5] Description Min Typ Max Unit
VCC1 Core supply voltage 1 1.70 1.80 1.90 V
VCC2 Core supply voltage 2 1.425 1.5 1.575 V
VREF Reference voltage (irrespective of I/O standard used) 0.7 0.75 0.8 V
VCCIO I/O supply voltage, read and write banks. LVCMOS33 3.00 3.30 3.60 V
LVCMOS18 1.70 1.8 1.90 V
Electrical Characteristics
Parameter Description Conditions Min Typ Max Unit
ICC Active current VCC1 = VCC1MAX ––300mA
VCC2 = VCC2MAX
(All I/O switching, 133 MHz) ––600mA
VCCIO = VCCIOMAX
(All outputs disabled) ––100mA
IIInput pin leakage current VIN = VCCIOmax to 0 V –15 – 15 µA
IOZ I/O pin leakag e cu rre nt VO = VCCIOmax to 0 V –15 – 15 µA
CPCapacitance for TMS and TCK – – – 16 pF
CPIO Capacitance for all other pins
except TMS and TCK – ––8pF
Note
5. Device operation guaranteed for a supply rate > 1 V / µs.
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Document Number: 001-53687 Rev. *N Page 16 of 35
I/O Characteristics
(Over the operating range)
I/O standard Nominal
I/O supply
voltage
Input Voltage (V) Output voltage (V) Output Current (mA)
VIL(max) VIH(min) VOL(max) VOH(min) IOL(max) IOH(max)
LVCMOS33 3.3 V 0.80 2.20 0.45 2.40 24 24
LVCMOS18 1.8 V 30 % VCCIO 65% VCCIO 0.45 VCCIO – 0.45 16 16
Latency Table
Latency Parameter Number of cycles Detail
LFF_ASSERT Max = 4 Last data write to FF going low.
LEF_ASSERT 0 Last data read to EF going low.
LPRS_TO_ACTIVE 32 [6] PRS deassert to normal operation.
LMAILBOX 2 Latency from write port to read port when MB = 1 (wrt WCLK).
LREN_TO_DATA 4 Latency when REN is asserted low to first data output from FIFO.
LREN_TO_CONFIG 4 Latency when REN is asserted along with LD to first data read from configuration
registers.
LWEN_TO_PAE_HI 5 [6] Write to PAE goi ng high.
LWEN_TO_PAF_LO 5 [6] Write to PAF going low.
LREN_TO_PAE_LO 7 [6] R ead to PAE going low.
LREN_TO_PAF_HI 7 [6] Read to PAF goin g high.
LFF_DEASSERT 8 [6] Read to FF going high.
LRT_TO_REN 17 First RCLK posedge after RT goes low to initiation of reads by pulling REN low . Flags
update within th is period after initiation of a retransmit operation.
LRT_TO_DATA Max = 21 [6] First RCLK posedge after RT goes LOW to valid data on Q[35:0].
LIN Max = 26 [6] Initial latency for data read after FIFO goes empty during simultaneous read/write.
LEF_DEASSERT Max = 24 [6] Write to EF going high.
LFF_RELEASE [7] Max = 6 EF going low to FF deassert during retransmit reads.
Note
6. These latency values are valid for a clock ratio of 1.
7. Errata: Refer to Errata on page 31 for details on flag operation and full bound ary freezing during Mark and Retransmit operation.
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Document Number: 001-53687 Rev. *N Page 17 of 35
Figure 5. AC Test Load Conditions
(a) VCCIO = 1.8 Volt
(b) VCCIO = 3.3 Volt
(c) All Input Pulses
30
0.9 V
30
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Document Number: 001-53687 Rev. *N Page 18 of 35
Switching Characteristics
Parameter Description -133 Unit
Min Max
tPU Power-up time after all supplies reach minimum value – 2 ms
tSClock cycle frequency 3.3 V LVCMOS 24 133 MHz
tSClock cycle frequency 1.8 V LVCMOS 24 133 MHz
tAData access time –10 ns
tCLK Clock cycle time 7.5 41.67 ns
tCLKH Clock high time 3.375 –ns
tCLKL Clock low time 3.375 –ns
tDS Data setup time 3 – ns
tDH Data hold time 3 – ns
tENS Enable setup time 3 – ns
tENH Enable hold time 3 – ns
tENS_SI Setup time for SPI_SI and SPI_SEN pins 5 – ns
tENH_SI Hold time for SPI_SI and SPI_SEN pins 5 – ns
tRATE_SPI Freq uency of SCLK –25 MHz
tRS Reset pulse width 100 –ns
tPZS Port size select to MRS seup time 25 –ns
tPZH MRS to port size select hold time 25 –ns
tRSF Reset to flag output time –50 ns
tPRT Retransmit pulse width 5 – RCLK
cycles
tOLZ Output enable to output in Low Z 415 ns
tOE Output enable to output valid –15 ns
tOHZ Output enable to output in High Z –15 ns
tWFF Write clock to FF –8.5 ns
tREF Read clock to EF –8.5 ns
tPAF Clock to PAF flag –17 ns
tPAE Clock to PAE flag –17 ns
tHF Clock to HF flag –17 ns
tPLL Time required to synchronize PLL –1024 cycles
tRATE_JTAG JTAG TCK cycle time 100 –ns
tS_JTAG Setup time for JTAG TMS,TDI 8 – ns
tH_JTAG Hold time for JTAG TMS,TDI 8 – ns
tCO_JTAG JTAG TCK low to TDO valid –20 ns
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CYF0072V
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Switching Waveforms Figure 6. Write Cycle Timing
Figure 7. Read Cycle Timing
tCLKH tCLKL
NO OPERATION
tDS
tENS
WEN
, IE
tCLK
tDH
tENH
WCLK
D[35:0]
NO OPERATION
t
CLK
t
OHZ
RCLK
REN
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
L
REN_TO_DATA
DVal
Q[35:0]
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Figure 8. Reset Timing
Figure 9. MRS to PORTSZ[2:0]
Switching Waveforms (continued)
t
RS
–
MRS / PRS
t
RSF
t
RSF
t
RSF
OE=1
OE=0
EF,PAE
FF,PAF,
HF
Q[35:0]
DVal,
WCLK/RCLK
PORTSZ[2:0]
MRS
tPZS
tPZH
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Figure 10. Empty Flag Timing
Figure 11. Full Flag Timing
Switching Waveforms (continued)
EF
REN
OE
RCLK
tREF
Q(Last)-2 Q(Last)-1 Q(Last) Invalid DataQ(Last)-3
DVal
Q[35:0]
EF
REN
OE
FF
WCLK
tDS
WEN
tWFF
D1 (written) D2 (written) D3 (not written) D4 (not written)D0 (written)
D[35:0]
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Document Number: 001-53687 Rev. *N Page 22 of 35
Figure 12. Initial Data Latency
Figure 13. Flow-through Mailbox Operation
Switching Waveforms (continued)
L IN (iNITIAL LATENCY)
D[35:0]
Q
[35:0
WEN
REN
RCLK
WCLK
Q6Q5Q4Q1 Q2QO Q3
DVal
tA
D0 D1 D2 D3 D4 D5 D6
WCLK
D[35:0]
REN / WEN
MB
DO D1 D3
Q4Q1 Q2QO Q3
Q[35:0]
D2 D4
DVal0/
123
L MAILBOX
DVal1
DVal
2
1
0
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Figure 14. Configuratio n Reg is te r Write
Figure 15. Conf iguration Register Read
Figure 16. Empty Flag Deasser tion
Switching Waveforms (continued)
LD
D[35:0] config-reg 0 config-reg 1 config-reg 2 config-reg 3 config-reg 4 config-reg 5
WCLK
WEN
tENS
tDS tDH
WCLK
/RCLK
REN
LD
Q[35:0] Reg - 1
LREN_TO_CONFIG
t
A
WCLK
RCLK
REN
EF
D[35:0]
WEN
D0 D1
/ IE
L EF_DEASSERT
tREF
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Figure 17. Empty Fla g Asse rtio n
Figure 18. Full Flag Asserti on
Switching Waveforms (continued)
RCLK
REN
12345
Q
[35:0]
Q
LAST
EF
DVal
L
REN_TO_DATA
t
A
t
REF
L
FF_RELEASE
FF
0
1
2
3
4
8
WCLK
WEN
D[35:0]
FF
D
0
D
1
D
x
D
LAST-1
D
LAST
NOT
WRITTEN
NOT
WRITTEN
/ IE
Note
8. Errata: Refer to Errata on page 31 for details on flag operation and full bound ary freezing during Mark and Retransmit operation.
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Document Number: 001-53687 Rev. *N Page 25 of 35
Figure 19. Full Flag Deassertion
Figure 20. PAE Assertion an d Deassertion
Switching Waveforms (continued)
WCLK
WEN
D[35:0]
FF
D
LAST-4
D
LAST-3
D
LAST-2
D
LAST-1
D
LAST
RCLK
REN
123 8
D
LAST-5
L FF_DEASSERT
/ IE
0
WCLK
WEN
RCLK
REN
PAE
1 READ
tPAE tPAE
L WEN_TO_PAE_HI L REN_TO_PAE_LO
/ IE
Note 9
Note
9. Refer to Table 2 on page 8 and Latency Table on page 16 for the Programmable Flag boundaries.
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Document Number: 001-53687 Rev. *N Page 26 of 35
Figure 21. PAF Assertion and Deassertion
Figure 22. HF Assertion and Deassertion
Switching Waveforms (continued)
WCLK
RCLK
REN
PAF
1 READ
tPAF tPAF
L WEN_TO_PAF_LO
L REN_TO_PAF_HI
WEN/ IE
Note 10
WCLK
WEN
RCLK
REN
HF
FULL / 2
WRITE
1 READ
tHF tHF
/ IE
L REN_TO_PAF_HI
L WEN_TO_PAF_LO
Note
10.Refer to Table 2 on page 8 and Latency Table on page 16 for the Programmable Flag boundaries.
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Document Number: 001-53687 Rev. *N Page 27 of 35
Figure 23. Mark
Figure 24. Retransmit
Switching Waveforms (continued)
DVal
RCLK
MARK
REN
Q[35:0]
DATA MARKED
Q (N-1) Q (N) Q (N+1) Q (N+3)
Q (N+2) Q (N+5)
Q (N+4) Q (N+6)Q (N-2)
tENS
tENH
RETRANSMIT FROM
DATA MARKED
Q (N+1)
Q (N)
DVal
RT
RCLK
REN
Q[35:0]
tPRT LRT_TO_REN
LRT_TO_DATA
FLAGS UPDATED AFTER RT
All Flags
11
11
Note
11. Errata: Refer to Errata on p age 31 for details on flag operation and full boundary freezing during Mark and Retransmit operation.
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Ordering Information
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
133 CYF0018V33L-133BGXI 51-85167 209-ball FBGA (14 × 22 × 1.76 mm) Industrial
CYF0036V33L-133BGXI
CYF0072V33L-133BGXI
CYF0018V18L-133BGXI
CYF0072V18L-133BGXI
Ordering Code Definitions
I/O Voltage:
V18 = 1.8 V
Density:
018 = 18M
Cypress
CY F X XXX VXX X - XXX BGXI
FIFO
I/O Standard:
L = LVCMOS
036 = 36M
072 = 72M
V33 = 3.3 V
Speed:
133 MHz
0 - single-queue
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Package Diagram
Figure 25. 209-ball FBGA (14 × 22 × 1.76 mm) BB209A Packa ge Outline, 51-85167
51-85167 *C
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Acronyms Document Conventions
Units of Measure
Acronym Description
FF Full Flag
FIFO First In First Out
HF Half Full
IE Input Enable
I/O Input/Output
FBGA Fine-Pitch Ball Grid Array
JTAG Joint Test Action Group
LSB Least Significant Bit
LVCMOS Low V oltage Complementary Metal Oxide
Semiconductor
MB Mailbox
MRS Master Reset
MSB Most Significant Bit
OE Output Enable
PAF Programmable Almost-Full
PAE Programmable Almost-Empty
PRS Partial Reset
RCLK Read Clock
REN Read Enable
RCLK Read Clock
SCLK Serial Clock
TCK Test Clock
TDI Test Data In
TDO Test Data Out
TMS Test Mode Select
WCLK Write Clock
WEN Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
mA milliampere
mm millimeter
ms millisecond
ns nanosecond
ohm
pF picofarad
Vvolt
Wwatt
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Errata
This section describes the errata for the 18-Mbit, 36-Mbit, and 72-Mbit programmable FIFOs. Details include errata trigger conditions,
scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative or raise a
technical support case at www.cypress.com/support if you have questions.
Part Numbers Affected
18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Qualification Status
Product Status: In Production
18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO Errata Summary
This table defines the errata applicability to available 18-Mbit, 36-Mbit, and 72-Mbit Programmable FIFO family devices.
1. Retransmit Issue
■Problem Definition
Flag Failure during Retransmit cycles: Flags (PAE, HF, PAF, and FF) are not updated during a retransmit cycle. These flags do not
recover on completion of retransmit cycles. The functionality of Empty Flag (EF) and Data Valid signal (DVal) remain intact
throughout device operation.
■Parameters Affected
Because flags (PAE, HF, PAF, and FF) are not updated during a retransmit cycle, their associated latencies and timing parameters
are not app l ica b le.
■Trigger Condition
Initiation of a retransmit cycle using RT signal.
■Scope of Impact
On initiation of a retransmit cycle, flags (PAE, HF, PAF, and FF) may not accurately reflect FIFO status. Customer applications
relying on these flags to keep track of number of words in the FIFO during retransmit may observe errors because these flags are
not updated. The failure mandates a reset cycle (Partial Reset for Single queue and Master Reset for Multi queue devices) to
ensure flag recovery after a retransmit cycle, that is, to restore flag functionality and resume normal FIFO operations after
completion of retransmit cycles.
■Workaround
During retransmit cycles, there is no workaround to restore PAE, HF, PA F, and FF functionalities.
After completion of retransmit cycles, a reset cycle (Partial Reset for Single queue and Master Reset for Multi queue devices) can
be performed to restore PAE, HF, PAF, and FF functionalities for normal FIFO operation.
■Fix Status
The fix for the retransmit issue is in progress. In devices wi th the de sign fix, the i ntended flag functiona lity will be restor ed d uring
retransmit cycles. Reset will not be mandatory after a retransmit cycle to resume normal FIFO operation. Fixed devices will be
available from February 04, 2013.
Part Number Device Characteristics
CYF0018V33L-133BGXI 18-Mbit Programmable Singl e-Queue FIFOs (3.3-V LVCMOS)
CYF0018V18L-133BGXI 18-Mbit Programmable Singl e-Queue FIFO (1.8-V LVCMOS)
CYF0036V33L-133BGXI 36-Mbit Programmable Singl e-Queue FIFO (3.3-V LVCMOS)
CYF0072V33L-133BGXI 72-Mbit Programmable Singl e-Queue FIFO (3.3-V LVCMOS)
CYF0072V18L-133BGXI 72-Mbit Programmable Singl e-Queue FIFO (1.8-V LVCMOS)
CYF2072V33L-100BGXI 72-Mbit Programmable Eight-Qu eue FIFO (3.3-V LVCMOS)
Items Part Numbers Fix Status
1. Retransmit Issue CYF0 018V, CYF0036V, CYF0072V, CYF2072V Fix in progress.
Fixed devices to be available from
February 04, 2013
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Document History Page
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 -Mb it Pro gr ammab le FIFOs
Document Number: 001-53687
Revision ECN Orig. of
Change Submission
Date Description of Change
** 2711566 VKN /
PYRS 05/27/09 New data sheet
*A 2725088 NXR 06/26/20 09 Included pinout, AC and DC specs, timing diagrams and package diagram
*B 2839536 NXR 01/28/2010 Changed Balls B5, D5, F6, K1, K2, K4, K8 and U2 from NC to DNU, Balls C5,
C7, G6, H6, J6, L6, M6, N6, T5, T7 from NC to VCC1, Balls K9, K10, K11 from
NC to VCCIOR, Ball W9 from NC to Vr ef in pin configuration table
Swapped Voltage range of VSS1 and VSS2
Updated ICC spec
Removed TSKEW parameter
Added Ordering Information table
Added Part Numbering Nomenclature.
Changed title to CYF0018V/CYF0036V/CYF0072V/CYFX144VXXX,
18/36/72-Mbit Programmable FIFOs.
*C 2884377 HKV 02/25/2010 Post to external web.
*D 2963225 AJU / HPV 06/28/2010 Changed frequency of operation from 250 MHz to 150 MHz
Removed Depth Expansion feature and changed associated pin functi onality
Removed Independent Port size selectability feature
Added Data Valid (DVal) signal feature
Updated Logic Block Diagram to reflect above changes.
Pinout changes:
Balls V5, V8, A7, B7, D7, and C6 renamed DNU
Ball U1 changed from RXO to DVal
Ball V2 changed from WXO/HF to HF
Ball A5, A6, B6 changed from WPORTSZ to PORTSZ
Ball A9 changed from RT/FL to RT
Renamed pwr as POWER, gnd as GND
Added Table 4
Table 6 – LD changed to ‘1’ for serial writes
Updated Electrical Chara c teristics and I/O Characteristics
Switching Characteristics Table:
Renamed tPC as tPU
Min frequency changed from 110MH to 24MHz
Changed tCLKH and tCLKL to 3.15 ns
Changed All setup and hold times to 3 ns
Changed tRSF to 50 ns
Removed tRSR
Changed All clock-to-flag timing to min = 8 ns and max = 14 ns
TPLL changed to 6 ms
Changed all OE-related parameters to 15 ns
Scaled ICC for reduced frequency
Updated all wave forms
Added the following table: “Word Size Selection”.
Added the sections JTAG Operation, and Latency Table
Added Acronyms.
*E 2994379 AJU 07/26/2010 Updated Ordering Information
*F 3101023 SIVS 12/03/2010 Added supply-wise current consumption data in El ectrical Characteristics.
Changed initial latency LIN from 34 to 26 and added initial latency LIN for
110 MHz part in L atency Table.
Added 110 MHz part information in JTAG Operation
Added details for the 110 MHz part in Switching Characteristics.
Added details for the 110 MHz part in Ordering Information.
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*G 3129722 HKV 01/06/2011 Post to external web.
*H 3197271 SIVS 03/31/2011 Removed 144 Mbit parts from the data sheet
Removed multi-queue information from data sheet
Removed 2.5 V an d 1. 5 V op ti o ns
Removed HSTL I/II I/O standard
Added clock ratio requirement between RCLK and WCLK
Removed redundant Xs from part number to improve readability
Removed tie to GND option on DNU pins in pin description
Added information on Flag operations to add clarity
Added explanation for flow-through mailbox operation
Added details on active pins in various port sizes in Table 1.
Added Configuration register write to normal ope ration latency details.
Changed configuration register definitions and default values
Changed number of unusable locations to four to eight
Added JTAG related operation
Added latch-up current parameter in maximum operating conditions.
Removed 2.5 V and 1.5 V options from DC operating condition table 6.
Removed 110 MHz part details and added Cpio parameter in table 7.
Removed 2.5 V an d 1. 5 V opti ons from Table 8.
Added latency parameters in Table 9.
changed VOL(max) value of LVCMOS33 in table11
Removed 110 MHz part detail from switching characteristics
Added timing waveform to improve clarity.
Modified ordering information and definition.
*I 3388143 AJU 09/29/2011 Updated Pin Diagram for CYF0XXXVXXL [1] (Added Note 2 and referred the
same note in DNU in ball U6).
Updated Programming Flag Offsets and Configuration Registers (Updated
Table 4 (WCLK column in first row)).
Updated Recommended DC Operating Conditions (Added Note 5 and referred
the same note in Parameter column).
Updated Latency Table (Changed Details for the parameters L WEN_TO_PAE_HI
and LREN_TO_PAE_LO).
Updated Switching W aveforms (Removed the clock cycle numbers in
Figure 12, Figure 13, Figure 17, and Figure 19).
Updated Package Diagram.
Updated in new template.
*J 3652368 ADMU 08/16/2012 Updated Pin Diagram for CYF0XXXVXXL [1] (Updated Figure 1 on page 4 (W9
ball marked as DNU)).
Added Figure 5 (Test Load Conditions).
Updated Switching Characteristics (Changed minimum values of t S_JTAG,
tH_JTAG parameters from 5 ns to 8 ns, changed maximum value of tCO_JTAG
parameter from 10 ns to 20 ns).
*K 3735896 ADMU 09/07/2012 Update d package diagram 51-85167 to *C
Updated “Output current into outputs (LOW)” parameter under Maximum
Ratings section from 20 mA to 24 mA.
Document History Page (continued)
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 -Mb it Pro gr ammab le FIFOs
Document Number: 001-53687
Revision ECN Orig. of
Change Submission
Date Description of Change
CYF0018V
CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *N Page 34 of 35
*L 3940217 ADMU 03/22/2013 Updated Features.
Updated Functional Description.
Updated Logic Block Diagram.
Updated Pin Diagram for CYF0XXXVXXL [1]:
Added Note 1 and referred the same note in Figure 1.
Updated Pin Defini tions.
Updated Architecture:
Updated Reset Logic, Data Valid Signal (DVal), Flag Operation , Retransmit
from Mark Operation, Programming Flag Offsets and Configuration Registers,
Read/Write Clock Requirements.
Added Table 2.
Updated Latency Table.
Updated Switching W aveforms:
Updated Figure 12, Figure 13, Figure 17, Figure 19, Figure 20, Figure 21,
Figure 22, Figure 24.
Added Note 9 and referred the same note in WEN / IE in Figure 20.
Added Note 10 and referred the same note in WEN / IE in Figure 21.
Updated Ordering Information (Updated part numbers).
*M 3997615 ADMU 05/11/2013 Added Errata.
*N 4078255 ADMU 07/26/2013 Added Errata footnotes (Note 4, 7, 8, 11).
Updated Architecture:
Updated Retransmit from Mark Operation:
Added Note 4 and referred the same note in 2nd paragraph and last paragraph.
Updated Latency Table:
Added Note 7 and referred the same note in “LFF_RELEASE” parameter.
Updated Switching W aveforms:
Added Note 8 and referred the same note in “LFF_RELEASE” in Figure 17.
Added Note 11 and referred the same note in “All Flags” and “FLAGS
UPDATED AFTER RT” in Figure 24.
Updated in new template.
Document History Page (continued)
Document Title: CYF0018V/CYF0036V/CYF0072V, 18/36/72 -Mb it Pro gr ammab le FIFOs
Document Number: 001-53687
Revision ECN Orig. of
Change Submission
Date Description of Change
Document Number: 001-53687 Rev. *N Revised July 26, 2013 Page 35 of 35
All products and company names mentioned in this document may be the trademarks of their respective holders.
CYF0018V
CYF0036V
CYF0072V
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