LTC4354
1
4354fb
TYPICAL APPLICATIO
U
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
The LTC
®
4354 is a negative voltage diode-OR controller
that drives two external N-channel MOSFETs. It replaces
two Schottky diodes and the associated heatsink, saving
power and area. The power dissipation is greatly reduced
by using N-channel MOSFETs as the pass transistors.
Power sources can easily be ORed together to increase
total system power and reliability.
When first powered up, the MOSFET body diode conducts
the load current until the pass transistor is turned on. The
LTC4354 servos the voltage drop across the pass transis-
tors to ensure smooth transfer of current from one tran-
sistor to the other without oscillation.
The MOSFETs are turned off in less than 1µs whenever the
corresponding power source fails or is shorted. Fast turn-
off prevents the reverse current from reaching a level that
could damage the pass transistors.
A fault detection circuit with an open drain output capable
of driving an LED or opto-coupler indicates either MOSFET
short, MOSFET open or supply failed.
■
AdvancedTCA
®
Systems
■
–48V Distributed Power Systems
■
Computer Systems/Servers
■
Telecom Infrastructure
■
Optical Networks
■
Controls N-Channel MOSFETs
■
Replaces Power Schottky Diodes
■
Less Than 1µs Turn-off Time Limits Peak
Fault Current
■
80V Operation
■
Smooth Switchover Without Oscillation
■
No Reverse DC Current
■
Fault Output
■
Selectable Fault Thresholds
■
Available in 8-Pin (3mm × 2mm) DFN and 8-Pin SO
Packages
Negative Voltage
Diode-OR Controller
and Monitor
–48V Diode-OR
LTC4354 LOAD
DB GA
DA GB V
SS
V
B
= –48V
V
A
= –48V
–48V_RTN
FAULT
IRF3710
IRF3710
4354 TA01
V
CC
33k
12k
2k2k LED
1µF
Power Dissipation vs Load Current
CURRENT (A)
0
0
POWER DISSIPATION (W)
1
2
3
4
6
5
246
4354 TA01b
810
DIODE (MBR10100)
FET (IRF3710)
POWER
SAVED
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC4354
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TOP VIEW
DDB8 PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
EXPOSED PAD (PIN 9) IS VSS,
CONNECTION TO PCB OPTIONAL
5
6
7
8
9
4
3
2
1DA
VSS
VCC
GA
DB
FAULT
GB
VSS
I
CC
(100µs duration) ............................................. 50mA
Output Voltages
GA, GB....................................... –0.3V to V
CC
+ 0.3V
FAULT .................................................... –0.3V to 7V
Input Voltages
DA, DB.................................................. –0.3V to 80V
Input Current
DA, DB Current .................................. –1mA to 20mA
T
JMAX
= 125°C, θ
JA
= 76°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
Operating Temperature Range
LTC4354C ............................................... 0°C to 70°C
LTC4354I............................................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
T
JMAX
= 125°C, θ
JA
= 150°C/W
1
2
3
4
8
7
6
5
TOP VIEW
DB
FAULT
GB
V
SS
DA
V
SS
V
CC
GA
S8 PACKAGE
8-LEAD PLASTIC SO
ORDER PART
NUMBER
LTC4354CDDB
LTC4354IDDB
DDB8 PART
MARKING
LBBK
LBMB
ORDER PART
NUMBER
LTC4354CS8
LTC4354IS8
S8 PART
MARKING
4354
4354I
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC4354
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: I
CC
is defined as the current level where the V
CC
voltage is lower
by 100mV from the value with 2mA of current.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. ICC = 5mA, VSS = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
Z
Internal Shunt Regulator Voltage I
CC
= 5mA ●10.25 11 11.75 V
∆V
Z
Internal Shunt Regulator Load Regulation I
CC
= 2mA to 10mA 200 300 mV
V
CC
Operating Voltage Range ●4.5 V
Z
V
I
CC
V
CC
Supply Current V
CC
= (V
Z
– 0.1V), Note 2 ●1.2 2 mA
V
CC
= 5V ●0.5 0.8 1.1 mA
V
GATE
GATE Pins Output High Voltage V
CC
= 10.25V 10 10.25 V
V
CC
= 5V 4.75 V
I
GATE
GATE Pins Pull-Up Current V
SD
= 60mV; V
GATE
= 5.5V –15 –30 –60 µA
GATE Pins Pull-Down Current V
SD
= 0V; V
GATE
= 5.5V 15 30 60 µA
∆V
SD
Source Drain Sense Threshold Voltage (V
SS
– V
DX
)●10 30 55 mV
∆V
SD(FLT)
Source Drain Fault Detection Threshold (V
SS
– V
DX
); V
CC
= 7V to V
Z
●200 260 320 mV
t
OFF
Gate Turn-Off Time in Fault Condition C
GATE
= 3300pF; V
GATE
≤ 2V; V
SD
= –0.4V 0.7 1.2 µs
V
FAULT
FAULT Pin Output Low I
FAULT
= 5mA ●200 400 mV
I
FAULT
FAULT Pin Leakage Current V
FAULT
= 5V ●±1µA
I
D
Drain Pin Input Current V
DX
= 0V –3.5 –2.5 –1.5 µA
V
DX
= 80V 1.1 1.5 1.9 mA
Note 3: An internal shunt regulator limits the V
CC
pin to less than 12V
above V
SS
. Driving this pin to voltages beyond the clamp may damage the
part.
Note 4: All currents into pins are positive; all voltages are referenced to
V
SS
unless otherwise specified.
LTC4354
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
Specifications are at TA = 25°C, ICC = 5mA,
VSS = 0V unless otherwise noted.
Shunt Regulator Voltage vs Input
Current
Shunt Regulator Voltage vs Input
Current at Temperature
Source Drain Sense Voltage vs
Supply Voltage
Source Drain Sense Voltage vs
Temperature
Gate Turn-Off Time vs
Temperature
Fault Threshold Voltage vs
Temperature
IGATE(UP) vs ∆VSD
Drain Pin Current vs Temperature Drain Pin Current vs Voltage
I
CC
(mA)
0
V
Z
(V)
11.0
20
4354 G01
10.0
11.5
10.5
10
515
12.0
TEMPERATURE (°C)
–50
V
Z
(V)
11.4
11.0
10.6
11.2
10.8
–25 0 25
4354 G02
50 75 100 125
I
CC
= 10mA
I
CC
= 5mA
I
CC
= 2mA
V
CC
(V)
5
20
∆V
SD
(mV)
30
25
35
79
11 12
4354 G03
40
68
10
TEMPERATURE (°C)
–50
∆VSD (mV)
40
30
20
35
25
–25 0 25
4354 G04
50 75 100 125
TEMPERATURE (°C)
–50
tOFF (ns)
740
700
660
720
680
–25 0 25
4354 G05
50 75 100 125
TEMPERATURE (°C)
–50
∆V
SD(FLT)
(mV)
290
250
210
270
230
–25 0 25
4354 G06
50 75 100 125
∆VSD (mV)
30
IGATE(UP) (µA)
100
40
60
0
80
20
40 50 60
4354 G07
70 80 90
TEMPERATURE (°C)
–50
I
D
(µA)
–3.2
–2.8
–2.4
–3.0
–2.6
–25 0 25
4354 G08
50 75 100 125
V
DX
= 0V
V
DX
(V)
0.3
I
D
(mA)
–1
–0.5
–0.75
–0.25
0
0.4 0.5 0.6
4354 G09
0.7 0.8 0.9 1
90°C
25°C
–45°C
LTC4354
5
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PI FU CTIO S
UUU
DA, DB (Pins 1, 8): Drain Voltage Sense Inputs. These
pins sense source-drain voltage drop across the N-Chan-
nel MOSFETs. An external resistor is recommended to
protect these pins from transient voltages exceeding 80V
in extreme fault conditions. For Kelvin sensing, connect
these pins as close to the drains as possible. Connect to
V
SS
if unused.
V
CC
(Pin 3): Positive Supply Voltage Input. Connect this
pin to the positive side of the supply through a resistor. An
internal shunt regulator that can sink up to 20mA typically
clamps V
CC
at 11V. Bypass this pin with a 1µF capacitor to
V
SS
.
GA, GB (Pins 4, 6): Gate Drive Outputs. Gate pins pull high
to 10V minimum, fully enhancing the N-Channel MOSFET,
when the load current creates more than 30mV of drop
across the FET. When the load current is small, the gates
are actively servoed to maintain a 30mV drop across the
MOSFET. If reverse current develops more than –140mV
of voltage drop across the MOSFET, the pins pull low to
V
SS
in less than 1µs. Quickly turning off the pass transis-
tors prevents excessive reverse currents. Leave the pins
open if unused.
V
SS
(Pins 2, 5): Negative Supply Voltage Input. This is the
device negative supply input and connects to the common
source connection of the N-Channel MOSFETs. It also
connects to the source voltage sense input of the servo
amplifiers. For Kelvin sensing, connect pin 5 as close to
the common source terminal of the MOSFETs as possible.
FAULT (Pin 7): Fault Output. Open drain output that
normally pulls the FAULT pin to V
SS
and shunts current to
turn off an external LED or optocoupler. In the fault
condition, where the pass transistor is fully on and the
voltage drop across it is higher than the fault threshold, the
FAULT pin goes high impedance, turning on the LED or
optocoupler. This indicates that one or both of the pass
transistors have failed open or failed short creating a cross
conduction current in between the two power supplies.
Connect to V
SS
if unused.
EXPOSED PAD (Pin 9): Exposed pad is common to V
SS
and may be left open or connected to pins 2 and 5.
FU CTIO AL DIAGRA
UU
W
DB
GB
DA
GA
30mV
BV = 11V
30mV
V
SS
V
CC
V
SS
V
SS
55k
4354 FD01
V
SS
FAULT
–
+
–
+
+
–
+
–
FAULT DETECTION
AMP B
AMP A
5
4
1
6
8
2
7
3
V
SS
55k
LTC4354
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TI I G DIAGRA
WUW
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been a
popular means of connecting these supplies at the point of
load. The disadvantage of this approach is the significant
forward voltage drop and resulting efficiency loss. This
drop reduces the available supply voltage and dissipates
significant power. A desirable circuit would behave like
diodes but without the voltage drop and the resulting
power dissipation.
The LTC4354 is a negative voltage diode-OR controller
that drives two external N-channel MOSFETs as pass
transistors to replace ORing diodes. The MOSFETs are
connected together at the source pins. The common
source node is connected to the V
SS
pin which is the
negative supply of the device. It is also connected to the
positive inputs of the amplifiers that control the gates to
regulate the voltage drop across the pass transistors.
Using N-channel MOSFETs to replace Schottky diodes
reduces the power dissipation and eliminates the need for
costly heat sinks or large thermal layouts in high power
applications.
At power-up, the initial load current flows through the
body diode of the MOSFET and returns to the supply with
the lower terminal voltage. The associated gate pin will
immediately start ramping up and turn on the MOSFET.
The amplifier tries to regulate the voltage drop between the
source and drain connections to 30mV. If the load current
causes more than 30mV of drop, the gate rises to further
enhance the MOSFET. Eventually the MOSFET gate is
driven fully on and the voltage drop is equal to the R
DS(ON)
• I
LOAD
.
When the power supply voltages are nearly equal, this
regulation technique ensures that the load current is
smoothly shared between them without oscillation. The
current level flowing through each pass transistor de-
pends on the R
DS(ON)
of the MOSFET and the output
impedance of the supplies.
In the case of supply failure, such as if the supply that is
conducting most or all of the current is shorted to the
return side, a large reverse current starts flowing through
the MOSFET that is on, from any load capacitance and
through the body diode of the other MOSFET, to the
second supply. The LTC4354 detects this failure condition
as soon as it appears and turns off the MOSFET in less than
1µs. This fast turn-off prevents the reverse current from
ramping up to a damaging level.
In the case where the pass transistor is fully on but the
voltage drop across it exceeds the fault threshold, the
FAULT pin goes high impedance. This allows an LED or
optocoupler to turn on indicating that one or both of the
pass transistors have failed.
The LTC4354 is powered from system ground through a
current limiting resistor. An internal shunt regulator that
can sink up to 20mA clamps the V
CC
pin to 11V above V
SS
.
A 1µF bypass capacitor across V
CC
and V
SS
pins filters
supply transients and supplies AC current to the device.
OPERATIO
U
4354 TD01
VSS – VDX
VGATE
tOFF
100mV
2V
–400mV
LTC4354
7
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APPLICATIO S I FOR ATIO
WUUU
Input Power Supply
The power supply for the device is derived from –48_RTN
through an external current limiting resistor (R
IN
). An
internal shunt regulator clamps the voltage at V
CC
pin to
11V. A 1µF decoupling capacitor to V
SS
is recommended.
It also provides a soft-start to the part.
R
IN
should be chosen to accommodate the maximum
supply current requirement of 2mA at the expected input
operating voltage.
RVV
I
IN IN MIN Z MAX
CC MAX
≤
−()
() ( )
()
The power dissipation of the resistor is calculated at the
maximum DC input voltage:
PVV
R
IN MAX CC MIN
IN
=
−()
() ()
2
If the power dissipation is too high for a single resistor, use
multiple low power resistors in series instead of a single
high power component.
MOSFET SELECTION
The LTC4354 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance R
DS(ON)
, the maximum drain-source volt-
age V
DSS
, and the threshold voltage.
The gate drive for the MOSFET is guaranteed to be more
than 10V and less than 12V. This allows the use of
standard threshold voltage N-channel MOSFETs. An ex-
ternal zener diode can be used to clamp the potential at the
V
CC
pin to as low as 4.5V if the gate to source rated
breakdown voltage is less than 12V.
The maximum allowable drain-source voltage, V
(BR)DSS,
must be higher than the supply voltages. If the inputs are
shorted, the full supply voltage will appear across the
MOSFETs.
The LTC4354 tries to servo the voltage drop across the
MOSFET to 30mV in the forward direction by controlling
the gate voltage and sends out a fault signal when the
voltage drop exceeds the 260mV fault threshold. The
R
DS(ON)
should be small enough to conduct the maximum
load current while not triggering a fault, and to stay within
the MOSFET’s power rating at the maximum load current
(I
2
• R
DS(ON)
).
Fault Conditions
LTC4354 monitors fault conditions and turns on an LED or
optocoupler to indicate a fault. When the voltage drop
across the pass transistor is higher than the 260mV fault
threshold, the internal pull-down at the FAULT pin turns off
and allows the current to flow through the LED or
optocoupler. Conditions that cause high voltage across
the pass transistor include: short in the load circuitry,
excessive load current, FET open while conducting cur-
rent, and FET short on the channel with the higher supply
voltage. The fault threshold is internally set to 260mV.
In the event of FET open on the channel with the more
negative supply voltage, if the voltage difference is high
enough, the substrate diode on the DA or DB pins will
forward bias. The current flowing out of the pins must be
limited to a safe level (<1mA) to prevent device latch up.
Schottky diodes can be used to clamp the voltage at the DA
and DB pins, as shown in Figure 1.
4354 F01
DA GA
LTC4354
V
SS
MMBD2836LT1
1k
1k
Figure 1. Method of Protecting the DA and DB Pins from
Negative Inputs. One Channel Shown.
LTC4354
8
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APPLICATIO S I FOR ATIO
WUUU
Figure 2. –36V to –72V/5A Design Example
4354 F01
DA GA
LTC4354
V
SS
MMBD2836LT1
1k
1k
System Power Supply Failure
LTC4354 automatically supplies load current from the
system supply with the more negative input potential. If
this supply is shorted to the return side, a large reverse
current flows from its pass transistor. When this reverse
current creates –140mV of voltage drop across the drain
and source pins of the pass transistor, the LTC4354 drives
the gate low fast and turns it off.
The remaining system power supply will deliver the load
current through the body diode of its pass transistor until
the channel turns on. The LTC4354 ramps the gate up and
turns on the N-Channel MOSFET to reduce the voltage
drop across it, a process that takes less than 1ms depend-
ing on the gate charge of the MOSFET.
Drain Resistor
Two resistors are required to protect the DA and DB pins
from transient voltages higher than 80V. In the case when
the supply with the lower potential is shorted to the return
side due to supply failure, a reverse current flows briefly
through the pass transistor to the other supply to dis-
charge the output capacitor. This current stores energy in
the stray inductance along the current path. Once the pass
transistor is turned off, this energy forces the drain termi-
nal of the FET high until it reaches the breakdown voltage.
If this voltage is higher than 80V, the internal ESD devices
at the DA and DB pins might break down and become
damaged. The external drain resistors limit the current
into the pins and protect the ESD devices. A 2k resistor is
recommended for 48V applications. Larger resistor values
increase the source drain sense threshold voltage due to
the input current at the drain pins.
Loop Stability
The servo loop is compensated by the parasitic capaci-
tance of the power N-channel MOSFET. No further com-
pensation components are normally required. In the case
when a MOSFET with very small parasitic capacitance is
chosen, a 1000pF compensation capacitor connected
across the gate and source pins might be required.
Design Example
The following demonstrates the calculations involved for
selecting components in a –36V to –72V system with 5A
maximum load current, see Figure 2.
First, select the input dropping resistor. The resistor
should allow 2mA of current with the supply at –36V.
RVV
mA k
IN
≤−=
(.)
.
36 11 5
212 25
The nearest lower 5% value is 12k.
LTC4354
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–5.2V Diode-Or Controller
LTC4354 LOAD
DB GA
DA GB VSS
VB = –5.2V
VA = –5.2V
GND
FAULT
M2
Si4466DY
M1
Si4466DY
4354 TA02
VCC
R3
2k
D1
LED
CIN
1µF
2, 56148
3
7
The worst case power dissipation in R
IN
:
PVV
kW=−=
(.)
.
72 10 5
12 0 315
2
Choose a 12k 0.5W resistor or use two 5.6k 0.25W
resistors in series.
Next, choose the N-channel MOSFET. The 100V, IRF3710S
in D
2
Pak package with R
DS(ON)
= 23mΩ (max.) offers a
good solution. The maximum voltage drop across it is:
∆V = (5A)(23mΩ) = 115mV
The maximum power dissipation in the FET is a mere:
P = (5A)(115mV) = 0.6W
R1 and R2 are chosen to be 2k to protect DA and DB pins
from being damaged by high voltage spikes that can occur
during an input supply fault.
The LED, D1, requires at least 1mA of current to fully turn
on, therefore R3 is set to 33k to accommodate lowest input
supply voltage of –36V.
Layout Considerations
The following advice should be considered when laying
out a printed circuit board for the LTC4354.
The bypass capacitor provides AC current to the device so
place it as close to the V
CC
and V
SS
pins as possible. The
inputs to the servo amplifiers, DA, DB and V
SS
pins, should
be connected directly to the MOSFETs’ terminals using
Kelvin connections for good accuracy.
Keep the traces to the MOSFETs wide and short. The PCB
traces associated with the power path through the MOSFETs
should have low resistance.
APPLICATIO S I FOR ATIO
WUUU
12V
470Ω
240Ω*
1.2V, 200A
OUTPUT BUS
4354 TA02b
*OPTIONAL PRELOAD
HAT2165 ×6
HAT2165 ×6
1.2V
100A
INPUT
1µF
VEE GA,GB
VCC
LTC4354
DA,DB
12V
470Ω
240Ω*
1.2V
100A
INPUT
1µF
VEE GA,GB
VCC
LTC4354
DA,DB
Positive Low Voltage Diode-OR Combines
Multiple Switching Converters
LTC4354
10
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APPLICATIO S I FOR ATIO
WUUU
–36V to –72V/20A High Current with Parallel FETs
3
LTC4354
DB GADA GB V
SS
V
B
= –48V
FAULT
M4
IRF3710
M3
IRF3710
4354 TA03
V
CC
3
R6
30k
R
IN2
10k
R5
2k
R4
2k
D2
LED
C
IN2
1µF
LTC4354
DB GADA GB V
SS
V
A
= –48V –48V OUT
–48V_RTN RTN
RTN
FAULT
M2
IRF3710
M1
IRF3710
V
CC
R3
30k
R
IN1
10k
R2
2k
R1
2k
D1
LED
C
IN1
1µF
2, 56148
7
2, 56148
7
–12V Diode-OR Controller
LTC4354 LOAD
DB GA
DA GB VSS
2, 56148
VB = –12V
VA = –12V
GND
FAULT
M2
Si4862DY
3
7
M1
Si4862DY
4354 TA04
VCC
R3
10k
RIN
2k IN754
BV = 6.8V
CIN
1µF
D1
LED
DZ
LTC4354
11
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PACKAGE DESCRIPTIO
U
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.15 ±0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
14
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0 – 0.05
(DDB8) DFN 1103
0.25 ± 0.05
2.20 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.675 ±0.05
2.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
PIN 1
CHAMFER OF
EXPOSED PAD
0.50 BSC
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4354
12
4354fb
LTC4354 LOAD
DB GA
DA GB VSS
VB = –48V
VA = –48V
–48V_RTN
FAULT
IRF540NS
IRF540NS
4354 TA05
VCC
33k
12k
0.5W
1k
1k
1k
1k
LED
1µF
MMBD2836LT1
MMBD2836LT1
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT/LWI 0606 REV B • PRINTED IN USA
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–48V Diode-OR Controller with Fuse Monitoring
