UT54ACTS220-PCX - Aeroflex Incorporated

145 RadHard MSI Logic

UT54ACTS220

Clock and Wait-State Generation Circuit

FEATURES

• 1.2µ radiation-hardened CMOS

- Latchup immune

• High speed

• Low power consumption

• Single 5-volt supply

• Available QML Q or V processes

• Flexible package

- 14-pin DIP

- 14-lead flatpack

DESCRIPTION

The UT54ACTS220 is designed to be a companion chip to

UTMC’s UT69151 SµMMIT family for the purpose of gener-

ating clock and wait-state signals. The device contains a divide

by two circuit that accepts TTL input levels and drives CMOS

output buffers. The chip accepts a 48MHz clock and generates

a 24MHz clock. The 48MHz clock can have a duty cycle that

varies by ± 20%. The UT54ACT220 generates a 24MHz clock

with a ± 5% duty cycle variation. The wait-state circuit generates

a single wait-state by delaying the falling edge of DTACK into

the SµMMIT. The clock/timing device generates DTACK from

the falling edge of input RCS which is synchronized by the

falling edge of 24MHz. The SµMMIT drives inputs RCS and

DMACK.

The devices are characterized over full military temperature

range of -55°C to +125°C.

LOGIC SYMBOL

PINOUTS 14-Pin DIP

Top View

14-Lead Flatpack

Top View

114

213

312

411

510

6 9

7 8

NC

CLKOUT

CLKIN

NC

48MHz

VSS

VDD

24MHz

DTACK

MRST

RCS

DMACK

TEST

1 14

2 13

3 12

411

5 10

6 9

7 8

NC

CLKOUT

CLKIN

NC

48MHz

VSS

VDD

24MHz

DTACK

MRST

RCS

DMACK

TEST

(10)

MRST

(8)

DMACK

(6)

48MHz

(9)

RCS

(13) 24MHz

(11)

(12) DTACK

(4)

CLKIN

(2) CLKOUT

(3) CLKOUT

S

CTR1

SRG2

1D

S

TEST

Note:

1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC

Publication 617-12.

RadHard MSI Logic 146

UT54ACTS220

PIN DESCRIPTION

FUNCTIONAL TIMING: Single SµMMIT Wait-State

For both read and write memory cycles, DTACK is an input to the SµMMIT E and SµMMIT LXE/DXE. A non-wait state mem-

ory requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to

a logical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SµMMIT E

and SµMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the ris-

ing edge of the clock, the SµMMIT E and SµMMIT LXE/DXE extends the memory cycle.

Pin Number Pin Name Description

2CLKOUT Buffered version of CLKIN.

3CLKOUT Inverted version of CLKIN.

4CLKIN Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.

648MHz 48MHz Clock. The 24MHz clock is created by dividing this signal by two.

8DMACK DMA Acknowledge. This input is generated by the SµMMIT. When high, this signal will

cause DTACK output to be forced high.

9RCS RAM Chip Select. This input is generated by the SµMMIT.

10 MRST Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal

operation tie MRST to VDD through a resistor.

11 TEST Test output signal.

12 DTACK Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the

SµMMIT if the user requires one wait state during the memory transfer.

13 24MHz 24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling

edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high

whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%.

48MHz

24MHz T1T2

DMACK

RCS

DTACK

TW

Figure 1. Functional Timing

147 RadHard MSI Logic

UT54ACTS220

LOGIC DIAGRAM

CLKIN

CLKOUT

DTACK

DMACK

RCS

MRST

48MHz

24MHz

CK

D

RSTQCK

D

PRE

Q

CK

D

PRE

Q

TEST

RadHard MSI Logic 148

UT54ACTS220

RADIATION HARDNESS SPECIFICATIONS

Notes:

1. Device storage elements are immune to SEU affects.

2. Not tested, inherent of CMOS technology.

ABSOLUTE MAXIMUM RATINGS

Note:

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device

at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

PARAMETER LIMIT UNITS

Total Dose 1.0E6 rad(Si)

SEU Threshold 180 MeV-cm2/mg

SEL Threshold >120 MeV-cm2/mg

Neutron Fluence21.0E14 n/cm2

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage -0.3 to 7.0 V

VI/O Voltage any pin -0.3 to VDD +0.3 V

TSTG Storage Temperature range -65 to +150 °C

TJMaximum junction temperature +175 °C

TLS Lead temperature (soldering 5 seconds) +300 °C

ΘJC Thermal resistance junction to case 20 °C/W

IIDC input current ±10 mA

PDMaximum power dissipation 1W

SYMBOL PARAMETER LIMIT UNITS

VDD Supply voltage 4.5 to 5.5 V

VIN Input voltage any pin 0 to VDD V

TCTemperature range -55 to + 125 °C

48MHz Duty Cycle 50 ± 20% MHz

149 RadHard MSI Logic

UT54ACTS220

DC ELECTRICAL CHARACTERISTICS 7

(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C)

SYMBOL PARAMETER CONDITION MIN MAX UNIT

VIL Low-level input voltage 1

TTL 0.8 V

VIH High-level input voltage 1

TTL 2.25VDD V

IIN Input leakage current

TTL VDD = 5.5V

VIN = VDD or VSS -1 1µA

VOL1 Low-level output voltage 3

Except CLKOUT/CLKOUT

IOL = 8mA, VDD = 4.5V

IOL = 100µA0.4

0.25 V

VOH1 High-level output voltage 3

Except CLKOUT/CLKOUT

IOH = -8mA, VDD = 4.5V 3.15VDD V

VOL2 CLKOUT/CLKOUT Low-level output

voltage 3IOL = 100µA0.25 V

VOH2 CLKOUT/CLKOUT High-level output

voltage 3

IOH = -100µA VDD4.25 V

IOS Short-circuit output current 2 ,4 VO = VDD and VSS

VDD = 5.5V

+300 mA

IOL1 Output current10

(Sink), Except CLKOUT/CLKOUT

VIN = VDD or VSS

VOL = 0.4V

8mA

IOH1 Output current10

(Source), Except CLKOUT/CLKOUT

VIN = VDD or VSS

VOH = VDD - 0.4V

-8 mA

IOL2 CLKOUT/CLKOUT output current10

(Sink)

VIN = VDD or VSS

VOL = 0.4V

12 mA

IOH2 CLKOUT/CLKOUT output current10

(Source)

VIN = VDD or VSS

VOH = VDD - 0.4V

-12 mA

IIH Input current high VIN = VDD or VSS

VIN = 5.5V

+1.0 µA

IIL Input current low VIN = VDD or VSS

VIN = VSS

-1.0 µA

Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.0 mW/

MHz

IDDQ Quiescent Supply Current VDD = 5.5V

VIN = VDD or VSS

10 µA

RadHard MSI Logic 150

UT54ACTS220

Notes:

1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,

- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but

are guaranteed to VIH(min) and VIL(max).

2. Supplied as a design limit but not guaranteed or tested.

3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed

3,765 pF/MHz.

4. Not more than one output may be shorted at a time for maximum duration of one second.

5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS

at frequency of 1MHz and a signal amplitude of 50mV rms maximum.

6. Maximum allowable relative shift equals 50mV.

7. All specifications valid for radiation dose ≤ 1E6 rads(Si).

8. Power does not include power contribution of any TTL output sink current.

9. Power dissipation specified per switching output.

10. This value is guaranteed based on characterization data, but not tested.

∆IDDQ Quiescent Supply Current Delta

For input under test

VIN = VDD - 2.1V

For all other inputs

VIN = VDD or VSS

VDD = 5.5V

1.6 mA

CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF

COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF

151 RadHard MSI Logic

UT54ACTS220

AC ELECTRICAL DIAGRAM

24MHz TWT2

RCS

DTACK

tPHL or tPLH

tSU tH

or

CLKOUT

CLKIN

CLKOUT

tSUR

TW

T1

48MHz

RadHard MSI Logic 152

UT54ACTS220

AC ELECTRICAL CHARACTERISTICS 2

(VDD = 5.0V ±10%; VSS = 0V1, -55°C < TC < +125°C)

Notes:

1. Maximum allowable relative shift equals 50mV.

2. All specifications valid for radiation dose ≤ 1E6 rads(Si).

3. Guaranteed by design but not tested.

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

tPHL148MHz ↑ to 24MHz ↓0 15 ns

tPLH148MHz ↑ to 24MHz ↑0 15 ns

tPHL224MHz ↓ to DTACK ↓ 0 7 ns

tPLH224MHz ↓ to DTACK ↑0 6 ns

tPLH3DMACK ↑ to DTACK ↑3 16 ns

tPLH4MRST ↓ to 24MHz ↑, DTACK ↑ 3 16 ns

tPHL5CLKIN ↓ to CLKOUT ↓011 ns

tPLH5CLKIN ↑ to CLKOUT ↑ 011 ns

tPHL6CLKIN ↑ to CLKOUT ↓011 ns

tPLH6CLKIN ↓ to CLKOUT ↑011 ns

tSU3DTACK ↓ to 24MHz ↑, setup time 12 ns

tH324MHz ↑ to DTACK ↑, hold time 20 ns

tSUR Setup time from RCS ↓ to 24MHz ↓ 7ns

tWM MRST pulse width low 5ns

tWC CLKIN pulse width 12 ns

fMAX Maximum CLKIN frequency 40 MHz