RadHard MSI Logic 146
UT54ACTS220
PIN DESCRIPTION
FUNCTIONAL TIMING: Single SµMMIT Wait-State
For both read and write memory cycles, DTACK is an input to the SµMMIT E and SµMMIT LXE/DXE. A non-wait state mem-
ory requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to
a logical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SµMMIT E
and SµMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the ris-
ing edge of the clock, the SµMMIT E and SµMMIT LXE/DXE extends the memory cycle.
Pin Number Pin Name Description
2CLKOUT Buffered version of CLKIN.
3CLKOUT Inverted version of CLKIN.
4CLKIN Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.
648MHz 48MHz Clock. The 24MHz clock is created by dividing this signal by two.
8DMACK DMA Acknowledge. This input is generated by the SµMMIT. When high, this signal will
cause DTACK output to be forced high.
9RCS RAM Chip Select. This input is generated by the SµMMIT.
10 MRST Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal
operation tie MRST to VDD through a resistor.
11 TEST Test output signal.
12 DTACK Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the
SµMMIT if the user requires one wait state during the memory transfer.
13 24MHz 24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling
edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high
whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%.
48MHz
24MHz T1T2
DMACK
RCS
DTACK
TW
Figure 1. Functional Timing