2003-2012 Microchip Technology Inc. DS21801G-page 1
MCP2515
Features:
• Implements CAN V2.0B at 1 Mb/s:
- 0 – 8 byte length in the data field
- Standard and extended data and remote
frames
• Receive Buffers, Masks and Filters:
- Two receive buffers with pri oritized message
storage
- Six 29-bit filters
-Two 29-bit masks
• Data Byte Filtering on the First Two Data Bytes
(applies to standard data frames)
• Three Transmit Buffers with Prioritization and
Abort Features
• High-Speed SPI Interface (10 MHz):
- SPI modes 0,0 and 1,1
• One-Shot mode Ensures Message Transmission
is Attempted Only One Time
• Clock Out Pin with Progra mm ab le Prescaler:
- Can be used as a clock source for other
device(s)
• Start-of-Frame (SOF) Signal is Available for
Monitori ng the SOF Signal :
- Can be used for time-slot-based protocols
and/or bus diagnostics to detect early bus
degradation
• Interrupt Output Pin with Selectable Enables
• Buffer Full Output Pins Configurable as:
- Interrup t output for each receive buffer
- General purpose output
• Request-to-Send (RTS) Input Pins Individually
Configurable as:
- Control pi ns to request transmis sion for e ac h
transmit buffer
- General purpose inputs
• Low-Power CMOS Technology:
- Operates from 2.7V – 5.5V
- 5 mA active cur rent ( typical)
- 1 µA standby current (typical) (Sleep mode)
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
Description
Microchip Technology’s MCP2515 is a stand-alone
Controller Area Network (CAN) controller that
implements the CAN specification, version 2.0B. It is
capable of transmitting and receiving both standard
and extended data and remote frames. The MCP2515
has two acceptance masks and six acceptance filters
that ar e us ed to fi lte r out unwa nte d m ess ag es , the reb y
reducing the host MCU’s overhead. The MCP2515
interfac es wi th microc ontr ollers ( MCUs) via an indu stry
stan dard Serial Peri phe ral Inte rfac e (SPI).
Package Types
16
5
TXCAN
RXCAN
VDD
RESET
CS
SO
MCP2515
1
2
3
4
18
17
16
15
SI
SCK
INT
RX0BF
14
13
12
11
RX1BF
10
OSC2
OSC1
CLKOUT/SOF
TX2RTS
5
6
7
8
Vss 9
TX0RTS
TX1RTS
MCP2515
TXCAN
RXCAN
TX0RTS
OSC1
CLKOUT/SOF
OSC2
CS
VDD
RESET
SO
SCK
INT
SI
RX0BF
RX1BF
VSS
TX1RTS
TX2RTS
NC NC
13
12
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
11
10
18-Lead PDIP/ SOIC
20-LEAD TSSOP
2
MCP2515
20-Lead 4x4 QFN*
NC
TX2RTS
TX0RTSSO
SI
OSC2
NC
OSC1
GND
RX1BF
SCK
RXCAN
TXCAN
VDD
RESET
TX1RTSEP
20
119 18 17
3
4
14
13
12
11
6789
21
10
15
CLKOUT
CS
INT
RX0BF
* Includes Exposed Thermal
Pad (EP); see Table 1-1.
Stand-Alone CAN Controller with SPI Interface
MCP2515
DS21801G-page 2 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 3
MCP2515
1.0 DEVICE OVERVIEW
The MCP2515 is a stand-alone CAN controller
developed to simplify applications that require
interfacing with a CAN bus. A simple block diagram of
the MCP2515 is shown in Figure 1-1. The device
consists of three main blocks:
1. The CAN module, which includes the CAN
protocol engine, masks, filters, transmit and
rec eive buffers.
2. The control logic and registers that are used to
configure the device and its operation.
3. The SPI protocol block.
An examp le system im plement ation usi ng the de vice is
shown in Figure 1-2.
1.1 CAN Module
The CAN module handles all functions for receiving
and t ransmitting mes sages on th e CAN bus. Mes sages
are transmitted by first loading the appropriate
message buffer and control registers. Transmission is
initiated by using control register bits via the SPI
interface or by using the transmit enable pins. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against the user-
defined filters to see if it should be moved into one of
the two receive buffers.
1.2 Control Logic
The contro l logic block controls the setu p and operation
of the MCP2515 by interfacing to the other blocks in
order to pass information and control.
Interrupt pins are provided to allow greater system
flexibility. There is one multi-purpose interrupt pin (as
well as specific interrupt pins) for each of the receive
registers that can be used to indicate a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional.
The general purpose interrupt pin, as well as status
regi st er s ( acc es se d v i a t he S PI i n te rf ac e ), c an a ls o be
used to determine when a valid message has been
received.
Additionally, there are three pins available to initiate
immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
these pins is optional, as initiating message
transmissions can also be accomplished by utilizing
control registers, accessed via the SPI interface.
1.3 SPI Protocol Block
The MCU in terfaces to the device via the SPI interf ace.
Writing to, and reading from, all registers is
accomplished using standard SPI read and write
commands, in addition to specialized SPI commands.
FIGURE 1-1: BLOCK DIAGRAM
SPI
Interface
Logic SPI
Bus
INT
CS
SCK
SI
SO
CAN
Protocol
Engine
RXCAN
TXCAN
Control Logic
RX0BF
RX1BF
TX0RTS
TX1RTS
TX2RTS
TX and RX Buffers
Masks and Filters
CAN Module
RESET
Timing
Generation
OSC1
OSC2
CLKOUT
Control
and
Interrupt
Registers
MCP2515
DS21801G-page 4 2003-2012 Microchip Technology Inc.
FIGURE 1- 2: EX AMP LE SY ST E M IMPL E ME NTATI ON
TABLE 1-1: PINOUT DESCRIPTION
Name PDIP/
SOIC
Pin #
TSSOP
Pin # QFN
Pin # I/O/P
Type Description Alternate Pin Function
TXCAN 1 1 19 O Transmit output pin to CAN bus —
RXCAN 2 2 20 I Receive input pin from CAN bus —
CLKOUT 3 3 1 O Clock output pin with programmable
prescaler Start-of-Frame signal
TX0RTS 4 4 2 I T ransmit buffer TXB0 request-to-send.
100 kinternal pull-up to VDD
General purpose di gital input.
100 kinternal pull-up to VDD
TX1RTS 5 5 3 I T ransmit buffer TXB1 request-to-send.
100 kinternal pull-up to VDD
General purpose di gital input.
100 kinternal pull-up to VDD
TX2RTS 6 7 5 I T ransmit buffer TXB2 request-to-send.
100 kinternal pull-up to VDD
General purpose di gital input.
100 kinternal pull-up to VDD
OSC2 7 8 6 O Oscillator output —
OSC1 8 9 7 I Oscillator input External clock input
VSS 9 10 8 P Ground reference for logic and I/O
pins —
RX1BF 10 11 9 O Recei ve buffer RXB1 interrupt pin or
general purpose digital output General purpose digital output
RX0BF 11 12 10 O R ec ei ve buffer RXB0 interr upt pin or
general purpose digital output General purpose digital output
INT 12 13 11 O Interrupt output pin —
SCK 13 14 12 I Clock input pin for SPI interface —
SI 14 16 14 I Data input pin for SPI interface —
SO 15 17 15 O Data output pin for SPI interface —
CS 16 18 16 I Chip select in put pin for SPI interface —
RESET 17 19 17 I Active-low device Reset input —
VDD 18 20 18 P Positive supply for logic and I/O pins —
NC — 6,15 4,13 — No internal connection —
Note: Type Identification: I = Input; O = Output; P = Power
Node
Controller
MCP2515
XCVR
SPI
TX RX
CANH
CANL
Node
Controller
MCP2515
XCVR
SPI
TX RX
Node
Controller
MCP2515
XCVR
SPI
TX RX
2003-2012 Microchip Technology Inc. DS21801G-page 5
MCP2515
1.4 Transmit/Receive Buffers/Masks/
Filters
The MCP2515 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer) and a total of six acceptance filters. Figure 1-3
shows a block diagram of these buffers and their
connection to the protocol engine.
FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
Acceptance Filter
RXF2
R
X
B
1
Identifier
Data Field Data Field
Identifier
Acceptance Mask
RXM1
Acceptance Filter
RXF3
Acceptance Filter
RXF4
Acceptance Filter
RXF5
M
A
B
Acceptance Filter
RXF0
Acceptance Filter
RXF1
R
X
B
0
TXREQ
TXB2
ABTF
MLOA
TXERR
MESSAGE
Message
Queue
Control Transmit Byte Sequencer
TXREQ
TXB0
ABTF
MLOA
TXERR
MESSAGE
CRC<14:0>
Comparator
Receive<7:0>Transmit<7:0>
Receive
Error
Transmit
Error
Protocol
REC
TEC
ErrPas
BusOff
Finite
State
Machine
Counter
Counter
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Transmit
Logic
Bit
Timing
Logic
TX RX Configuration
Registers
Clock
Generator
PROTOCOL
ENGINE
BUFFERS
TXREQ
TXB1
ABTF
MLOA
TXERR
MESSAGE
Acceptance Mask
RXM0
A
c
c
e
p
t
A
c
c
e
p
t
SOF
MCP2515
DS21801G-page 6 2003-2012 Microchip Technology Inc.
1.5 CAN Protocol Engine
The CAN protocol engine combines several func tional
blocks, sh own in Figure 1-4 and described below.
1.5.1 PROTOCOL FINITE STATE
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.2 CYCLIC REDUNDANCY CHECK
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
1.5.3 ERROR MANAGEMENT LOGIC
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
erro r-passive or bus-off.
1.5.4 BIT TIMING LOGIC
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
FIGURE 1-4: CAN PROTOCOL ENGINE BLOCK DIAGRAM
Bit Timing Logic
CRC<14:0>
Comparator
Receive<7:0> Transmit<7:0>
Sample<2:0>
Majority
Decision
StuffReg<5:0>
Comparator
Transmit Logic
Receive
Error Counter
Transmit
Error Counter
Protocol
FSM
RX
SAM
BusMon
Rec/Trm Addr.
RecData<7:0> TrmData<7:0>
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
TX
REC
TEC
ErrPas
BusOff
Interface to Standard Buffer
SOF
2003-2012 Microchip Technology Inc. DS21801G-page 7
MCP2515
2.0 CAN MESSAGE FRAMES
The MCP2515 supports standard data frames,
extended data frames and remote frames (standard
and extended), as defined in the CAN 2.0B
specification.
2.1 Standard Data Frame
The CAN standard data frame is shown in Figure 2-1.
As with all other frames, the frame begins with a Start-
Of-Frame (SOF) b it, whic h is o f the do mina nt st ate an d
allows hard synchronization of all nodes.
The SOF is followed by the arbitration field, consisting
of 12 bits: the 11-bit identifier and the Remote
Transmission Request (RTR) bit. The RTR bit is used
to distinguish a data frame (RTR bit dominant) from a
remote frame (RTR bit recessive).
Following the arbitration field is the control field,
consisting of six bits. The first bit of this field is the
Identifier Extension (IDE) bit, which must be dominant
to specify a standard frame. The following bit, Reserved
Bit Zero (RB0), is reserved and is defined as a dominant
bit by the C AN protocol. Th e remaining four bits of th e
control field are the Data Length Code (DLC), which
specifies the number of bytes of data (0-8 bytes)
contained in the message.
After the control field, is the data field, which contains
any data bytes that are being sent, and is of the length
defined by the DLC (0-8 bytes).
The Cyclic Redundancy Check (CRC) field follows the
data field an d is used to detect transmission errors. The
CRC field consists of a 15-bit CRC sequence, followed
by the recessive CRC Delimiter bit.
The final field is the two-bit Acknowledge (ACK) field.
During the ACK Slot bit, the transmitting node sends
out a recessive bit. Any node that has received an
error-free f r am e a cknow l edg es the c orrect recepti on of
the frame by sending back a dominant bit (regardless
of whether the node is configured to accept that
specific message or not). The recessive acknowledge
delimi ter comple tes the ack nowled ge field an d may not
be overwritten by a dominant bit.
2.2 Extended Data Frame
In the extended CAN data frame, shown in Figure 2-2,
the SOF bit is followed by the arbitration field, which
consists of 32 bits. The first 11 bits are the Most
Significant bits (MSb) (Base-lD) of the 29-bit identifier.
These 11 bits are followed by the Substitute Remote
Request (SRR) bit, which is defined to be recessive.
The SRR bit is followed by the lDE bit, which is
recessive to denote an extended CAN frame.
It should be noted that if arbitration remains unresolved
after t ransmission of the first 11 bits of the identifie r, and
one of the nodes involved in the arbitration is sending
a standard CAN frame (11-bit identifier), the standard
CAN frame w i ll win arbi trat ion due to the ass erti on of a
dominant lDE bit. Also, the SRR bit in an extended
CAN fram e must be reces si ve to al low the asse rtio n of
a dominant RTR bit by a node that is sending a
standard CAN remote frame.
The SRR and lDE bits are followed by the remaining
18 bits of the identifier (Extended lD) and the remote
transmission request bit.
To enable standard and extended frames to be sent
across a share d netwo rk, the 29-bit ext ended messag e
identifi er i s sp lit into 11-bit (M os t Si gni fic ant ) an d 18-bit
(Least Significant) sections. This split ensures that the
lDE bit can remain at the same bit position in both the
standard and extended frames.
Following the arbitration field is the six-bit control field.
The first two bits of this field are reserved and must be
dominant. The remaining four bits of the control field
are the DLC, which specifies the number of data bytes
contained in the message .
The remaining portion of the frame (data field, CRC
field, acknowledge field, end-of-frame and
intermission) is constructed in the same way as a
standard data frame (see Se ction 2.1 “S t andard Da t a
Frame”).
2.3 Remote Frame
Normally, data transmission is performed on an
autonomous basis by the data source node (e.g., a
sensor sending out a data frame). It is possible,
however, for a destination node to request data from
the source. To accomplish this, the destination node
sends a remote frame with an identifier that matches
the identifier of the required data frame. The
appropriate data source node will then send a data
frame in response to the remote frame request.
There are two differences between a remote frame
(shown in Figure 2-3) and a data frame. First, the RTR
bit is at the recessive state and, second, there is no
data field. In the event of a data frame and a remote
frame with the same identifier being transmitted at the
same time, the data frame wins arbitration due to the
dominant RTR bit following the identifier. In this way,
the node that transmitted the remote frame receives
the desired data immediately.
2.4 Error Frame
An error frame is generate d by any no de that detect s a
bus error. An error frame, sho wn in Figure 2-4, consists
of two fields: an error flag field followed by an error
delimiter field. There are two types of error flag fields.
The type of er ror flag fie ld sent de pends upon the e rror
statu s of the no de that detec t s and genera tes the error
flag field.
MCP2515
DS21801G-page 8 2003-2012 Microchip Technology Inc.
2.4.1 ACTIVE ERRORS
If an error-active node detects a bus error, the node
interrupts transmission of the current message by
generating an active error flag. The active error flag is
composed of six consecutive dominant bits. This bit
sequen ce activ ely violat es the bi t-stuf fing ru le. All oth er
stat ions reco gnize the resulting bit-stuf fing erro r and, in
turn, generate error frames themselves, called error
echo flags.
The error flag field, therefore, consists of between six
and twelve consecutive dominant bits (generated by
one or more nodes). The error delimiter field (eight
recessive bits) completes the error frame. Upon
completion of the error frame, bus activity returns to
normal a nd the interrupt ed node attemp ts to rese nd the
aborted message.
2.4.2 PASSIVE ERRORS
If an error-passive node detects a bus error, the node
transmits an error-passive flag followed by the error
delimiter field. The error-passive flag consists of six
consecutive recessive bits. The error frame for an error-
passive node consists of 14 recessive bits. From this, it
follows that unless the bus error is detected by an error-
active node or the transmitt ing node, the message will
continue transmission because the error-passive flag
does not interfere with the bus.
If the transmitting node generates an error-passive flag,
it will cause other nodes to generate error frames due to
the resulting bit-stuffing violation. After transmission of
an error fr ame, an error -passive node must wait for six
consecutive recessive bits on the bus before attempting
to rejoin bus communications.
The error delim ite r consists of e igh t re ce ss iv e b it s , an d
allows the bus nodes to restart bus communications
cleanly after an error has occurred.
2.5 Overload Frame
An overload frame, shown in Figure 2-5, has the same
format as an active-error frame. An overload frame,
however, can only be generated during an interframe
space. In this way, an overload frame can be
differentiated from an error frame (an error frame is
sent during the transmission of a message). The
overload frame consists of two fields: an overload flag
followed by an overload delimiter. The overload flag
consis ts of six do minan t bit s fo llowed by overlo ad flag s
generated by other nodes (and, as for an active error
flag, giving a maximum of twelve dominant bits). The
overload delimiter consists of eight recessive bits. An
overloa d frame can be genera ted by a node as a re sult
of two conditions:
1. The node detects a dominant bit during the
interframe space, an illegal condition.
Exception: The dominant bit is detected during
the third bit of IFS. In th is case, th e rece ivers will
interpret this as a SOF.
2. Due to internal conditions, the node is not yet
able to begin reception of the next message. A
node may generate a maximum of two
sequential overload frames to delay the start of
the next message.
2.6 Interframe Space
The interframe space separates a preceding frame (of
any type) from a subsequent data or remote frame.
The interframe space is composed of at least three
recessive bits called the Intermission. This allows
nodes time for internal processing before the start of
the next message frame. After the intermission, the
bus line remains in the recessive state (bus idle) until
the next transmission starts.
Note: Error echo flags typically occur when a
localized disturbance causes one or more
(but not all) nodes to send an error flag.
The remaining nodes generate error flags
in response (echo) to the original error
flag.
Note: Case 2 should never occur with the
MCP2515 due to very short internal
delays.
2003-2012 Microchip Technology Inc. DS21801G-page 9
MCP2515
FIGU RE 2-1: S T AN DARD DAT A FR AM E
0 0 0011 1 1 1 1 1 1
Start-of-Frame
Data Frame (number of bits = 44 + 8N)
12
Arbitration Field
ID 10
11
ID3
ID0
Identifier
Message
Filtering
St ored in Buffers
RTR
IDE
RB0
DLC3
DLC0
6
4
Control
Field
Data
Length
Code
Reserved Bit
8N (0N8)
Data Field
88
Stored in T r ansmit/Receive Buffers
Bit-stuffing
16
CRC Field
15
CRC
7
End-of-
Frame
CRC Del
Ack Slot Bit
ACK Del
IFS
1 1 11
MCP2515
DS21801G-page 10 2003-2012 Microchip Technology Inc.
FIGU RE 2-2: EXTE NDED DATA FRAME
0 1 1 0 0 0 1
Start-Of-Frame
Arbitration Field
32
11
ID10
ID3
ID0
IDE
Identifier
Message
Filtering Stored in Buffers
SRR
EID17
EID0
RTR
RB1
RB0
DLC3
18
DLC0
6
Control
Field4
Reserved bits
Data
Length
Code
Stored in Transmit/Receive Buffers
8 8
Data Frame (number of bits = 64 + 8N)
8N (0 N 8)
Data Field
11111111
16
CRC Field
15
CRC
CRC Del
Ack Slot Bit
ACK Del
End-of-
Frame
7
Bit-stuffing
IFS
Extended Identifier
1 1 1
2003-2012 Microchip Technology Inc. DS21801G-page 11
MCP2515
FIGURE 2-3: REMOTE FRAME
0 1 1 1 0 0
Start-Of-Frame
Arbitration Field
32
11
ID10
ID3
ID0
IDE
Identifier
Message
Filtering
SRR
EID17
EID0
RTR
RB1
RB0
DLC3
18
DLC0
6
Control
Field4
Reserved bits
Data
Length
Code
Extended Identifier
1 1 1 1 1 1 1 1 1
16
CRC Field
15
CRC
CRC Del
Ack Slot Bit
ACK Del
End-of-
Frame
7
Remote Frame with Extended Identifier
1 1 1
IFS
No data field
MCP2515
DS21801G-page 12 2003-2012 Microchip Technology Inc.
FIGURE 2-4: ACTIVE ERROR FRAME
0 0 00
Start-Of-Frame
Interrupted Data Frame
12
Arbitration Field
ID 10
11
ID3
ID0
Identifier
Message
Filtering
RTR
IDE
RB0
DLC3
DLC0
6
4
Control
Field
Data
Length
Code
Reserved Bit
8N (0N8)
Data Field
88
Bit-stuffing
0000000 00111111110
Data Frame or
Remote Frame
Error Frame
6
Error
Flag
£ 6
Echo
Error
Flag
8
Error
Delimiter
Inter-Frame Space or
Overload Frame
2003-2012 Microchip Technology Inc. DS21801G-page 13
MCP2515
FIGURE 2-5: OVERLOAD FRAME
0 1 00111111111
Start-Of-Frame
Remote Frame (number of bits = 44)
12
Arbitration Field
ID 10
11
ID0
RTR
IDE
RB0
DLC3
DLC0
6
4
Control
Field
16
CRC Field
15
CRC
7
End-of-
Frame
CRC Del
Ack Slot Bi t
ACK Del
000000011111111
Overload Frame
End-of-Frame or
Error D elimiter or
Overload Delimiter 6
Overload
Flag Overload
Delimiter
8Inter-Frame Space or
Error Frame
MCP2515
DS21801G-page 14 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 15
MCP2515
3.0 MESSAGE TRANSMISSION
3.1 Transmi t B u ff e rs
The MC P2515 impl ements t hree transmit buffers. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into the device memory map.
The first byte, TXBnCTRL, is a control register
associated with the message buffer. The information in
this register determines the conditions under which the
messa ge will b e tran smit ted and i ndica tes the sta tus of
the message transmission (see Register 3-2).
Five by tes a r e u se d to ho ld the s t andard an d extende d
identifiers, as well as other message arbitration
information (see Register 3-4 through Register 3-7).
The last eight bytes are for the eight possible data
bytes of the message to be transmitted (see
Register 3-8).
At a minimum, the TXBnSIDH, TXBnSIDL and
TXBnDLC registers must be loaded. If data bytes are
present in the message, the TXBnDm registers must
also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the TXBnSIDL.EXIDE bit set.
Prior to sending the message, the MCU must initialize
the CANINTE.TXInE bit to enable or disable the
generation of an interrupt when the message is sent.
3.2 Transmi t P r io r ity
Transmit priority is a prioritization within the MCP2515
of the pending transmittable messages. This is
independent from, and not necessarily related to, any
priori tization implicit i n the message arbitratio n scheme
built into the CAN protocol.
Prior to sending the SOF, the priority of all buffers that
are qu eued f or trans mission is com pare d. The t ransm it
buffer with the highest priority will be sent first. For
example, if transmit buf fer 0 has a higher priority setting
than transmit buffer 1, buffer 0 will be sent first.
If two buffers have the same priority setting, the buffer
with the highest buffer number will be sent first. For
example, if transmit buffer 1 has the same priority
setting as transmit buffer 0, buffer 1 will be sent first.
There are four levels of transmit priority. If
TXBnCTRL.TXP<1:0> for a particular message buffer
is set to 11, that buf fe r has the highest possible priority.
If TX BnCTRL. TXP<1: 0> for a par ticular message buf-
fer is 00, that buffer has the lowest possible priority.
3.3 Initiating Transmission
In order to initiate message transmission, the
TXBnCTRL.TXREQ bit must be set for each buffer to
be transmitted. This can be accomplished by:
• Writing to the register via the SPI write command
• Sendi ng the SPI RT S comm an d
• Setting the TXnRTS pin low for the particular
transmit buffer(s) that are to be transmitted
If transmission is initiated via the SPI interface, the
TXREQ bit can be set at the same time as the TXP
priori ty bits.
When TXBnCTRL.TXREQ is set, the TXBnCTRL.ABTF,
TXBnCTRL.MLOA and TXBnCTRL.TXERR bits will be
cleared automatically.
Once the transmission has completed successfully , the
TXBnCTRL.TXREQ bit will be cleared, the
CANINTF.TXnIF bit will be set and an interrupt will be
generated if the CANINTE.TXnIE bit is set.
If the message transmission fails, the
TXBnCTRL.TXREQ wil l remain set. Th is in dic at es th at
the message is still pending for transmission and one
of the following condition flags will be set:
• If the message started to transmit but encoun-
tered an error condi tion , the TXBn CTRL.TXERR
and the CANINTF.MERRF bits will be set and an
interrupt will be generated on the INT pin if the
CANINTE.MERRE bit is set
• If the message is lost, arbitration at the
TXBnCTRL.MLOA bit will be set
3.4 One-Shot Mode
One-Shot mode ensures that a message will only
attempt to transmit one time. Normally, if a CAN
message loses arbitration, or is destroyed by an error
frame, the message is retransmitted. With One-Shot
mode en abled, a message will on ly atte mp t to t r ans m it
one time, regardless of arbitration loss or error frame.
One-Shot mode is required to maintain time slots in
deterministic systems, such as TTCAN.
Note: The TXBnCTRL.TXREQ bit must be clear
(indicating the transmit buffer is not
pending transmission) before writing to
the transmit buffer.
Note: Setting the TXBnCTRL.TXREQ bit does
not initiate a message transmission. It
merely flags a message buffer as being
ready for transmission. Transmission will
start when the device detects that the bus
is available.
Note: If One-Shot mode is enabled
(CANCTRL.OSM), the above conditions
will still exist. However, the TXREQ bit will
be cleared and the message will not
attempt transmission a second time.
MCP2515
DS21801G-page 16 2003-2012 Microchip Technology Inc.
3.5 TXnRTS PINS
The TXnRTS pins a re input pi ns that ca n be co nfigured
as:
• Request-to-send inputs, which provide an
alternative means of initiating the transmission of
a message from any of the transmit buffers
• Standard digital inputs
Configuration and control of these pins is accomplished
using the TXRTSCTRL register (se e Register 3-3). The
TXRTSCTRL register can only be modified when the
MCP2515 is in Configuration mode (see Section 10.0
“Modes of Operation”). If configured to operate as a
request-to-send pin, the pin is mapped into the
respective TXBnCTRL.TXREQ bit for the transmit
buffer. The TXREQ bit is latched by the falling edge of
the TXnRTS pin. The TXnRTS pins are designed to
allow them to be tied directly to the RXnBF pins to
automatically initiate a message transmission when the
RXnBF pin goes low.
The TXnRTS pins have internal pull-up resistors of
100 k (nominal).
3.6 Aborting Transmission
The MCU c an re que st to abort a m es sag e in a sp ec ific
message buffer by clearing the associated
TXBnCTRL.TXREQ bit.
In addition, all pending messages can be requested to
be aborted by setting the CANCTRL.ABAT bit. This bit
MUST be reset (typically after the TXREQ bits have
been verified to be cleared) to continue transmitting
messages. The TXBnCTRL.ABTF flag will only be set
if the a bort w as re que ste d v ia the CANC TRL .ABAT bit.
Aborting a message by resetting the TXREQ bit does
NOT cause the ABTF bit to be set.
Note 1: Messages that were transmitting when
the abort was requested will continue to
transmit. If the message does not
successfully complete transmission (i.e.,
lost arbitration or was interrupted by an
error frame), it will then be aborted.
2: When One-Shot mode is enabled, if the
message is interrupted due to an error
frame or loss of arbitration, the
TXBnCTRL.ABTF bit will set.
2003-2012 Microchip Technology Inc. DS21801G-page 17
MCP2515
FIGURE 3-1: TRANSMIT MESSAGE FLOWCHART
Start
Is
CAN bus available
to start transmission?
No
Examine TXBnCTRL.TXP <1:0> to
Are any
TXBnCTRL.TXREQ
?
bits = 1
The message transmission
sequence begins when the
device determines that the
TXBnCTRL. TXREQ for a ny of
the transmit registers has been
set.
Clear:
TXBnCTRL.ABTF
TXBnCTRL.MLOA
TXBnCTRL.TXERR
Yes
is
TXBnCTRL.TXREQ=0
or CANC TRL . ABAT=1
Clearing the TxBnCTRL.TXREQ bit
while it is set, or setting the CANC-
TRL.ABAT bit before the message
has started transmission, will abort
the message.
No
Transmit Message
Was
Message Transmitted
Successfully?
No
Yes
Clear TxBnCTRL.TXREQ
CANINTE.TXnIE=1?
Generate
Interrupt
Yes
Message
Yes
Set
Set
TxBnCTRL.TXERR
Lost
Determine Highest Priority Message
No
?
Set
TxBNCTRL.MLOA
The CANINTE.TXnIE bit
determines if an interrupt
should be generated when
a message is successfully
transmitted.
GOTO START
CANTINF.TXnIF
Yes
No
Message error
or
Lost arbitration
Arbitration
Error
CANINTE.MEERE?
No Generate
Interrupt
Yes
Set
CANTINF.MERRF
?
MCP2515
DS21801G-page 18 2003-2012 Microchip Technology Inc.
REGISTER 3-1: TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER
(ADDRESS: 30h, 40h, 50h)
U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0
— ABTF MLOA TXERR TXREQ — TXP1 TXP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ABTF: Message Aborted Flag bit
1 = Message was aborted
0 = Message completed transmission successfully
bit 5 MLOA: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbi tration while being sent
bit 4 TXERR: Transmission Error Detected bit
1 = A bus error occurred while the message was being transmitted
0 = No bus er ror occurred whil e the message was being transmitted
bit 3 TXREQ: Message Transmit Request bit
1 = Buffer is currently pending transmission
(MCU sets this bit to request message be transmitted - bit is automatically cleared when
the message is sent)
0 = Buffer is not currently pending transmission
(MCU can clear this bit to request a message abort)
bit 2 Unimplemented: Read as ‘0’
bit 1-0 TXP<1:0>: Transmit Buffer Priority bits
11 = Highest Message Priority
10 = High Intermediate Message Priority
01 = Low Intermediate Message Priority
00 = Lowest Message Priority
2003-2012 Microchip Technology Inc. DS21801G-page 19
MCP2515
REGISTER 3-2: TXRTSCTRL – TXnRTS PIN CONTROL AND STATUS REGISTER
(ADDRESS: 0Dh)
U-0 U-0 R-x R-x R-x R/W-0 R/W-0 R/W-0
—— B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 B2RTS: TX2RTS Pin Stat e bit
- Reads state of TX 2RTS pin w hen i n Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 4 B1RTS: TX1RTX Pin Stat e bit
- Reads state of TX 1RTS pin w hen i n Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 3 B0RTS: TX0RTS Pin Stat e bit
- Reads state of TX 0RTS pin w hen i n Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 2 B2RTSM: TX2RTS Pin mode bit
1 = Pin is used to request message transmission of TXB2 buffer (on falling edge)
0 = Digital input
bit 1 B1RTSM: TX1RTS Pin mode bit
1 = Pin is used to request message transmission of TXB1 buffer (on falling edge)
0 = Digital input
bit 0 B0RTSM: TX0RTS Pin mode bit
1 = Pin is used to request message transmission of TXB0 buffer (on falling edge)
0 = Digital input
REGISTER 3-3: TXBnSIDH – TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH
(ADDRESS: 31h, 41h, 51h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 SID<10:3>: Standard Identifier bits
MCP2515
DS21801G-page 20 2003-2012 Microchip Technology Inc.
REGISTER 3-4: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW
(ADDRESS: 32h, 42h, 52h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID2 SID1 SID0 — EXIDE —EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 SID<2:0>: Standard Identifier bits
bit 4 Unimplemented: Reads as ‘0’
bit 3 EXIDE: Extended Identifier Enable bit
1 = Message will transmit extended identifier
0 = Message will transmit standard identifier
bit 2 Unimplemented: Reads as ‘0’
bit 1-0 EID<17:16>: Extend ed Ide ntif ier bits
REGISTER 3-5: TXBnEID8 – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 33h, 43h, 53h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<15:8>: Extended Identifier bits
REGISTER 3-6: TXBnEID0 – TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW
(ADDRESS: 34h, 44h, 54h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<7:0>: Extended Identifier bits
2003-2012 Microchip Technology Inc. DS21801G-page 21
MCP2515
REGISTER 3-7: TXBnDLC - TRANSMIT BUFFER n DATA LENGTH CODE
(ADDRESS: 35h, 45h, 55h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—RTR—— DLC3 DLC2 DLC1 DLC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Reads as ‘0’
bit 6 RTR: Remote Transmission Request bit
1 = Transmitted Message will be a Remote Transmit Request
0 = Transmitted Message will be a Data Frame
bit 5-4 Unimplemented: Reads as ‘0’
bit 3-0 DLC<3:0>: Data Length Code bits
Sets the number of data bytes to be transmitted (0 to 8 bytes)
Note: It is possible to set the DLC to a value greater than eight, however only eight bytes are
transmitted
REGISTER 3-8: TXBnDm – TRANSMIT BUFFER n DATA BYTE m
(ADDRESS: 36h - 3Dh, 46h - 4Dh, 56h - 5Dh)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Bytes m
MCP2515
DS21801G-page 22 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 23
MCP2515
4.0 MESSA GE RE C EPTIO N
4.1 Receive Message Buffering
The MCP2515 includes two full receive buffers with
multiple acceptance filters for each. There is also a
sep arate Mes sage Assem bly Buf fer ( MAB) tha t acts as
a third receive buffer (see Figure 4-2).
4.1.1 MESSAGE ASSEMBLY BUFF ER
Of the three receive buffers, the MAB is always
commi tted t o r eceiv ing t he ne xt me ss age f rom th e bus .
The MAB assembles all messages received. These
messages will be transferred to the RXBn buffe rs (see
Register 4-4 to Register 4-9) only if the acceptance
filter criteria is met.
4.1.2 RXB0 AND R XB1
The remaining two receive buffers, called RXB0 and
RXB1, can receive a complete message from the
protocol engine via the MAB. The MCU ca n access one
buffer, while the other buffer is available for message
reception, or for holding a previously received
message.
4.1.3 RECEIV E FLAGS/INTE RRUP TS
When a message is moved into either of the receive
buff ers, the a ppropriate CANINTF.R XnIF bit is set. Thi s
bit must be cl eared by the MCU in order to a llow a new
message to be received into the buffer. This bit
provide s a posi tive l ockou t to ensu re that the MCU has
finished with the message before the MCP2515
attempt s to load a ne w message into the receive bu ffer .
If the CANINTE.RXnIE bit is set, an interrupt will be
generated on the INT pin to indicate that a valid
message has been received. In addition, the
associated RXnBF pin will drive low if configured as a
receive buffer full pin. See Section 4.4 “RX0BF and
RX1BF Pins” for details.
4.2 Receive Prio rity
RXB0, the hi gher prio rity buf fer, has one m ask and tw o
message acceptance filters associated with it. The
receive d m es sag e is ap pli ed to the ma sk and filt ers for
RXB0 first.
RXB1 is the lower priority buffer, with one mask and
four acceptance filters associated with it.
In addition to the message being applied to the RB0
mask and filters first, the lower number of acceptance
filters makes the match on RXB0 more restrictive and
implies a higher priority for that buffer.
When a message is received, bits <3:0> of the
RXBnCTRL register will indicate the acceptance filter
number that enabled reception and whether the
received message is a remote transfer request.
4.2.1 ROLLOVER
Addition ally , the RXB0C TRL register can be co nfigured
such that, if RXB0 contains a valid message and
another valid message is received, an overflow error
will not occur and the new message will be moved into
RXB1, regardless of the acceptance criteria of RXB1.
4.2.2 RXM BITS
The RXBnCTRL.RXM bits set special receive modes.
Normally, these bits are cleared to 00 to enable
reception of all valid messages as determined by the
appropriate acceptance filters. In this case, the
determination of whether or not to receive standard or
extended messages is determined by the
RFXnSIDL.EXIDE bit in the acceptance filter register.
If the RXBnCTRL.RXM bits are set to 01 or 10, the
receiver will only accept messages with standard or
extended identifiers, respectively. If an acceptance
filter ha s the RFXnSI DL.EXIDE bit set suc h that it doe s
not correspond with the RXBnCTRL.RXM mode, that
acceptance filter is rendered useless. These two
modes of RXBnCTRL.RXM bits can be used in
systems where it is known that only standard or
extended messages will be on the bus.
If the RXBnCTRL.RXM bit s are se t to 11, the buf fer will
receive all messages, regardless of the values of the
acceptance filters. Also, if a message has an error
before the EOF, that portion of the message assembled
in the MAB before the error frame will be loaded into th e
buf fer. This m ode has some v alue in debuggi ng a CAN
system and would not be used in an actual system
environment.
Note: The entire content of the MAB is moved
into the receive buffer once a message is
accepted. This means, that regardless of
the type of identifier (standard or
extended) and the number of data bytes
received, the entire receive buffer is
overwritten with the MAB contents.
Therefore, the contents of all registers in
the buffer must be assumed to have been
modified when any message is received.
MCP2515
DS21801G-page 24 2003-2012 Microchip Technology Inc.
4.3 Start-of-Frame Signal
If enabled, the Start-Of-Frame signal is generated on
the SOF pin at the beginning of each CAN message
detected on the RXCAN pin.
The RXCAN pin monitors an idle bus for a recessive-
to-dominant edge. If the dominant condition remains
until the sample point, the MCP2515 interprets this as
a SOF and a SOF pulse is generated. If the dominant
condition does not remain until the sample point, the
MCP2515 interprets this as a glitch on the bus and no
SOF signal is generated. Figure 4-1 illustrates SOF
signalling and glitch-filtering.
As with One-Shot mode, one use for SOF signaling is
for TTCAN-type systems. In addition, by monitoring
both the RXCAN pin and the SOF pin, an MCU can
detect early physical bus problems by detecting small
glitches before they affect the CAN communications.
4.4 RX0BF and RX1BF Pins
In addition to the INT pin, which provides an interrupt
signal to the MCU for many different conditions, the
receive buffer full pins (RX0BF and RX1BF) can be
used to i ndi cate that a v al id m es sa ge h as bee n loaded
into RXB0 or RXB1, respectively. The pins have three
different configurations (Register 4-1):
1. Disabled
2. Buffer Full Interru pt
3. Digital Output
4.4.1 DISABLED
The RXBnBF pins can be disabled to the high-
impedance state by clearing BFPCTRL.BnBFE.
4.4.2 CONFIGURED AS BUFFER FULL
The RXBnBF pins can be configured to act as either
buffer full interrupt pins or as standard digital outputs.
Configuration and status of these pins is available via
the BFPCTRL register (Register 4-3). When set to
operate i n Interrupt mode (by setting BFPCT RL.BxBFE
and BFPCTRL.BxBFM bits), these pins are active-low
and are mapped to the CANINTF.RXnIF bit for each
receive buffer. When this bit goes high for one of the
receive buffers (indicating that a valid message has
been loaded into the buffer), the corresponding
RXBnBF pin will go low. When the CANINTF.RXn IF bit
is cleared by the MCU, the corresponding interrupt pin
will go to the logic-high state until the next message is
loaded into the receive buffer.
FIGURE 4-1: START-OF-FRAME SIGNALING
START-OF-FRAME BIT
Sample
Point
ID BIT
RXCAN
SOF
EXPECTED START-OF-FRAME BIT
Sample
Point BUS IDLE
RXCAN
SOF
Expected
Normal SOF Signaling
Glitch-Filtering
2003-2012 Microchip Technology Inc. DS21801G-page 25
MCP2515
4.4.3 CONFIGURED AS DIGITAL OUTPUT
When use d as digital outputs, the BFPCTRL.BxBFM bit
must be cleare d and BF PCTRL.BnBFE m ust be s et for
the associated buffer. In this mode, the state of the pin
is control led by the BFPCTRL .BnBFS bit s. W rit ing a ‘ 1’
to the BnBFS bit w i ll c aus e a hi gh l eve l to b e driv en on
the associated buffer full pin, while a ‘0’ will cause the
pin to drive low. When using the pins in this mode, the
stat e of the p in should be m odified o nly by us ing the Bit
Modify SPI command to prevent glitches from
occu rring on either of the buffer full pi ns.
TABLE 4-1: CONFIGURING RXNBF PINS
FIGURE 4-2: RECEIVE BUFFER BLOCK DIAGRAM
BnBFE BnBFM BnBFS Pin Status
0XXDisabled, high- impedance
11XReceive buffer i nterrupt
100Digital output = 0
101Digital output = 1
Acceptance Mask
RXM1
Acceptance Filter
RXF2
Acceptance Filter
RXF3
Acceptance Filter
RXF4
Acceptance Filter
RXF5
Acceptance Mask
RXM0
Acceptance Filter
RXF0
Acceptance Filter
RXF1
Identifier
Data Field Data Field
Identifier
Note: Messag es rece iv ed in the M AB are intially
applied to the mas k and f ilters o f RXB0. In
addition, only one filter m atch occurs (e.g. ,
if the message matches both RXF0 and
RXF2, the match will be for RXF0 and the
message will be moved into RXB0).
A
c
c
e
p
t
A
c
c
e
p
t
R
X
B
0
R
X
B
1
M
A
B
MCP2515
DS21801G-page 26 2003-2012 Microchip Technology Inc.
FIGURE 4-3: RECEIVE FLOW FLOWCHART
Set RXBF0
Start
Detect
Start of
Message?
Valid
Message
Received?
Generate
Error
Meets
a filter criteria
Is
CANINTF.RX0IF = 0?
Go to Start
Move message into RXB0
Set RXB0CTRL.FILHIT <2:0>
Is
CANINTF.RX1 IF = 0?
Move message into RXB1
Set CANINTF.RX1IF = 1
Yes
No
Generate
Interrupt on INT
Yes Yes
No No
Yes
Yes
No
No
Yes
Yes
Frame
No Yes
No
Begin Loading Message into
Message Assembly B uffer (MAB)
according to which filter criteria
was met
Set RXB0CTRL.FILHIT <0>
according to which filter criteria
Set CANSTAT <3:0> accord-
ing to which receive buffer
the m essage was lo aded i nto
Is
RXB0CTRL.BUKT = 1?
Generate Overflow Error:
Set EFLG.RX1OVR
Is
CANINTE.ERRIE = 1?
No
Go to Start
Yes
No
Are
BFPCTRL.B0BFM = 1
BF1CTRL.B0BFE = 1?
and Pin = 0
No
Set RXBF1
Pin = 0
No
Yes
Yes
CANINTE.RX0IE = 1?CANINTE.RX1IE = 1?
RXB1
RXB0
Set EFLG.RX0OVR
Generate Over flow Erro r:
Set CANINTF.RX0IF = 1
Are
BFPCTRL. B1 BFM =
1
BF1CTRL.B1BFE =
1
?
and
Meets
a filter criteria
for RXB1?
for RXB0? No Yes
Generate
Interrupt on INT
Determines if the receive
register is empty and able
to accept a new message
Determines if RXB0 can roll
over into RXB1, if it is full.
2003-2012 Microchip Technology Inc. DS21801G-page 27
MCP2515
REGISTER 4-1: RXB0CTRL – RECEIVE BUFFER 0 CONTROL
(ADDRESS: 60h)
U-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0
— RXM1 RXM0 — RXRTR BUKT BUKT1 FILHIT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-5 RXM<1:0>: Receive Buffer Operating mode bits
11 = Turn mask /filters off; receive any message
10 = Receive only valid messages with extended identifiers that meet filter criteria
01 = Receive only valid messages with standard identifiers that meet filter criteria. Extended ID filter
registers RXFnEID8:RXFnEID0 are ignore d for the messages with standard IDs.
00 = Receive al l v al id messages using ei ther standard or ext ended ide ntifie rs that me et filter crit eria.
Extended ID filter registers RXFnEID8:RXFnEID0 are applied to first two bytes of data in the
messages with standard IDs.
bit 4 Unimplemented: Read as ‘0’
bit 3 RXRTR: Received Remote Transfer Request bit
1 = Remote Transfer Request Received
0 = No Remote Transfer Request Received
bit 2 BUKT: Rollover Enable bit
1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full
0 = Rollover disabled
bit 1 BUKT1: Read-only Copy of BUKT bit (used internally by the MCP2515)
bit 0 FILHIT0: Filter Hit bit – indicates which acceptance filter enabled reception of message
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)
Note: If a rollover from RXB0 to RXB1 occurs, the FILHIT bit will reflect the filter that accepted
the message that rolled over.
MCP2515
DS21801G-page 28 2003-2012 Microchip Technology Inc.
REGISTER 4-2: RXB1CTRL – RECEIVE BUFFER 1 CONTROL
(ADDRESS: 70h)
U-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0
— RXM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-5 RXM<1:0>: Receive Buffer Operating mode bits
11 = Turn mask/filters off; receive any message
10 = Receive only valid messages with extended identifiers that meet filter criteria
01 = Receive only valid messages with standard identifiers that meet filter criteria
00 = Receive all valid messages using either standard or extended identifiers that meet filter criteria
bit 4 Unimplemented: Read as ‘0’
bit 3 RXRTR: Received Remote Transfer Request bit
1 = Remote Transfer Request Received
0 = No Remote Transfer Request Received
bit 2-0 FILHIT<2:0>: Filter Hit bits - indicates which acceptance filter enabled reception of message
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL)
000 = Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL)
2003-2012 Microchip Technology Inc. DS21801G-page 29
MCP2515
REGISTER 4-3: BFPCTRL – RXnBF PIN CONTROL AND STATUS
(ADDRESS: 0Ch)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 B1BFS: RX1BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ wh en RX1BF is co nfig ure d as interr upt pin
bit 4 B0BFS: RX0BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ wh en RX0BF is co nfig ure d as interr upt pin
bit 3 B1BFE: RX1BF Pin Function Enable bit
1 = Pin function enabled, operation mode determined by B1BFM bit
0 = Pin function disabled, pin goes to high-impedance state
bit 2 B0BFE: RX0BF Pin Function Enable bit
1 = Pin function enabled, operation mode determined by B0BFM bit
0 = Pin function disabled, pin goes to high-impedance state
bit 1 B1BFM: RX1BF Pin Operation mode bit
1 = Pin is used as interrupt when valid message loaded into RXB1
0 = Digital Output mode
bit 0 B0BFM: RX0BF Pin Operation mode bit
1 = Pin is used as interrupt when valid message loaded into RXB0
0 = Digital Output mode
REGISTER 4-4: RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER HIGH
(ADDRESS: 61h, 71h)
R-x R-x R-x R-x R-x R-x R-x R-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 SID<10:3>: Standard Identifier bits
These bits contain the eight Most Significant bits of the Standard Identifier for the received message
MCP2515
DS21801G-page 30 2003-2012 Microchip Technology Inc.
REGISTER 4-5: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW
(ADDRESS: 62h, 72h)
R-x R-x R-x R-x R-x U-0 R-x R-x
SID2 SID1 SID0 SRR IDE —EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 SID<2:0>: Standard Identifier bits
These bits contain the three Least Significant bits of the Standard Identifier for the received message
bit 4 SRR: Standard Frame Remote Transmit Request bit (valid only if IDE bit = ‘0’)
1 = Standard Frame Remote Transmit Request Received
0 = Standard Data Frame Received
bit 3 IDE: Extended Ide ntif ier Fla g bit
This bit indicates whether the received message was a Standard or an Extended Frame
1 = Received message was an Extended Frame
0 = Received message was a Standard Frame
bit 2 Unimplemented: Reads as ‘0’
bit 1-0 EID<17:16>: Extend ed Ide ntif ier bits
These bits contain the two Most Significant bits of the Extended Identifier for the received message
REGISTER 4-6: RXBnEID8 – RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 63h, 73h)
R-x R-x R-x R-x R-x R-x R-x R-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<15:8>: Extended Identifier bits
These bits hold bits 15 through 8 of the Extended Identifier for the received message
2003-2012 Microchip Technology Inc. DS21801G-page 31
MCP2515
REGISTER 4-7: RXBnEID0 – RECEIVE BUFFER n EXTENDED IDENTIFIER LOW
(ADDRESS: 64h, 74h)
R-x R-x R-x R-x R-x R-x R-x R-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<7:0>: Extended Identifier bits
These bits hold the Least Significant eight bits of the Extended Identifier for the received message
REGISTER 4-8: RXBnDLC – RECEIVE BUFFER n DATA LENGTH CODE
(ADDRESS: 65h, 75h)
R-x R-x R-x R-x R-x R-x R-x R-x
— RTR RB1 RB0 DLC3 DLC2 DLC1 DLC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Reads as ‘0’
bit 6 RTR: Extended Frame Remote Transmission Request bit
(valid only when RXBnSIDL.IDE = 1)
1 = Extended Frame Remote Transmit Request Received
0 = Extended Data Frame Received
bit 5 RB1: Reserved Bit 1
bit 4 RB0: Reserved Bit 0
bit 3-0 DLC<3:0>: Data Length Code bits
Indicates number of data bytes that were received
REGISTER 4-9: RXBnDM – RECEIVE BUFFER n DATA BYTE M
(ADDRESS: 66h - 6Dh, 76h - 7Dh)
R-x R-x R-x R-x R-x R-x R-x R-x
RBnD7 RBnD6 RBnD5 RBnD4 RBnD3 RBnD2 RBnD1 RBnD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RBnD7:RBnD0: Receive Buffer n Data Field Bytes m
Eight bytes containing the data bytes for the received message
MCP2515
DS21801G-page 32 2003-2012 Microchip Technology Inc.
4.5 Message Acceptance Filters and
Masks
The me ssage acc eptance filters and masks ar e used to
determine if a message in the message assembly buf-
fer should be loaded into either of the receive buffers
(see Figure 4-5). Once a valid message has been
received into the MAB, the identifier fi elds of the mes-
sage are compared to the filter values. If there is a
match, that message will be loaded into the appropriate
rec eive buffer.
4.5.1 DATA BYTE FILTERING
When recei ving stand ard data frames (11-bit ident ifier),
the MCP2515 automatically applies 16 bits of masks
and filters normally associated with extended
identifi ers to the first 16 bi ts of t he data field (dat a byte s
0 and 1). Figure 4-4 illustrates how masks and filters
apply to extended and standard data frames.
Data b yte fi lter ing redu ces the lo ad on th e MC U w hen
implementing Higher Layer Protocols (HLPs) that filter
on the first data byte (e.g., DeviceNet™).
4.5.2 FILTER MATCHING
The filter masks (see Register 4-14 through
Reg ister 4-17 ) ar e used to dete rmi ne w hich bi ts in th e
identifier are examined with the filters. A truth table is
shown in Table 4-2 th at indicates how ea ch bit in the
iden tifier is comp ared to the m asks an d filter s to d eter-
mine if the message should be loaded into a receive
buffer. T he mask e ssential ly det ermines w hich bits t o
apply the acceptance filters to. If any mask bit is set to
a zero, that bit will automatically be accepted,
regar d les s of th e fi lt er bit .
TABLE 4-2: FILTER/MASK TRUTH TABLE
As shown in the receive buffers block diagram
(Figure 4-2), acceptance filters RXF0 and RXF1 (and
filter mask RXM0) are associated with RXB0. Filters
RXF2, RXF3, RXF4, RXF5 and mask RXM1 are
associated with RXB1.
FIGURE 4-4: MASKS AND FILTERS APPLY TO CAN FRAMES
Mask Bit n Filter Bit n Message
Identifier
bit
Accept or
Reject bit n
0XX
Accept
100
Accept
101
Reject
110
Reject
111
Accept
Note: X = don’t care
Extended Frame
Standard Data Frame
ID10 ID0 EID17 EID0
Masks and Filters apply to the entire 29-bit ID field
ID10 ID0 Data Byte 0 Data Byte 1
11 -bit ID Standard frame
*
16-bit data filtering *
* The two MSb (EID17 and EID16) mask and filter bits are not used.
2003-2012 Microchip Technology Inc. DS21801G-page 33
MCP2515
4.5.3 FILHIT BITS
Filter matches on received messages can be
determined by the FILHIT bits in the associated
RXBnCTRL register. RXB0CTRL.FILHIT0 for buffer 0
and RXB1CTRL.FILHIT<2:0> for buffer 1.
The three FILHIT bits for receive buffer 1 (RXB1) are
coded as follows:
-101 = Acceptance Filter 5 (RXF5)
-100 = Acceptance Filter 4 (RXF4)
-011 = Acceptance Filter 3 (RXF3)
-010 = Acceptance Filter 2 (RXF2)
-001 = Acceptance Filter 1 (RXF1)
-000 = Acceptance Filter 0 (RXF0)
RXB0CTRL contains two copies of the BUKT bit and
the FILHIT<0> bit.
The coding of the BUKT bit enables these three bits to
be used similarly to the RXB1CTRL.FILHIT bits and to
distinguish a hit on filter RXF0 and RXF1 in either
RXB0 or after a roll over into RXB1.
-111 = Acceptance Filter 1 (RXB1)
-110 = Acceptance Filter 0 (RXB1)
-001 = Acceptance Filter 1 (RXB0)
-000 = Acceptance Filter 0 (RXB0)
If the BUKT bit is clear, there are six codes
corresponding to the six filters. If the BUKT bit is set,
there are six cod es corres ponding t o the six filters, p lus
two add itional code s correspon ding to RXF0 a nd RXF1
filters that roll over into RXB1.
4.5.4 MULTIPLE FILTER MATCHES
If more than one ac cept ance filter matc hes, the FILHIT
bits will encode the binary value of the lowest
numbered filter that matched. For example, if filter
RXF2 an d filter RXF4 m atch, FILHIT w ill be loaded w ith
the value for RXF2. This essentially prioritizes the
acceptance filters with a lower-numbered filter having
higher priority. Messages are compared to filters in
ascend ing order of fi lter num ber . T his als o ensures that
the message will only be received into one buffer. This
implies that RXB0 has a higher priority than RXB1.
4.5.5 CONFIGURING THE MASKS AND
FILTERS
The mask and filter registers can only be modified
when the MCP2515 is in Configuration mode (see
Section 10.0 “Modes of Operation”).
FIGU RE 4-5: MESSAG E ACCE PT AN CE MA SK AND FILTE R OPER ATION
Note: 000 and 001 can only occur if th e BUKT bit
in RXB0CTRL is set, allowing RXB0
messages to roll over into RXB1.
Note: The mask and filter registers read all '0'
when in any mode except Configuration
mode.
Acceptance Filter Register Acceptance Mas k Register
RxRqst
Message Assembly Buffer
RXFn0
RXFn1
RXFnn
RXMn0
RXMn1
RXMnn
Identifier
MCP2515
DS21801G-page 34 2003-2012 Microchip Technology Inc.
REGISTER 4-10: RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH
(ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 SID<10:3>: Standard Identifier Filter bits
These bi ts hol d the fil ter bit s to be applie d to bit s <10:3 > of the S ta ndard Ide ntifier po rtion of a receive d
message
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
REGISTER 4-11: RXFnSIDL – FILTER n STANDARD IDENTIFIER LOW
(ADDRESS: 01h, 05h, 09h, 11h, 15h, 19h)
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x
SID2 SID1 SID0 — EXIDE —EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 SID<2:0>: Standard Identifier Filter bits
These bits hold the fi lter bits to be appli ed to b it s <2 :0> of the Standa rd I den tifi er p orti on of a recei ved
message
bit 4 Unimplemented: Reads as ‘0’
bit 3 EXIDE: Exte nded Id entifie r Enab le bit
1 = Filter is applied only to Extended Frames
0 = Filter is applied only to Standard Frames
bit 2 Unimplemented: Reads as ‘0’
bit 1-0 EID<17:16>: Extend ed Ide ntif ier Fil ter bit s
These bits hold the filter bits to be applied to bits <17:16> of the Extended Identifier portion of a
received me ss age
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
2003-2012 Microchip Technology Inc. DS21801G-page 35
MCP2515
REGISTER 4-12: RXFnEID8 – FILTER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<15:8>: Extended Identifier bits
These bit s hold th e filter bit s to be app lied to bit s <15:8> o f the Extended Identifier po rtion of a recei ved
message or to byte 0 in received data if corresponding RXM = 00 and EXIDE = 0
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
REGISTER 4-13: RXFnEID0 – FILTER n EXTENDED IDENTIFIER LOW
(ADDRESS: 03h, 07h, 0Bh, 13h, 17h, 1Bh)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<7:0>: Extended Identifier bits
These bit s ho ld the filter b its to be a pplied to bit s <7 :0> of th e Exten ded Ide ntifie r portion of a rec eived
message or to byte 1 in received data if corresponding RXM = 00 and EXIDE = 0.
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
REGISTER 4-14: RXMnSIDH – MASK n STANDARD IDENTIFIER HIGH
(ADDRESS: 20h, 24h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 SID<10:3>: Standard Identifier Mask bits
These bit s hold the mask bits to be applied to bits <10:3> of the S tandard Identifier portion of a received
message
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
MCP2515
DS21801G-page 36 2003-2012 Microchip Technology Inc.
\
REGISTER 4-15: RXMnSIDL – MASK n STANDARD IDENTIFIER LOW
(ADDRESS: 21h, 25h)
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
SID2 SID1 SID0 — — —EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 SID<2:0>: Standard Identifier Mask bits
These bit s h old the mask bit s to be appl ied to bit s<2:0> of the Stand ard Iden tifier p ortion of a rec eived
message
bit 4-2 Unimplemented: Reads as ‘0’
bit 1-0 EID<17:16>: Extend ed Ide ntif ier Ma sk bit s
These bits hold the mask bits to be applied to bits <17:16> of the Extended Identifier portion of a
received me ss age
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
REGISTER 4-16: RXMnEID8 – MASK n EXTENDED IDENTIFIER HIGH
(ADDRESS: 22h, 26h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<15:8>: Extended Identifier bits
These bit s hold th e filter bit s to be app lied to bit s <15:8> o f the Extended Identifier po rtion of a recei ved
message . If correspondi ng RXM = 00 an d EXIDE = 0, these bit s are appli ed to byte 0 in receiv ed data
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
2003-2012 Microchip Technology Inc. DS21801G-page 37
MCP2515
REGISTER 4-17: RXMnEID0 – MASK n EXTENDED IDENTIFIER LOW
(ADDRESS: 23h, 27h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EID<7:0>: Extended Identifier Mask bits
These bit s ho ld the filter b its to be a pplied to bit s <7 :0> of th e Exten ded Ide ntifie r portion of a rec eived
message. If corresponding RXM = 00 and EXIDE = 0, the se bit s are applied to byte 1 in received d ata.
Note: The mask and filter registers read all '0' when in any mode except Configura tion m ode.
MCP2515
DS21801G-page 38 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 39
MCP2515
5.0 BIT TIMING
All nodes on a given CAN bus must have the same
nomina l bit rate . The CAN pro tocol uses Non Re turn to
Zero (NRZ) coding, which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission times may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data
transmission edges to synchronize and maintain the
receiver clock. Since the data is NRZ-coded, it is
necess ary t o inc lude b it-stuf fi ng to ensure that an edge
occurs at least every si x bit times to mai ntain t he Digital
Phase Lock Loop (DPLL) synchronization.
The bit timing of th e MCP2515 is implemented using a
DPLL that is c onfigured to synchron ize to the incoming
data, as well as provide the nominal timing for the
transmitted data. The DPLL breaks each bit time into
multiple segments made up of minimal periods of time,
called the Time Quanta (TQ).
Bus timi ng functions execu ted w ith in th e b it ti me fram e
(such as synchro nization to the local os cillato r , netw ork
transmission delay compensation and sample point
positioning) are defined by the programmable bit timing
logic of the DPLL.
5.1 The CAN Bit TIme
All devi ces on the CAN bus must use th e same bi t rate.
Howeve r , a ll devic es are no t required t o have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the Baud
Rate Prescaler and number of time quanta in each
segment.
The CAN bit time is made up of non-overlapping
segments. Each of these segments are made up of
inte ger u nits call ed Time Quan ta (TQ) , expl ained later
in this data sheet. The Nominal Bit Rate (NBR) is
defined in the CAN specification as the number of bits
per second transmitted by an ideal transmitter with no
resynchronization. It can be described with the
equation:
EQUATION 5-1:
Nominal Bit Time
The Nominal Bit Time (NBT) (tbit) is made up of non-
overlapping segments (Figure 5-1). Therefore, the
NBT is the summation of the following segments:
Associated with the NBT are the sample point,
Synchronization Jump Width (SJW) and Information
Processing Time (IPT), which are explained later.
SYNCHRONIZATION SEGMENT
The Synchronization Segment (SyncSeg) is the first
segment in the NBT and is used to synchronize the
nodes on the bus. Bit edges are expected to occur
within the SyncSeg. This segment is fixed at 1 TQ.
FIGURE 5-1: CAN BIT TIME SEGMENTS
NBR fbit 1
tbit
-------==
tbit tSyncSeg tPropSeg tPS1 tPS2
+++=
Nominal Bit Time (NBT), tbit
Sample
Point
SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)
MCP2515
DS21801G-page 40 2003-2012 Microchip Technology Inc.
PROPAGATION SEGMENT
The Propagation Segment (PropSeg) exists to
compensate for physical delays between nodes. The
propagation delay is defined as twice the sum of the
signal’s propagation time on the bus line, including the
delays associated with the bus driver. The PropSeg is
programm ab le from 1-8 TQ.
PHASE SEGMENT 1 (PS1) AND PHASE
SEGMENT 2 (PS2)
The two phase segments, PS1 and PS2, are used to
compensate for edge phase errors on the bus. PS1 can
be length ened (or PS2 shorte ned) by resync ronizatio n.
PS1 is programmable from 1-8 TQ and PS2 is
programm ab le from 2-8 TQ.
SAMPLE POINT
The sam ple point is the point in the bit time at which the
logic level is read and interpreted. The sample point is
located at the end of PS1. The exception to this rule is
if the sample mo de is c onfigu red to sampl e three ti mes
per bit. In this case, while the bit is still sampled at the
end of PS1, two additional samples are taken at one-
half TQ inte rva ls p rior to th e end of PS1 , wi th the value
of the bit being determined by a majority decision.
INFORMATION PROCESSING TIME
The Information Processing Time (IPT) is the time
required for the logic to determine the bit level of a
sampled bit. The IPT begins at the sample point, is
measured in TQ and is fixed at 2 TQ for the Microchip
CAN module. Since PS2 also begins at the sample
point and is the last segment in the bit time, it is
required that the PS2 mi nimum is not less than t he IPT.
Therefore:
SYNCHRONIZATION JUMP WIDTH
The S ynchro niz at ion Jum p W id t h (SJ W) adj us t s the bit
clock as necessary by 1-4 TQ (as configured) to
maintain synchronization with the transmitted
message. Synchronization is covered in more detail
later in this dat a sh eet.
Time Quantum
Each of t he segments th at make up a bit time are made
up of int eger units ca lled T ime Quant a (TQ). The leng th
of each T ime Q uantum is bas ed on the oscilla tor period
(tOSC). The base TQ equ als twic e the os cillator pe rio d.
Figure 5-2 shows how the bit period is derived from
TOSC and TQ. The TQ length equals one TQ clock
period (tBRPCLK), which is programmable using a
programmable prescaler, called the Baud Rate
Prescaler (BRP). This is illustrated in the following
equation:
EQUATION 5-2:
FIGURE 5-2: TQ AND THE BIT PERIOD
PS2min IPT 2TQ==
TQ 2 BRP TOSC
2BRP
FOSC
-------------------==
Where: BRP equals the configuration as s ho wn in
Register 5-1.
tOSC
TBRPCLK
tBIT Sync
(fixed) PropSeg
(Programmable) PS2
(Programmable)
PS1
(Programmable)
TQ
(tTQ)
CAN B it Time
2003-2012 Microchip Technology Inc. DS21801G-page 41
MCP2515
5.2 Synchronization
To compensate for phase shifts between the oscillator
frequenc ies of ea ch of the nod es on the bu s, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. Synchronization is
the process by which the DPLL function is
implemented.
When an edge in the tran smitt ed data is detect ed, the
logic will compare the location of the edge to the
expected time (SyncSeg). The circuit will then adjust
the values of PS1 and PS2 as necessary.
There are two mechanisms used for synchronization:
1. Hard synchronization
2. Resynchronization
5.2.1 HARD SYNCHRONIZATION
Hard sy nchronization is only performed when there is a
recessive-to-dominant edge during a BUS IDLE
condition, indicating the start of a message. After hard
synchronizatio n, the bit time counters are rest arted with
SyncSeg.
Hard synchronization forces the edge that has
occurred to lie within the synchronization segment of
the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs , there
will not be a resynchronization within that bit time.
5.2.2 RESYNCHRONIZATION
As a result of resynchronization, PS1 may be
lengthened or PS2 may be shortened. The amount of
lengthe ning or shortening of the phase buf fer segment s
has an upper-bound, given by the Synchronization
Jump Width (SJW).
The value of the SJW will be added to PS1 or
subtracted from PS2 (see Figure 5-3). The SJW
represents the loop filtering of the DPLL. The SJW is
progra mmab le betw e en 1 TQ and 4 TQ.
5.2.2.1 Phase Errors
The NRZ bit coding method does not encode a clock
into the message. Clocking information will only be
derived from recessive-to-dominant transitions. The
property which states that only a fixed maximum
number of successive bits have the same value (bit-
stuffing) ensures resynchronization to the bit stream
during a frame.
The phase er ror of an edg e is given by the pos ition of
the edge relative to SyncSeg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
•e = 0 if the edge lies within SYNCSEG
•e > 0 if the edge lies before the SAMPLE POINT
(TQ is added to PS1)
•e < 0 if the edge lies after the SAMPLE POINT of
the previous bit (TQ is subtracted from PS2)
5.2.2.2 No Phase Error (e = 0)
If the m agnitude of the p hase erro r is less than or e qual
to the programmed value of the SJW, the effect of a
resynchronization is the same as that of a hard
synchronization.
5.2.2.3 Positive Phase Error (e > 0)
If the magnitude of the phase error is larger than the
SJW and, if the phase error is positive, PS1 is
lengthened by an amount equal to the SJW.
5.2.2.4 Negative Phase Error (e < 0)
If the magnitude of the phase error is larger than the
resynchronization jump width and the phase error is
negative, PS2 is shortened by an amount equal to the
SJW.
5.2.3 SYNCHRONIZATION RULES
1. Only recessive-to-dominant edges will be used
for synchronization.
2. Only one synchronization within one bit time is
allowed.
3. An ed ge wi ll b e us ed f or sy nc hroni zat ion onl y if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
4. A transmitting node will not resynchronize on a
positiv e phas e error (e > 0).
5. If the absolute magnitude of the phase error is
greater than the SJW, the appropriate phase
segment will adjust by an amount equal to the
SJW.
MCP2515
DS21801G-page 42 2003-2012 Microchip Technology Inc.
FIGU RE 5-3: SYN CHR ONIZI NG TH E BI T TI ME
SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)
Sample
Point
SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)
Sample
Point
SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)
Sample
Point
Nominal Bit Time (NBT)
SJW (PS1)
SJW (PS2)
Nominal Bit Time (NBT)
SJW (PS1)
SJW (PS2)
Actual Bit Time
Resynchronization to a Slower Transmitter (e > 0)
Input Signal
Input Signal (e < 0)
SJW (PS1)
SJW (PS2)
Nomin al Bit Time (NBT)
Actual Bit Time
Resynchronization to a Faster Transmitter (e < 0)
Input Signal (e = 0)
No Resynchronization (e = 0)
(e > 0)
2003-2012 Microchip Technology Inc. DS21801G-page 43
MCP2515
5.3 Programming Time Segments
Some requirements for programming of the time
segments:
• PropSeg + PS1 >= PS2
• PropSeg + PS1 >= TDELAY
• PS2 > SJW
For example, assuming that a 125 kHz CAN baud rate
with FOSC = 20 MHz is desired:
TOSC = 50 ns, choose BRP<5:0> = 04h, then
TQ= 500 ns. To obtain 125 kHz, the bit time must be 16
TQ.
Typically, the sampling of the bit should take place at
about 60-7 0% of the bit time, de pendin g on the sys tem
parameters. Also, typically, the TDELAY is 1-2 TQ.
SyncSeg = 1 TQ and PropSeg = 2 TQ. So setting
PS1 = 7 TQ would place the sample at 10 TQ after the
transition. This would lea ve 6 TQ for PS2.
Since PS2 is 6, a cc ord ing to the rule s, SJW could be a
maximum of 4 TQ. However, a large SJW is typically
only n ecessary when the clock generat ion of the dif f er-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. So a SJW of 1 is usually enough.
5.4 Oscillator Tolerance
The bit timing requirements allow ceramic resonators
to be used in appl icatio ns with tra nsmi ssion rate s of up
to 125 kbit/sec as a rule of thumb. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
5.5 Bit Timing Configurat ion
Registers
The configuration registers (CNF1, CNF2, CNF3)
control the bit timing for the CAN bus interface. These
registers can onl y be mod ified when the MCP251 5 is in
Configuration mode (see Section 10.0 “Modes of
Operation”).
5.5.1 CNF1
The BRP<5:0> bits control the Baud Rate Prescaler.
These bits set the length of TQ relative to the OSC1
input frequency, with the minimum TQ length being
2T
OSC (when BRP<5:0> = ‘b000000’). The
SJW<1:0> bits select the SJW in terms of number of
TQs.
5.5.2 CNF2
The PRSEG<2:0> bits set the length (in TQ’s) of the
propagation segment. The PHSEG1<2:0> bits set the
length (in TQ’s) of PS1.
The SAM bit controls how many times the RXCAN pin
is sampl ed. Setting this bit t o a ‘1’ cau ses t he bus to b e
sampled three times: twice at TQ/2 before the sample
point and once at the normal sample point (which is at
the end of PS1). The value of the bus is determined to
be the majority sampled. If the SAM bit is set to a ‘0’,
the RXCAN pin is sampled only once at the sample
point.
The BTLMODE bit controls how the length of PS2 is
determin ed. If t his b it is s et to a ‘1’, the l ength of PS 2 is
determined by the PHSEG2<2:0> bits of CNF3 (see
Section 5.5.3 “CNF3”). If th e BTLM O DE bit is s et to a
‘0’, the length of PS2 is greate r than that of PS1 and the
information processing time (which is fixed at 2 TQ for
the MCP2515).
5.5.3 CNF3
The PHSEG2<2 :0> bit s set the len gth (in TQ’s) of PS2,
if the CNF2.BTLMODE bit is set to a ‘1’. If the
BTLMODE bit is set to a ‘0’, the PHSEG2<2:0> bits
have no effect.
MCP2515
DS21801G-page 44 2003-2012 Microchip Technology Inc.
REGISTER 5-1: CNF1 – CONFIGURATION 1 (ADDRESS: 2Ah)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 SJW<1:0>: Synchronization Jump Width Length bits
11 = Length = 4 x TQ
10 = Length = 3 x TQ
01 = Length = 2 x TQ
00 = Length = 1 x TQ
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
TQ = 2 x (BR P + 1)/FOSC
REGISTER 5-2: CNF2 – CONFIGURATION 1 (ADDRESS: 29h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTLMODE: PS2 Bit Time Length bit
1 = Length of PS2 determined by PHSEG22:PHSEG20 bits of CNF3
0 = Length of PS2 is the greater of PS1 and IPT (2 TQ)
bit 6 SAM: Sample Point Configuration bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 PHSEG1<2:0>: PS1 Length bits
(PHSEG1 + 1) x TQ
bit 2-0 PRSEG<2:0>: Propagation Segment Length bits
(PRSEG + 1) x TQ
2003-2012 Microchip Technology Inc. DS21801G-page 45
MCP2515
REGISTER 5-3: CNF3 - CONFIGURATION 1 (ADDRESS: 28h)
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SOF WAKFIL — — — PHSEG22 PHSEG21 PHSEG20
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SOF: Start-of-Frame signal bit
If CANCTRL.CLKEN = 1:
1 = CLKOUT pin enabled for SOF signal
0 = CLKOUT pin enabled for clockout function
If CANCTRL.CLKEN = 0, Bit is don’t care.
bit 6 WAKFIL: Wake-up Filter bit
1 = Wake-up filter enabled
0 = Wake-up filter disabled
bit 5-3 Unimplemented: Reads as ‘0’
bit 2-0 PHSEG2<2:0>: PS2 Length bits
(PHSEG2 + 1) x TQ
Minimum valid setting for PS2 is 2 TQ
MCP2515
DS21801G-page 46 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 47
MCP2515
6.0 ERROR DETECTION
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
6.1 CRC Error
With the Cyclic Redundancy Check (CRC), the
transmitter calculates special check bits for the bit
sequence from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC Field. The receiving node also calculates the
CRC sequence usi ng the same formula a nd performs
a comparison to the received sequence. If a mismatch
is detected, a CRC error has occurred and an error
frame is generated. The message is repeated.
6.2 Acknowledge Error
In the acknowledge field of a message, the transmitter
checks if the acknowledge slot (which has been sent
out as a recessive bit) cont ains a dominant bit. If not, no
other node has received the frame correctly. An
acknowledge error has occurred, an error frame is
generated and the message will have to be repeated.
6.3 Form Error
If a node detects a dominant bit in one of the four
segments (including end-of-frame, interframe space,
acknowledge delimiter or CRC delimiter), a form error
has occurred and an error frame is generated. The
messa ge is repe ate d.
6.4 Bit Error
A bit error occurs if a transmitter detects the opposite
bit level to what it transmitted (i.e., transmitted a
dominant and detected a recessive, or transmitted a
recessive and detected a dominant).
Exception: In the case where the transmitter sends a
recessive bit and a dominant bit is detected during the
arbit ration field a nd the acknow ledge slot, no bi t error is
generated because normal arbitration is occurring.
6.5 Stuff Error
lf, between the start-of-frame and the CRC delimiter,
six consecutive bits with the same polarity are
detecte d, the bit-s tuffing rule has bee n vi ola ted . A stuff
error occurs and an error frame is generated. The
messa ge is repe ate d.
6.6 Error States
Detected errors are made known to all other nodes via
error frames. The transmission of the erroneous mes-
sage is aborted and the frame is repeated as soon as
possib le. Furtherm ore, eac h C AN no de i s in one of th e
three err or states accord ing to the v alue of the internal
error counters:
1. Error-active
2. Error-passive
3. Bus-off (transmitter only)
The error-act ive state is the usua l state where the nod e
can transmit messages and active error frames (made
of dominant bits) without any restrictions.
In the error-passive state, messages and passive error
frames (made of recessive bits) may be transm itted.
The bus-off state makes it temporarily impossible for
the station to participate in the bus communication.
During thi s state, messages c an nei ther b e re ce iv ed or
transmitted. Only transmitters can go bus-off.
6.7 Error Modes and Error Counters
The MCP2515 contains two error counters: the
Receive Error Counter (REC) (see Register 6-2) and
the Transmit Error Counter (TEC) (see Register 6-1).
The values of both counters can be read by the MCU.
These counters are incremented/decremented in
accordance with the CAN bus specificati on.
The MCP2515 is error-active if both error counters are
below the error-passive limit of 128.
It is error-passive if at least one of the error counters
equals or exc eed s 128.
It goes to bu s-of f if the TEC exc eeds th e bus-o f f lim it of
255. The device remains in this state until the bus-off
recovery sequence is received. The bus-off recovery
sequence consists of 128 occurrences of 11
consecutive recessive bits (see Figure 6-1).
The Current Error mode of the MCP2515 can be read
by the MCU via the EFLG register (see Register 6-3).
Additionally, there is an error state warning flag bit
(EFLG:EWARN) which is set if at lea st one of the error
counters equals or exceeds the error warning limit of
96. EW ARN is reset if both err or counters are less than
the error warning limit.
Note: The MCP2515, after going bus-off, will
recover back to error-active without any
interven tion by the MCU if the bus remains
idle for 128 x 11 bit times. If this is not
desired, the error interrupt Service
Routine should address this.
MCP2515
DS21801G-page 48 2003-2012 Microchip Technology Inc.
FIGURE 6-1: ERROR MODES STATE DIAGRAM
Bus-Off
Error-Active
Error-Passive
REC < 127 or
TEC < 127
REC > 127 or
TEC > 127
TEC > 255
RESET
128 occurrences of
11 consecutive
“recessive” bits
REGISTER 6-1: TEC – TRANSMIT ERROR COUNTER
(ADDRESS: 1Ch)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TEC<7:0>: Transmit Error Count bits
REGISTER 6-2: REC – RECEIVER ERROR COUNTER
(ADDRESS: 1Dh)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 REC<7:0>: Receive Error Count bits
2003-2012 Microchip Technology Inc. DS21801G-page 49
MCP2515
REGISTER 6-3: EFLG – ERROR FLAG
(ADDRESS: 2Dh)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RX1OVR: Receive Buffer 1 Overflow Flag bit
- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1
- Must be reset by MCU
bit 6 RX0OVR: Receive Buffer 0 Overflow Flag bit
- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1
- Must be reset by MCU
bit 5 TXBO: Bus-Off Error Flag bit
- Bit set when TEC reaches 255
- Reset after a successful bus recovery sequence
bit 4 TXEP: Transmit Error-Passive Flag bit
- Set when TEC is equal to or greater than 128
- Reset when TEC is less than 128
bit 3 RXEP: Receive Error-Passive Flag bi t
- Set when REC is equal to or greater than 128
- Reset when REC is less than 128
bit 2 TXWAR: Transm it Err or Warning Flag bit
- Set when TEC is equal to or greater than 96
- Reset when TEC is less than 96
bit 1 RXWAR: Receive Error Warning Flag bit
- Set when REC is equal to or greater than 96
- Reset when REC is less than 96
bit 0 EWARN: Error Warning Flag bit
- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)
- Reset when both REC and TEC are less than 96
MCP2515
DS21801G-page 50 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 51
MCP2515
7.0 INTERRUPTS
The MCP2515 has eight sources of interrupts. The
CANINTE register contains the individual interrupt
enable bits for each interrupt source. The CANINTF
register co nta ins the c orrespo nding interrup t flag b it for
each interrupt source. When an interrupt occurs, the
INT pin is driven low by the MCP2515 and will remain
low until the interrupt is cleared by the MCU. An
interrupt can not be cleared if the respective condition
still prevails.
It is recommended that the Bit Modify command be
used to reset flag bits in the CANINTF register rather
than normal write operations. This is done to prevent
uninten tion ally chan ging a fl ag th at changes during the
Write command, potentially causing an interrupt to be
missed.
It should be noted that the CANINTF flags are
read/write and an interrupt can be generated by the
MCU setti ng any of thes e bit s, provid ed the assoc iated
CANINTE bit is also set.
7.1 Interrupt Code Bits
The source of a pending interrupt is indicated in the
CANSTAT.ICOD (interrupt code) bits, as indicated in
Register 10-2. In the event that multiple interrupts
occur, the INT will remain low until all interrupts have
been reset by the MCU. The CANSTAT.ICOD bits will
reflect the code for the highest priority interrupt that is
currently pending. Interrupts are internally prioritized
such that the lower the ICOD value, the higher the
interrupt priority. Once the highest priority interrupt
condition has been cleared, the code for the next
highest priority interrupt that is pending (if any) will be
reflected by the ICOD bits (see Table 7-1). Only those
interrupt sources that have their associated CANINTE
enable bit set will be reflected in the ICOD bits.
TABLE 7-1: ICOD<2:0> DECODE
7.2 Transmit Interrupt
When the transmit interrupt is enabled
(CANINTE.TXnIE = 1), an interrupt will be generated on
the INT pin once the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The CANINTF.TXnIF bit will be set to indicate
the source of the interrupt. The interrupt is cleared by
clearing the TXnIF bit.
7.3 Receive Interrupt
When the receive interrupt is enabled
(CANINTE.RXnIE = 1), an interrupt will be generated
on the INT pin once a message has been successfully
receive d and load ed into the assoc iated rec eive bu ffe r.
This interrupt is activated immediately after receiving
the EOF field. The CANINTF.RXnIF bit will be set to
indicate the source of the interrupt. The interrupt is
cleared by clearing the RXnIF bit.
7.4 Message Error Int errupt
When an error occurs during the transmission or
reception of a message, the message error flag
(CANINTF.MERRF) will be set and, if the
CANINTE.MERRE bit is set, an interrupt will be
generated on the INT pin. This is intended to be used
to facilitate baud rate determination when used in
conjunction with Listen-Only mode.
7.5 Bus Activity Wake-up Interrupt
When the MCP2515 is in Sleep mode and the bus activity
wake-up interr upt is enabled (CANI NTE.WAKIE = 1), an
interrupt will be generated on the INT pin and the
CANINTF.WAKIF bit will be set when activit y is detected
on the CAN bus. This int errupt causes the MCP2515 to
exit Sleep mode. The interrupt is reset by clearing the
WAKIF bit.
7.6 Error Int errupt
When the error interrupt is enabled
(CANINTE.ERRIE = 1), an interrupt is generated on
the INT pin if a n overflow co ndition occurs or i f the error
state of the transmitter or receiver has changed. The
Error Flag (EFLG) register will indicate one of the
following conditions.
7.6.1 RECEIVER OVERFLOW
An overflow condition occurs when the MAB has
assembled a valid receive message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
EFLG.RXnOVR bit will be set to indicate the overflow
condition. This bit must be cleared by the MCU.
ICOD<2:0> Boolean Expression
000 ERR•WAK•TX0•TX1•TX2•RX0•RX1
001 ERR
010 ERR•WAK
011 ERR•WAK•TX0
100 ERR•WAK•TX0•TX1
101 ERR•WAK•TX0•TX1•TX2
110 ERR•WAK•TX0•TX1•TX2•RX0
111 ERR•WAK•TX0•TX1•TX2•RX0•RX1
Note: ERR is associated with CANINTE,ERRIE.
Note: The MCP2515 wakes up into Listen-Only
mode.
MCP2515
DS21801G-page 52 2003-2012 Microchip Technology Inc.
7.6.2 RECEIVER WARNING
The REC has reached the MCU warning limit of 96.
7.6.3 TRANSMITTER W ARNING
The TEC has reached the MCU warning limit of 96.
7.6.4 RECEIVER ERROR-PASSIVE
The REC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
7.6.5 TRANSMITTER ERROR-PASSIVE
The TEC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
7.6.6 BUS-OFF
The TEC has exceeded 255 and the device has gone
to bus-off state.
7.7 Interrupt Acknowledge
Interrupts are directly associated with one or more
status flags in the CANINTF register. Interrupts are
pending as long as one of the flags is set. Once an
interrupt flag is set by the device, the flag can not be
reset by the MCU until the interrupt condition is
removed.
REGISTER 7-1: CANINTE – INTERRUPT ENABLE
(ADDRESS: 2Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MERRE: Message Error Interrupt Enab le bit
1 = Interrupt on error during message reception or transmission
0 =Disabled
bit 6 WAKIE: Wake-up Interrupt Enable bit
1 = Interrupt on CAN bus activity
0 =Disabled
bit 5 ERRIE: Error Interrupt Enable bit (multi ple sources in EFLG register)
1 = Interrupt on EFLG error condition change
0 =Disabled
bit 4 TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit
1 = Interrupt on TXB2 becoming empty
0 =Disabled
bit 3 TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit
1 = Interrupt on TXB1 becoming empty
0 =Disabled
bit 2 TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit
1 = Interrupt on TXB0 becoming empty
0 =Disabled
bit 1 RX1IE: Receive Buffer 1 Full Interrupt Enable bit
1 = Interrupt when message received in RXB1
0 =Disabled
bit 0 RX0IE: Receive Buffer 0 Full Interrupt Enable bit
1 = Interrupt when message received in RXB0
0 =Disabled
2003-2012 Microchip Technology Inc. DS21801G-page 53
MCP2515
REGISTER 7-2: CANINTF – INTERRUPT FLAG
(ADDRESS: 2Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MERRF: Message Error Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 6 WAKIF: Wake-up Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in EFLG register)
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 4 TX2IF: Transmit Buffer 2 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 3 TX1IF: Transmit Buffer 1 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 2 TX0IF: Transmit Buffer 0 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 1 RX1IF: Receive Buffer 1 Full Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
bit 0 RX0IF: Receive Buffer 0 Full Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrup t pending
MCP2515
DS21801G-page 54 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 55
MCP2515
8.0 OSCILLATOR
The MC P2515 is designed to b e operated with a cry stal
or ceramic resonator connected to the OSC1 and
OSC2 pins. The MCP2515 oscillator design requires
the use of a parallel cut crystal. Use of a series cut
crystal may give a frequency out of the crystal
manufacturer’s spe cifications. A typica l oscillator ci rcuit
is shown in Figure 8-1. The MCP2515 may also be
driven by an external clock source connected to the
OSC1 pin, as shown i n Figure 8-2 and Figure 8-3.
8.1 Oscillator Start-up Timer
The MCP2515 utilizes an Oscillator Start-up Timer
(OST) that hold s the MCP251 5 in R eset to ens ure that
the oscillator has stabilized before the internal state
machine begins to operate. The OST maintains Reset
for the first 128 OSC1 clock cycles after power-up or a
wake-up from Sleep mode occurs. It should be noted
that no SPI protocol operations should be attempted
until after the OST has expired.
8.2 CLKOUT Pin
The CLKOUT pin is provid ed to the system desi gner for
use as the main system clock or as a clock input for
other devices in th e system. The CLKOUT has an inter-
nal prescaler which can divide FOSC by 1, 2, 4 a nd 8.
The CLKOUT function is enabled and the prescaler is
selected via the CANCNTRL register (see
Register 10-1).
The CL KOUT pin will be a ctive upo n syste m Rese t and
default to the slowe st sp eed (divi de by 8) so that it ca n
be used as the MCU clock.
When Sleep mode is requested, the MCP2515 will
drive sixteen additional clock cycles on the CLKOUT
pin before entering Sleep mode. The Idle state of the
CLKOUT p in in Slee p mode is l ow. When the CLKO UT
function is disabled (CANCNTRL.CLKEN = 0) the
CLKOUT pin is in a high-impedance state.
The CLKOUT function is designed to ensure that
thCLKOUT and tlCLKOUT timi ng s are preserved w he n th e
CLKOUT pin function is enabled, disabled or the
presca l er val ue is ch ang ed.
FIGU RE 8-1: CRYSTAL/CER AMI C RE S ONA TO R OP ER AT I O N
FIGU RE 8-2: EXTERNA L C LOC K S OUR CE
Note: The maximum frequency on CLKOUT is
specified as 25 MHz (See Table 13-5).
C1
C2
XTAL
OSC2
RS(1)
OSC1
RF(2) Sleep
To internal logic
Note 1: A series resistor (RS) may be required for AT strip-cut crystals.
2: The feedback resistor (RF), is typically in the range of 2 to 10 M.
Clock from
external system OSC1
OSC2
Open
(1)
Note 1: A resi st or to ground m ay be us ed to r edu ce sy st em noi se. This may inc rea se sys tem c urren t .
2: Duty cycle restrictions must be observed (see Table 12-1).
MCP2515
DS21801G-page 56 2003-2012 Microchip Technology Inc.
FIGU RE 8-3: EXTERNA L SE R IE S R E SO NA NT CR Y STAL OS CI LLA T OR CI RC UI T(1)
TABLE 8-1: CAP ACIT OR SELECTION FOR
CERAMIC RESO NATORS TABLE 8-2: CAPACIT OR SELECTION FOR
CRYSTAL OSCILLATOR
330 k
74AS04 74AS04 MCP2510
OSC1
To Other
Devices
XTAL
330 k
74AS04
0.1 mF
Note 1: Duty cycle restrictions must be observed (see Table 12-1).
Typical Capacitor Values Used:
Mode Freq. OSC1 OSC2
HS 8.0 MHz 27 pF 27 pF
16.0 MHz 22 pF 22 pF
Capacitor values are for design guidance only:
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to
produce acceptable oscillator operation. The user
should test the p erfor manc e of the os cilla tor ove r the
expected VDD and temperature range for the
application.
See the notes following Table 8-2 for additional
information. Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz
Osc
Type(1)(4) Crystal
Freq.(2)
Typical Capacitor
Values Tested :
C1 C2
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20MHz 15pF 15pF
Capacitor values are for design guidance only:
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to
produce acceptable oscillator operation. The user
should t est the perfo rmance of the os cilla tor o ver the
expected VDD and temperature range for the
application.
See the notes following this Table for additional
information.
Crystals Used(3):
4.0 MHz
8.0 MHz
20.0 MHz
Note 1: While higher capacitance increases the
stability of the oscillator, it also increases
the start-up time.
2: Since each r esonator/c rystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
3: RS may be required to avoid overdriving
crystals with low drive level specification.
4: Alw ays verify oscillator perfor mance o ver
the VDD and temperature range that is
expected for the application.
2003-2012 Microchip Technology Inc. DS21801G-page 57
MCP2515
9.0 RESET
The MCP2515 differentiates between two Resets:
1. Hardware Reset – Low on RESET pin
2. SPI Reset – Reset via SPI command
Both of these Resets are functionally equivalent. It is
important to provide one of these two Resets after
power-up to ensure that the logic and registers are in
their default state. A hardware Reset can be achieved
automat ically by pla cing a n RC on the RESET pin (se e
Figure 9-1). Th e values m ust be such that the de vice is
held in Res et fo r a mi ni mu m of 2 µs afte r V DD reaches
operating voltage, as indicated in the electrical
specification (tRL).
FIGURE 9-1: RESET PIN CONFIGURATION EXAMPLE
RESET
R1(2)
VDD
VDD
R
C
D(1)
Note 1: The diode D helps discharge the capacitor quickly when VDD powers down.
2: R1 = 1 k to 10 k will limit any current flowing into RESET from external
capacitor C, in the event of RESET pin breakdown due to Electrostatic
Discharge (ESD) or Electrical Overstress (EOS).
MCP2515
DS21801G-page 58 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 59
MCP2515
10.0 MODES OF OPERATION
The MCP2515 has five modes of operation. These
modes are:
1. Configur ation mode
2. Normal mode
3. Sleep mode
4. List en-O n ly mo de
5. Loop bac k mo de
The operational mode is selected via the
CANCTRL. REQOP bits (see Register 10-1).
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. The requested mode must be verified by
reading the CANSTAT.OPMODE bits (see
Register 10-2).
10.1 Configuration Mode
The MCP2515 must be initialized before activation.
This is o nly possible if the device is in the Configuratio n
mode. Configuration mode is automatically selected
after power-up, a Reset or can be entered from any
other mode by setting the CANTRL.REQOP bits to
‘100’. When Configuration mode is entered, all error
counters are cleared. Configuration mode is the only
mode where the following registers are modifiable:
• CNF1, CNF2, CNF3
• TXRTSCTRL
• Filter registers
• Mask registers
10.2 Sleep Mode
The MC P2515 has a n inte rnal Sl eep mode tha t is use d
to minimize the current consumption of the device. The
SPI interface remains ac tive for readin g even when the
MCP2515 is in Sleep mode, allowing access to all
registers.
To enter Sleep mode, the mode request bits are set in
the CANCTRL register (REQOP<2:0>). The
CANSTAT.OPMODE bits indicate operation mode.
These bits should be read after sending the Sleep
command to the MCP2515. The MCP2515 is active
and has not yet entered Sleep mode until these bits
indicate that Sleep mode has been entered.
When in internal Sleep mode, the wake-up interrupt is
still active (if enabled). This is done so that the MCU
can also be placed into a Sleep mode and use the
MCP2515 to wake it up upon detecting activity on the
bus.
When in Sleep mode, the MCP2515 stops its internal
oscillator . The MCP2515 will wake-up when bus activity
occurs or whe n the MCU set s, via the SPI interf ace, the
CANINTF.WAKIF bit to ‘generate’ a wake-up attempt
(the CANINTE.WAKIE bit must also be set in order for
the wake-up interrupt to occur).
The TXCAN pin will re main in the reces sive stat e while
the MCP2515 is in Sleep mode.
10.2.1 WAKE-UP FUNCTIONS
The device will monitor the RXCAN pin for activit y while
it is in Sleep mode. If the CANINTE.WAKIE bit is set,
the device will wake-up and generate an interrupt.
Since the internal oscil lator is shut do wn whil e in Slee p
mode, i t wi ll t ake some amou nt of t ime fo r the oscil lator
to start-up and the device to enable itself to receive
messages. This Oscillator Start-up Timer (OST) is
defined as 128 TOSC.
The device will ignore the message that caused the
wake-up from Sleep mode, as well as any messages
that occur while the device is ‘waking up’. The device
will wake-up in Listen-Only mode. The MCU must set
Normal mode before the MCP2515 will be able to
communica te on the bus.
The device can be programmed to apply a low-pass
filt er fu nctio n to the RXCAN input line wh ile in inter nal
Sleep mode. This feature can be used to prevent the
device from waking up due to short glitches on the CAN
bus lines. The CNF3.WAKFIL bit enables or disables
the filter.
10.3 Listen-Only Mode
Listen-Only mode provides a means for the MCP2515
to receive all messages (including messages with
errors) by configuring the RXBnCTRL.RXM<1:0> bits.
This mode can be used for bus monitor applications or
for detecting the baud rate in ‘hot plugging’ situations.
For auto-baud detection, it is necessary that at least
two other nodes are communicating with each other.
The baud rate can be detected empirically by testing
different values until valid messages are received.
Listen-Only mode is a silent mode, meaning no
messages will be transmitted while in this mode
(including error flags or acknowledge signals). In
List en-Only mode, bo th val id and inva lid m essag es w ill
be received regardless of filters and masks or RXMn
Receive Buffer mo de bit s. The error counte rs are res et
and deactivated in this state. The Listen-Only mode is
activated by setting the mode request bits in the
CANCTRL register.
MCP2515
DS21801G-page 60 2003-2012 Microchip Technology Inc.
10.4 Loopback Mode
Loopback mode will allow internal transmission of
messages from the transmit buffers to the receive
buffers without actually transmitting messages on the
CAN bus. This mode can be used in system
development and testing.
In this mo de, the ACK bi t is i gno red a nd th e de vic e w il l
allow incoming messages from its elf just a s if they w ere
coming from another node. The Loopback mode is a
silent mode, meaning no messages will be transmitted
while in this st ate (inc luding error flags or Acknowledg e
signals). The TXCAN pin will be in a recessive state.
The filters and masks can be used to allow only
particular messages to be loaded into the receive
regi ste rs . The ma sk s ca n be set to al l ze ro s to prov i de
a mode that accepts all messages. The Loopback
mode is activated by setting the mode request bits in
the CANCTRL register.
10.5 Normal Mode
Normal mode is the standard operating mode of the
MCP2515. In this mode, the device act ively monitors all
bus messages and generates Acknowledge bits, error
frames, etc. This is also the only mode in which the
MCP2515 wil l tran s mit messages over the CAN bus.
REGISTER 10-1: CANCTRL – CAN CONTROL REGISTER
(ADDRESS: XFh)
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
REQOP2 REQOP1 REQOP0 ABAT OSM CLKEN CLKPRE1 CLKPRE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 REQOP<2:0>: Request Operation mode bits
000 = Set Normal Operation mode
001 = Set Sleep mode
010 = Set Loopback mode
011 = Set Listen- Only mode
100 = Set Co nfig uration mode
All other values for REQOP bits are invalid and should not be used
On power-up, REQOP = b’111’
bit 4 ABAT: Abort All Pending Transmissions bit
1 = Request abort of all pending transmit buffers
0 = Terminate request to abort all transmissions
bit 3 OSM: One-Shot mode bit
1 = Enabled. Message will only attempt to transmit one time
0 = Disabled. Messages will reattempt transmission, if required
bit 2 CLKEN: CLKOUT Pin Enable bit
1 = CLKOUT pin enabled
0 = CLKOUT pin disabled (Pin is in high-impedance state)
bit 1-0 CLKPRE<1:0>: CLKOUT Pin Prescaler bits
00 =F
CLKOUT = System Clock/1
01 =F
CLKOUT = System Clock/2
10 =F
CLKOUT = System Clock/4
11 =F
CLKOUT = System Clock/8
2003-2012 Microchip Technology Inc. DS21801G-page 61
MCP2515
REGISTER 10-2: CANS TAT – CAN STATUS REGISTER
(ADDRESS: XEh)
R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0
OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 OPMOD<2:0>: Opera tion mode bits
000 = Device is in the Normal Operation mode
001 = Device is in Sleep mode
010 = Device is in Loopback mode
011 = Device is in Listen-Only mode
100 = Device is in Configuration mode
bit 4 Unimplemented: Read as ‘0’
bit 3-1 ICOD<2:0>: Interrupt Flag Code bits
000 = No Interrupt
001 = Error Interrupt
010 = Wake-up Interrupt
011 = TXB0 Interrupt
100 = TXB1 Interrupt
101 = TXB2 Interrupt
110 = RXB0 Interrupt
111 = RXB1 Interrupt
bit 0 Unimplemented: Read as ‘0’
MCP2515
DS21801G-page 62 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 63
MCP2515
11.0 REGISTER MAP
The register map for the MCP2515 is shown in
Table 11-1. Address locations for each register are
determined by using the column (higher-order four
bit s) a nd row (l owe r-ord er fo ur bi ts ) val ues. T he re gis-
ters have been arranged to optimize the sequential
reading and writing of data. Some specific control and
status reg ister s allow in dividu al bit mo difica tion us ing
the SPI Bit Mod if y comma nd. Th e re gis ters t hat all ow
this command are shown as shaded locations in
Table 11-1. A summary of the MCP2515 control
registers is shown in Table 11-2.
TABLE 11-1: CAN CONTROLLER REGISTER MAP
TABLE 11-2: CONTROL REGISTER SUMMARY
Lower
Address
Bits
Higher-Order Address Bits
0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx
0000 RXF0SIDH RXF3SIDH RXM0SIDH TXB0CTRL TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL
0001 RXF0SIDL RXF3SIDL RXM0SIDL TXB0SIDH TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH
0010 RXF0EID8 RXF3EID8 RXM0EID8 TXB0SIDL TXB1SIDL TXB2SIDL RXB0SIDL RXB1SIDL
0011 RXF0EID0 RXF3EID0 RXM0EID0 TXB0EID8 TXB1EID8 TXB2EID8 RXB0EID8 RXB1EID8
0100 RXF1SIDH RXF4SIDH RXM1SIDH TXB0EID0 TXB1EID0 TXB2EID0 RXB0EID0 RXB1EID0
0101 RXF1SIDL RXF4SIDL RXM1SIDL TXB0DLC TXB1DLC TXB2DLC RXB0DLC RXB1DLC
0110 RXF1EID8 RXF4EID8 RXM1EID8 TXB0D0 TXB1D0 TXB2D0 RXB0D0 RXB1D0
0111 RXF1EID0 RXF4EID0 RXM1EID0 TXB0D1 TXB1D1 TXB2D1 RXB0D1 RXB1D1
1000 RXF2SIDH RXF5SIDH CNF3 TXB0D2 TXB1D2 TXB2D2 RXB0D2 RXB1D2
1001 RXF2SIDL RXF5SIDL CNF2 TXB0D3 TXB1D3 TXB2D3 RXB0D3 RXB1D3
1010 RXF2EID8 RXF5EID8 CNF1 TXB0D4 TXB1D4 TXB2D4 RXB0D4 RXB1D4
1011 RXF2EID0 RXF5EID0 CANINTE TXB0D5 TXB1D5 TXB2D5 RXB0D5 RXB1D5
1100 BFPCTRL TEC CANINTF TXB0D6 TXB1D6 TXB2D6 RXB0D6 RXB1D6
1101 TXRTSCTRL REC EFLG TXB0D7 TXB1D7 TXB2D7 RXB0D7 RXB1D7
1110 CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT
1111 CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL
Note: Shaded register locations indicate that these allow the user to manipulate individual bits using the Bit Modify command.
Register
Name Address
(Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/RST
Value
BFPCTRL 0C — — B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM --00 0000
TXRTSCTRL 0D — — B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM --xx x000
CANSTAT xE OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 — 100- 000-
CANCTRL xF REQOP2 REQOP1 REQOP0 ABAT OSM CLKEN CLKPRE1 CLKPRE0 1110 0111
TEC 1C Transmit Error Counter (TEC) 0000 0000
REC 1D Receive Error Counter (REC) 0000 0000
CNF3 28 SOF WAKFIL — — — PHSEG22 PHSEG21 PHSEG20 00-- -000
CNF2 29 BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 0000 0000
CNF1 2A SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0000 0000
CANINTE 2B MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE 0000 0000
CANINTF 2C MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF 0000 0000
EFLG 2D RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN 0000 0000
TXB0CTRL 30 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00
TXB1CTRL 40 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00
TXB2CTRL 50 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 -000 0-00
RXB0CTRL 60 — RXM1 RXM0 — RXRTR BUKT BUKT FILHIT0 -00- 0000
RXB1CTRL 70 — RSM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0 -00- 0000
MCP2515
DS21801G-page 64 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 65
MCP2515
12.0 SPI INTERFACE
12.1 Overview
The MCP2 515 is desig ned to inte rface dire ctly with the
Serial Perip heral Interface (SPI) port avail able on many
microc ontrollers and supports Mode 0,0 and M ode 1,1.
Commands and data are sent to the device via the SI
pin, with data being clocked in on the rising edge of
SCK. Data is driven out by the MCP2515 (on the SO
line) on the falling edge of SCK. The CS pin must be
held low whi le any o perati on is pe rformed . Table 12-1
shows the instruction bytes for all operations. Refer to
Figure 12-10 and Figure 12-11 for detailed input and
output timing diagrams for both Mode 0,0 and Mode
1,1 operation.
12.2 RESET Instruction
The RESET instruction can be used to re-initialize the
internal registers of the MCP2515 and set Configuration
mode. This command provides the same functionality,
via the SPI interface, as the RESET pin.
The RESET instruction is a single-byte instruction that
requires selecting the device by pulling CS low,
sending the instruction byte and then raising CS. It is
highly recommended that the Reset command be sent
(or the RESET p in be l owere d) a s part of th e p ow er-on
initialization sequence.
12.3 READ Instruction
The READ instruction is started by lowering the CS pin.
The READ instruction is then sent to the MCP2515
followed by the 8-bit address (A7 through A0). Next, the
data stored in the register at the selected address will
be shifted out on the SO pin.
The internal Address Pointer is automatically
incremented to the next address once each byte of
data is shifted out. Therefore, it is possible to read the
next consec utive regis ter addr ess by contin uing t o pr o-
vide clock pulses. Any number of consecutive register
locations can be read sequentially using this method.
The read operation is terminated by raising the CS pin
(Figure 12-2).
12.4 READ RX BUFFER Instructio n
The READ RX BUFFER instruction (Figure 12-3) pro-
vides a means to quickly address a receive buffer for
reading. This instruction reduces the SPI overhead by
one byte, the address byte. The command byte actually
has four possible values that determine the Address
Pointer location. Once the command byte is sent, the
controller clocks out the data at the address location
the sam e as the READ instruction (i.e., sequential reads
are possible). This instruction further reduces the SPI
overhead by automatically clearing the associated
receive f lag (CANINTF.RXnIF) when CS is raised at the
end of the command.
12.5 WRITE Instruction
The WRITE instruction is started by lowering the CS
pin. The WRITE instruction is then sent to the MCP2515
followed by the address and at least one byte of data.
It is possible to write to sequential registers by
continuing to clock in data byte s, as long as CS is hel d
low. Data will actually be written to the register on the
rising ed ge of the SC K lin e for th e D0 bit. If the CS line
is brought high before eight bits are loaded, the write
will be aborted for that data byte and previous bytes in
the command will have been written. Refer to the timing
diagram in Figure 12-4 for a more detailed illustration of
the byte write sequence.
12.6 LOAD TX BUFFER Inst ruction
The LOAD TX BUFFER instruction (Figure 12-5) elimi-
nates the eight-bit address required by a normal Write
command. The eight-bit instruction sets the Address
Pointer to one of six addresses to quickly write to a
tran smit buffer that po ints to the “ID” or “da ta” addr ess
of any of the three transmit buffers.
12.7 REQUEST-TO-SEND (RTS)
Instruction
The RTS command can be used to initiate message
transmission for one or more of the transmit buffers.
The MCP2515 is selected by lowering the CS pin. The
RTS com mand byte is then sent. Shown in Figure 12-6,
the last 3 bits of this command indicate which transmit
buf fer(s) are enabled to send .
This command will set the TxBnCTRL.TXREQ bit for
the respective buffer(s). Any or all of the last three bits
can be set in a single command. If the RTS command
is sent with nnn = 000, the command will be ignored.
12.8 READ STATUS Instruction
The READ STATUS inst ruction al lows si ngle i nstruc tio n
access to some of the often used status bits for
message reception and transmission.
The MCP2515 is selected by lowering the CS pin and
the Rea d Status comm and by te, s hown in Figure 12-8,
is sent to the MCP2515. Once the command byte is
sent, the MCP2515 will return eight bits of data that
contain the status.
If ad di t i on al c lo ck s a r e s e nt afte r t he fi rs t ei g ht b its are
transmitted, the MCP2515 will continue to output the
status bits as long as the CS pin is h eld low and clocks
are provided on SCK.
Note: The MCP2515 expects the first byte after
lowering CS to be the instruction/
command byte. This implies that CS must
be raised and then lowered again to
invoke another command.
MCP2515
DS21801G-page 66 2003-2012 Microchip Technology Inc.
Each status bit returned in this command may also be
read by using the standard Read command with the
appropri ate regi ste r addre ss.
12.9 RX STATUS Instruction
The RX STATUS instruction (Figure 12-9) is used to
quickly determine which filter matched the message
and message type (standard, extended, remote). After
the command byte is sent, the controller will return
8 bits of data that contain the status data. If more clocks
are sent after the eight bits are transmitted, the
controll er will cont inue to output th e same sta tus bits a s
long as the CS pin stays low and clocks are provided.
12.10 BIT MODIFY Instruction
The BIT MODIFY instruc tion prov ides a m eans for set-
ting or clearing individual bi ts in specific status and co n-
trol registers. This command is not available for all
registers. See Section 11.0 “Register Map” to
determine which registers allow the use of this
command.
The part is selected by lowering the CS pin and the Bit
Modify command byte is then sent to the MCP2515.
The command is followed by the address of the
register, the mask byte and finally the data byte.
The ma sk byte determi nes whic h bits in the register will
be allowed to change. A ‘1’ in the mask byte will allow
a bit in the regi ster to change, while a ‘0’ will not.
The data byte determines what value the modi fied bits
in the register will be changed to. A ‘1’ in the data byte
will set the bit and a ‘0’ will clear the bit, provided that
the mask for that bit is set to a ‘1’ (see Figure 12-7).
FIGU RE 12- 1: BIT MODIFY
TABLE 12-1: SPI INSTRUCTION SET
Note: Executing the Bit Modify command on
registers that are not bit-modifiable will
force the mask to FFh . This will allow by te-
writes to the registers, not bit modify.
Mask byte
Data byte
Previous
Register
Contents
Resulting
Register
Contents
001 11100
XX1 100XX
010 11000
011 10000
Instruction Name Instruction Format Description
RESET 1100 0000 Resets internal registers to default state, set Configuration mode.
READ 0000 0011 Read data from register beginning at selected address.
READ RX BUFFER 1001 0nm0 When reading a receive buffer, reduces the overhead of a normal
Read command by placing the Address Pointer at one of four
locations, as indicated by ‘n,m’. Note: The associated RX flag bit
(CANINTF.RXn IF) will be cleared after bringing C S high.
WRITE 0000 0010 Write data to register beginning at selected address.
LOAD TX BUFFER 0100 0abc When loading a transmit buffer, reduces the overhead of a normal
Write command by placing the Address Pointer at one of six
locations as indicated by ‘a,b,c’.
RTS
(Message
Request-To-Send)
1000 0nnn Instructs controller to begin message transmission sequence for
any of the transmit buffers.
READ STATUS 1010 0000 Quick polling command that reads several status bits for transmit
and receive functions.
RX STATUS 1011 0000 Quick polling command that indicates filter match and message
type (standard, extended and/or remote) of received message.
BIT MODIFY 0000 0101 Allows the user to set or clear individual bits in a particular
register. Note: Not all registers can be bit-modified with this
command. Executing this command on registers that are not bit-
modifiable will force the mask to FFh. See the register map in
Section 11.0 “Register Map” for a list of the registers that apply.
1000 0nnn Request-to-send for TXBO
Request-to-send for TXB1
Request-to-send for TXB2
2003-2012 Microchip Technology Inc. DS21801G-page 67
MCP2515
FIGURE 12-2: READ INSTRUCTION
FIGURE 12-3: READ RX BUFFER INSTRUCTION
FIGURE 12-4: BYTE WRITE INSTRUC TION
SO
SI
SCK
CS
0 23456789101112131415161718192021221
01000001
A7 6 5 4 1A0
76543210
Instruction Address Byte
Data Out
High-Impedance
23
32 Don’t Care
SO
SI
SCK
CS
0 234567891011121314151
mn
76543210
Instruction
Data Out
High-Impedance
Don’t Care
n m Address Points to Address
00Receive Buffer 0,
Start at RXB0SIDH 0x61
01Receive Buffer 0,
Start at RXB0D0 0x66
10Receive Buffer 1,
Start at RXB1SIDH 0x71
11Receive Buffer 1,
Start at RXB1D0 0x76
0
01001
SO
SI
SCK
CS
0 23456789101112131415161718192021221
0000000 A7 6 5 4 1A076543210
Instruction
High-Impedance
23
32
1
Address Byte Data Byte
MCP2515
DS21801G-page 68 2003-2012 Microchip Technology Inc.
FIGURE 12-5: LOAD TX BUFFER
FIGURE 12-6: REQUEST-TO-SEND (RTS) INSTRUCT ION
FIGURE 12-7: BIT MODIFY INSTRUCTION
SO
SI
SCK
CS
0 234567891011121314151
ac00010 b76543210
Instruction Data In
High-Impedance
a b c Address Points to Addr
000TX buff er 0, Start at
TXB0SIDH 0x31
001TX buff er 0, Start at
TXB0D0 0x36
010TX buff er 1, Start at
TXB1SIDH 0x41
011TX buff er 1, Start at
TXB1D0 0x46
100TX buff er 2, Start at
TXB2SIDH 0x51
101TX buff er 2, Start at
TXB2D0 0x56
SO
SI
SCK
CS
0 2345671
T2 T000
0
01
Instruction
High-Impedance
T1
SO
SI
SCK
CS
0 2 3 4 5 6 7 8 9 101112131415161718192021221
1100000 A7 6 5 4 1A0 76543210
Instruction
High-Impedance
32
0
Address By te Mask By te
76543210
2324 25 26 2728 29 30 31
Data Byte
Note: Not all registers can be accessed with
this comm and. See the register ma p for a
list of the registers that apply.
2003-2012 Microchip Technology Inc. DS21801G-page 69
MCP2515
FIGURE 12-8: READ STATUS INSTRUCTION
FIGURE 12-9: RX ST ATUS INSTRUCTION
SO
SI
SCK
CS
0 23456789101112131415161718192021221
00001010
76543210
Instruction
Data Out
High-Impedance
23
Don’t Care
CANINTF.RX0IF
CANINTFL.RX1IF
CANINTF.TX0IF
CANINTF.TX1IF
CANINTF.TX2IF
TXB2CNTRL.TXREQ
TXB1CNTRL.TXREQ
TXB0CNTRL.TXREQ
76543210
Data Ou t
Repeat
SO
SI
SCK
CS
0 23456789101112131415161718192021221
00011010
76543210
Instruction
Data Out
High-Impedance
23
Don’t Care
76543210
Data Out
Repeat
2 1 0 Filter Match
000RXF0
001RXF1
010RXF2
011RXF3
100RXF4
101RXF5
110RXF0 (rollover to RXB1)
111RXF1 (rollover to RXB1)
CANINTF.RXnIF bit s a re map ped to
bits 7 and 6.
7 6 Received Message
00No RX message
01Message in RX B0
10Message in RX B1
11Messages in both buffers* The extended ID bit is mapped to
bit 4. The RTR bit is mapped to
bit 3.
4 3 Msg Type Received
00Standard data frame
01Standard remote frame
10Extended data frame
11Extended remote frame
* Buffer 0 has higher priority, therefore, RXB0 status is
reflected in bits 4:0.
MCP2515
DS21801G-page 70 2003-2012 Microchip Technology Inc.
FIGURE 12 - 10: SPI INPUT TIMING
FIGU RE 12-11: SPI O U TP UT TI MI NG
CS
SCK
SI
SO
1
5
4
7
6
3
10
2
LSB in
MSB in
High-Impedance
11
Mode 1,1
Mode 0,0
CS
SCK
SO
8
13
MSB out LSB out
2
14
Don’t Care
SI
Mode 1,1
Mode 0,0
9
12
2003-2012 Microchip Technology Inc. DS21801G-page 71
MCP2515
13.0 ELECTR ICAL CHARACTERISTICS
13.1 Absolute Maximum Ratings †
VDD.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ................................................................. .........................................-0.6V to V DD +1.0V
Storage temperature...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
Soldering temperature of leads (10 seconds).......................................................................................................+300°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stres s ra tin g on ly a nd functio nal operation of the device at those or any ot her c onditions abo ve thos e indica ted i n
the opera tional listi ngs of this s pecificatio n is not implie d. Exposure to maximum ra ting conditi ons for extend ed periods
may affect device reliability.
MCP2515
DS21801G-page 72 2003-2012 Microchip Technology Inc.
TABLE 13-1: DC CHARACTERISTICS
DC Charac teristics Industrial (I): TAMB = -40°C to +85°C VDD = 2.7V to 5.5V
Extended (E) : TAMB = -40°C to +125°C VDD = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
VDD Supply Voltage 2.7 5.5 V
VRET Register Retention Voltage 2.4 — V
High-Level Input Voltage
VIH RXCAN 2 VDD + 1 V
SCK, CS, SI, TXnRT S Pins 0.7 VDD VDD + 1 V
OSC1 0.85 VDD VDD V
RESET 0.85 VDD VDD V
Low-Level Input Voltage
VIL RXCAN, TXnRTS Pins -0.3 .15 VDD V
SCK, CS, SI -0.3 0.4 VDD V
OSC1 VSS .3 VDD V
RESET VSS .15 VDD V
Low-Level Output Voltage
VOL TXCAN — 0.6 V IOL = +6.0 mA, VDD = 4.5V
RXnBF Pins — 0.6 V IOL = +8.5 mA, VDD = 4.5V
SO, CLKOUT — 0.6 V IOL = +2.1 mA , V DD = 4.5V
INT —0.6VIOL = +1.6 mA, VDD = 4.5V
High-Level Output Voltage V
VOH TXCAN, RXnBF Pins VDD – 0.7 — V IOH = -3.0 mA , V DD = 4.5V
SO, CLKOUT VDD – 0.5 — V IOH = -400 µA, VDD = 4.5V
INT VDD – 0.7 — V IOH = -1 .0 mA, VDD = 4.5V
Input Leakage Current
ILI All I/O except OSC1 and
TXnRTS pins -1 +1 µA CS = RESET = VDD,
VIN = VSS to VDD
OSC1 Pin -5 +5 µA
CINT Internal Capacitance
(All Inputs and Outputs) —7pFTAMB = 25°C, fC = 1.0 MHz,
VDD = 0V (Note 1)
IDD Operating Current — 10 mA VDD = 5.5V, FOSC = 25 MHz,
FCLK = 1 MHz, SO = Open
IDDS Standby Current (Sleep mode) — 5 µA CS, TXnRT S = VDD, Inputs tied to
VDD or VSS, -40°C TO +85° C
—8µACS,
TXnRT S = VDD, Inputs tied to
VDD or VSS, -40°C TO +125°C
Note 1: This parameter is periodically sampled and not 100% tested.
2003-2012 Microchip Technology Inc. DS21801G-page 73
MCP2515
TABLE 13-2: OSCILLATOR TIMING CHARACTERISTICS
TABLE 13-3: CAN INTERFACE AC CHARACTERISTICS
TABLE 13-4: RESET AC CHARACTERISTICS
Oscillator Timing Characteristics(Note) Industrial (I): TAMB = -40°C to +85°C VDD = 2.7V to 5.5V
Extende d (E) : TAMB = -40°C to +125°C VDD = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
FOSC Clock-In Frequency 1
140
25 MHz
MHz 4.5V to 5.5V
2.7V to 5.5V
TOSC Clock-In Period 25
40 1000
1000 ns
ns 4.5V to 5.5V
2.7V to 5.5V
TDUTY Duty Cycle
(External Clock Input) 0.45 0.55 — TOSH/(TOSH + TOSL)
Note: This parameter is periodically sampled and not 100% tested.
CAN Interface AC Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 2.7V to 5.5V
Extende d (E) : TAMB = -40°C to +125°C VDD = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
TWF Wake-up Noise Filter 100 — ns
RESET AC Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 2.7V to 5.5V
Extende d (E) : TAMB = -40°C to +125°C VDD = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
trl RESET Pin Low Time 2 — µs
MCP2515
DS21801G-page 74 2003-2012 Microchip Technology Inc.
TABLE 13-5: CLKOUT PIN AC CHARACTERISTICS
FIGURE 13-1: ST ART-OF-FRAME PIN AC CHARACTERISTICS
CLKOUT Pin AC/DC Characteristics Industrial (I): TAMB = -40°C to +85°C VDD = 2.7V to 5.5V
Extended (E) : TAMB = -40°C to +125°C VDD = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
thCLKOUT CLKOUT Pin High Time 15 — ns TOSC = 40 ns (Note 1)
tlCLKOUT CLKOUT Pin Low Time 15 — ns TOSC = 40 ns (Note 1)
trCLKOUT CLKOUT Pin Rise Time — 5 ns Measured from 0.3 VDD to 0.7 VDD
(Note 1)
tfCLKOUT CLKOUT Pin Fall Time — 5 ns Me asured fro m 0.7 VDD to 0.3 VDD
(Note 1)
tdCLKOUT CLOCKOUT Propagation Delay — 100 ns Note 1
15 thSOF Start-Of-Frame High Time — 2 TOSC ns Note 1
16 tdSOF Start-Of-Frame Propagation
Delay —2TOSC +
0.5 TQns Measured fro m CAN bit sample
point. Device is a receiver.
CNF1.BRP<5:0> = 0 (Note 2)
Note 1: All CLKOUT mode functionality and output frequency is tested at device frequency limits, however, CLKOUT prescaler
is set to divide by one. This parameter is periodically sampled and not 100% tested.
2: Design guidance only, not tested.
RXCAN 16
15
sample point
2003-2012 Microchip Technology Inc. DS21801G-page 75
MCP2515
TABLE 13-6: SPI INTERFACE AC CHARACTERISTICS
SPI Interface AC Characteristics Industrial (I ): TAMB = -40°C to +85°C VDD = 2.7V to 5.5V
Extend ed (E): TAMB = -40°C to +125°C VDD = 4.5V to 5.5V
Param.
No. Sym Characteristic Min Max Units Conditions
FCLK Clock Frequency — 10 MHz
1T
CSS CS Setup Time 50 — ns
2T
CSH CS Hold Time 50 — ns
3T
CSD CS Disable T ime 50 — ns
4T
SU Data Setup Time 10 — ns
5T
HD Data Hold Time 10 — ns
6T
RCLK Rise Time — 2 µs Note 1
7T
FCLK Fall Time — 2 µs Note 1
8T
HI Clock High Time 45 — ns
9T
LO Clock Low Time 45 — ns
ns
10 TCLD Clock Delay Time 50 — ns
11 TCLE Clock Enable Ti me 50 — ns
12 TVOutput Valid from Clock Low — 45 ns
13 THO Output Hold Time 0 — ns
14 TDIS Output Disable Time — 100 ns
Note 1: This parameter is not 100% tested.
MCP2515
DS21801G-page 76 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 77
MCP2515
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
18-Lead PDIP (300 mil)
18-Lead SOIC (300 mil)
20-Lead TSSOP (4.4 mm)
XXXXXXXX
XXXXXNNN
YYWW
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example:
Example:
Example:
MCP2515
IST ^ 256
1035
MCP2515
1035256
MCP2515-I/P^^
0434256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanume ric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designat or ( )
can be found on the outer packaging for this package.
Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
E/SO^^
3
e
3
e
3
e
XXXXX
20-Lead QFN (4x4)
YWWNNN
Example:
XXXXXX
2515
035256
E/ML^^
3
e
MCP2515
DS21801G-page 78 2003-2012 Microchip Technology Inc.
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2003-2012 Microchip Technology Inc. DS21801G-page 79
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2515
DS21801G-page 80 2003-2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2012 Microchip Technology Inc. DS21801G-page 81
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2515
DS21801G-page 82 2003-2012 Microchip Technology Inc.
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2003-2012 Microchip Technology Inc. DS21801G-page 83
MCP2515
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP2515
DS21801G-page 84 2003-2012 Microchip Technology Inc.
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2003-2012 Microchip Technology Inc. DS21801G-page 85
MCP2515
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MCP2515
DS21801G-page 86 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 87
MCP2515
APPENDIX A: REVISION HISTORY
Revision G (August 2012)
The following is the list of modifications:
1. Upda t ed c on t en t in R eg ist er 4 -1, Regis t er 4- 12 ,
Register 4-13, Register 4-16, Register 4-17.
Revision F (October 2010)
The following is the list of modifications:
1. Added 20-lead QFN package (4x4) and related
information.
2. Updated Table 1-1.
3. Updated the Product Identification System
section.
Revision E (November 2007)
• Removed preliminary watermark.
• Updated templates.
• Updated register information.
• Updated package outline drawings.
Revision D (April 2005)
• Added Table 8-1 and Table 8-2 in Section 8.0
“Oscillator”. Added note box following tables.
• Changed address bits in column heading in
Table 11-1, Section 11.0 “Register Map”.
• Modified Section 14.0 “Pa ckaging Information ”
to reflect pb free device markings.
• Appendix A Revision History: Rearranged order of
importance.
Revision C (November 2004)
•Section 9.0 “RESET” add ed.
• Heading 12.1: added notebox.
Heading 12.6: Changed verbiage within
paragraph in Section 12.0 “SPI Interface”.
• Added Appendix A: Revision History.
Revision B (September 2003)
• Front p age bull et: S tan dby current (typical) (Sle ep
mode) changed from 10 µA to 1 µA.
• Added notebox for maximum frequency on
CLKOUT in Section 8.2 “CLKOUT Pin”.
•Section 12.0 “SPI Interface”, Table 12-1:
- Changed supply voltage minimum to 2.7V.
- Internal Capacit ance: Changed VDD condition
to 0V.
- Standby Current (Sleep mode): Split
specification into -40°C to +85°C and
-40°C to +125°C.
Revision A (May 2003)
• Original Release of this Document.
MCP2515
DS21801G-page 88 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 89
MCP2515
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP2515: CAN Controller with SPI Interface
MCP2515T: CAN Controller with SPI Interface
(Tape and Reel)
Temperature
Range: I= -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package: P = Plastic DIP (300 mil Body), 18-Lead
SO = Plastic SOIC (300 mil Body), 18-Lead
ST = TSSOP, (4.4 mm Body), 20-Lead
ML = Plastic QFN, (4x4 mm Body), 20-Lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP2515-E/P: Extended Tem perature,
18LD PDIP package.
b) MCP2515-I/P: Industrial Temperature,
18LD PDIP package.
c) MCP2515-E/SO: Extended Temperature,
18LD SOIC package.
d) MCP2515-I/SO: Industrial Tem perat ure,
18LD SOIC package.
e) MCP2515T-I /SO :Tape and Reel,
Industrial Temperature,
18LD SOIC package.
f) MCP2515-I/ST: In dustrial Tem perat ure,
20LD TSSOP package.
g) MCP2515T-I /ST: Tape and Reel,
Industrial Temperature,
20LD TSSOP package.
h) MCP2515-E/ML: Extended Temperature,
20LD QFN package.
i) MC P2515T-E/MLTape and Reel,
Extended Temperature,
20LD QFN package.
j) MC P2515-I /ML: Industr ial Tem perature,
20LD QFN package.
k) MCP2515T-I/ML Tape and Reel,
Industrial Temperature,
20LD QFN package.
–
MCP2515
DS21801G-page 90 2003-2012 Microchip Technology Inc.
NOTES:
2003-2012 Microchip Technology Inc. DS21801G-page 91
Information contained in this publication regarding device
applications a nd t he lik e is provided only for yo ur conve nience
and may be superseded by updates . It is y our responsibilit y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporat ed in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor ,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE, In-Cir c u it Se r i a l
Programming, ICSP, Mindi, MiWi, MPAS M, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporat ed in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-504-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCU s and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS21801G-page 92 2012 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Su pport:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
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Tel: 678-957-9614
Fax: 678-957-1455
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Fax: 774-760-0088
Chicago
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Fax: 630-285-0075
Cleveland
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Tel: 216-447-0464
Fax: 216-447-0643
Dallas
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Fax: 972-818-2924
Detroit
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Fax: 248-538-2260
Indianapolis
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Los A n ge les
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Fax: 949-462-9608
Santa Clara
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Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
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Fax: 86-28-8665-7889
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Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
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Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
China - Hong K ong SAR
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Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
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Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
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Fax: 86-29-8833-7256
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Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
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ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
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Tel: 91-20-2566-1512
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Japan - Osaka
Tel: 81-66-152-7160
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Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
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Fax: 82-53-744-4302
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Fax: 82-2-558-5932 or
82-2-558-5934
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Fax: 886-7-330-9305
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Fax: 886-2-2508-0102
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Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
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Fax: 45-4485-2829
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/11
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