© Copyright 2006 Advanced Micro Devices, Inc. All rights reserved. Publication# 20732 Rev: EAmendment/0
Issue Date: March 2006
DRAFT
Am186 and Am188
High-Performance, 80C186- and 80C188-Compatible,
16-Bit Embedded Microcontrollers with RAM
DISTINCTIVE CHARACTERISTICS
nE86TM family 80C186- and 80C188-compatible
microcontrollers with enhanced bus interface
— Lower system cost with high performance
—3.3-V
± 0.3-V operation with 5-V tolerant I/O
nMemory integration
— 32 Kbyte of internal SRAM
— Internal SRAM provides same performance as
zero-wait-state extern al mem ory
nHigh performance
— 25-, 33-, 40- and 50-MHz operating frequencies
— Supports zero-wait-state operation at 50 MHz
with 55-ns external memory
— 1-Mbyte memory address space
— 64-Kbyte I/O space
nEnhanced features provide faster access to
memory and various clock input modes
— Nonmultiplexed address bus provides glueless
interface to external RAM and ROM
— Phase-locked loop (PLL) enables processor to
operate at up to four times clock input frequency
nEnhanced integrated peripherals
— Thirty-two programmable I/O (PIO) pins
— Asynchronous serial port allows full-duplex, 7-bit
or 8-bit data transfers
— DMA to and from asynchronous serial port
— Synchronous serial in terface allows half-duplex,
bidirectional data transfer to and from ASICs
— Reset co nfig uration regi ste r
— Additional external interrupts
— Hardware watchdog timer can generate NMI or
system re set
— Pseudo static RAM (PSRAM) controller includes
auto refresh capability
nFamiliar 80C186 peripherals with enhanced
functionality
— Two independent DMA channels
— Programmable interrupt controller with six
external interrupts
— Three programmable 16-bit timers
— Programmable memory and peripheral
chip-select logic
— Programmable wait state generator
— Power-save clock mode
nSoftware-compatible with the 80C186 and
80C188 microcontrollers
nWidely available native development tools,
applications, and system software
nAvailable in the following packages:
— 100-pin, thin quad flat pack (TQFP)
— 100-pin, plastic quad flat pack (PQFP)
GENERAL DESCRIPTION
The Am186TMER and Am188TMER microcontrollers are
part of the AMD E86™ family of embedded
microcontrollers and microprocessors based on the
x86 architecture. The Am186ER and Am188ER
microcontrollers are the ideal upgrade for designs
requiring 80C186/80C188 microcontroller
compatibility, increased performance, serial
communica tions, a dire ct bus in terf ace, a nd i ntegrate d
memory.
The Am186ER and Am188ER microcontrollers
integrate memory and the functions of the CPU,
nonmultiplexed address bus, timers, chip selects,
interr upt control ler, DM A cont roller, PSRAM controll er,
watchdog timer, asynchronous serial port,
synchronous serial interface, and programmable I/O
(PIO) pins on one chip. Compared to the 80C186/
80C188 microcontrollers, the Am186ER and
Am188ER microcontrollers enable designers to reduce
the size, power consumption, and cost of embedded
systems, while increasing functionality and
performance.
The Am186ER and Am188ER microcontrollers have
been designed to meet the most common
requirements of embedded products developed for the
communications, office automation, mass storage, and
general embedded markets. Specific applications
include feature phones, cellular phones, PBXs,
multiplex ers, modems, disk drives, hand-held terminals
and desktop terminals, fax machines, printers,
photocopiers, and industrial controls.
ER
TMTM
ER
2Am186
TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Am186™ER MICROCONTROLLER BLOCK DIAGRAM
Note:
* All PIO s ign als are shared with other physic al pins. See the p in descriptions beg in nin g on page 30 and Table 3 on page 36 for
information on shared functions.
Registers
Control
S2
Interrupt
Control Unit
Timer Control
Unit DMA
Unit
Bus
Interface
Unit
Execution
Unit
Chip-Select
Unit
Clock and
Power
Management
Unit
Control
Registers
16-Bit Count
Registers
Max Count A
Registers 16-Bit Count
Registers
20-Bit Destination
Pointers
20-Bit Source
Pointers
Control
Registers
Control
Registers
Control
Registers
01 (WDT)2 0 1
Max Count B
Registers
Refresh
Control
Unit
Control
Registers Control
Registers Control
Registers
CLKOUTB
CLKOUTA INT4
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
INT0 TMROUT0 TMROUT1
DRQ0 DRQ1
VCC
GND
TMRIN0 TMRIN1
ARDY
SRDY
DT/R
DEN
HOLD
HLDA
Asynchronous
Serial Port
Synchronous Serial
Interface
TXD
RXD
SCLK SDATA
SDEN0 SDEN1
NMI
A19–A0
AD15–AD0
ALE
BHE/ADEN
WR
WLB
WHB
RD
RES
LCS/ONCE0
MCS2–MCS0
PCS6/A2
PCS3–PCS0
PCS5/A1
UCS/ONCE1
X2
X1
Control
Registers
PSRAM
Control
Unit
MCS3/RFSH
PIO
Unit PIO31–
PIO0*
S6/
UZI/
CLKSEL2
CLKSEL1
32 Kbyte
SRAM
(16K x 16)
S1/IMDIS
S0/SREN
Watchdog
Timer (WDT)
Am186TMER and Am188TMER Microcontrollers Data Sheet 3
DRAFT
Am188™ER MICROCONTROLLER BLOCK DIAGRAM
Notes:
* All PIO s ign als are shared with other physic al pins. See the p in descriptions beg in nin g on page 30 and Table 3 on page 36 for
information on shared functions.
20-Bit Source
Pointers
Interrupt
Control Unit
Timer Control
Unit DMA
Unit
Bus
Interface
Unit
32 Kbyte
SRAM
(32K x 8) Chip-Select
Unit
Clock and
Power
Manage men t
Control
Registers
16-Bit Coun t
Registers
Max Count A
Registers 16-Bit Count
Registers
20-Bit Destination
Pointers
Control
Registers
Control
Registers
Control
Registers
01 (WDT)2 0 1
Max Count B
Registers
Refresh
Control
Unit
Control
Registers Control
Registers Control
Registers
CLKOUTB
CLKOUTA INT4
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
INT0 TMROUT0 TMROUT1
DRQ0 DRQ1
VCC
GND
TMRIN0 TMRIN1
Asynchronous
Serial Port
Synchronous Serial
Interface
TXD
RXD
SCLK SDATA
SDEN0 SDEN1
NMI
A19–A0
AD7–AD0
ALE
WR
WB
RD
RES
LCS/ONCE0
MCS2–MCS0
PCS6/A2
PCS3–PCS0
PCS5/A1
UCS/ONCE1
X2
X1
Control
Registers
PSRAM
Control
Unit
MCS3/RFSH
PIO
Unit PIO31–
PIO0*
Control
Registers
AO15–AO8
RFSH2/ADEN
Execution
Unit
ARDY
SRDY
DT/R
DEN
HOLD
HLDA
S6/
UZI/
CLKSEL2
CLKSEL1
S1/IMDIS
S0/SREN
S2
Watchdog
Timer (WDT)
4Am186
TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order numbers (valid combinations) are
formed by a combination of th e elements below.
–25 = 25 MHz
–33 = 33 MHz
–40 = 40 MHz
–50 = 50 MHz
TEMPERATURE RANGE
C = ER Commercial (TC=0°C to +100°C)
I = ER Industrial (TA=–40°C to +85°C)
where: TC= case temperature
where: TA= ambient temperature
SPEED OPTION
DEVICE NUMBER/DESCRIPTION
LEAD FORMING
\W=Trimmed and Formed
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
PACKAGE TYPE
V=100-Pin Thin Quad Flat Pack (TQFP)
K=100-Pin Plastic Quad Flat Pack (PQFP)
Am186ER = High-Performance, 80C186-Compatible,
16-Bit Embedded Microcontroller with RAM
Am188ER = High-Performance, 80C188-Compatible,
16-Bit Embedded Microcontroller with RAM
–50 V C \WAm186ER
Valid Combinations
Am186ER–25
Am186ER–33
Am186ER–40
Am186ER–50
VC\W or
KC\W
Am188ER–25
Am188ER–33
Am188ER–40
Am188ER–50
VC\W or
KC\W
Am186ER–25
Am186ER–33
Am186ER–40
Am186ER–50
KI\W or
VI\W
Am188ER–25
Am188ER–33
Am188ER–40
Am188ER–50
KI\W or
VI\W
Am186TMER and Am188TMER Microcontrollers Data Sheet 5
DRAFTDRAFT
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ................. ................................................................... ................................. 1
Am186™ER Microcontroller Block Diagram .......................... .. ....... .......... ................ ................... 2
Am188™ER Microcontroller Block Diagram ........ .. .. .................................................................... 3
Ordering Information .................................................................................................................... 4
List of Figures .............................................................................................................................. 9
List of Tables ................................................................................... ............................................ 9
Revision History ......................................................................................................................... 10
E86™ Family of E mbedded Microprocessors and Microcontrollers .................... ...................... 12
Relate d D o c um e n ts ........ ...... .. ....... .. ....... ....... .. ...... ... ...... ....... .. ....... .. ....... ...... .. ....... .. ..... 13
Demonstration Boar d Products .................................................... .................................. 13
Third-Party Development Support Products ........ ..... ... ..... ... .. ..... ... ..... ... ... ..... ... ..... .. ... ..... ... .....13
Customer Service .......................................................................................................... 13
Key Features and Benefits ............... .................................... ............. ...................... .................. 14
Application Considerations ............................................................................................ 14
Comparison of the Am186™ER and 80C 186 Microcontroller s ................................................. 15
TQFP Connection Diagram and Pinouts—Am186™E R Mic ro c o n tr o lle r .......... ....... .. ....... .. ....... 1 6
TQFP Pin Assignments—Am186™ER Microcontroller (Sorted by Pin Number) ............ .......... 17
TQFP Pin Assignments—Am186™ER Microcontroller (Sorted by Pin Name) .......................... 18
TQFP Connection Diagram and Pinouts—Am188™ ER Mic ro c o n tr o lle r .......... ....... .. ....... .. ....... 1 9
TQFP Pin Assignments—Am188™ER Microcontroller (Sorted by Pin Number) ............ .......... 20
TQFP Pin Assignments—Am188™ER Microcontroller (Sorted by Pin Name) ........ ................. 21
PQFP Connection Diagram and Pinouts—Am186™ER Microcontroller ................................... 22
PQFP Pin Assignments—Am186™ER Microcontr oller (Sorted by Pin Number) ....... ............... 23
PQFP Pin Assignments—Am186™ER Microcontr oller (Sorted by Pin Name) .......... .. ............. 24
PQFP Connection Diagram and Pinouts—Am188™ER Microcontroller ................................... 25
PQFP Pin Assignments—Am188™ER Microcontr oller (Sorted by Pin Number) ....... ............... 26
PQFP Pin Assignments—Am188™ER Microcontr oller (Sorted by Pin Name) .......... .. ............. 27
Logic Symbol—Am186™ER Microcontroller ......... ................ ...................... .. ....... .. ....... .......... .. 28
Logic Symbol—Am188™ER Microcontroller ......... ................ ...................... .. ....... .. ....... .......... .. 29
Pin De sc ripti ons .... .. ...... ... ...... .. ....... ....... .. ....... .. ...... ....... .. ....... .. ....... ...... .. ....... .. ....... ............. .. ... 30
Pins Used by Emulators ................................................................................................. 30
A19–A0 (A19/PIO9 , A18/PIO8, A17/PIO7) ........................... .. ....... ................................ 30
AD7–AD0 ....................................................................................................................... 30
AD15–AD8 (Am186™ER Microcontroller) ................... .. .. .. ....................... .. .. .. .. ............. 30
AO15–AO8 (Am188™ER Microcontroller) ............ ................ .. ....... ................................ 30
ALE ................................................................................................................................ 31
ARDY ............................................................................................................................. 31
BHE/ADEN (Am186™ER Microcontroller Only) .......... ....... .......... ................ ................. 31
CLKOUTA ...................................................................................................................... 31
CLKOUTB ...................................................................................................................... 31
DEN/PIO5 ...................................................................................................................... 31
DRQ1 – DR Q 0 (DRQ1 /PIO13, D R Q0 /P I O1 2 ) ....... .. ....... .. ....... ...... ... ...... ... ...... ....... .. ....... 32
DT/R/PIO4 ..................................................................................................................... 32
GND ............................................................................................................................... 32
HLDA ............................................................................................................................. 32
HOLD ............................................................................................................................. 32
INT0 ............................................................................................................................... 32
INT1/SELECT ................................................................................................................ 32
INT2/INTA0/PIO31 ......................................................................................................... 33
INT3/INTA1/IRQ ........... ................ ........... ............... ........... ................ ............... ........... ... 33
INT4/PIO30 .................................................................................................................... 33
6Am186
TMER and Am188TMER Microcontrollers Data Sheet
DRAFTDRAFT
LCS/ONCE0 .... ....... ......... ........ ......... ....... ......... ......... ...... ......... ......... ......... ...... ......... ..... 33
MCS3/RFSH/PIO25 ....................................................................................................... 33
MCS2–MCS0 (MCS2/PIO24, MCS1/PIO15, MCS0/PIO14) .......................................... 34
NMI ................................................................................................................................ 34
PCS3–PCS0 (PCS3/PIO19, PCS2/PIO18, PCS1/PIO17, PCS0/PIO16) ...................... 34
PCS5/A1/PIO3 ............................................................................................................... 34
PCS6/A2/PIO2 ............................................................................................................... 34
PIO31–PIO0 (Shared) .................................................................................................... 35
RD .................................................................................................................................. 35
RES .... ......... ......... ........ ....... ......... ......... ......... ...... ......... ......... ...... ......... ......... ......... ....... 35
RFSH2/ADEN (Am188™ER Microcontroller Only) ......................... .................... ........... 35
RXD/PIO28 .................................................................................................................... 35
S2 ..... ......... ...... ......... ......... ......... ...... ......... ......... ....... ........ ......... ......... ....... ......... ........... 35
S1/IMDIS ....... ......... ...... ......... ......... ....... ......... ........ ......... ....... ......... ......... ........ ....... ....... 37
S0/SREN ..... ......... ...... ......... ......... ......... ...... ......... ......... ....... ........ ......... ......... ....... ......... 3 7
S6/CLKSEL1/P IO29 ..... ......... ....... ......... ......... ........ ....... ......... ......... ...... ......... ......... ....... 37
SCLK/PIO20 .................................................................................................................. 37
SDATA/PIO21 ................................................................................................................ 37
SDEN1/PIO23, SDEN0/PIO22 ....................................................................................... 37
SRDY/PIO6 .................................................................................................................... 38
TMRIN0/PIO11 .............................................................................................................. 38
TMRIN1/PIO0 ................................................................................................................ 38
TMROUT0/PIO10 .......................................................................................................... 38
TMROUT1/PIO1 ............................................................................................................ 38
TXD/P IO27 .... ....... ........ ......... ......... ....... ......... ........ ......... ....... ......... ......... ...... ......... ....... 38
UCS/ONCE1 .................................................................................................................. 38
UZI/CLKSEL2/PIO26 ..................................................................................................... 38
VCC ................................................................................................................................ 39
WHB (Am186™ER Microcontroller Only) ...................................................................... 39
WLB (Am186™ER Microcontrolle r Only).................... .. ....... .......... ................ .. ............... 39
WB (Am188™ER Microcontroller Only) ......................................................................... 39
WR ................................................................................................................................. 39
X1 ... ........ ......... ......... ....... ........ ......... ....... ......... ......... ........ ....... ......... ......... ......... ........... 39
X2 ... ........ ......... ......... ....... ........ ......... ....... ......... ......... ........ ....... ......... ......... ......... ........... 39
Functional Description ..... ..................................................... ..................................................... 40
Memor y Or ga n i za t i on ... ... .. ...... ... ...... ....... .. ....... .. ....... ...... .. ....... .. ....... ....... .. ...... ... ...... ..... 40
I/O Space ....................................................................................................................... 40
Bus Operation ............................................................................................................................ 41
Bus Interface Unit ............................................................................................................ .......... 41
Nonmultiplexed Address Bus ......................................................................................... 41
Byte Write Enables ........................................................................................................ 41
Output Enable ................ .......... ................ ............................... .. ....... .............................. 41
Pseudo Static RAM (PSRAM) Support ................................... .. ....... .............................. 44
Peripheral Control Block (PCB) ....... .. .. ......................................................................................44
Reading and Writing the PCB ...................... ....................... .. .. .. .. .. ................................. 44
Clock and Power Management ............. .. .. .. .. ...................... ................................ .. .. .. .. .. ........... .. 44
Phase-Locked Loop (PLL) ................. .. .. .. .. .. ...................... ..................... .. .. .. .. .. ............. 44
Crystal-Driven Clock Source .......................................................................................... 45
External Source Clock ................................................................................................... 45
System Clocks ............................................................................................................... 48
Powe r- S a ve Op e ration .......... ....... .. ....... .. ....... ...... .. ....... .. ....... ...... ... ...... ... ...... ....... .. ....... 4 8
Initialization and Processor Reset .................................................................................. 48
Reset Configuration Register ......................................................................................... 48
Am186TMER and Am188TMER Microcontrollers Data Sheet 7
DRAFTDRAFT
Chip-Select Unit ......................................................................................................................... 49
Chip-Select Timing ......................................................................................................... 49
Ready and Wait-State Programming ............. ................................................................ 49
Memor y Map s . ....... .. ....... .. ...... ....... .. ....... .. ....... ...... ... ...... .. ....... ....... .. ....... .. ...... ....... .. ..... 50
Chip-Select Overlap ....................................................................................................... 51
Upper Memory Chip Select ............................ ..................................................... ........... 51
Low Memory Chip Select ............................................................................................... 51
Midra n ge Me mo r y C h ip S e le c ts . .. ....... .. ...... ... ...... ....... .. ....... .. ...... ....... .. ....... .. ....... ...... ... 51
Peripheral Chip Selects ................................................................................................. 52
Inter n a l Me mory . ... .. ...... ....... .. ....... .. ....... ...... ... ...... .. ....... ....... .. ...... ... ...... ....... .. ....... .. ....... ........... 52
Interaction with External RAM ........................................................................................ 52
Emulator and Debug Modes ................................................ .......................................... 52
Refresh Control Unit .................................................................................................................. 53
Interrupt Control Unit ................................................................................................................. 53
Programming the Interrupt Control Unit ......................................................................... 53
Timer Control Unit ...................................................................................................................... 53
Watchdog Timer .... .............................................. .. ................ ........................ .. ................ .......... 54
Direct Memory Access ............................................................................................................... 54
DMA Op e ration . ... ...... .. ....... ....... .. ....... .. ...... ....... .. ....... .. ....... ...... .. ....... .. ....... ....... .. ...... ... 55
Asynchronous Serial Port/DMA Transfers .......... ....... .. ....... .......... ................ ................. 55
DMA Channel Control Registers .................................................................................... 55
DMA P ri or it y .. .. .. ....... ....... .. ...... ... ...... ....... .. ....... .. ....... ...... .. ....... .. ....... ....... .. ...... ... ...... .....55
Asynchronous Serial Port ....................... ....... .. ...................... .. ....... .......... ................ .. ............... 56
DMA Transfers through the Serial Port .......................................................................... 56
Synchronous Serial Interface ..................................................................................................... 56
Four-Pin Int erface ......... ................ ....... .. ....... .......... ................ ............................... .. ...... 57
Programmable I/O (PIO) Pins ....................................................................................................57
Low-Voltage Operation .................... .. .. .......... .. .. .. .. .. ............................................. .. .. .. .. ............. 59
Low-Voltage Standard ............................. .. ................ ...................... .. ....... .. ....... .......... .. 59
Power Savings ............................................................................................................... 59
Input/Out put Circuitry ....... .. ....... .. ....... .......... ................ ............................... .. ....... .......... 59
Absolute Maximum Ratings .......................................................................................................60
Operating Ranges ................................. ..................................................... ................................ 60
DC Characteristics Over Commerci al and Industrial Operating Ranges .................. .. .. ............. 60
Thermal Charact eristics ........ ............................... .. ................ ...................... .. ....... .. ....... ............ 61
TQFP Package ............. .................................. .. .. .. .. .................................. .. .. .. .. ............. 61
Typical Ambient Temperatures ...................................................................................... 62
Commercial and Industrial Switching Characteristics and Waveforms ........................... ........... 67
Key to Switching Waveforms ......................................................................................... 67
Alphabetical Key to Switching Parameter Symbol s .............. ........................ .. ............... 68
Numerical Key to Switching Parameter Symbols .......................................................... 69
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Read Cycle (25 MHz and 33 MHz) .......... .. .. .................................................................. 70
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Read Cycle (40 MHz and 50 MHz) .......... .. .. .................................................................. 71
Read Cycle Waveforms ....... ....... ............................... .. ....... .......... ................ ................. 72
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Write Cycle (25 MHz and 33 MHz) ................................................................................ 73
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Write Cycle (40 MHz and 50 MHz) ................................................................................ 74
Write Cycle Waveforms ................................................................................................. 75
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Internal RAM Show Read Cycle (25 MHz and 33 MHz) ....... ............................... .. ....... . 76
8Am186
TMER and Am188TMER Microcontrollers Data Sheet
DRAFTDRAFT
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Internal RAM Show Read Cycle (40 MHz and 50 MHz) ....... ............................... .. ....... . 76
Internal RAM Show Read Cycle Waveform ...................................... ............................. 77
Switching Char acteristics over Commercial and Industrial Operating Ranges,
PSRAM Read Cycle (25 MHz and 33 MHz) ................ .. .. .. .................................. .. .. .. .. .. 78
Switching Char acteristics over Commercial and Industrial Operating Ranges,
PSRAM Read Cycle (40 MHz and 50 MHz) ................ .. .. .. .................................. .. .. .. .. .. 79
PSRAM Read Cycle Waveforms ...................... .. ....... ............................. .......... ............. 80
Switching Char acteristics over Commercial and Industrial Operating Ranges,
PSRAM Write Cycle (25 MHz and 33 MHz) ................................................................... 81
Switching Char acteristics over Commercial and Industrial Operating Ranges,
PSRAM Write Cycle (40 MHz and 50 MHz) ................................................................... 82
PSRAM Write Cycle Waveforms .............................................................. ...................... 83
Switching Char acteristics over Commercial and Industrial Operating Ranges,
PSRAM Refresh Cycle (25 MHz and 33 MHz) .................... .......................................... 84
Switching Char acteristics over Commercial and Industrial Operating Ranges,
PSRAM Refresh Cycle (40 MHz and 50 MHz) .................... .......................................... 85
PSRAM Refresh Cycle W aveforms .......................... ..................................................... 86
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Interrupt Acknowledge Cycle (25 MHz and 33 MHz) ....... ................ .. ....... ..................... 87
Switching Characteristics over Commercial Operating Ranges,
Interrupt Acknowledge Cycle (40 MHz and 50 MHz) ....... ................ .. ....... ..................... 88
Interrupt Acknowledge Cycle Waveforms ..... .. ........................ .. ....... .. ....... ..................... 89
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Software Halt Cycle (25 MHz and 33 MHz) .............. ...................... ............. .................. 90
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Software Halt Cycle (40 MHz and 50 MHz) .............. ...................... ............. .................. 90
Software Halt Cycle Waveforms .................................................................................... 91
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Clock (25 MHz) .............................................................................................................. 92
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Clock (33 MHz) .............................................................................................................. 93
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Clock (40 MHz and 50 MHz) ................................................ .......................................... 94
Clock Waveforms—Active Mode ................................................................................... 95
Clock Waveform s—Power-Save Mode ...................... ...................... .. ....... .. ....... .......... .. 95
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Ready and Peri pheral Timing (25 MHz and 33 MHz) .................. ............ ............. ......... 96
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Ready and Peri pheral Timing (40 MHz and 50 MHz) .................. ............ ............. ......... 96
Synch r o n ou s Re ad y Wa v e fo rms ........ .. ...... ... ...... ....... .. ....... .. ...... ....... .. ....... .. ....... ...... ... 9 7
Asynchronous Ready Wav eforms ................... .............................................. .. ............... 97
Peripheral Waveforms ................................................................................................... 98
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Reset and Bus Hold (25 MHz and 33 MHz) ................. .. .. .. ..................... .. .. .. .. .. ........... .. 99
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Reset and Bus Hold (40 MHz and 50 MHz) ................. .. .. .. ..................... .. .. .. .. .. ........... .. 99
Reset Waveforms ........................................................................................................ 100
Signals Relat ed to Reset Waveforms ................................ ................ ....... .. ....... .. ........ 100
Bus Hold Waveforms—Entering .................................................................................. 101
Bus Hold Waveforms—Leaving ...... .............. .. ........................ .. ....... .. ....... ................... 101
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Synchronous Serial Interface (SSI) (25 MHz and 33 MHz) ........ .............. .. ....... .. ........ 102
Am186TMER and Am188TMER Microcontrollers Data Sheet 9
DRAFTDRAFT
Switching Char acteristics over Commercial and Industrial Operating Ranges,
Synchronous Serial Interface (SSI) (40 MHz and 50 MHz) ........ .............. .. ....... .. ........ 102
Synchronous Serial Interface (SSI) Waveforms .......................................................... 103
TQFP Physical Dimensions ..................................................................................................... 104
PQFP Ph ys ical Dimensio n s ... .. ... ...... ....... .. ....... .. ....... ...... .. ....... .. ....... ...... ... ...... ... ...... ....... .. ..... 105
Index................................................................................................................................... Index-1
LIST OF FIGURES
Figure 1. Am186ER 50-MHz Example System Design ......................................................... 15
Figure 2. Typical 80C186 System Design .............. .............................................. .. ............... 15
Figure 3. Two-Component Address Example .................. ............................... ...................... 40
Figure 4. Am186™ER Microcontroll er Address Bus—Normal Operation .............. .. ............. 42
Figure 5. Am186™ER Microcontroller—Address Bus Disable in Effect ................... .. .......... 42
Figure 6. Am188™ER Microcontroller Address Bus—Normal Operation ............................. 43
Figure 7. Am188™ER Microcontroller—Address Bus Disable in Effect ................... .. .......... 43
Figure 8. Am186™ER and Am188™ER Microcontrollers Oscillator Configurations .......... .. 45
Figure 9. Peripheral Control Block Register Map .................................................................. 46
Figure 10. Clock Organization ................ ............................................................ .................... 48
Figure 11. ARDY and SRDY Synchronization Logic Diagram ................................ ................ 49
Figure 12. Example Memory Maps ......................................................................................... 50
Figure 13. DMA Unit Block Diagram ....................................................................................... 56
Figure 14. Synchronous Serial Interface Multiple Write .......................................................... 58
Figure 15. Synchronous Serial Interface Multiple Read .......................................................... 58
Figure 16. Thermal Resistance (°C/Watt) .... ............... ........... ............... ................ ........... ....... 61
Figure 17. Thermal Characteristics Equations ........................................................................ 61
Figure 18. Typical Ambient Temperatures for PQFP with Two-Layer Board .......................... 63
Figure 19. Typical Ambient Temperatures for TQFP with Two-Layer Board ....... ................... 64
Figure 20. Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board ..... 65
Figure 21. Typical Ambient Temperatures for TQFP with Four-Layer to Six-L ayer Board ..... 66
LIST OF TABLES
Table 1. Related AMD Products—E86™ Family Devices ........ .. .. .. .. .. ................................. 12
Table 2. Data Byte Encoding ............ .. .. .. ................................. ..................... .. .. .. .. .. ............. 31
Table 3. Numeric PIO Pin Assignments ................... .. .. .................................. .. .. .. .. ............. 36
Table 4. Alphabetic PIO Pin Assi gnments ........................................................................... 36
Table 5. Bus Cycle Encoding ................... .. .. .. .. .. .................................................................. 37
Table 6. Clocking Modes ..... .. ............................... ...................... .. ....... .. ....... .. ..................... 39
Table 7. Segment Register Selection Rules ...... ................ .. ....... ............................... .. ....... . 40
Table 8. Maximum and Minimum Clock Frequencies ............ .. ..................... .. .. .. .. .. ............. 44
Table 9. Am186ER Microcontroll er Maximum DMA Transfer Rates ............... .. .. .. ............. 55
Table 10. Thermal Characteristics (°C/Watt) ......................................................................... 61
Table 11. Typical Power Consumption Calculation ...................... .. ....... ................................ 62
Table 12. Junction Temperature Calculation .......... .. .. .. .. ....................................................... 62
Table 13. Typical Amb ient Temperatures for PQFP with Two-Layer Board ................ .. ....... . 63
Table 14. Typical Amb ient Temperatures for TQFP with Two-Layer Board ...................... .... 64
Table 15. Typical Amb ient Temperatures for PQFP with Four-Layer to Six-Lay er Board ..... 65
Table 16. Typical Amb ient Temperatures for TQFP with Four-Layer to Six-Layer Board ..... 66
10 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
REVISION HISTORY
Date Rev Description
Feb. 2000 D Replaced block diagrams on page 2 and page 3 with updated diagrams showing that the internal data
bus interfaces via th e BIU and not RAM.
Feb. 2000 D Added new industrial parts for “Ordering Information” on page 4.
Feb. 2000 D Updated product listings and customer service matter on page 12 and page 13.
Feb. 2000 D Replaced Figure 8 on page 45 (microcontroller oscillator configurations) with updated figure.
Feb. 2000 D Updated several references to watchdog timer on page 54 to reflect that the WDT is inactive after
reset, not active).
Feb. 2000 D Provided a value for the TBD in the tab le entitled, “DC Characteristics Over Commercial and Industrial
Operating Ranges” on page 60.
Feb. 2000 D Updated table title and "Min" values for No. 66 in the switching characteristics table, “Read Cycle (40
MHz and 50 MHz)” on page 71.
Feb. 2000 D Updated tab le tit le and "Max" v alues for No . 87 i n the sw itching ch aracteristics table , “Write Cycle (40
MHz and 50 MHz)” on page 74.
Feb. 2000 D Updated table title and "Min" value for No. 9 (50 MHz) in the switching characteristics table, “Internal
RAM Show Read Cycle (40 MHz and 50 MHz)” on page 76.
Feb. 2000 D Updated table title and "Min" values for No. 66 in the switching characteristics table, “PSRAM Read
Cycle (40 MHz and 50 MHz)” on page 79.
Feb. 2000 D Updated table title and "Max" value for No. 68 (40 MHz) in the switching charac teristics table,
“PSRAM Write Cycle (40 MHz and 50 MHz)” on page 82.
Feb. 2000 D Updated table title in the switching characteristics table, “PSRAM Refresh Cycle (40 MHz and 50
MHz)” on page 85.
Feb. 2000 D Updated tab le titl e in the s witc hing char acteristic s tabl e, “Softw are Halt C ycle (40 MHz and 50 MH z)”
on page 90.
F eb . 2000 D Updated "Min" and "M ax" v alues in the switc hing char acterist ics tab le, “Cloc k (33 MHz) ” on page 93.
Feb. 2000 D Updated table title in the switching characteristics table, “Clock (40 MHz and 50 MHz)” on page 94.
Feb. 2000 D Updated table t itl e in the switchin g ch aracteristics t able, “Read y an d Pe riph er al Timing (40 M Hz and
50 MHz)” on page 96.
Feb. 2000 D Updated ta b le title in the s witchi ng char acteristics tabl e, “Rese t and Bus Ho ld (40 MH z and 5 0 MHz)”
on page 99.
Feb. 2000 D Updated tab le title in the s witching characteristics tab le, “Synchronous Serial Interface (SSI) (40 MHz
and 50 MHz)” on page 102.
Feb. 2000 D In the table "Switching Characteristics o ver Commercial and Industrial Opera ting Ranges Read Cycle
(40 MHz and 50 MHz)", row 9, column "50 MHz" - "Min", the "0" is deleted.
Feb. 2000 D In the table "Switching Characteristics o ver Commercial and Industrial Opera ting Ranges Read Cycle
(40 MHz and 50 MHz)", row 66, column "40 MHz" - "Min", the value is changed.
Feb. 2000 D In the table "Switching Characteristics o ver Commercial and Industrial Opera ting Ranges Read Cycle
(40 MHz and 50 MHz)", row 66, column "50 MHz" - "Min", the value is changed.
Feb. 2000 D In the table "Switching Characteristics over Commerci al and Industrial Operating Ranges PSRAM
Write Cycle (40 MHz and 50 MHz)", row 68, column "40 MHz" - "Max", the value is changed.
May 2000 D Under “Key Features and Benefits” on page 14, in the third bullet "Enhanced functionality," the
feature, "a PSRAM controller" was added.
May 2000 D Under “HOLD” on page 32, the sentence, "A HOLD request is second only to DRAM or PSRAM
refresh requests in priority of activity requests received by the processor." is changed.
Am186TMER and Am188TMER Microcontrollers Data Sheet 11
DRAFT
May 2000 D Under “SRDY/PIO6” on page 38, the following sentence was added: "When SRDY is configured as
P106, the internal SRDY signal is driven Low."
May 2000 D In Table 8, “Maximum and Minimum Clock Frequencies,” on page 44, the values are changed in the
cell of row "Divide by 2" and column "X1/X2 Min" and in the cell o f row "Divide by 2" and column
"CLKOUTA Min".
May 2000 D In “Switching Characteristics over Commercial and Industrial Operating Ranges” on page 93, Max
value in the number "36" row was changed to "33."
May 2000 D In “Switching Characteristics over Commercial and Industrial Operating Ranges” on page 94, the
value in "40 MHz Max" for row number 36 was changed to "33."
May 2000 D In “Synchronous Ready Waveforms” on page 97, the diagram was changed.
May 2000 D In “Asynchronous Ready Waveforms” on page 97, the diagram wa s changed.
May 2000 D In "BHE/ADEN", on page 31, the second paragraph under ADEN was changed.
May 2000 D In "UZI/CLKSEL2/PIO26", on page 38, the paragraph description of UZI was changed.
May 2000 D In “Read Cycle Waveforms” on page 72, the UZI line in the diagram was changed.
May 2000 D In “Write Cycle Waveforms” on page 75, the UZI line in the diagram was changed.
May 2000 D Added the diagram, Table 11, “ARDY and SRDY Synchronization Logic Diagram,” on page 49.
May 2000 D Added an index.
Date Rev Description
March 2006 E Updated pin assignment tables for missng PIO signal names and added note on pin diagrams.
12 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
E86™ FAMILY OF EMBEDDED MICROPROCESSORS AND MICROCONTROLLERS
Table 1. Related AMD Products—E86™ Family Devices
Device1
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit
external data bus and 8 0C188-compatible (except where noted otherwise); LV = low voltage
Description
80C186/80C188 16-bit microcontroller
80L186/80L188 Low-voltage, 16-bit microcontroller
Am186™EM/Am188™EM High-performance, 16-bit embe dded micr ocontroller
Am186EMLV/Am188E MLV High-performance, 16-bit embedd ed microcontroller
Am186ES/Am188ES High-performance, 16-bit embedded microcontroller
Am186ESLV/Am188 ESLV High-performance, 16-bit embe dded micr ocontroller
Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or
16-bit external data bus
Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded
microcontroller with 8- or 16-bit external data bus
Am186ER/Am1 88ER High-p erformance , low-v oltage , 16-bit embe dded microcon troller with 32 Kb yte of in ternal SRAM
Am186CC High-performance, 16-bit embedded communications controller
Am186CH High-performance, 16-bit embedded HDLC microcontroller
Am186CU High-performance, 16-bit embedded USB microcontroller
ÉlanSC300 High-performance, highly integrated, low-voltage, 32 -bit embedded microcontroller
ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT-compatible microcontroller
ÉlanSC40 0 High-p erfo rmance, si ngle-chip , low-power, PC/AT-compatible microcontro ll er
ÉlanSC410 High-performance, single-chip, PC/AT-compatible microcontroller
ÉlanSC520 High-performance, single-chip, 32-bit embedded microcon troller
Am386®SX High-performance, 32-bit embe dded micr opro cessor with 16-bit external data bus
Am386®DX High-performance, 32-bit embe dded micr opro cessor with 32-bit external data bus
Am486®DX High-performance, 32-bit embe dded micr opro cessor with 32-bit external data bus
Am5x86® High-performance, 32-bit embe dded micr opro cessor with 32-bit external data bus
AMD-K6™-2E High-performance, 32-bit embe dded micr opro cessor with 64-bit external data bus
and 3DNo w !™ tec hno lo gy
Am386
®
SX/DX
Microprocessors
Am486
®
DX
Microprocessor
E86™ Family of Embedded Microprocessors and Microcontrollers
Am186ES and
Am188™EM
Am188EMLV Microcontrollers
Am188ER
— Microprocessors
— 16- and 32-bit microcontrollers
— 16-bit microcontrollers
AMD-K6™-2E
Microprocessor
Am5x86®
Microprocessor
Am186CC
Communications
Controller
Am186™CU USB
Microcontroller
Am186CH HDLC
Microcontroller
80C186 and 80C188
Microcontrollers
Am188ES
Microcontrollers
Am186EM and
Microcontrollers
80L186 and 80L188
Microcontrollers
Am186EMLV &
Microcontrollers
Am186ESLV &
Am188ESLV
Am186ER and
Microcontrollers
Am186ED
Am186EDLV
Microcontroller
Microcontroller
Élan™SC310
Microcontroller
ÉlanSC300
Microcontroller
ÉlanSC410
Microcontroller
ÉlanSC400
Microcontroller
ÉlanSC520
Microcontroller
Am186TMER and Am188TMER Microcontrollers Data Sheet 13
DRAFT
Related Documents
The following documents provide additional informa-
tion regarding the Am186ER and Am188ER microcon-
trollers.
n
Am186ER and Am188ER Microcontrollers User’s
Manual
, order #21684
n
FusionE86
SM
Catalog
, order #19255
n
Making the Most of the Am186™ER or Am188™ER
Microcontroller Application Note
, order #21046
n
Using the 3.3-V Am186™ER or Am188™ER Micro-
controller in a 5-V System Application Note,
order #21045
n
Comparin g the Am186™EM and A m186ER Micro-
controllers
Technical Bulletin (Available only at
www.amd.com/products/epd/techdocs.)
n
The Adva ntages of Integrated RAM
Technical Bul-
letin (Available only at www.amd.com/products/
epd/techdocs.)
A full description of the Am186ER and Am188ER mi-
crocon trollers’ reg isters an d instruc tions is inc luded in
the
Am186ER and Am188ER Microcontrollers User’s
Manual
listed above.
To order literature, contact the nearest AMD sales of-
fice or call the literature center at one of the numbers
listed on the back cover of this manual. In add ition, all
these documents are available in PDF form on the
AMD web site. To access the AMD home page, go to
www.amd.com. Then follow the Embedded Processor
link for information about E86 microcontrollers.
Demonstration Board Products
The SD186ER demonstration board product is a stand-
alone, low-cost evaluation platform for the Am186ER
microcontroller.
The SD186ER board demonstrates the basic proces-
sor functionality and features of the Am186ER micro-
controller and the simplicity of its system design. The
SD186ER demonstration board is designed with the
Am186/Am188 expansion interface that provides ac-
cess to the Am186ER microcontroller signals. The
104-pin expansion interface facilitates prototyping by
enabling the demonstration board to be used as the
minimal system core of a design. Contact your local
AMD sales office for more information on demonstra-
tion board availability and pricing.
Third-Party Development Support Products
The FusionE86 Program of Partnerships for Applica-
tion Solutions provides the customer with an array of
products designed to meet critical time-to-market
needs. Products and solutions a vailable from the AMD
FusionE86 partners include protocol stacks, emulators,
hardware and software debuggers, board-level prod-
ucts, and software development tools, among others.
In addition, mature de v elopment tools and applications
for the x8 6 pl atfo r m are widel y available in the general
marketplace.
Customer Service
The AMD customer ser vice network includes U.S. of-
fices, international offices, and a customer training cen-
ter. Exper t technical assistance is available from the
AMD worldwide staff of field application engineers and
factory support staff to answer E86 and Comm86 fam-
ily hardware and software development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail suppor t as well as a toll-free number for direct
access to our corporate applications hotline.
Note: The support telephone numbers listed below
are subject to change. For current telephone numbers,
refer to
www.amd.com/support/literature.
The AMD World Wide Web home page provides the
latest product information, including technical informa-
tion and data on upcoming product releases. In addi-
tion, EPD CodeKit software on the Web site provides
tested source code example applications.
Additional contact information is listed on the back of
this datasheet. For technical suppor t questions on all
E86 and Comm86 products, send e-mail to epd.sup-
port@amd.com.
World Wide Web Home Page
To access the AMD home page go to: www.amd.com.
Then follow the Embedded Processor s link for infor-
mation about E86 family and Comm86™ products.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to webmas-
ter@amd.com.
Documentation and Literature
Free i nformati on such as data bo oks, user’s manuals,
data sheets, application notes, the <Italics>E86™
Family Products and Development Tools CD, order
#21058, a nd other literature is available with a simple
phone call. Internationally, contact your local AMD
sales office for product literature. Additional contact
information is listed on the back of this data sheet.
Corporate Applications Hotline
(800) 222-9323 Toll-free for U .S. and Canada
44-(0) 1276-803-299 U.K. and Europe hotline
Literature Ordering
(800) 222-9323 Toll-free for U .S. and Canada
14 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
KEY FEATURES AND BENEFITS
The Am186ER and Am188ER microcontrollers are
higher-performance, highly integrated versions of the
80C186/80C188 microprocessors, offering a migration
path that was previously unavailable. New peripherals,
on-chip system interface logic, and 32 Kbyte of internal
memory on the Am186ER microcontroller reduce the
cost of existing 80C186/80C188 designs. Upgrading to
the Am186ER microcontroller is an attractive solution
for several reasons:
nIntegrated SRAM—32 Kbyte of internal SR AM en-
sures a low-cost supply of memory and a smaller
form factor for system designs. The internal mem-
ory provides the same performance as external
zero-wait-state SRAM devices.
n3.3-V operation with 5-V -tolerant I/O—3.3-V oper-
ation provides much lower power consumption
when compared to existing 5-V designs. Plus, the
Am186ER and Am188ER controllers accommodate
current 5-V designs with 5-V-tolerant I/O drivers.
nx86 software compatibility—80C186/80C188-
compatible and upward-compatible with the other
members of the AMD E86 family.
nEnhanced performance—The Am186ER and
Am188ER microcontrollers increase the perfor-
mance of 80C186/80C188 systems, and the non-
multiplexed address bus offers faster, unbuffered
access to commodity-speed, external memory.
nEnhanced functionality—Enhanced on-chip
peripherals include an asynchronous serial port, up
to 32 PIOs, a hardware watchdog timer, an
additional interrupt pin, a synchronous serial
interface, a PSRAM controller, a 16-bit reset
configuration register, and enhanced chip-select
functionality.
Application Considerations
The integration enhancements of the Am186ER micro-
controller provide a high-performance, low-system-
cost solution for 16-bit embedded microcontroller de-
signs. Both multiplexed and nonmultiplexed address
buses are available on the Am186ER and Am188ER
microcontrollers. The nonmultiplexed address bus
eliminates system-support logic ordinarily needed to
interface with external memory devices, while the mul-
tiplexed address/data bus maintains the value of pre vi-
ously engineered, customer-specific peripherals and
circuits within the upgraded design. Figure 1 on page
15 illus trates an example sys tem desi gn that uses the
integrated per ipheral set to achieve high p erformance
with reduced system cost.
Internal Memory
The 32-Kbyte internal RAM fulfills the memory require-
ments for many embedded systems. These systems
can take advantage of the increa sed r eli abili ty, sm all er
system form factor, decreased system power, stable
RAM supply, and lower system cost compared with
buying external SRAM. The integrated RAM also en-
sures that an entire emb edded system will not requi re
requalification based on the short life cycles of external
SRAM. Additionally, for those systems using more
RAM than required because of the granularity of e xter-
nal RAM, the Am186ER microcontroller provides a
closer system match.
Clock Generation
The integrated clock generation circuitry of the
Am186ER and Am188ER microcontrollers enables the
processors to operate at up to four times the crystal fre-
quency. The design in Figure 1 achieves 50-MHz CPU
operation while using a 12.5-MHz crystal. The clocking
frequency function is controlled by an internal PLL. The
following mode s are availa ble (see Figure 10 o n page
48):
nDivide by Two—The frequency of the fundamental
clock is half the frequency of the crystal with the PLL
disabled.
nTimes One—The frequency of the fundamental
clock will be the same as the external crystal with
the PLL enabled.
nTimes Four—The frequency of the fundamental
clock is fo ur times the frequenc y of the cry stal with
the PLL enabled.
The default mode is Times Four.
Memory Interface
The integrated memory controller logic of the
Am186ER and Am188ER microcontrollers provides a
direct address bus to memory de vices. Using an e xter-
nal address latch controlled by the address latch en-
able (ALE) signal is no longer necessary. Individual
byte-write-enable signals on the Am186ER and
Am188ER microcontrollers eliminate the need for ex-
ternal high/low byte-write-enable circuitry. The maxi-
mum bank size programmable for the memory chip-
select s ignals is increas ed to facilit ate the use of high-
density memory devices.
The improved memory timing specifications for the
Am186ER and Am188ER microcontrollers facilitate the
use of external memory devices with 55-ns access
times at 50-MHz CPU operation. As a result, overall
system cost is significantly reduced as system design-
ers are able to use common ly available memory tec h-
nology.
Am186TMER and Am188TMER Microcontrollers Data Sheet 15
DRAFT
Direct Memory Interface Example
Figure 1 illustrates the direct interface to memory of the
Am186ER microcontroller. The A19–A0 bus connects
to the memory address inputs, the AD bus connects to
the data inputs and o utputs, and the chip selects con-
nect to the memory chip-select inputs.
Figure 1 also shows an implementation of an RS-232
console or modem communications port. The RS-232-
to-CMOS voltage-level converter is required for the
electrical interface with the external device.
COMPARISON OF THE Am186™ER AND
80C186 MICROCONTROLLERS
Figure 1 shows an example system using a 50-MHz
Am186ER microcontroller. Figure 2 shows a compara-
ble system impl ementation wit h an 80C186 micr ocon-
troller. Because of its superior integration, the
Am186ER system does not require the support devices
required on the 80C186 example system. In addition,
the Am186ER microcontroller provides significantly
better performance with its 50-MHz clock rate. Figure 1. Am186™ER 50-MHz Example
System Design
Figure 2. Typical 80C186 System Design
X2
X1
RS-232
Level
Converter
TXD
RXD
UCS
WR
RD
WE
OE
CS
AD15–AD0
A19–A0
Serial Port
Am186ER
Microcontroller
12.5-MHz
Crystal Address
Data
32 Kbyte
SRAM
Timer 0–2
INT4–INT0
DMA 0–1
CLKOUTA 50 MHz
Am29F400
Flash
UCS
WR WE
OE
CS
AD15–AD0
ALE
40-MHz
Crystal
Address
Data
Timer 0–2
INT3
DMA 0–1
CLKOUT 20 MH z
X2
X1
SRAM
WE
WE
Address
Data
OE
CS
RD
LCS
BHE
A0
PAL
LATCH
PCS0
LATCH
Serial
Port RS-232
Level
Converter
INT2–INT0
PIOs
Am29F400
Flash
16 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
TQFP CONNECTION DIAGRAM AND PINOUTS—Am186™ER MICROCONTROLLER
To p Side View—100-Pin Thin Quad Flat Pack (TQFP)
Notes:
Pin 1 is mark ed for orienta tion.
GND
6/A2
5/A1
3
2
AD0 1
AD8 2
AD1 3
AD9 4
AD2 5
AD10 6
AD3 7
AD11 8
AD4 9
AD12 10
AD5 11
12
AD13 13
AD6 14
15
AD14 16
AD7 17
AD15 18
19
20
TXD 21
RXD 22
SDATA 23
SDEN1 24
SDEN0 25
VCC
75 INT4
74
73
72
71
70 NMI
69 SRDY
68 HOLD
67 HLDA
66
65
64
63 A0
62 A1
61
60 A2
59 A3
58 A4
57 A5
56 A6
55 A7
54 A8
53 A9
52 A10
51 A11
VCC
100 DRQ0
99 DRQ1
98 TMRIN0
97 TMROUT0
96 TMROUT1
95 TMRIN1
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79 INT0
78 INT1/
77 INT2/
76 INT3/
VCC
VCC
1
0
0
1/IRQ
SCLK 26
27
28
29
ALE 30
ARDY 31
32
33
34
35
X1 36
37
38
CLKOUTA 39
40
41
A19 42
A18 43
44
A17 45
A16 46
A15 47
A14 48
A13 49
A12 50
X2
VCC
CLKOUTB
VCC /0
/1
2
3/
GND
GND GND
GND
GND
WHB
WLB
DT/R
DEN
MCS0
MCS1
BHE/ADEN
WR
RD
S2
S1/IMDIS
S0/SREN
INTA
INTA
SELECT
UCS ONCE
ONCE
PCS
PCS
PCS
PCS
PCS
PCS
MCS
MCS RFSH
RES
LCS
S6/CLKSEL1
UZI/CLKSEL2
Am186ER Microcontroller
For dual function pins, signal names for
PIO31-PIO0 are not included in the diagram.
See Tabes 3 and 4 on page 36 for pins that
are multiplexed with PIO31-PIO0.
Am186TMER and Am188TMER Microcontrollers Data Sheet 17
DRAFT
TQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1AD0 26 SCLK/PIO20 51 A11 76 INT3/INTA1/IRQ
2AD8 27 BHE/ADEN 52 A10 77 INT2/INTA0/PIO31
3AD1 28 WR 53 A9 78 INT1/SELECT
4AD9 29 RD 54 A8 79 INT0
5AD2 30 ALE 55 A7 80 UCS/ONCE1
6AD10 31 ARDY 56 A6 81 LCS/ONCE0
7AD3 32 S2 57 A5 82 PCS6/A2/PIO2
8AD11 33 S1/IMDIS 58 A4 83 PCS5/A1/PIO3
9AD4 34 S0/SREN 59 A3 84 VCC
10 AD12 35 GND 60 A2 85 PCS3/PIO19
11 AD5 36 X1 61 VCC 86 PCS2/PIO18
12 GND 37 X2 62 A1 87 GND
13 AD13 38 VCC 63 A0 88 PCS1/PIO17
14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16
15 VCC 40 CLKOUTB 65 WHB 90 VCC
16 AD14 41 GND 66 WLB 91 MCS2/PIO24
17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/PIO25
18 AD15 43 A18/PIO8 68 HOLD 93 GND
19 S6/CKLSEL1/PIO29 44 VCC 69 SRDY/PIO6 94 RES
20 UZI/CLKSEL2/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0
21 TXD/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1
22 RXD/PIO28 47 A15 72 DEN/PIO5 97 TMROUT0/PIO10
23 SDATA/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11
24 SDEN1/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/PIO13
25 SDEN0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/PIO12
18 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
TQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 63 AD5 11 GND 93 S2 32
A1 62 AD6 14 HLDA 67 S6/CLKSEL1/PIO29 19
A2 60 AD7 17 HOLD 68 SCLK/PIO20 26
A3 59 AD8 2 INT0 79 SDATA/PIO21 23
A4 58 AD9 4 INT1/SELECT 78 SDEN0/PIO22 25
A5 57 AD10 6 INT2/INTA0 77 SDEN1/PIO23 24
A6 56 AD11 8 INT3/INTA1/IRQ 76 SRDY/PIO6 69
A7 55 AD12 10 INT4 75 TMRIN0/PIO11 98
A8 54 AD13 13 LCS/ONCE081 TMRIN1/PIO0 95
A9 53 AD14 16 MCS0/PIO14 73 TMROUT0/PIO10 97
A10 52 AD15 18 MCS1/PIO15 74 TMROUT1/PIO1 96
A11 51 ALE 30 MCS291 TXD 21
A12 50 ARDY 31 MCS3/RFSH 92 UCS/ONCE1 80
A13 49 BHE/ADEN 27 NMI 70 UZI/CLKSEL2/PIO26 20
A14 48 CLKOUTA 39 PCS0/PIO16 89 VCC 15
A15 47 CLKOUTB 40 PCS1/PIO17 88 VCC 38
A16 46 DEN/PIO5 72 PCS2/PIO18 86 VCC 44
A17/PIO7 45 DRQ0/PIO12 100 PCS3/PIO19 85 VCC 61
A18/PIO8 43 DRQ1/PIO13 99 PCS5/A1/PIO3 83 VCC 84
A19/PIO9 42 DT/R/PIO4 71 PCS6/A2/PIO2 82 VCC 90
AD0 1GND 12 RD 29 WHB 65
AD1 3GND 35 RES 94 WLB 66
AD2 5GND 41 RXD 22 WR 28
AD3 7GND 64 S0/SREN 34 X1 36
AD4 9GND 87 S1/IMDIS 33 X2 37
Am186TMER and Am188TMER Microcontrollers Data Sheet 19
DRAFT
TQFP CONNECTION DIAGRAM AND PINOUTS—Am188™ER MICROCONTROLLER
To p Side View—100-Pin Thin Quad Flat Pack (TQFP)
Notes:
Pin 1 is mark ed for orienta tion.
GND
6/A2
5/A1
3
2
AD0 1
AO8 2
AD1 3
AO9 4
AD2 5
AO10 6
AD3 7
AO11 8
AD4 9
AO12 10
AD5 11
12
AO13 13
AD6 14
15
AO14 16
AD7 17
AO15 18
19
20
TXD 21
RXD 22
SDATA 23
SDEN1 24
SDEN0 25
VCC
75 INT4
74
73
72
71
70 NMI
69 SRDY
68 HOLD
67 HLDA
66
65
64
63 A0
62 A1
61
60 A2
59 A3
58 A4
57 A5
56 A6
55 A7
54 A8
53 A9
52 A10
51 A11
VCC
100 DRQ0
99 DRQ1
98 TMRIN0
97 TMROUT0
96 TMROUT1
95 TMRIN1
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79 INT0
78 INT1/
77 INT2/
76 INT3/
VCC
VCC
1
0
0
1/IRQ
SCLK 26
27
28
29
ALE 30
ARDY 31
32
33
34
35
X1 36
37
38
CLKOUTA 39
40
41
A19 42
A18 43
44
A17 45
A16 46
A15 47
A14 48
A13 49
A12 50
X2
VCC
CLKOUTB
VCC /0
/1
2
3/
GND
GND GND
GND
GND
GND
WB
DT/R
DEN
MCS0
MCS1
RFSH2/ADEN
WR
RD
S0/SREN
INTA
INTA
SELECT
UCS ONCE
ONCE
PCS
PCS
PCS
PCS
PCS
PCS
MCS
MCS RFSH
RES
LCS
S6/CLKSEL1
UZI/CLKSEL2
S2
S1/IMDIS
Am188ER Microcontroller
For dual function pins, signal names for
PIO31-PIO0 are not included in the diagram.
See Tables 3 and 4 on page 36 for pins that
are multiplexed with PIO31-PIO0.
20 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
TQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1AD0 26 SCLK/PIO20 51 A11 76 INT3/INTA1/IRQ
2AO8 27 RFSH2/ADEN 52 A10 77 INT2/INTA0/PIO31
3AD1 28 WR 53 A9 78 INT1/SELECT
4AO9 29 RD 54 A8 79 INT0
5AD2 30 ALE 55 A7 80 UCS/ONCE1
6AO10 31 ARDY 56 A6 81 LCS/ONCE0
7AD3 32 S2 57 A5 82 PCS6/A2/PIO2
8AO11 33 S1/IMDIS 58 A4 83 PCS5/A1/PIO3
9AD4 34 S0/SREN 59 A3 84 VCC
10 AO12 35 GND 60 A2 85 PCS3/PIO19
11 AD5 36 X1 61 VCC 86 PCS2/PIO18
12 GND 37 X2 62 A1 87 GND
13 AO13 38 VCC 63 A0 88 PCS1/PIO17
14 AD6 39 CLKOUTA 64 GND 89 PCS0/PIO16
15 VCC 40 CLKOUTB 65 GND 90 VCC
16 AO14 41 GND 66 WB 91 MCS2/PIO24
17 AD7 42 A19/PIO9 67 HLDA 92 MCS3/RFSH/PIO25
18 AO15 43 A18/PIO8 68 HOLD 93 GND
19 S6/CLKSEL1/PIO29 44 VCC 69 SRDY/PIO6 94 RES
20 UZI/CLKSEL2/PIO26 45 A17/PIO7 70 NMI 95 TMRIN1/PIO0
21 TXD/PIO27 46 A16 71 DT/R/PIO4 96 TMROUT1/PIO1
22 RXD/PIO28 47 A15 72 DEN/PIO5 97 TMROUT0/PIO10
23 SDATA/PIO21 48 A14 73 MCS0/PIO14 98 TMRIN0/PIO11
24 SDEN1/PIO23 49 A13 74 MCS1/PIO15 99 DRQ1/PIO13
25 SDEN0/PIO22 50 A12 75 INT4/PIO30 100 DRQ0/PIO12
Am186TMER and Am188TMER Microcontrollers Data Sheet 21
DRAFT
TQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 63 AD5 11 GND 93 S1/IMDIS 33
A1 62 AD6 14 HLDA 67 S2 32
A2 60 AD7 17 HOLD 68 S6/CLKSEL1/PIO29 19
A3 59 ALE 30 INT0 79 SCLK/PIO20 26
A4 58 AO8 2INT1/SELECT 78 SDATA/PIO21 23
A5 57 AO9 4INT2/INTA0/PIO31 77 SDEN0/PIO22 25
A6 56 AO10 6INT3/INTA1/IRQ 76 SDEN1/PIO23 24
A7 55 AO11 8INT4/PIO30 75 SRDY/PIO6 69
A8 54 AO12 10 LCS/ONCE0 81 TMRIN0/PIO11 98
A9 53 AO13 13 MCS0/PIO14 73 TMRIN1/PIO0 95
A10 52 AO14 16 MCS1/PIO15 74 TMROUT0/PIO10 97
A11 51 AO15 18 MCS2/PIO24 91 TMROUT1/PIO1 96
A12 50 ARDY 31 MCS3/RFSH/PIO25 92 TXD/PIO27 21
A13 49 CLKOUTA 39 NMI 70 UCS/ONCE180
A14 48 CLKOUTB 40 PCS0/PIO16 89 UZI/CLKSEL220
A15 47 DEN/PIO5 72 PCS1/PIO17 88 VCC 15
A16 46 DRQ0/PIO12 100 PCS2/PIO18 86 VCC 38
A17/PIO7 45 DRQ1/PIO13 99 PCS3/PIO19 85 VCC 44
A18/PIO8 43 DT/R/PIO4 71 PCS5/A1/PIO3 83 VCC 61
A19/PIO9 42 GND 12 PCS6/A2/PIO2 82 VCC 84
AD0 1GND 35 RD 29 VCC 90
AD1 3GND 41 RES 94 WB 66
AD2 5GND 64 RFSH2/ADEN 27 WR 28
AD3 7GND 65 RXD/PIO28 22 X1 36
AD4 9GND 87 S0/SREN 34 X2 37
22 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
PQFP CONNECTION DIAGRAM AND PINOUTS—Am186™ER MICROCONTROLLER
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Notes:
Pin 1 is marked for orient ation.
AD0
AD8
AD1
AD9
AD2
AD10
AD3
AD11
AD4
AD12
AD5
AD13
AD6
AD14
AD7
AD15
TXD
RXD
SDATA
SDEN1
SDEN0
GND
GND
SCLK
ALE
ARDY
X1
CLKOUTA
A19
A18
A17
A16
A15
A14
A12
A13
X2
VCC
CLKOUTB
VCC
GND
INT4
DT/R
NMI
SRDY
HOLD
HLDA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
VCC
GND
TMRIN0
TMROUT0
TMROUT1
TMRIN1
INT0
GND
GND
VCC
S6/CLKSEL1
DRQ1
DRQ0
VCC
VCC
Am186ER Microcontroller
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BHE/ADEN
UZI/CLKSEL2
WHB
WLB
DEN
MCS0
WR
RD
S2
S1/IMDIS
S0/SREN
MCS1
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
UCS/ONCE1
LCS/ONCE0
PCS6/A2
PCS5/A1
PCS3
PCS2
PCS1
PCS0
MCS2
MCS3/RFSH
RES
For dual function pins, signal names for
PIO31-PIO0 are not included in the diagram.
See Tables 3 and 4 on page 36 for pins that are
multiplexed with PIO31-PIO0.
Am186TMER and Am188TMER Microcontrollers Data Sheet 23
DRAFT
PQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 SDEN1/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/PIO13
2 SDEN0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/PIO12
3SCLK/PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0
4BHE/ADEN 29 A10 54 INT2/INTA0/PIO31 79 AD8
5WR 30 A9 55 INT1/SELECT 80 AD1
6RD 31 A8 56 INT0 81 AD9
7 ALE 32 A7 57 UCS/ONCE182 AD2
8ARDY 33 A6 58 LCS/ONCE0 83 AD10
9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3
10 S1/IMDIS 35 A4 60 PCS5/A1/PIO3 85 AD11
11 S0/SREN 36 A3 61 VCC 86 AD4
12 GND 37 A2 62 PCS3/PIO19 87 AD12
13 X1 38 VCC 63 PCS2/PIO18 88 AD5
14 X2 39 A1 64 GND 89 GND
15 VCC 40 A0 65 PCS1/PIO17 90 AD13
16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6
17 CLKOUTB 42 WHB 67 VCC 92 VCC
18 GND 43 WLB 68 MCS2/PIO24 93 AD14
19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7
20 A18/PIO8 45 HOLD 70 GND 95 AD15
21 VCC 46 SRDY/PIO6 71 RES 96 S6/CLKSEL1/PIO29
22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/CLKSEL2/PIO26
23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD/PIO27
24 A15 49 DEN/PIO5 74 TMROUT0/PIO10 99 RXD/PIO28
25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 SDATA/PIO21
24 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
PQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 40 AD5 88 GND 89 S2 9
A1 39 AD6 91 HLDA 44 S6/CLKSEL1/PIO29 96
A2 37 AD7 94 HOLD 45 SCLK/PIO20 3
A3 36 AD8 79 INT0 56 SDATA/PIO21 100
A4 35 AD9 81 INT1/SELECT 55 SDEN0/PIO22 2
A5 34 AD10 83 INT2/INTA0/PIO31 54 SDEN1/PIO23 1
A6 33 AD11 85 INT3/INTA1/IRQ 53 SRDY/PIO6 46
A7 32 AD12 87 INT4/PIO30 52 TMRIN0/PIO11 75
A8 31 AD13 90 LCS/ONCE058 TMRIN1/PIO0 72
A9 30 AD14 93 MCS0/PIO14 50 TMROUT0/PIO10 74
A10 29 AD15 95 MCS1/PIO15 51 TMROUT1/PIO1 73
A11 28 ALE 7MCS2/PIO24 68 TXD/PIO27 98
A12 27 ARDY 8MCS3/RFSH/PIO25 69 UCS/ONCE157
A13 26 BHE/ADEN 4 NMI 47 UZI/CLKSEL2/PIO26 97
A14 25 CLKOUTA 16 PCS0/PIO16 66 VCC 15
A15 24 CLKOUTB 17 PCS1/PIO17 65 VCC 21
A16 23 DEN/PIO5 49 PCS2/PIO18 63 VCC 38
A17/PIO7 22 DRQ0/PIO12 77 PCS3/PIO19 62 VCC 61
A18/PIO8 20 DRQ1/PIO13 76 PCS5/A1/PIO3 60 VCC 67
A19/PIO9 19 DT/R/PIO4 48 PCS6/A2/PIO2 59 VCC 92
AD0 78 GND 12 RD 6WHB 42
AD1 80 GND 18 RES 71 WLB 43
AD2 82 GND 41 RXD/PIO28 99 WR 5
AD3 84 GND 64 S0/SREN 11 X1 13
AD4 86 GND 70 S1/IMDIS 10 X2 14
Am186TMER and Am188TMER Microcontrollers Data Sheet 25
DRAFT
PQFP CONNECTION DIAGRAM AND PINOUTS—Am188™ER MICROCONTROLLER
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Notes:
Pin 1 is marked for orient ation.
AD0
AD8
AD1
AD9
AD2
AD10
AD3
AD11
AD4
AD12
AD5
AD13
AD6
AD14
AD7
AD15
TXD
RXD
SDATA
SDEN1
SDEN0
GND
GND
SCLK
ALE
ARDY
X1
CLKOUTA
A19
A18
A17
A16
A15
A14
A12
A13
X2
VCC
CLKOUTB
VCC
GND
INT4
DT/R
NMI
SRDY
HOLD
HLDA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
VCC
GND
TMRIN0
TMROUT0
TMROUT1
TMRIN1
INT0
GND
GND
VCC
S6/CLKSEL
DRQ1
DRQ0
VCC
VCC
Am188ER Microcontroller
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RFSH2/ADEN
1
UZI/CLKSEL2
GND
WB
DEN
MCS0
WR
RD
S2
S1/IMDIS
S0/SREN
MCS1
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
UCS/ONCE1
LCS/ONCE0
PCS6/A2
PCS5/A1
PCS3
PCS2
PCS1
PCS0
MCS2
MCS3/RFSH
RES
For dual function pins, signal names for
PIO31-PIO0 are not included in the diagram.
See Tables 3 and 4 on page 36 for pins that
are multiplexed with PIO31-PIO0.
26 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
PQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name Pin No. Name Pin No. Name Pin No. Name
1 SDEN1/PIO23 26 A13 51 MCS1/PIO15 76 DRQ1/PIO13
2 SDEN0/PIO22 27 A12 52 INT4/PIO30 77 DRQ0/PIO12
3SCLK/PIO20 28 A11 53 INT3/INTA1/IRQ 78 AD0
4 RFSH2/ADEN 29 A10 54 INT2/INTA0/PIO31 79 AO8
5WR 30 A9 55 INT1/SELECT 80 AD1
6RD 31 A8 56 INT0 81 AO9
7 ALE 32 A7 57 UCS/ONCE182 AD2
8ARDY 33 A6 58 LCS/ONCE0 83 AO10
9 S2 34 A5 59 PCS6/A2/PIO2 84 AD3
10 S1/IMDIS 35 A4 60 PCS5/A1/PIO3 85 AO11
11 S0/SREN 36 A3 61 VCC 86 AD4
12 GND 37 A2 62 PCS3/PIO19 87 AO12
13 X1 38 VCC 63 PCS2/PIO18 88 AD5
14 X2 39 A1 64 GND 89 GND
15 VCC 40 A0 65 PCS1/PIO17 90 AO13
16 CLKOUTA 41 GND 66 PCS0/PIO16 91 AD6
17 CLKOUTB 42 GND 67 VCC 92 VCC
18 GND 43 WB 68 MCS2/PIO24 93 AO14
19 A19/PIO9 44 HLDA 69 MCS3/RFSH/PIO25 94 AD7
20 A18/PIO8 45 HOLD 70 GND 95 AO15
21 VCC 46 SRDY/PIO6 71 RES 96 S6/CLKSEL1/PIO29
22 A17/PIO7 47 NMI 72 TMRIN1/PIO0 97 UZI/CLKSEL2/PIO26
23 A16 48 DT/R/PIO4 73 TMROUT1/PIO1 98 TXD/PIO27
24 A15 49 DEN/PIO5 74 TMROUT0/PIO10 99 RXD/PIO28
25 A14 50 MCS0/PIO14 75 TMRIN0/PIO11 100 SDATA/PIO21
Am186TMER and Am188TMER Microcontrollers Data Sheet 27
DRAFT
PQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name No. Pin Name No. Pin Name No. Pin Name No.
A0 40 AD5 88 GND 89 S1/IMDIS 10
A1 39 AD6 91 HLDA 44 S2 9
A2 37 AD7 94 HOLD 45 S6/CLKSEL1/PIO29 96
A3 36 ALE 7INT0 56 SCLK/PIO20 3
A4 35 AO8 79 INT1/SELECT 55 SDATA/PIO21 100
A5 34 AO9 81 INT2/INTA0/PIO31 54 SDEN0/PIO22 2
A6 33 AO10 83 INT3/INTA1/IRQ 53 SDEN1/PIO23 1
A7 32 AO11 85 INT4/PIO30 52 SRDY/PIO6 46
A8 31 AO12 87 LCS/ONCE058 TMRIN0/PIO11 75
A9 30 AO13 90 MCS0/PIO14 50 TMRIN1/PIO0 72
A10 29 AO14 93 MCS1/PIO15 51 TMROUT0/PIO10 74
A11 28 AO15 95 MCS2/PIO24 68 TMROUT1/PIO1 73
A12 27 ARDY 8MCS3/RFSH/PIO25 69 TXD/PIO27 98
A13 26 CLKOUTA 16 NMI 47 UCS/ONCE157
A14 25 CLKOUTB 17 PCS0/PIO16 66 UZI/CLKSEL2/PIO26 97
A15 24 DEN/PIO5 49 PCS1/PIO17 65 VCC 15
A16 23 DRQ0/PIO12 77 PCS2/PIO18 63 VCC 21
A17/PIO7 22 DRQ1/PIO13 76 PCS3/PIO19 62 VCC 38
A18/PIO8 20 DT/R/PIO4 48 PCS5/A1/PIO3 60 VCC 61
A19/PIO9 19 GND 12 PCS6/A2/PIO2 59 VCC 67
AD0 78 GND 18 RD 6 VCC 92
AD1 80 GND 41 RES 71 WB 43
AD2 82 GND 42 RFSH2/ADEN 4WR 5
AD3 84 GND 64 RXD/PIO28 99 X1 13
AD4 86 GND 70 S0/SREN 11 X2 14
28 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
LOGIC SYMBOL—Am186™ER MICROCONTROLLER
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See the pin desc riptions beginning on page 30 and
Table 3 on page 36 for information on shared function.
** All PIO signals are shared with other physical pins.
X1
X2
CLKOUTA
CLKOUTB
A19–A0
AD15–AD0
ALE
WHB
WLB
RD
WR
S2
HOLD
HLDA
DT/R
DEN
ARDY
SRDY
TMRIN0
TMROUT0
SDEN1–SDEN0
SCLK
SDATA
20
16
Clocks
Address and
Address/Data Buses
Bus Contro l
Timer Control
Synchronous
Serial Port Control
RES
INT4
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
INT0
NMI
PCS6/A2
PCS5/A1
PCS3–PCS0
LCS/ONCE0
MCS2–MCS0
UCS/ONCE1
DRQ1–DRQ0
TXD
RXD
PIO32–PIO0
4
Reset Control and
Interrupt Service
Memory and
Peripheral Control
DMA Control
Asynchronous
Serial Port Control
Programmable
I/O Contro l
2
TMRIN1
TMROUT1
2
MCS3/RFSH
S6/CLKSEL1
BHE/ADEN
UZI/CLKSEL2
**
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
32
shared
S1/IMDIS
S0/SREN 3
Am186TMER and Am188TMER Microcontrollers Data Sheet 29
DRAFT
LOGIC SYMBOL—Am188™ER MICROCONTROLLER
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 30 and
Table 3 on page 36 for information on shared function.
** All PIO signals are shared with other physical pins.
X1
X2
CLKOUTA
CLKOUTB
AO15–AO8
AD7–AD0
S6/CLKSEL1
ALE
RFSH2/ADEN
RD
WR
HOLD
HLDA
DT/R
DEN
ARDY
SRDY
TMRIN0
TMROUT0
SDEN1–SDEN0
SCLK
SDATA
8
8
Clocks
Address and
Address/Data Buses
Bus Contro l
Timer Control
Synchronous
Serial Port Control
RES
INT4
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
INT0
NMI
PCS6/A2
PCS5/A1
PCS3–PCS0
LCS/ONCE0
MCS2–MCS0
UCS/ONCE1
DRQ1–DRQ0
TXD
RXD
PIO31–PIO0
4
32
shared
Reset Control and
Interrupt Service
Memory and
Peripheral Control
DMA Control
Asynchronous
Serial Port Control
Programmable
I/O Contro l
2
UZI/CLKSEL2
TMRIN1
TMROUT1
3
2
MCS3/RFSH
A19–A0
20
WB
**
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
S2
S1/IMDIS
S0/SREN
30 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
PIN DESCRIPTIONS
Pins Used by Emulators
The following pins are used by emulators: A19–A0,
AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the
Am186ER microcontroller), CLKOUTA, RFSH2/ADEN
(on the A m18 8E R mi croc on troll er ), RD, S2, S1/IMDIS,
S0/SREN, S6/CLKSEL1, and UZI/CLKSEL2.
Emulators require that S6/CLKSEL1 and UZI/
CLKSEL2 be configured in their normal functionality,
that is, as S6 and UZI. If BHE/ADEN (on the Am186ER
microcontroller) or RFSH2/ADEN (on the Am188ER
microcontroller) is held Low during the rising edge of
RES, S6 and U ZI are configured in their normal func-
tionality and cannot be programmed as PIOs.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O ad-
dresses to the system one-half of a CLKOUTA period
earlier than the multiplexed address and data bus
(AD15–AD0 on the Am186ER microcontroller or
A O15–AO8 and AD7–AD0 on the Am188ER microcon-
troller). During a bus hold or reset condition, the ad-
dress bus is in a high-impe dan ce state.
AD7–AD0
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These tim e-multiplexed pi ns supply p ar tial memor y or
I/O addresses, as well as data, to the system. AD7–
AD0 supply the low-order 8 bits of an address to the
system duri ng the first per iod o f a bus cy cle (t 1). On a
writ e, these pins s upply data to the system dur ing the
remaining periods of that cycle (t2, t3, and t4). On a
read, these pins latch data at the end of t3.
Also, if S0/SREN (show read enable) was pulled Low
during reset or if the SR bit is set in the Internal Memory
Chip Select (IMCS) Register, these pins supply the
data read from internal memory during t3 and t4.
On the Am186ER microcontroller, AD7–AD0 combine
with AD15–AD8 to form a complete multiplexed ad-
dress and 16-bi t data bus.
On the Am188ER m icrocontroller, AD7–AD0 combine
with AO15–AO8 to form a complete multiplexed ad-
dress bus while AD7–AD0 is the 8-bit data bus.
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WLB is n egated, th ese p ins are three-s tated d uring t 2,
t3, and t4.
During a bus hold or reset condition, the address and
data bus are in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the Am186ER microcontroller,
AO15–AO8 and AD7–AD0 for the Am188ER microcon-
troller) can also be used to load system configuration
information into the internal reset configuration regis-
ter. The system information is latched on the rising
edge of RES.
AD15–AD8 (Am186™ER Microcontroller)
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These ti me-multiplexed pi ns supply p ar tial memor y or
I/O addresses, as well as data, to the system. AD15–
AD8 supply the hig h-order 8 bits of an a ddress to the
system dur ing th e first per iod of a bus cycle ( t1). On a
writ e, these pin s supply data to th e system dur ing the
remaining periods of that cycle (t2, t3, and t4). On a
read, these pins latch data at the end of t3.
Also, if S0/SREN (show read enable) was pulled Low
during reset or if the SR bit is set in the Internal Memory
Chip Select (IMCS) Register, these pins supply the
data read from internal memory during t3 and t4.
On the Am186ER microcontroller , AD15–AD8 combine
with AD7–AD0 to form a complete multiplexed address
and 16-bit data bus.
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is negated, these pins are three-stated during t2,
t3, and t4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the Am186ER microcontroller,
AO15–AO8 and AD7–AD0 for the Am188ER microcon-
troller) can also be used to load system configuration
information into the internal reset configuration regis-
ter. The system information is latched on the rising
edge of RES.
AO15–AO8 (Am188™ER Microcontroller)
Address-Only Bus (output, three-state,
synchronous, level-sensitive)
On the Am188ER microcontroller, the address-only
bus (AO15–AO8) contains valid high-order address bits
from bus cycles t1–t4. These outputs are three-stated
during a bus hold or reset.
On the Am188ER microcontroller, AO15–AO8 combine
with AD7–AD0 to form a complete multiplexed address
bus while AD7–AD0 is the 8-bi t data bus.
On the Am188ER microcontroller during a power-on
reset, the AO15–AO8 and AD7 –AD0 pins can als o be
used to load system configuration information into an
internal register for later use.
Am186TMER and Am188TMER Microcontrollers Data Sheet 31
DRAFT
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address ap-
pears on the address and data bus (AD15–AD0 for
the Am186ER microcontroller or AO15–AO8 and
AD7–AD0 for the Am188ER microcontroller). The ad-
dress is guaranteed valid on the trailing edge o f ALE .
This pin is thr ee-stated du r ing O NCE mode.
ARDY
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin indicates to the microcontroller that the ad-
dressed memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that
is async hronous to CLKOUTA and is active High. Th e
falling edge of ARDY must be synchronized to
CLKOUTA. To always assert the ready condition to the
microcon troller, tie ARDY H igh. If th e sys tem do es no t
use ARDY, tie the pin Low to yield control to SRDY.
BHE/ADEN
(Am186™ER Microcontroller Only)
Bus High Enable (three-state, output, synchronous)
Address Enable (input, internal pullup)
BHE—During a memory access, this pin and the least-
signifi cant ad dress b it (A D0 or A0) indic ate to t he sys -
tem which bytes of the data bus (upper, lower, or both)
participate in a bus cycle. The BHE/ADEN and AD0
pins are encoded as shown in Table 2.
BHE is asserted during t1 and remains asserted
through t3 and tW. BHE does not need to be latched.
BHE is three-stated during bus hold and reset condi-
tions.
On the Am186ER microcontroller, WLB and WHB im-
plement the functionality of BHE and AD0 for high an d
low by te wr ite enables.
Table 2. Data Byte Encoding
BHE/ADEN also signals DRAM refresh cycles when
using the multiplex ed address and data (AD) bus. A re-
fresh cycle is indicated when both BHE/ADEN and AD0
are High. Durin g refres h cycl es, the A bus and t he AD
bus are not guaranteed to provide the same address
during the address phase of the AD bus cycle. For this
reason, the A0 signal cannot be used in place of the
AD0 signal to determine refresh cycles. PSRAM re-
freshes also provide an additional RFSH signal (see
the MCS3/RFSH pin description on page 33).
ADEN—If BHE/ADEN is hel d High or left floatin g dur-
ing power-on reset, the a ddress portion of the AD bus
(AD15–AD0) is enabled or disabled during LCS and
UCS bus cycles based on the DA bit in the LM CS and
UMCS registers. If the DA bit is set, the memory ad-
dress is accessed on the A19–A0 pins. This mode of
operation reduces power consumption. For more infor-
mation, see the Bus Operation section on page 41.
There is a weak i nte rnal pullup re sistor on B HE/ADEN
so no external pullup is required.
If BHE/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data. Changing the DA
bit of the LMCS and UMCS registers will have no effect.
(S6 and UZI also assume their nor mal functionality in
this instance. The PIO Mode and Direction registers
cannot reconfigure these pins as PIOs. See Table 3 on
page 36.) The pin is sampled within three crystal clock
cycles after the rising edge of RES. BHE/ADEN is
three-stated during bus holds and ONCE mode.
Note: Once the above modes are set, they can be
changed only by resetting the processor.
CLKOUTA
Clock Output A (output, synchronous)
This pin suppli es the inter nal clock to the system. De-
pending on the value of the P ower-Sav e Control Regis-
ter (PDCON), CLKOUTA operates at either the CPU
fundamental frequency (which varies with the divide by
two, times one, and times four clocking modes), the
power-sav e frequency , or is three-stated (see Figure 10
on page 48). CLKOUTA remains active during reset
and bus hold conditions.
CLKOUTB
Clock Output B (output, synchronous)
This pin su pplies a c lock to the system. Dep ending on
the value of the Power-Save Control Register (PD-
CON), CLKOUTB operates at either the CPU funda-
mental fre quency (whic h va ries with the divide by two,
times one, and times four clocking modes), the power-
save frequency, or is three-stated (see Figure 10 on
page 48). CLKOUTB remains active during reset and
bus hold condition s.
DEN/PIO5
Data Enable (output, three-state, synchronous)
This pin supplies an output enable to an external data-
bus transceiver. DEN is asserted during memory, I/O,
and inter rupt acknowledge cycles. DEN is deasser te d
when DT/R chan ges st ate. DEN is three-stated dur ing
a bus hold or reset condition.
BHE AD0 Type of Bus Cycle
0 0 Word Tra nsfer
0 1 High Byte Transfer (Bits 15–8)
1 0 Low Byte Transfer (Bits 7–0)
1 1 Refresh
32 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
DRQ1–DRQ0
(DRQ1/PIO13, DRQ0 /PI O12 )
DMA Requests (input, synchronous,
level-sensitive)
These pins indicate to the microcontroller that an exter-
nal device is ready for DMA ch annel 1 or chann el 0 to
perform a transfer. DRQ1–DRQ0 are level-triggered
and internally synchronized.
The DRQ si gna ls are n ot l atc hed and must re mai n ac -
tive until serviced.
DT/R/PIO4
Data Transmit or Receive (output, three-state,
synchronous)
This pin indicates which direction data should flow
through an external data-bus transceiver. Wh en DT/R
is asserted High, the microcontroller transmits data.
When this pin is deasser ted Low, the microcontroller
receives data. DT/R is three-stated during a b us hold or
reset condition.
GND
Ground
The ground pins connect the system ground to the mi-
crocontroller.
HLDA
Bus Hold Acknowledge (output, synchronous)
When an external bus master requests control of the
local bus (by asserting HOLD), the microcontroller
completes the bus cycle in progress and then relin-
quishes control of the bus to the external bus master by
asserting HLDA and floating DEN, RD, WR, S2–S0,
AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and DT/R,
and then driving the chip selects UCS, LCS, MCS3–
MCS0, PCS6–PCS5, and PCS3–PCS0 High.
When the external bus master has finished using the
local bus, it indicates this to the microcontroller by
deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (that is,
for refresh), it will deasser t HLDA before the external
bus master deass er t s HOLD. The exter nal bus master
must be able to deasser t HOLD and allow the micro-
controller access to the bus. See the timing diagrams
for bus hold on page 101 . This pin is th ree-sta ted dur-
ing ONCE mode.
HOLD
Bus Hold Request (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that an external
bus master needs control of the local bus. For more in-
formation, see the HLDA pin description.
The Am186E R and A m18 8E R mic roc ont ro ll ers’ HOL D
latency time, the time between HOLD request and
HOLD acknowledge, is a fun ct ion of th e ac ti vity oc cur-
ring in the processor when the HOLD request is re-
ceived. A HOLD request is second only to DRAM or
PSRAM refresh requests in priority of activity requests
received by the processor. This implies that if a HOLD
request is rece ived just as a DMA t ransfer be gins, the
HOLD latency can be as great as four bus cycles. This
occurs if a DMA word transfer operation is taking place
(Am186ER microcontroller only) from an odd address
to an odd a ddres s. This is a total of 16 c lock cycles or
more if wait states are required. In addition, if locked
transfers are performed, the HOLD latency time is in-
creased by the length of the locked transfer.
INT0
Maskable Interrupt Request 0 (input,
asynchronous)
This pin indicates to the microcontroller that an inter-
rupt request has occurred. If the INT0 pin is not
masked, the microcontroller transfers program execu-
tion to the location specified by the INT0 vector in the
microcontroller interrupt vector table.
Interr upt requ ests are sync hronized in ter nal ly an d can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT0 until the request is acknowledged.
INT1/SELECT
Maskable Interrupt Request 1 (input,
asynchronous)
Slave Select (input, asynchronous)
INT1—This pi n indicat es t o the mic r ocontroll er t hat an
interr upt request h as occurred . If INT1 is not ma sked ,
the microcontroller transfers program execution to the
location specified by the INT1 vector in the microcon-
troller interrupt vector table.
Interr upt requ ests are sy nchroni zed inter nal ly an d can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT1 until the request is acknowledged.
SELECT—When the microcontroller interrupt control
unit is operating as a slave to an external master inter-
rupt controller, this pin indicates to the microcontroller
that an interrupt type appears on the address and data
bus. The INT0 pin must indicate to the microcontroll er
that an inter rupt has oc curred before the S ELECT pin
indicates to the microcontroller that the interrupt type
appears on the bus.
Am186TMER and Am188TMER Microcontrollers Data Sheet 33
DRAFT
INT2/INTA0/PIO31
Maskable Interrupt Request 2 (input,
asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
INT2—This pi n indic ates t o the microc ontrol ler that a n
interrupt request has occurred. If the INT2 pin is not
masked, the microcontroller transfers program execu-
tion to the loca tion specified by the INT2 vector in the
microcontroller interrupt vector table.
Interr upt requ ests a re syn chroni zed inter nal ly and can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT2 until the request is acknowledged.
INT2 becomes INTA 0 when INT0 is conf igure d in cas-
cade mode.
INTA0—When the microcontroller interrupt control unit
is operatin g in casc ade mode, this pin indicates to th e
system that the microcontroller needs an interrupt type
to process the interrupt request on INT0. The periph-
eral issui ng the interr upt request mus t provide th e mi-
crocontroller with the corresponding interrupt type.
INT3/INTA1/IRQ
Maskable Interrupt Request 3
(input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pi n indic ates t o the microc ontrol ler that a n
interrupt request has occurred. If the INT3 pin is not
masked, the microcontroller then transfers program ex-
ecution to the location specified by the INT3 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT3 until the request is acknowledged.
INT3 becomes INTA 1 when INT1 is conf igure d in cas-
cade mode.
INTA1—When the microcontroller interrupt control unit
is operatin g in casc ade mode, this pin indicates to th e
system that the microcontroller needs an interrupt type
to process the interrupt request on INT1. The periph-
eral issui ng the interr upt request mus t provide th e mi-
crocontroller with the corresponding interrupt type.
IRQ—When the microcontroller interrupt control unit is
operating as a slave to an external master interrupt
controller, this pin lets the microcontroller issue an i n-
terrupt request to the external master interrupt control-
ler.
INT4/PIO30
Maskable Interrupt Request 4 (input,
asynchronous)
This pin indicates to the microcontroller that an inter-
rupt request has occurred. If the INT4 pin is not
masked, the microcontroller then transfers program ex-
ecution to the location specified by the INT4 vector in
the microcontroller interrupt vector table.
Interr upt requ ests are sync hronized in ter nal ly an d can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT4 until the request is acknowledged.
LCS/ONCE0
Lower Memory Chip Select (output, synchronous,
internal pullup)
ONCE Mode Request 0 (input)
LCS—This pin indicates to th e system that a mem ory
access is in progress to th e lower me mor y bl ock. The
size of the lower m emo ry block is programmable up t o
512 Kbyte. LCS is held High dur ing a bus hold condi-
tion.
ONCE0—During reset, this pin and ONCE1 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode; otherwise, it operates normally.
In ONCE mode, all pins assume a high-impedance
state and r emain in that state un til a subs equen t rese t
occur s. To guarantee that the mic rocontr oller do es not
inadvertently enter ONCE mode, ONCE0 has a weak
internal pullup resistor that is active only during reset.
MCS3/RFSH/PIO25
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
MCS3—This pin indicates to the system that a memory
access is in progress to the fourth region of the
midrange memory block. The base address and size of
the midrange memory bloc k are programmable. MCS3
is held High during a bus hold condition. In addition,
this pin has a weak internal pullup resistor that is active
during reset.
RFSH—This pin provides a signal timed for auto re-
fresh to PS RAM devices. It is only enabled to function
as a refres h pul se when the PSR AM m ode bit i s set i n
the LMCS Register. An active Low pulse is generated
for 1.5 clock cycles with an adequate deasser tion pe-
riod to ensure that overall auto refresh cycle time is
met.
34 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
MCS2–MCS0
(MCS2/PIO24, MCS1/PIO15, MCS0/PIO14)
Midrange Memory Chip Selects (output,
synchronous, internal pullup)
These pins indicate to the system that a memory ac-
cess is in progress to the correspon ding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable.
MCS2–MCS0 are held High during a bus hold condi-
tion. In addition, they have weak internal pullup resis-
tors that are active during reset. Unlike the UCS and
LCS chip selec ts, the MCS outputs assert with the mul-
tiplexed AD address bus.
NMI
Nonmaskable Interrupt (input, synchronous, edge-
sensitive)
This pin indicates to the microcontroller that an inter-
rupt r equ est ha s occu rred . The NM I s ig nal i s the hig h-
est priority hardware interrupt and, unlike the INT4–
INT0 pins, cannot be masked. The microcontroller al-
ways transfers program execution to the location spec-
ified by the nonmaskable interrupt vector in the
microcontroller interr upt vector table when NMI is as-
ser ted.
Although NMI is th e highe st pr ior ity int err upt sou rce, it
does not participate in the priority resolution process of
the maskable interrupts. There is no bit associated with
NMI in the i nter r upt in-se rvi c e or i nterrup t requ es t reg-
isters. This means that a new NMI request can interrupt
an executing NMI interrupt service rout ine. As with all
hardware interrupts, the IF (interrupt flag) is cleared
when the processor takes the interrupt, disabling the
maskable interrupt sources. However, if maskable in-
terrupts are reenabled by software in the NMI interrupt
ser v ice routi ne, via the S TI instr uc tion fo r example, an
NMI curr en tly i n s erv ic e wil l n ot h ave any effect on th e
priority resolution of maskable interrupt requests. For
this reason, it is strongly advised that the interrupt ser-
vice r outine fo r NMI do es not en able the mask able in-
terrupts.
An NMI transition from Low to High is latched and syn-
chroni zed inter nally, an d it initiate s the interr upt at th e
next instruc tion boundar y. To guarant ee that the i nter-
rupt is recognized, the NMI pin must be asserted for at
least one CLKOUTA period. Because NMI is rising
edge sensitive, holding the pin High during reset has no
effect on program execution.
PCS3–PCS0
(PCS3/ PIO19, PCS2/PIO18,
PCS1/PIO17, PCS0/PIO16)
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory ac-
cess is in progress to the correspon ding region of the
peripheral memory block (either I/O or memory ad-
dress space). The base address of the peripheral
memory block is programmable. PCS3–PCS0 are held
High during a bus hold condition. They are also held
High during reset.
PCS4 is not av ailab le on the Am186ER and Am188ER
microcontrollers.
Unlike the UCS/LCS chip selects, the PCS outp uts as-
sert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in the
80C186 /80C1 88 micr oc ont roll er s.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory
access is in progres s to the sixt h region of the peri ph-
eral memory block (either I/O or memory address
space). The base address of the peripheral memory
bloc k is programmab le. PCS5 is held High during a bus
hold condition. It is also held High during reset.
Unlike the UCS and LCS chip sel ects, the PCS outputs
assert with t he mul tip lexe d A D ad dres s bus. Note al s o
that each peripheral chip select asserts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in the 80C186
and 80C188 microcontrollers.
A1—When the EX bit in the MCS and PCS auxiliary
regist er is 0 , th is pin s upp lies a n internally latch ed ad-
dress bit 1 t o the sy stem. Dur ing a bus hold con dition ,
A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory
access is in progress to the seve nth region of the pe-
ripheral memor y block (either I/O or memor y address
space). The base address of the peripheral memory
bloc k is programmab le. PCS6 is held High during a bus
hold condition or reset.
Unlike the UCS and LCS chip sel ects, the PCS outputs
assert with t he mul tip lexe d A D ad dres s bus. Note al s o
that each peripheral chip select asserts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in earlier gen-
erations of the Am186/Am188 microcontrollers.
A2—When the EX bit in the MCS and PCS auxiliary
regist er is 0 , th is pin s upp lies a n internally latch ed ad-
dress bit 2 t o the sy stem. Dur ing a bus hold con dition ,
A2 retains its previously latched value.
Am186TMER and Am188TMER Microcontrollers Data Sheet 35
DRAFT
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ER and Am188ER microcontrollers provide
32 individually programmable I/O pins. Each PIO can
be progr amm ed w it h t he f o ll o wi n g a t tributes: PI O f u nc -
tion (enabled/disabled), direction (input/output), and
weak pullup or pulldown.
On the Am186 ER and Am 188ER mi crocon troller s, the
internal pullup resistor has a value of approximately
100 kohms. The int ernal p ull down r esi sto r ha s a value
of approximately 100 kohms.
The pins that are multiplexed with PIO31–PIO0 are
listed in Table 3 and Table 4 on page 36.
After power-on reset, the PIO pins default to various
configurations. The column titled
Power-On Reset Sta-
tus
in Table 3 and Table 4 lists the defaults for the PIOs.
The system initialization code must reconfigure any
PIOs as required.
If PIO29 (S6/CLKSEL1) is to be used in input mode, the
input device must not drive PIO29 Low during power-
on reset. The pin defaults to a PIO input with pullup, so
it does not need to be driven High externally.
The A19–A17 address pins default to normal operation
on power-on reset, allowing th e processor to cor rectly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, a nd SRDY pins also defaul t
to normal operation on power-on reset.
RD
Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the microcontroller
is perfo r ming a m emory or I/O re ad cycl e. RD is guar-
anteed not to be asserted before the address and data
bus is floated during the address-to-data transition. RD
is three-stated during bus holds and ONCE mode.
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller immedi-
ately terminates its present activity, clears its internal
logic, and CPU control is transferred to the reset ad-
dress FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLK OUTA be-
cause RES is synchronized internally . For proper initial-
ization, VCC must be within specifications, and
CLK OUTA must be stable for more than four CLK OUTA
periods during which RES is asserted.
The microcontroller begins fetching instructions ap-
proximately 6.5 CLKOUTA periods after RES is deas-
ser ted. This input is provided with a Schmitt tri gger to
facilitate power-on RES generation via an RC network.
RFSH2/ADEN
(Am188™ER Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—A sserted L ow to si gn ify a DRAM r efres h bus
cycle. The use of RFSH2/ADEN to signal a refresh is
not valid whe n PSR AM mo de is selec ted. In st ead, th e
MCS3/RFSH signal i s pr ovided to the PS RA M. D uring
reset, this pin is a pullup. This pin is three-stated during
bus holds and ONCE mode.
ADEN—If RFSH2/ADEN is held High or left floating on
power-on reset, the AD bus (A O15–AO8 and AD7–AD0)
is enabled or disabled during the address portion of LCS
and UCS bus cycles ba sed on the DA bit in the LMCS
and UMCS r egisters . If the D A bit is set , the memory ad-
dress is accessed on the A19–A0 pi ns. This mode of op-
eration reduces power consumption. For more
informatio n, see the Bus Operation section on page 41.
There is a weak internal pullup resistor on RFSH2/
ADEN so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data. Changing the DA
bit of the LMCS and UMCS registers will have no effect.
(S6 and UZI also assume their nor mal functionality in
this instance. The PIO Mode and Direction registers
cannot reconfigure these pins as PIOs. See Table 3
and Table 4 on page 36.) The pin is sampled within
three crystal clock cy c les af ter the ris ing edg e of RE S .
RFSH2/ADEN is three-stated during bus holds and
ONCE mode.
Note: Once the above modes are set, they can be
changed only by resetting the processor.
RXD/PIO28
Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data
from the s ystem to th e i nte rnal UART o f th e m icr ocon-
troller.
S2
Bus Cycle Status (output, three-state,
synchronous)
S2—This pin indicates to the system the type of bus
cycle in p ro g re ss. S2 can be used as a logical memory
or I/O indicator. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, t hese pins are pul lups. The S2–S0 pins ar e en-
coded as shown in Table 5 on page 37.
36 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Table 3. Numeric PIO Pin Assignments
Notes:
1. These pins are used by emulators. (Emulators also use
S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0,
and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN
(Am186ER microcontroller) or RFSH2/ADEN (Am 188ER
microcontroller) is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
Table 4. Alphabetic PIO Pin Assignments
Notes:
1. These pins are used by emulators. (Emulators also use
S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0,
and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN
(Am186ER microcontroller) or RFSH2/ADEN (Am188ER
microcontroller) is held Low during powe r-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
PIO No. Associated Pin Power-On Reset Status
0TMRIN1 Input with pullup
1TMROUT1 Input with pulldown
2PCS6/A2 Input w ith pullup
3PCS5/A1 Input w ith pullup
4DT/R Normal operation(3)
5DEN Normal operation(3)
6SRDY Normal operation(4)
7(1) A17 Normal operation(3)
8(1) A18 Normal operation(3)
9(1) A19 Normal operation(3)
10 TMROUT0 Input with pulldown
11 TMRIN0 Input with pullup
12 DRQ0 Input with pullup
13 DRQ1 Input with pullup
14 MCS0Input with pullup
15 MCS1Input with pullup
16 PCS0Input with pullup
17 PCS1Input with pullup
18 PCS2Input with pullup
19 PCS3Input with pullup
20 SCLK Input with pullup
21 SDATA Input with pullup
22 SDEN0 Input with pulldown
23 SDEN1 Input with pulldown
24 MCS2Input with pullup
25 MCS3/RFSH Input with pullup
26(1,2) UZI/CLKSEL2Input w ith pul lup
27 TXD Input with pullup
28 RXD Input with pullup
29(1,2) S6/CLKSEL1In put with pul lup
30 INT4 Input with pullup
31 INT2 Input with pullup
Associated Pin PIO No. Power-On Reset Status
A17(1) 7Normal operation(3)
A18(1) 8Normal operation(3)
A19(1) 9Normal operation(3)
DEN 5Normal operation(3)
DRQ0 12 Input with pullup
DRQ1 13 Input with pullup
DT/R 4Normal operation(3)
INT2 31 Input with pullup
INT4 30 Input with pullup
MCS014 Input with pullup
MCS115 Input with pullup
MCS224 Input with pullup
MCS3/RFSH 25 Input with pullup
PCS016 Input with pullup
PCS117 Input with pullup
PCS218 Input with pullup
PCS319 Input with pullup
PCS5/A1 3Inp ut with pul lup
PCS6/A2 2Inp ut with pul lup
RXD 28 Input with pullup
S6/CLKSEL1(1,2) 29 Input with pul lup
SCLK 20 Input with pullup
SDATA 21 Input with pullup
SDEN0 22 Input with pulldown
SDEN1 23 Input with pulldown
SRDY 6Normal operation(4)
TMRIN0 11 Input with pullup
TMRIN1 0Input with pullup
TMROUT0 10 Input with pulldown
TMROUT1 1Input with pulldown
TXD 27 Input with pullup
UZI/CLKSEL2(1,2) 26 Input with pullup
Am186TMER and Am188TMER Microcontrollers Data Sheet 37
DRAFT
S1/IMDIS
Bus Cycle Status (output, three-state,
synchronous)
Internal Memory Disable (input, internal pullup)
S1—This pin indicates to the system the type of bus
cycle in progress. S1 can be used as a data transmit or
receive indicator. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, the se pins are pullups. The S 2–S0 pins a re en-
coded as shown in Table 5.
IMDIS—If ass erted during r eset , this pin di sab les in ter-
nal memory. Internal memory disable mode is provided
for emulation and debugging purposes.
S0/SREN
Bus Cycle Status (output, three-state,
synchronous)
Show Read Enable (input, internal pullup)
S0—This pin indicates to the system the type of bus
cycle in progress. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, the se pins are pullups. The S 2–S0 pins a re en-
coded as shown in Table 5.
SREN—I f asser ted du ring reset, this pin en ables data
read from internal memor y to be shown/driven on the
AD15–AD0 bus. Note that if a byte read is being shown,
the unused byte will al so be driven on the A D15–AD0
bus.This mode is provided for emulation and debug-
ging purposes.
Table 5. Bus Cycle Encoding
S6/CLKSEL1/PIO29
Bus Cycle Status Bit 6 (output, synchronous)
Clock Select 1 (input, internal pullup)
S6—During the second and remaining periods of a
cycle (t 2, t3, and t4), this pin is asserted High to indicate
a DMA-initiated bus cycle. During a bus hold or reset
condition, S6 is three-stated.
CLKSEL1—The clocking mode of the Am186ER and
Am188ER microcontrollers is controlled by UZI/
CLKSEL2/PIO26 and S6/CLKSEL1/PIO29. Both
CLKSEL2 and CLKSEL1 are he ld High du ring power-
on rese t becaus e of an in ter nal pul lup resis tor. This is
the default clocking mode—Times Four. If CLKSEL1 is
held Low during power-on reset, the chip enters the Di-
vide by Two clocking mode where the fundamental
clock is der ived by divid ing the ex terna l clock input by
2. If Divide by Two mode is selected, the PLL is dis-
abled. This pin i s latc hed w ithin three cr y stal c lock cy-
cles after the rising edge of RES. Refer to Reset
W a veforms on page 100 and Signals Related to Reset
Waveforms on page 100 to determine signal hold
times. See Table 6 on page 39 for more information on
the clocking modes.
If S6 is use d as P IO29 in inp ut mo de, the device driving
PIO29 must not drive the pin Low during power-on reset.
S6/CLKSEL1/PIO29 defaults to a PIO input with pullup,
so the pin does not ne ed to be driven High externally.
SCLK/PIO20
Serial Clock (output, synchronous)
This pin supplies the synchronous serial interface (SSI)
clock to a slave device, allowing transmit and receive
operations to be synchroni ze d between the m icrocon-
troller and the slave. SCLK is derived from the micro-
control ler inter nal clo ck and then divi ded by 2, 4, 8, or
16 depending on register sett ing s.
An access to any of the SSR or SSD registers acti-
v ates SCLK for eight SCLK cycles (see Figure 14 and
Figure 15 on page 58). When SCLK is inactive, it is
held High by the microcontroller . SCLK is t hree-stated
during ONCE mode.
SDATA/PIO21
Serial Data (input/output, synchronous)
This pin transm its and re ceives synchr onous ser ial in-
terface (SSI) data to and from a slave device. When
SDATA is inactive, a weak keeper holds the last value
of SDATA on the pin.
SDEN1/PIO23, SDEN0/PIO22
Serial Data Enables (output, synchronous)
These pin s enable data t ransfers on port 1 a nd por t 0
of the synchronous serial interface (SSI). The micro-
controller asserts either SDEN1 or SDEN0 at the be-
ginning o f a transfer an d deasserts it after the transfer
is complete. When SDEN1–SDEN0 are inactive, they
are held Low by the microcontroller. SDEN1–SDEN0
are three-stated during ONCE mode.
S2 S1 S0 Bus Cycle
0 0 0 Interrupt acknowledge
0 0 1 Read data from I/O
0 1 0 Write data to I/O
0 1 1 Halt
1 0 0 Instruction fetc h
1 0 1 Read data from memory
1 1 0 Write data to memory
1 1 1 None (passive)
38 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
SRDY/PIO6
Synchronous Ready (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that the ad-
dressed memory space or I/O device will complete a
data transfer. The SRDY pin accepts an active High
input synchronized to CLKOUTA.
Using SRDY instead of AR DY allows a rela xed system
timing b ecaus e of the elimi natio n of the o ne-half clock
period required to inter nally synchronize ARDY. To al-
ways asse r t the r eady condi tion to th e micr ocontr oller,
tie SRD Y High. If the system does not use SRD Y, tie the
pin Low to yield control to ARD Y. When SRDY is config-
ured as P106, the internal SRDY signal is driven low.
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 0. After internally synchronizing a
Low-to-High trans ition on TMRIN0 , the microc ontroll er
increm ents th e timer. TMRIN0 must be tied Hi gh if no t
being used.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 1. After internally synchronizing a
Low-to-High trans ition on TMRIN1 , the microc ontroll er
increm ents th e timer. TMRIN1 must be tied Hi gh if no t
being used.
TMROUT0/PIO10
Ti mer Output 0 (output, synchronous)
This pin sup plies the sy stem w ith eith er a sin gle puls e
or a continuous waveform with a programmable duty
cycle.
TMROUT1/PIO1
Ti mer Output 1 (output, synchronous)
This pin sup plies the sy stem w ith eith er a sin gle puls e
or a continuous waveform with a programmable duty
cycle.
TXD/PIO27
Transmit Data (output, asynchronous)
This pin supp lies async hronous serial tran smit data to
the system from the internal UART of the microcontrol-
ler.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
UCS—This pin ind icates to the s ystem that a memor y
access is in progress to the upper memor y bl ock. The
base addr ess and si ze of the upper mem or y block are
programmable up to 512 Kbyte. UCS is hel d H igh dur -
ing a bus hold condition.
After pow er-on res et, UCS is asserted because the mi-
crocontroller begins executing at FFFF0h and the de-
fault conf iguration for the UCS chi p select i s 64 Kbyte
from F0000h to FFFFFh.
ONCE1—During reset, this pin and ONCE0 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode. Otherwise, it operates normally. In
ONCE mode, all p ins assume a hi gh-impedan ce state
and remain in that state until a subsequent reset oc-
curs. To guarantee the microcontroller does not inad-
vertently enter ONCE mode, ONCE1 has a weak
internal pullup resistor that is active only during a reset.
UZI/CLKSEL2/PIO26
Upper Zero Indicate (output, synchronous)
UZI—This pin lets the designer determine if an ac-
cess to the interrupt vector table is in progress by
ORing it with bits 15–10 of the address and data bus
(AD15–AD10 on the Am186ER microcontroller and
AO15–AO10 on the Am188ER microcontroller). UZI
is the logical AND of the inver ted A19–A16 bits. UZI
is not held throughout the cycle. UZI is asserted in
the first period and deasser ted in the second period
of a bus cycle. UZI/CLKSEL2 is three-stated during
bus holds and ONCE mode.
CLKSEL2—The clocking mode of the Am186ER and
Am188ER microcontrollers is controlled by UZI/
CLKSEL2/PIO26 and S6/CLKSEL1/PIO29 during re-
set. Both CLKSEL2 and CLKSEL1 are held High during
power-on reset because of an inter nal pullup resistor.
This is the default clocking mode—Times Four, which
is used if neither clock select is asserted Low during re-
set.
If CLKSEL2 is held Low during power-on reset, the mi-
crocontroller enters Times One mode.
This p in is latc hed within three crystal clock cycles aft er
the r ising edge of RE S. Refer to Reset Waveform s on
page 100 and Signals Related to Reset W a veforms on
page 100 to determine signal hold times. Note that
cloc k s elec tion mus t be s tab le four cloc k cycles p rior to
exiting re set (th at is, RES goi ng High) . See Table 6 on
page 39 for specifics on the clocking modes and how to
specify them. UZI/CLKSEL2 is three-stated during bus
holds and ONCE mode.
Am186TMER and Am188TMER Microcontrollers Data Sheet 39
DRAFT
Table 6. Clocking Modes
VCC
Power Supply (input)
These pins supply power (+3. 3 V) to the mic rocontro l-
ler.
WHB (Am186™ER Microcontroller Only)
Write High Byte (output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of
the data bus (upper, lower, or both) participate in a
write cycle. In 80C186 designs, this information is pro-
vided by BHE, AD0, and WR. However, by using WHB
and WLB, the s tandard system inter face lo gic and ex-
ternal address latch that were required are eliminated.
WHB is asser ted with AD15–AD8. WHB is the logical
OR of BHE and WR. Dur ing res et, this pin is a p ullup.
This pin is three-stated during bus holds and ONCE
mode.
WLB (Am186™ER Microcontroller Only)
WB (Am188™ER Microcontroller Only)
Write Low Byte (output, three-state, synchronous)
Write Byte (output, three-state, synchronous)
WLB—This pin and WHB indicate to the system which
bytes of the data bus (upper, lower , or both) participate
in a wr ite cy cle. In 80C1 86 des igns, this infor ma tion is
provided by BHE, AD0, and WR. However, by using
WHB and WLB, the standard system interface logic
and external address latch that were required are elim-
inated.
WLB is asserted with AD7–AD0. WLB is the logica l OR
of A0 and WR. This pin is three-stated during bus holds
and ONCE mode.
WB—On the Am188ER microcontroller, this pin indi-
cates a write to the bus. WB uses the same early timing
as the non multiplexed address bus. WB i s associate d
with AD7–AD0. This pin is three-stated during bus
holds and ONCE mode.
WR
Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus
is to be written to a memory or I/O device. WR is three-
stated during a bus hold or reset condition.
X1
Crystal Input (input)
This pin an d the X2 pin provide c onnection s for a fun-
damental mode crystal used by the internal oscillator
circuit. If providing an external clock source, connect
the source to X1 and leave X2 unconnected. Unlike the
rest of the pins on the Am186ER and Am188ER micro-
controlle rs, X1 is not 5- V tolera nt and has a maxi mum
input equ al to VCC.
X2
Crystal Output (output)
This pin an d the X1 pin provide c onnection s for a fun-
damental mode crystal used by the internal oscillator
circuit. If providing an external clock source, connect
the source to X1 and leave X2 unconnected. Unlike the
rest of the pins on the Am186ER and Am188ER micro-
controllers, X2 is not 5-V tolerant.
CLKSEL2CLKSEL1Clocking Mode
HH
Times Four
HL
Divide by Two
LH
Times One
LL
Reserved1
Notes:
1. The reserved clocking mode should not be used. Entering
the reserved clocking mode may cause unpredictable
system behavior.
40 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
FUNCTIONAL DESCRIPTION
The Am186ER and Am188ER microcontrollers are
based on the architecture of the original Am186 and
Am188 microcontrollers and they function in the en-
hance d mode of t he Am186 a nd Am188 microcont rol-
lers. Enhanced mode includes system features such as
power-save control.
Each of the 8086, 8088, 8018 6, and 80188 m icrocon-
trollers contains the same basic set of registers, in-
structions, and addressing modes. The Am186ER and
Am188ER microcontrollers are backward compatible
with the 80C186/80C188 and Am186/Am188 micro-
controllers.
A full description of the Am186ER and Am188ER mi-
crocon trollers’ reg isters an d instruc tions is inc luded in
the
Am186ER and Am188ER Microcontrollers User’s
Manual
, order #21684.
Memory Organization
Memory is organized in sets of segments. Each seg-
ment is a linear contiguous sequence of 64K (216) 8-bit
bytes. Memor y is addressed using a two-component
address consisting of a 16-bit segment v alue and a 16-
bit offse t. The 16-bit segment values are contained in
one of four i nter nal s egment regist ers (CS, DS, SS, or
ES). The physical addres s is cal culated by shifti ng the
segment value left by 4 bits and adding the 16-bit offset
value to y ie ld a 20-bi t physical a ddr es s (s ee Figu re 3).
This allow s fo r a 1-Mbyte physical address size.
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For spe ed and c ompac t inst r uction encod ing, the seg-
ment register used for physical address generation is
implied by the addressing mode used (see Table 7).
Figure 3. Two-Component Address Example
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN, INS and OUT, OUTS)
address the I/O space with either an 8-bit port address
specified in the instr uction, or a 16-bit por t address in
the DX register. Eight-bit port addresses are zero-
extended such that A15–A8 are Low.
Table 7. Segment Register Selection Rules
1 2 A 4 0
0 0 0 2 2
1 2 A 6 2
1 2 A 4
0 0 2 2
Segment
Base Logical
Address
Shift
Left
4 Bits
Physical Address
To Memory
15 0
19 0
19 0
15 0
15 0
Offset
Memory Reference Needed Segment Register Used Implicit Segment Selection Rule
Instructions Code (CS) Instructions (including immediate data)
Local Data Data (DS) All dat a references
Stack Sta ck (SS) All stack pushes and pops;
any memory references that use BP Register
External Data (Global) Extra (ES) All st ring instructio n references that use the DI Re gister as an in de x
Am186TMER and Am188TMER Microcontrollers Data Sheet 41
DRAFT
BUS OPERATION
The industry-standard 80C186/80C188 microcontrol-
lers use a multiple xed address and data (AD) bus. The
address is present on the AD bus only during the t1
clock phase. The Am186E R and Am188ER microcon-
trollers continue to provide the multiple xed AD bus and,
in add ition, provid e a nonmu ltiplexed a ddress (A) bus.
The A bus provides an address to the system for the
complete bus cycle (t1–t4).
For systems where power consumption is a concern,
the addr ess can be di sabled fr om being dr iven on the
AD bus on the Am186ER microcontroller and on the
AD and AO buses on the Am188ER microcontroller
duri ng the nor mal add ress portion of the bus cycle for
accesses to UCS and/or LCS address spaces. In this
mode, the affected bus is placed in a high -impeda nce
state dur ing the addre ss por tion of the bus cycl e. This
feature is enabled through the DA bits in the UMCS and
LMCS registers. When address disable is in effect, the
number of signals that assert on the bus during all nor-
mal bus cycle s to the a ssocia ted address space is re-
duced, thus decreasing power consumption, reducing
processor switching noise, and preventing bus conten-
tion with mem ory devices and periphera ls when oper-
ating at high clock rates. On the Am188ER
microcontroller, the address is driven on A015–A08
duri ng the data por tio n of the bu s cycle, regardless of
the setting of the DA bits.
If the ADEN pin is pulled Low during processo r re set,
the value of the DA bits in the UMCS and LMCS regis-
ters is ignored and the address is driven on the AD bus
for all accesses, thus preserving the industry-standard
80C186 and 80 C188 micr ocontrolle rs’ multip lexed ad-
dress bus an d providi ng support for existing emula tio n
tools.
Figure 4 on page 42 shows the affected signals during
a normal read or write operation for an Am186ER mi-
crocontroller. The address and data will be multiplexed
onto the AD bus.
Figure 5 on page 42 shows an Am186ER microcontrol-
ler bus cycle when address bus disable is in effect. This
results in having the AD bus operate in a nonmulti-
plexed data-only mode. The A bus will have the ad-
dress during a read or write operation.
Figure 6 on page 43 shows the affected signals during a
normal read or write operation for an Am188ER micro-
controller. The multiplexed address/data mode is com-
patible with the 80C188 microcontrollers and might be
used to take adv a nt ag e o f existi ng log ic o r periph er a l s .
Figure 7 on page 43 shows an Am188ER microcontrol-
ler b us cycle when addres s b us disa ble is in ef fect. The
address and data is not multiplexed. The AD7–AD0
signals will have only data on the bus, while the A bus
will have the address dur ing a read or wr ite o peration.
The A O bus will also have the address during t2–t4.
BUS INTERFACE UNIT
The bus in terface unit controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory- ma pped and I/O -map ped periphe rals an d th e
peripheral control block. The Am186ER and Am188ER
microcontrollers provide an enhanced bus interface
unit with the following features:
nA nonmultiplexed address bus
nSeparate byte write enables for h igh an d low bytes
on the Am186ER microcontroller and a write enable
on the Am188ER mic roco ntr ol le r
nPseudo Static RAM (PSRAM) support
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an ex-
ter na l ad dres s l atc h. On t he A m18 6ER and Am1 88E R
microcontrollers, new byte write enables, PSRAM con-
trol logic, and a new nonmultiplexed address bus can
reduce design costs by eliminating this external logic.
Nonmultiplexed Address Bus
The nonmultiplex ed address bus (A19–A0) is valid one-
half CLKOUTA cyc le in advance of the addre ss on th e
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte write enable sig-
nals, the A19–A0 bus provides a seamless interface to
external SRAM, PSRAM, and Flash/EPROM memory
systems.
Byte Write Enable s
The Am186ER microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals
which act as byte write enables. The Am188 ER micr o-
controller provides the WB (Write Byte) signal which
acts as a write enable.
WHB is the logical AND of BHE and WR . W HB is Low
when both BHE and WR are Low. WLB is the logical
AND of A0 and WR . WLB is Low when A0 and WR are
both Low. WB is Low whenever a byte is written by the
Am188 ER micr oc ont ro ll er.
The byte write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
Output Enable
The Am186ER and Am188ER microcontrollers provide
the RD (Read) signal which acts as an output enable .
The RD signal is Low when a word or byte is read by
the Am186ER or Am188ER microcontroller.
42 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Figure 4. Am186™ER Microcontroller Address Bus—Normal Operation
Figure 5. Am186™ER Microcontroller—Address Bus Disable in Effect
CLKOUTA
t1t2t3t4
AD15–AD0
(Read) Data
AD15–AD0
(Write)
LCS or UCS
Address
DataAddress
Address
Phase Data
Phase
A19–A0 Address
MCSx, PCSx
CLKOUTA
t1t2t3t4
AD15–AD0
(Write) Data
LCS or UCS
AD15–AD8
(Read)
AD7–AD0
(Read)
Address
Phase
Data
Data
Phase
Data
A19–A0 Address
Am186TMER and Am188TMER Microcontrollers Data Sheet 43
DRAFT
Figure 6. Am188™ER Microcontroller Address Bus—Normal Operation
Figure 7. Am188™ER Microcontroller—Address Bus Disable in Effect
CLKOUTA
t1t2t3t4
AD7–AD0
(Read) Data
AO15–AO8
(Read or Write)
AD7–AD0
(Write)
Address
Address
DataAddress
Address
Phase Data
Phase
A19–A0 Address
LCS or UCS
MCSx, PCSx
CLKOUTA
t1t2t3t4
AD7–AD0
(Read) Data
Address
AO15–AO8
LCS or UCS
AD7–AD0
(Write) Data
Address
Phase Data
Phase
A19–A0 Address
44 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Pseudo Static RAM (PSRAM) Support
The Am186ER and Am188ER microcontrollers support
the use of PSRA M devices i n low memor y chip -select
(LCS) space only. When PSRAM mode is enabled, the
ti ming for the LCS signal is modified by the chip-select
control unit to provide a CS precharge period during
PSRAM accesses. The 50-MHz timing of the
Am186ER and Am188ER microcontrollers is appropri-
ate to allow 70-ns PSRAM to run with one wait state.
PSRAM mode is enabled through a bit in the Low Mem-
ory Chip-Select (LMCS) Register. The PSRAM feature
is disabled on CPU reset.
In addition to the LCS timing changes for PSRAM pre-
charge, the PSRAM devices also require periodic re-
fresh of a ll inter nal row addresses to ret ain their data .
Although refresh of PSRAM can be accomplished se v-
eral ways, the Am18 6ER and Am188ER microcont rol-
lers implement auto refresh only.
The Am186ER an d Am188ER mi crocontr ollers gener-
ate RFSH, a refresh signal, to the PSRAM devices
when PSRA M mod e i s ena bled. No refr esh address is
required by the PSRAM when using the auto refresh
mechanism. The RFSH signal is multiplexed with the
MCS3 signal pin. When PSRAM mode is enabled,
MCS3 is not available for use as a chip-select signal.
The refresh control unit must be programmed before
access ing PSRA M in LCS spac e. The refresh coun ter
in the Clock Prescaler (CDRAM) Register must be con-
figured with the required refresh interval value. The re-
fresh counter reload value in the CDRAM Register
should n ot b e s et to le ss th an 1 8 ( 12h ) in or der to pro-
vide time for proc es so r cy cles between refre sh es. The
refresh address counter must be set to 000000h to pre-
vent the MCS3–MCS0 or PCS6–PCS0 chip selects
from asserting. UCS may randomly assert during a
PSRAM refresh.
LCS is he ld High an d the A bu s is not used dur ing r e-
fresh cycles. The LMCS Register must be configured to
external ready ignored (R2 = 1) with one wait state
(R1–R0 = 01b), and the PSRAM mode enable bit (SE)
must be set . The ending add ress of LCS space in the
LMCS Register must also be programmed.
PERIPHERAL CONTROL BLOCK (PCB)
The integrated peripherals of the Am186ER and
Am188ER microcontrollers are controlled by 16-bit
read/write registers. The peripheral registers are con-
tained within an internal 256-byte control block. The
registers are physically located in the peripheral de-
vices they control, but they are addressed as a single
256-byte block. Figure 9 on page 46 shows a map of
these regis te rs.
Reading and Wr iting the PCB
Code intended to execute on the Am188E R microc on-
troller should perform all writes to the PCB registers as
byte writes. These writes will transfer 16 bits of data to
the PCB Re gister even if an 8-bit reg ister is named i n
the instruction. For example, out dx, al results in
the ax value being written to the port address in dx.
Reads to the PCB should be done as word reads. Code
written in this manner will run correctly on the
Am188ER and Am 186ER microc ontrol le rs.
Unaligned reads and writes to the PCB result in unpre-
dictable behavior on both the Am186ER and Am188ER
microcontrollers.
For a complete description of all the registers in the
PCB, refer to the
Am186ER an d Am188ER Microc on-
trollers User’s Manual
, order #21684.
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the
Am186ER and Am188ER microcontrollers includes a
phase -locke d loop ( PLL) and a secon d programmable
system clock output (CLKOUTB).
Phase-Locked Loop (PLL)
In a t ra dit ion al 80C 18 6/8 0C188 d esign , th e inte rnal clock
frequ ency is half th e frequen cy of the crystal. Because of
the internal PLL on the Am186ER and Am188ER micro-
controllers, the internal clock generated by both micro-
controllers can operate at up to four times the frequency
of the crystal. The Am186ER and Am188ER microcon-
trolle rs operat e in the foll ow ing modes:
nDivide by Two—Frequency of the system clock is
half the frequency of the crystal with PLL disabled.
nTimes On e—Frequency of the sy stem cl ock will be
the same as the external crystal with PLL enabled.
nTimes Four—Fr equ ency of the system c lock is four
times the frequency of the crystal with PLL enabled.
The default Times Four mode must be used for processor
frequencies above 40 MHz. The Divide by Two mode
should be used for frequenci es below 16 MHz. The clock-
ing mode is selected using CLKSEL1 and CLKSEL2 on
reset. Table 8 provides the maximum and minimum fre-
quencies for X1, X2, and CLK OUTA according to clocking
mode.
T able 8. Maximum and Minimum Clock
Frequencies
Mode X1/X2
Max X1/X2
Min CLKOUTA
Max CLKOUTA
Min
Divide by 2 40 MHz 30 MHz 20 MHz 15 MHz
Times 1 40 MHz 16 MHz 40 MHz 16 MHz
Times 4 12.5 MHz 4 MHz 50 MHz 16 MHz
Am186TMER and Am188TMER Microcontrollers Data Sheet 45
DRAFT
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186ER and
Am188ER microcontrollers is designed to function with
a parallel-resonant fundamental mode crystal. Be-
cause o f the PLL, the cr ystal frequency can be twice,
equal to, or one quarter of the processor frequency. Do
not replace a crystal with an LC or RC equivalent. See
Figure 8 for a diagram of oscillator configurations.
The X1 and X2 signals are connected to an internal in-
verting amplifier (oscillator) that provides, along with
the external feedback loading, the necessary phase
shift. In such a positive feedback circuit, the inverting
amplifie r has an output s ignal (X2) 1 80 degrees out of
phase of the input signal (X1).
The external feedback network provides an additional
180-degree phase shift. In an ideal system, the input to
X1 will hav e 360 or zero degrees of phase shift. The ex-
ternal feedback network is designed to be as close to
ideal as possible. If the feedback network is not provid-
ing necessary phase shift, negative feedback will
dampen the output of the amplifier and negatively af-
fect the operation of the clock generator . Values for the
loading on X1 and X2 must be chosen to provide the
necessary phase shift and crystal operation.
Selecting a Crystal
When sel ecti ng a crystal , the l oad ca paci tance s houl d
always be specified (CL). This value can cause vari-
ance in the oscillation frequency from the desired spec-
ified value (resona nce). The lo ad capacitan ce and the
loading of the feedba ck networ k have the following re-
lationship:
wher e CS is the stra y capacitance of the circuit. Placing
the crystal and CL in series across the inverting ampli-
fier and tuning these values (C1, C2) allows the crystal
to oscillate at resonance. Finally, there is a relationship
between C1 and C2. To enhance the oscillation of the
inver ting a mplifier, the se values need to b e offse t with
the larger load on the output (X2). Equal values of
these loads will tend to balance the poles of the invert-
ing amplifier.
The characteristics of the inver ting amplifier set limits
on the following parameters for crystals:
ESR (Equivalent Series Resistance)60-ohm max
Drive Level.......................... 500-mW max
The recommended range of va lues for C1 and C2 are
as follows:
C1........................................ 15 pF ± 20%
C2........................................ 22 pF ± 20%
The specifi c values for C 1 and C2 must be deter mined
by the designer and are dependent on the characteris-
tics of the chosen crystal and board design.
External Source Clock
Alter nately, the inter nal oscillator can be driven by an
external clock source. The external clock source
should be connected to the input of the inv erting ampli-
fier (X1 ) wit h t he outp ut (X 2) left un connecte d. X1 an d
X2 are not 5-V tolerant and X1 has a maximum input
equal to VCC.
Figure 8. Am186™ER and Am188™ER Microcontrollers Oscillator Configurations
(C1 ⋅ C2)
CL = (C1 + C2)+ CS
Crystal
X1
b. Crystal Configuration
C1
C2X2 To PLL
Oscillator
a. External Clock Configuration
Microcontroller
Am188ER/
X1
X2 To PLL
Oscillator
Am186ER Microcontroller
Am188ER/
Am186ER
Notes:
X1 and X2 are not 5-V tolerant. The X1 maximum input is V
CC
.
46 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Figure 9. Peripheral Control Block Register Map
Serial Port Status Register
Serial Port Transmit Register
Serial Port Receive Register
Serial Port Baud Rate Divisor Register
PCS and MCS Auxiliar y Register
Memory Partition Register
PDCON Register
Reset Configuration Register
Upper Memory Chip Select Register
Enable RCU Register
A8
DA
E0
F0
F6
Peripheral Control Block Relocation Register
FE Register Na me
ww
ww
ww
ww
ww
Changed from original Am186
microcontroller
F4
Note: Gaps in offset addresses
indicate reserved regi sters. No
access should be made to reserved
registers.
Offset
(Hexadecimal)
E2
E4
D8
D6
D4
D2
CA
C8
C6
C4
C2
C0
Clock Prescaler Registe r
DMA 1 Control Register
DMA 1 Transfer Coun t Registe r
DMA 1 Destina t io n Addres s Lo w Re gi ste r
DMA 1 S ource Address High Regi ster
DMA 1 Source Address Low Regist er
DMA 0 Control Register
DMA 0 Transfer Coun t Registe r
DMA 0 Destination Address High Register
DMA 0 Destina t io n Addres s Lo w Re gi ste r
D0
DMA 0 Source Address Low Regist er
DMA 0 S ource Address High Regi ster
A6
A4
A2
A0
Midrange Memory Chip Select Register
Peripheral Chip Select Register
Low Memory Chip Select Register
80
82
84
86
88
Processor Release Level Register
DMA 1 Destination Address High Register
Serial Port Control Register
*
Changed from Am186EM and
Am188EM micro control le rs
*
Internal Memory Chip Select Register
AC
**
New to the Am186ER and
Am188ER microc ontrollers
**
Watchdog Timer Control RegisterE6
**
Am186TMER and Am188TMER Microcontrollers Data Sheet 47
DRAFT
Figure 9. Peripheral Control Block Register Map (Continued)
Offset
(Hexadecimal)
10
12
14
16
18
3E
40
42
70
72
74
Register Na me
ww
ww
ww
Chang ed from original Am18 6
microcontroller
44
76
78
7A
Notes: Gaps in offset addresses
indicate reserved regi sters. No
access sh ould be made to reserved
registers.
5C
5E
60
62
66
50
52
54
56
58
5A
Timer 2 Mode/Control Register
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode/Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Co unt Register
Timer 0 Mode/Control Register
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Co unt Register
3C
3A
38
36
34
32
30
2E
2C
2A
28
26
24
22
20
PIO Data 1 Regis t er
PIO Direction 1 Register
PIO Mode 0 Register
PIO Mode 1 Register
PIO Data 0 Regis t er
PIO Direction 0 Register
INT2 Control Register
INT1 Control Registe r
INT 0 Control Register
DMA 1 Interrupt Control Register
DMA 0 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-service Register
Interrupt Mask Register
Poll Status Register
Poll Register
End-of-Interrupt Register
Interrupt Vector Register
Synchronous Serial Transmit 1 Register
INT3 Control Register
Serial Port Inter rupt Co ntrol Register
Watchdog Timer Interrupt Control Register
INT4 Control Register
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
Priority Mask Register
48 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Figure 10. Clock Organization
System Clocks
The base system clock of the original Am186/Am188
microcontrollers is renamed CLKOUTA and the addi-
tional o utput i s called CLKOUTB. CLKOUTA and CL K-
OUTB operate at either the fundamental processor
frequency or the CPU clock (power-save) frequency.
Figure 10 shows the organization of the clocks.
The second clock output (CLKOUTB) allows one clock
to run at the fundamental frequency and the other clock
to run at the CPU (power-save) frequency. Individual
driv e enable bits allow selective enabling of just one, or
both, of these clock outputs.
Power-Save Operation
The Power-Save mode of the Am186ER and
Am188ER microcontrollers reduces power consump-
tion and heat dissipation, thereby extending battery life
in portable systems. In P ower-Sav e mode, operation of
the CPU and internal peripherals continues at a slower
clock frequency . When a hardware interrupt occurs, the
microcontroller automatically retur ns to its normal op-
erating frequency. The microcontroller remains in
Power-Save mode for software interrupts and traps.
Note: Power-save operation requires that clock-
dependent peripherals be reprogrammed for clock
frequency changes. Software drivers must be aware of
clock frequency.
Initialization and Processor Reset
Processor initialization or startup is accomplished by
drivi ng the RE S input pin Low. RES must be held L ow
for 1 ms during power-up to ensure proper device ini-
tialization. RES forces the Am186ER and Am188ER
microcontrollers to terminate all execution and local
bus activity. No instruction or bus activity occurs as long
as RES is active. After RES bec omes inactive and a n
internal processing interval elapses, the microcontrol-
ler begin s execution with the instr uction at physical lo-
cation FFFF0h. RES also sets some registers to
predefined values. Note that all clock selection (S6/
CLKSEL1 and UZI/CLKSEL2) must be stable four
clocks prior to the deassertion of RES. Activating the
PLL will require 1 ms to achieve a stable clock.
Reset Configuration Register
When the RES input is asserted Low, the contents of
the address/data bus (AD15–AD0) are written into the
Reset Configuration Register. The system can place
configuration information on the address/data bus
using weak external pullup or pulldown resistors, or
using an external driver that is enabled during reset.
The processor does not drive the address/data bus
during reset.
For example, the Reset Configuration Register could
be used to provide the software with the position of a
configuration switch in the system. Using weak external
pullup and pulldown resistors on the address and data
bus, the system would provide the microcontroller with
a v alue corresponding to the position of the jumper dur-
ing a reset.
The Reset Configuration Register can only be modified
during reset. This register is read-only during normal
operation.
Power-Save
Divisor1
(/1 to /128)
CBF1
Mux
CAF1
Mux
PSEN1
PLL
Mux
CLKOUTA
CLKOUTB
X1, X2
CPU Clock
Time
Delay
6 ± 2.5ns
÷2
Input Clock
CLKSEL2
CLKSEL1
CAD1
CBD1
Fundamental
Clock
1x or 4x Mux
Notes:
1. Set via PDCON Re gister
Am186TMER and Am188TMER Microcontrollers Data Sheet 49
DRAFT
CHIP-SELECT UNIT
The Am186ER and Am188ER microcontrollers contain
logic that provides programmable chip-select genera-
tion for bo th memories and periphe rals. The logic can
be programmed to provide external ready and wait-
state generation and latched address bits A1 and A2.
The chip-se lect l in es a r e active for a ll mem ory and I/O
cycles in their programmed areas, whether they are
generated by the CPU or by the integrated DMA unit.
Chip-Select Timing
The timing for the UCS and LCS outputs is modified
from the original Am186 microcontroller . These outputs
now asser t i n conjunction with the non multipl exe d ad-
dress bus for nor mal memor y timing. To enable these
outputs to be av ailable earlier in the bus cycle, the num-
ber of programmable memory size selections has been
reduced.
Ready and Wait-State Programming
The Am186ER an d Am188ER mi cro con tr oll ers can be
programmed to sense a ready signal for each of the e x-
ternal peripheral or memor y chip-select lines. The ex-
ternal ready signal can be either the ARDY or SRDY
signal as shown in Figure 11. For diagrams of the syn-
chronous ready waveforms and asynchronous ready
wa v eforms, refer to page 97. Each external chip-select
control register (UMCS, LMCS, MMCS, PACS, and
MPCS) contains a single-bit field that determines
whether the external ready signal is required or ig-
nored. The internal memory ignores the external ready
signal.
The number of wait states to be inser ted for each ac-
cess to an external peripheral or memory region is pro-
grammable. The chip-selec t control registe rs for UCS,
LCS, MCS3–MCS0, PCS6, and PCS5 contain a two-bit
field that determines the number of wait states from
zero to three to be inserted. PCS3–PCS0 use three bits
to provide additional values of 5, 7, 9, and 15 wait
states. The chip-select control register for internal
memory always specifies no wait states.
When external ready is required, internally pro-
grammed wait states will alwa ys complete before exter-
nal ready can terminate or extend a bus cycle. For
example, if the internal wait states are set to insert two
wait states, the processor samples the exter nal ready
pin during the first wait cycle. If external ready is as-
serted at that time, the access completes after six cy-
cles (four cycles plus two wait states). If external ready
is not asserted during the first wait state, the access is
extended until ready is asser ted, which is followed by
one more wait state followed by t4.
Figure 11. ARDY and SRDY Synchronization Logic Diagram
DQ
Rising Edge
DQ
Falling Edge
DQ
Falling Edge
Bus Ready
SRDY
CLKOUTA
ARDY
50 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Memory Maps
There are several possible ways to configure the ad-
dress space of the Am186ER and Am188ER microcon- trollers. Four of the most popular configurations are
shown in Figure 12.
Figure 12. Example Memory Maps
Ext ernal Flash
(UCS)
Internal RAM 0 Kbyte
32 Kbytes
512 Kbytes
1 Mbyte
512 Kbytes Flash 256 Kbytes Flash
No External RAM
External Flash
(UCS)
Internal RAM 0 Kbyte
32 Kbytes
768 Kbytes
1 Mbyte
External RAM
(MCS)
Internal RAM at 0
32 Kbytes External RAM
External Flash
(UCS)
Internal RAM 0 Kbyte
32 Kbytes
512 Kbytes
1 Mbyte
512 Kbytes Flash
256 Kbytes External RAM
256 Kbytes
External RAM
(MCS3–MCS0)
Internal RAM at 0
External Flash
(UCS)
0 Kbyte
768 Kbytes
1 Mbyte
512 Kbytes
External RAM
Internal RAM 544 Kbytes
(LCS)
256 Kbytes Flash
512 Kbytes External RAM
Internal RAM Located
Above External RAM
Shaded areas represent open memory that can be used by
other chip selects and the PCB, if located in memory.
Am186TMER and Am188TMER Microcontrollers Data Sheet 51
DRAFT
Chip-Select Ove rlap
Although programming the various chip selects on the
Am186ER microcontroller so that multiple chip select
signals are asser ted for the same physical address is
not recommended, it ma y be unav oidable in some sys-
tems. In such systems, the chip selects whose asser-
tions overlap must have the same configuration for
ready (external ready required or not required) and the
number of wait states to be inserted into the cycle by
the processor.
The peripheral control block (PCB) and the internal
memory are both accessed using internal signals.
These inte rnal s ignals functio n as chip sel ects config-
ured with zero wait states and no external ready. There-
fore, the PCB and internal memory can be
programmed to addresses that overlap external chip
select signals if those external chip selects are pro-
grammed to zero wait states with no external ready re-
quired.
When overlappin g an additional ch ip select with eith er
the LCS or UCS chip selects, it must be noted that set-
ting the Disable Address (DA) bit in the LMCS or UMCS
register will disable the address from being driven on
the AD bus for all accesses for which the associated
chip select is asserted, including any accesses for
which multiple chip selects assert.
The MCS a nd PCS chi p sele ct pins can be c onfigure d
as either chip selects (normal function) or as PIO inputs
or outputs. It sh ould be no ted; however, that the ready
and wait state generation logic for these chip selects is
in effect regardless of their configurations as chip se-
lects or PIOs. This means that if these chip selects are
enabled (by a write to the MMCS and MPCS for the
MCS chip selects, or by a write to the PACS and MPCS
registe rs for the PCS chip selects), the ready and wait
state programming for these signals must agree with
the programmi ng for any oth er ch ip se lects with whi ch
their assertion would overlap if the y were configured as
chip selects.
Although t he P C S4 signal is not available on an exter-
nal pin, the ready and wait state logic for this signal still
exists internal to the part. For this reason, the PCS4 ad-
dress space must follow t he r ul es for overlapping chi p
selects. The ready and wait-state logic for PCS6–PCS5
is disabled when these signals are configured as ad-
dress bit s A2–A 1.
Failure to configure overlapping chip selects with the
same ready and wait state requirements may cause the
processor to hang with the appearance of waiting for a
ready signal. This behavior may occur even in a system
in which ready is always asserted (ARDY or SRDY tied
High).
Configuring PCS in I/O space with LCS or any other chip
sele ct configured for memor y add ress 0 is not con sid-
ered over lapping of the chip selects. Overlapping chip
selects refers to configurations where more than one
chip select asserts for the same physical address.
Upper Memory Chip Select
The Am186ER and Am188ER microcontrollers provide
a UCS chip select for the top of memory. On reset, the
Am186ER and Am188ER microcontrollers begin fetch-
ing and ex ecuting instructions starting at memory loca-
tion FFFF0h. Therefore, upper memory is usually used
as instruction memory . To facilitate this usage, UCS de-
faults to active on reset, with a default memory range of
64 Kbyte from F0000h to FFFFFh, with external ready
required and three wait states automatically inserted.
The UCS memory range always ends at FFFFFh. The
lower boundar y is programm able. The Upp er Memor y
Chip Select is configured through the Upper Memory
Chip Select (UMCS) Register.
Duri ng t he ad dres s p has e of a bus cy cle whe n UCS is
asserted, the DA bit in the UMCS Regi ster enables or
disables the AD15–AD0 bus. If the DA bit is set to 1,
AD15–AD0 is not driven during the address phase of a
bus cycle when UCS is asserted. If DA is cleare d to 0 ,
AD15–AD0 is driven during the address phase of a bus
cycle. Disabling AD15–AD0 reduces power consump-
tion and eliminates potential bus conflicts with memory
or peripherals at high clock rates. The DA bit in the
UMCS Register defaults to 0 at power-on reset.
Low Memory Chip Select
The Am186ER and Am188ER microcontrollers provide
an LCS chip select for the bottom of memory. Because
the interrupt vector table is located at the bottom of
memor y starting at 00000h, the LCS pi n has tradition-
ally been used to control data memory. The LCS pin is
not active on res et. The Am18 6ER and Am 188ER mi-
crocontrollers also allow the IMCS Register and inter-
nal memory to be programmed to address 0. This
would allow the in ter na l memo r y to be used fo r the in-
terrupt vector table and data memory.
Midrange Memory Chip Selects
The Am186ER and Am188ER microcontrollers provide
four chip select s, MCS3–MCS0, for use in a user-locat-
able memor y block. The bas e address of the memor y
block can be located anywhere within the 1-Mbyte
memory address space, exclusive of the areas associ-
ated with the UCS and LCS chip selects, as well as the
address range of the Peripheral Chip Selects, PCS6,
PCS5, and PCS 3–PCS0, if they are mapped to mem-
or y. The M CS a ddres s range can overlap the P CS ad-
dress range if th e P CS c hi p s ele ct s ar e m app ed t o I/O
space.
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the multiplexed AD address bus.
52 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Peripheral Chi p Selec ts
The Am186ER and Am188ER microcontrollers provide
six chip selects, PCS6–PCS5 and PCS3–PCS0, for
use within a user-locatable memory or I/O b lock. PCS4
is not available on the Am186ER and Am188ER micro-
controllers. The base address of the memory bloc k can
be located anywhere within the 1-Mbyte memory ad-
dress space, e xclusive of the areas associated with the
UCS, LCS, and MCS chip se lec t s, or they can be co n-
figured to access the 64-Kbyte I/O space.
The PCS pins are not active on reset. PCS6–PCS5 can
have from zero to three wait states. PCS 3–PCS0 can
have four additional wait-state values—5, 7, 9, and 15.
Unlike the UCS and LCS chip se lects , the PCS outputs
assert with t he mul tip lexed AD add re ss bus. Note al s o
that each peripheral chip select asserts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in the 80C186
and 80C188 microcontrollers.
INTERNAL MEMORY
The Am186ER and Am188ER microcontrollers provide
32 Kbyte of on-chip RAM. The integration of memor y
helps to reduce the ov erall cost, power , and size of sys-
tem designs. The internal memory also improves reli-
ability with fewer connections and eases inventory
managemen t and system qual ification because of the
integrated suppl y.
The internal RAM for the Am186ER microcontroller is a
16K x 16-b it-wide array (32 Kbyte) whic h provides the
same performance as 16-bit external zero-wait-state
RAM. For the Am188ER microcontroller, the internal
RAM is a 32K x 8-bit-wide array (32 Kbyte) that pro-
vides the same performance as 8-bit external zero
wait-state RAM.
Interaction with External RAM
The Am186ER and Am188ER microcontrollers include
an Internal Memory Chip Select (IMCS) Register to
control the mapping of the inter nal RAM. The int ernal
address spac e c an be loc ate d at a ny 32-Kbyte boun d-
ary within the 1-Mbyte memory address space, pro-
vided that it does not ov erlap any external chip selects.
If an overlap does occur, the extern al chi p sele ct must
be set to 0 wait states and to ignore external ready. If
the internal and external chip selects overlap, both will
be active, b ut the internal memory data will be used on
reads. Wr ites, with all th e corre spond ing exter nal co n-
trol sign als, will occur to both devices. Special system
consideration must be made for show read cycles,
since those cycles will drive data out on reads.
If internal and external chip selects ov erlap and the e x-
ternal ch ip select s are no t set to 0 wait states and to ig -
nore external ready, the results are unpredictable.
Beca use of the many potential problems with overlap-
ping chip selects, this practice is not recommended.
The base address of the internal RAM is determined by
the value of bits BA19–BA15 in the IMCS Register . Be-
cause the interrupt vector table is located at 00000h, it
is not unus ual to store the in terrupt vector table in th e
internal RAM for faster access, and thus program the
IMCS Register for a base ad dress of 0. However, this
scenario may lead to a memory address overlap be-
tween the IMCS and low memor y chip select (LMCS)
registers, as the base address of the LMCS Register is
always 0 if activated.
Emulator and Debug Modes
There are two d ebug modes a ssocia ted with t he inter-
nal mem or y. One mode allows u sers t o disable th e in-
ternal RAM, and the other mode makes it possible to
drive data on the external data bus during internal RAM
read cycles.
Normal ope r ation of i nternal RAM ha s all cont rol s ign als
for reads and writes and data for writes visible externally .
Acces ses to int ernal mem ory can be detected ext ernally
by compar ing the addr ess on A19– A0 w ith the addres s
spac e of th e in t ernal mem ory.
Internal Memory Disable
When this mode is activated, the internal RAM is dis-
abled and all accesses into the internal memory space
are made externally for debugging purposes. This
mode is activated by pulling the S1/IMDIS pin Low dur-
ing reset. To use this debug mode, internal memory
space must first be activated via the IMCS Register.
Show Read Enable
When this mode is activated, the data from the internal
RAM read cycles are driven on the AD15–AD0 bus.
Note that if a byte read is bei ng shown, the unused byte
will also be driven on the AD15–AD0 bus. This mode
can be activated externally by pulling the S0/SREN pin
Low during reset or by setting the SR bit in the IMCS
Register. If this feature is activated externally using the
SREN pin, the value of the SR bit is ignored. Many em-
ulators assert the SREN pin.
During an internal memory read with show read en-
abled, the addres s will be dr i ven on the AD bus dur in g
t1 and t2. The data being read will be driven on the AD
bus during t3 and t4 by the Am186ER or Am188ER mi-
crocontrollers. Special system care must be taken to
avoid bus c ontention, becau se nor mal reads have the
AD bus three-stated during t2, t3, and t4. It is best to en-
sure that no e xte rnal de vic e ov erlaps th e internal me m-
ory space.
Am186TMER and Am188TMER Microcontrollers Data Sheet 53
DRAFT
REFRESH CONTROL UNIT
The Refr esh Cont ro l Uni t (RCU) aut oma tica lly gen er at es
refresh bus cycles. After a programmable per iod of time,
the RCU ge nerates a m emory read request to t he bus in-
terface unit. If the address generated during a refresh b us
cycle is within the range of a proper ly pr ogrammed chip
select, that chip select (with the exception of UCS and
LCS) is activ ated when the bus interface unit executes the
refresh bus cycle. The ready logic and wait states pro-
gr ammed fo r th e region are also in forc e. If no chip sele ct
is activated, then external ready is required to terminate
the refresh b us cycle .
If the HLDA pin is active when a refresh request is gen-
erated (indicating a bus hold condition), then the
Am186ER and Am188ER microcontrollers deactivate
the HLDA pin in order to perfor m a refresh cycle. The
exter nal bus master must remove the HOLD sig nal for
at least on e clock in order to allow the re fresh cy cle to
execute. The sequence of HLDA going inactive while
HOLD is being held active can be used to signal a
pending refresh request.
The Am186ER and Am188ER microcontrollers’ HOLD
latency time, the period between HOLD request and
HOLD acknowledge, is a function of the activity occur-
ring in the processor when the HOLD request is re-
ceived. A HOLD request is second only to DRAM
refresh requests in priority of activity requests received
by the processor. For example, in the case of a DMA
transfer, the HOLD latency can be as great as four bus
cycles. This occurs if a DMA word transfer operation is
taking place from an odd address to an odd address
(Am186ER microcontroller only). This is a total of 16 or
more clock cycles if wait states are required. I n addition,
if locked transfers are performed, the HOLD latency
time is increased by the lengt h of the locked transfer.
INT ERRUPT CONTROL UNIT
The Am186ER and Am188ER microcontrollers can re-
ceive interrupt requests from a variety of sources, both
internal and external. The internal interrupt controller
arranges these requests by priority and presents them
one at a time to the CPU.
There are six external interrupt sources on the
Am186ER/Am188ER microcontrollers—five maskable
int errupt pi ns and one no nm ask able int er rupt pi n. I n a d-
dition, there are six total internal interrupt sources—
three timers, two DMA channels, and the asynchronous
serial po rt—th at are no t co nnect e d t o external pin s .
The Am186ER and Am188ER microcontrollers provide
three interrupt sources not present on the Am186 and
Am188 microcontrollers. The first is an additional exter-
nal interrupt pin (INT4), which operates much like the
already existing interrupt pins (INT3–INT0). The sec-
ond is an internal maskable watchdog timer interrupt.
The third is an internal interrupt from the asynchronous
serial port.
The five maskable interrupt request pins can be used
as direct interrupt requests. Plus, INT3–INT0 can be
cascaded with an 82C59A-compatible external inter-
rupt controller if more inputs are needed. An external
interr upt controlle r can be us ed as the s ystem master
by programming the inter nal interrupt con troller to op-
erate in slave mode. In all cases, nesting can be en-
abled so that service routines for lower priority
interrupts are interrupted by a higher priority interrupt.
Programming the Interrupt Control Unit
The Am186ER and Am188ER microcontrollers provide
two methods for masking and unmasking the maskable
interrupt sources. Each interrupt source has an inter-
rupt control register (offsets 32h–44h) that contains a
mask bit specific to that interrupt. In addition, the Inter-
rupt Mas k Regi st er (o ffs et 28 h) is pr ovid ed as a si ngl e
source to access all of the mask bits. While changing a
mask bit in either the mask register or the individual
regist er will change the corres ponding mask bit in th e
other register, there is a difference in exactly how the
mask is updated.
If the Interrupt Mask Register is written while interrupts
are enabled, it is possible that an interrupt could occur
while the register is in an undefined state. This can
cause interrupts to be accepted even though they were
masked b oth befo re and a fter the write to the Inte rrup t
Mask Re gi ste r. There for e, the Inte rru pt M as k Reg ister
should only be written when interrupts are disabled.
Mask bits in the individual interrupt control registers
can be written while interrupts are enable d, and there
will be no erroneous interrupt operation.
TIMER CONTROL UNIT
There are three 16-bit programmable timers in the
Am186ER and Am188ER microcontrollers. Timer 0 and
timer 1 are connected to four external pins (each has an
input and an output). These two timers can be used to
count, time e xternal events, or generate nonrepetitiv e or
variable-duty-cycle waveforms. In addition, timer 1 can
be configured as a watchdog timer interrupt.
Note th at a h ardware watchd og timer (WDT) ha s been
added to the Am186ER and Am188ER microcontrollers.
Use of the WDT is recommended for applications requir-
ing this reset functionality. To maintain compatibility with
previous versions of the Am186ER and Am188ER mi-
crocontrollers, Timer 1 can be configured as a watchdog
timer and can generate a maskable watchdog timer in-
terrupt. The maskable watchdog timer interrupt provides
a mechanism for detecting software crashes or hang s.
The TMROUT1 output is internally connected to the
watchdog timer interrupt. The TIMER1 Count Register
must then be reloaded at intervals less than the TIMER1
max count to assure the watchdog interrupt is not taken.
54 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
If the code crashes or hangs, the TIMER1 countdown
will cause a watchdog interrupt.
Time r 2 is not conn ect ed to an y exte rnal pins . It c an be
used for real-time coding and time-delay applications.
It can also be used as a pr escale to tim ers 0 and 1, or
as a DMA request source.
The timers are controlled by eleven 16-bit registers in
the per ipheral con trol block. A timer’s time r-count re g-
ister contains the current v alue of that timer . The timer-
count register can be read or written with a value at any
time, whether the timer is running or not. The microcon-
troller i ncrements the va lue of the time r-cou nt register
each time a timer event occurs.
Each timer also has a maximum-count register that de-
fines the maximum value the timer will reach. When the
timer reaches the maximum value, it resets to 0 during
the same clock cycle—the value in the maximum-count
register is ne ver stored in the timer-count register . Also,
timers 0 and 1 h ave a secondary maximum- count reg-
ister . Using both the primary and secondary maximum-
count registers lets the timer alternate between two
maximum values.
If the timer is programmed to use only the primary max-
imum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is reached.
If the timer is programmed to use both of its maximum-
count registers, the output pin indicates which maxi-
mum-count r eg is ter is c ur rentl y in c on tro l, t her eby cre-
ating a waveform. The duty cycle of the waveform
depends on the values in the maximum-count regis-
ters.
Each timer is serviced every fourth clock cycle, so a
timer c an operate at a s peed of up to one-quar ter th e
inter nal clock frequen cy. A timer can be cl ocked exter-
nally at this same frequency; however, because of in-
ternal synchronization and pipelining of the timer
circuitr y, the timer output may take up to six clock cy-
cles to respond to the clock or gate input.
WATCHDOG TIMER
The Am186ER/Am188ER microcontrollers provide a
hardware watchdog timer . The W atchdog Timer (WDT)
can be used to regain control of the system when soft-
ware fails to respond as e xpected. The WDT is inactive
after reset. It can be modified only once by a k e y ed se-
quence of writes to the Watchdog Timer Control Regis-
ter (WDTCON) following reset. This single write can
either disable the timer or modify the timeout period
and the a ction taken upo n timeout. A keyed sequence
is also required to reset the current WDT count. This
behavior ensures that randomly ex ecuting code will not
prevent a WDT event from occurring.
The WDT supports up to a 1.34-second timeout period
in a 50-MHz system.
The WDT can be configured to cause either an NMI in-
terrupt or a system reset upon timeout. If the WDT is
configured for NMI, the NMIFLAG in the WDTCON
Register is set when the NMI is generated. The NMI in-
terrupt service routine (ISR) should examine this flag to
determine if the interrupt was generated by the WDT or
by an ex ternal sou rce. If the NM IFLAG i s set, th e ISR
should clear the flag by writing the correct keyed se-
quence to the WDTCON Register. If the NMIFLAG is
set when a second WDT timeout o ccurs, a WDT sys-
tem reset is generated rather than a second NMI e vent.
When the processor takes a WDT reset, either be-
cause of a single WDT event with the WDT configured
to generate resets or due to a WDT e vent with the NMI-
FLAG set, the RSTFLAG in the WDTCON Register is
set. This all ows sy stem initializati on code to differenti-
ate between a hardware reset and a WDT reset and
take appropriate action. The RSTFLAG is cleared
when the WDTCON Register is read or written. The
processor does not resample external pins during a
WDT reset. This means that the clocking, the Reset
Configuration Register, and any other features that are
user-selectable during reset do not change when a
WDT system reset occurs. PIO Mode and PIO Direc-
tion registers are not affected and PIO data is unde-
fined. All other activities are identical to those of a
nor m al sy s tem re se t.
Note: The Watchdog Timer (WDT) is inactive after
reset.
DIRECT MEMORY ACCESS
Direct m emory access (DMA ) permi ts transfer of dat a
between memory and peripherals without CPU involve-
ment. The DMA unit in the Am186ER and Am188ER
microcontrollers, shown in Figure 13, provides two
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., memory to I/O)
or within the same s pace (e.g., memory-to-mem or y or
I/O-to-I/O). Additionally, bytes (also words on the
Am186ER microcontroller) can be transferred to or
from even or odd addresses. Only two bus cycles (a
minimum o f eight clo cks) are neces sar y for eac h data
transfer.
Each c hannel accep ts a DMA r eques t from one of the
four sou rces: the ch annel reques t pin (DRQ1– DRQ0),
Timer 2, a serial port, or system software. The two
DMA channels can be programmed with different prior-
ities to resolve simultaneous DMA requests, and trans-
fers on one channel can interrupt the other channel.
The DMA channels can be directly connected to the
asynchronous serial port. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a data source in memory or
I/O space and a serial port transmit or receive register .
Am186TMER and Am188TMER Microcontrollers Data Sheet 55
DRAFT
DMA Operation
Each channel has six registers in the peripheral control
bloc k that define specific channel operations. The DMA
registers consist of a 20-bit source address (two regis-
ters), a 20-bit destination address (two registers), a 16-
bit transfer count register, and a 16-bit control register.
The DMA transfer count register (DTC) specifies the
number of DMA transfers to be perfor med. Up to 64K
transfers can be performed with automatic termination.
The DMA control registers define the channel opera-
tion. All registers can be modified during an y DMA ac-
tivity. Any changes made to the DMA registers are
reflected immediately in DMA operation.
The Am188ER microcontroller’s maximum DMA trans-
fer rates are half that of those listed in Table 9 for the
Am186ER microcontroller.
Table 9. Am186ER Microcontroller Maximum DMA
Transfer Rates
Asynchronous Serial Port/DMA Transfers
The enhanced Am186ER/Am188ER microcontrollers
can DMA to and from the asynchronous serial port.
This is accomplished by programming the DMA con-
troller to perform transfers between a data buffer (lo-
cated either in memory or I/O space) and an
asynchronous serial port data register (SPTD or
SPRD). Note that when a DMA channel is in use by the
asynchronous serial port, the corresponding external
DMA request signal is deactivated.
Fo r D M A
to
the a synchr onous ser ial port, the t ransmit
data register address, either I/O-mapped or memory-
mapped, s hould be spe cified as a byte desti nation for
the DMA by wr i tin g the add re ss of the r eg ister i nto th e
DMA destination low and DMA destination high regis-
ters. The destination address (the address of the trans-
mit data register) should be configured as a constant
througho ut the DM A ope ration. Th e async hronous se-
rial port transmitter acts as the synchronizing device;
therefore, the DMA channel should be configured as
destination-synchronized.
For DMA
from
the asynchronous serial port, the re-
ceive data register address, either I/O-mapped or
memory-mapped, should be specified as a byte source
for the DM A by writi ng the addres s of the register into
the DMA Source and DMA Source High registers. The
source add ress (t he ad dres s of th e re ce ive data re gis-
ter) should be configured as a constant throughout the
DMA. The asynchronous serial port receiver acts as
the syn chronizing device; th erefore, the DMA c hannel
should be configured as source- synchronized.
DMA Channel Control Registers
Each DMA control register determines the mode of op-
eration for the par ticular DMA channel. This register
specifies the following:
nMode of synchronization
nWhether bytes or words are transferred (Am186ER
microcontroller only)
nWhether an interrupt is generated after the last
transfer
nWhether DMA activity ceases after a programmed
number of DMA cycles
nRelative priority of the DMA channel with respect to
the other DMA channel
nWhether the source address is incremented, decre-
mented, or maintained constant after each transfer
nWhether the source address addresses memory or
I/O space
nWhether the destination address is incremented,
decremented, or maintained constant after trans-
fers
nWhether the destination address addresses mem-
ory or I/O space
DMA Priority
The DMA channels can be programmed so that one
channel is always gi ven priori ty over the other, o r they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles alwa ys ha v e
priority over internal CPU cycles, except between
locked memory accesses or word accesses to odd
memory locations. However , an external bus hold takes
priority over an internal DMA cycle.
Becaus e an i nte rr u pt r equ es t, oth er than an NM I, c an-
not suspend a DMA operation and the CPU cannot ac-
cess memory during a DMA cycle, interrupt latency
time suffe rs during seq uences of continuou s DMA cy-
cles. An NMI request, however, causes all internal
DMA activity to halt. This allows the CPU to respond
quickly to the NMI request.
Synchroniza tion Type Maxim um DMA
Transfer Rate (Mbyte/s)
50
MHz 40
MHz 33
MHz 25
MHz
Unsynchronized 12.5 10 8.25 6.25
Source Synch 12.5 10 8.25 6.25
Destin ati on Syn ch
(CPU needs bus) 8.33 6.6 5.5 4.16
Destin ati on Syn ch
(CPU does not need bus ) 10.00 86.6 5
56 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Figure 13. DMA Unit Block Diagram
ASYNCHRONOUS SERIAL PORT
The Am186ER and Am188ER microcontrollers provide
an asy nchrono us ser i al p or t. The a synchr onous se rial
por t is a two-pin inte rface that perm its full -duplex bidi-
rectional data transfer. The asynchronous serial port
supports the following features:
nFull-duplex operation
n7-bit or 8-bit data transfers
nOdd, even, or no parity
n1 or 2 stop bits
If additional RS-232 signals are required, they can be
created with av ailable PIO pins. The asynchronous se-
ria l port transmit an d rece ive sections a re dou ble buff-
ered. Break character, framing, parity, and overrun
error detection are provided. Exception interrupt gener-
ation is programmable by the user.
The transmit/receive clock is based on the internal pro-
cessor clock, which is divided down internally to the se-
rial port operating frequency. The serial port permits 7-
bit and 8-bit data transfers. DMA transfers using the se-
rial port are supported.
The serial port generates one interrupt for any of three
serial port events—transmit complete, data received,
and receive error.
The serial por t can be used in power-save mode, but
the software must adjust the transfer rate to correctly
reflect the new inter nal operating frequency and must
ensure that the serial por t does not receive any infor-
mation while the frequency is being changed.
DMA Transfers through the Serial Port
The DMA channels can be directly connected to the
asynchronous serial port. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a memory or I/O space and
a serial port transmit or receive register . For more infor-
mati on see the DM A cont rol r egist er des cription s in t he
Am186ER and Am188ER Microcontrollers User’s Man-
ual
, order #21684.
SYNCHRONOUS SERIAL INTERFACE
The synchronous serial interface (SSI) enables the
Am186ER and Am188ER micr ocontrollers to communi-
cate with application-specific integrated circuits (ASICs)
that require reprogrammability but are short on pins.
This fo ur-pin in terface pe rmi ts half-d uplex , bidirec tional
data transfer at speeds of up to 25 Mbit/s.
Unlike the asyn chronous serial po r t, the SSI operates
in a master/slave configuration. The Am186ER and
Am188ER microcontrollers are the master ports.
The SSI interface provides four pins for communicating
with system components: two enables (SDEN0 and
SDEN1), a clock (SCLK), and a data pin (SD ATA). Five
20-bit Adder/Subtractor
DMA
Control
Logic
Request
Selection
Logic
Adder Control
Logic
20
20
Channel Control Register 1
Channel Control Register 0
16
DRQ1/Serial Port
DRQ0/Serial Port
Timer Request
Interrupt
Request
Transfer Counter Ch. 1
Destination Address Ch. 1
Destination Address Ch. 0
Transfer Counter Ch. 0
Source Address Ch. 1
Source Address Ch. 0
Internal Address/Data Bus
Am186TMER and Am188TMER Microcontrollers Data Sheet 57
DRAFT
registers are used to control and monitor the interface.
Refer to Figure 14 and Figure 15 on page 58 for dia-
grams of SSI reads and writes.
Four-Pin Interface
The two enable pins SDEN1–SDEN0 can be used di-
rectly as enables for up to two peripheral devices.
Transmit and re ceive operations are synch ronized be-
tween the master (Am186ER or Am188ER microcon-
troller) and slave (per ipherals) by means of the SCLK
output. SCLK is derived from the internal processor
clock and is the processor clock divided by 2, 4, 8, or
16.
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186ER and Am188ER mi-
crocontrollers that are available as multipurpose sig-
nals. Table 3 and Table 4 on page 36 list the PIO pins.
Each of these pins can be used as a user-programma-
ble input or output s ignal if the no rm al sh ared fu nction
is not needed.
If a pin is enabled to fun ction as a PIO signal, the pre-
assigned signal function is disabled and does not affect
the level on the p in. A P IO s ignal ca n be co nfi gur ed t o
operate as an input (with or without a weak pullup or
pulldown), as an output, or as an open-drain output.
Configuration as an open-drain output is accomplished
by keeping the appr opr iat e PDATA b its con stant in th e
PIO data register and writing the data v alue into its as-
soc iated bi t positi on in the PI O direc tion reg ister , s o the
output is either driving Low or is disabled, depending
on the data.
After power-on reset, the PIO pins default to various
configurations. The column titled
Power-On Reset Sta-
tus
in Table 3 and Table 4 on page 36 lists the defaults
for the PIOs. The system initialization code must recon-
figure the PIOs as required.
Note: WDT reset does not reset PIO registers.
The A19–A17 address pins default to normal operation
on power-on reset, al lowi ng the processo r to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, a nd SRDY pins als o default
to normal operation on power-on reset.
Note that emulators use A 19, A18, A17 , S6, and UZI.
System designer s using these si gnals as PI Os shoul d
check with their emul ato r vendor fo r lim ita tio ns on em-
ulator operation.
If the AD15–AD0 bus override is enabled on power-on
reset, then S6/CLKSEL2 and UZI/CLKSEL1 revert to
normal operation instead of PIO input with pullup. Many
emulators assert the ADEN override. If BHE/ADEN
(Am186ER microcontroller) or RFSH2/ADEN
(Am188E R microcontrol ler) is held Low dur ing power-
on reset, the AD15–AD0 bus override is enabled.
58 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Figure 14. Synchronous Serial Interface Multiple Write
Figure 15. Synchronous Serial Interface Multiple Read
SCLK
SDEN1 or
SDEN0
SDATA
Write to SSC,
bit DE=1
Write to SSD
Poll SSS for
PB=0
Write to SSD
Poll SSS for
PB=0
Write to SSD Write to SSC, bit
DE=0
Poll SSS for
PB=0
PB=0
DR/DT=0 PB=1
DR/DT=0 PB=0
DR/DT=1 PB=1
DR/DT=0 PB=0
DR/DT=1 PB=1
DR/DT=0 PB=0
DR/DT=1 PB=0
DR/DT=0
SCLK
SDEN1 or
SDEN0
SDATA
Write to SSC,
bit DE=1
Write to SSD
Poll SSS for
PB=0
Read from SSR
(dummy)
Poll SSS for
PB=0
Read from
SSR Write to SSC,
bit DE=0
Poll SSS for
PB=0
PB=0
DR/DT=0 PB=1
DR/DT=0 PB=0
DR/DT=1 PB=1
DR/DT=0 PB=0
DR/DT=1 PB=1
DR/DT=0 PB=0
DR/DT=1 PB=0
DR/DT=0
Read from SSR
Am186TMER and Am188TMER Microcontrollers Data Sheet 59
DRAFT
LOW-VOLTAGE OPERATION
The low-voltage operation of the Am186ER and
Am188ER microcontrollers is an enabling technology
for the design of portable systems with long battery life.
This capability , combined with CPU clock management,
enables design of very low-power computing systems.
Low-Voltage Standard
Industry standards for low-voltage operation are
emerging to facilitate the design of components that
will make up a complete low-voltage system. As a
guideline, the Am186ER and Am188ER microcontrol-
ler specifications follow the first article or regulated ver-
sion of the JEDEC 8.0 low-voltage proposal. This
standard proposal calls for a VCC range of 3.3 V ± 10%.
Power Sa vings
CMOS dynamic power consumptio n is propor tional to
the square of the operating voltage multiplied by capac-
itance and operating frequency. Static CPU operation
can reduce power consumption by enabling the system
designer to reduce operating frequency when possible.
Howe ver , operating voltage is always the dominant fac-
tor in power consumption. By reducing the operating
voltage from 5 V to 3.3 V for any device, the power
consumed is reduced by 56%.
Reduction of CPU and core logic operating voltage dra-
matically reduces overall system power consumption.
Additional power savings can be realized as low-voltage
mass storage and peripheral devices become available.
Two basic strategies exist in designing systems con-
taining the Am186ER an d Am188ER m icrocontrol lers.
The first strategy is to design a homogenous system in
which al l logic comp onents op erate at 3.3 V. Thi s pro-
vides t he lowest ove rall p ower consu mption. However,
system designers may need to include devices for
which 3.3-V versions are not available. In the second
strategy, the system designer must then design a
mixed 5-V/3.3-V system. This compromise enables the
system designer to minimize the core logic power con-
sumption while still including functionality of the 5-V
feat u re s. The cho ice of a m ixed voltag e sy st em desi gn
also involves balancing design complexity with the
need for the additional features.
Input/Output Circuitry
To accommodate current 5-V systems, the Am186ER
and Am188ER microcontrollers have 5-V tolerant I/O
driv ers. The driv ers produce TTL-compatib le drive out-
put (minimum 2.4-V logic High) and receive TTL and
CMOS levels (up to VCC + 2.6 V). The following are
some design issues that should be considered when
upgrading an Am186ER microcontroller 5-V design:
nDuring power-up, if the 3.3-V supply has a signifi-
cant delay in achieving stable operation relative to
5-V supp l y, th en th e 5- V ci r c ui try in th e sys te m may
start driving the processor’s inputs above the maxi-
mum levels (VCC + 2.6 V). The system design
should en su re that the 5-V sup ply do es n ot exceed
2.6 V above the 3.3-V supply during a power-on se-
quence.
nPreferably, all inputs will be driven by sources that
can be three-stated during a system reset condition.
The sys tem re se t c ond iti on sh oul d p er sis t un til s ta-
ble VCC conditions are met. This should help ensure
that the maximum input levels are not exceeded
during power-up conditions.
nPreferably, all pullup resistors will be tied to the
3.3-V supply, which will ensure that inputs requiring
pullups are not over stressed during power-up.
60 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
ABSOLUTE MAXIMUM RATINGS
Temperature under bias:
Commercial (TC) ........................0°C to + 100°C
Storage temperature..................–65°C to + 125°C
Voltage on an y pin wit h
respect t o gr ou nd........ .. .. .... .. . .. .. ...–0.5 V to VCC + 2.6 V*
Notes:
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above th es e limits is not im pli ed. Exposure to a bso lu te m ax i-
mum ratings for extended periods may affect device reliability .
*
X1 and X2 are not 5-V -t olerant and have a range of
–0
.5 V to
V
CC
.
OPERATING RANGES
TC (Commercial)............................ 0°C to +100°C
Industrial* (TA)..............................–40°C to + 85°C
VCC up to 50 MHz .............................3.3 V ± 0.3 V
Where: TC
= case tem perature
TA = ambient temperature
Notes:
Operating Ranges define those limits between which the
functionality of the device is guaranteed.
*
Industrial versions of Am186ER and Am188ER microcon-
trollers are available in 25- and 33-MHz operating frequen-
cies only.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATIN G RA NGES
Notes:
1. This parameter is for inputs without pullup or pulldown resistors and for which 0
≤ VIN ≤ VCC.
2. This parameter is for inputs without pullup or pulldown resistors and for which 0
≤ VIN ≤ 5 V.
3. This parameter is for inputs with pulldown resistors and for which
VIH = 2.4 V.
4. This parameter is for inputs with pullup resistors and for which
VIL = 0.45 V.
5. This parameter is for three-state outputs where V
EXT
is driven on the three-state output and 0
≤
V
EXT
≤ VCC
.
6. This parameter is for three-state outputs where V
EXT
is driven on the three-state output and 0
≤
V
EXT
≤ 5 V
.
7. This parameter has not been fully tested.
8. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open
but held High or Low.
Preliminary
Symbol Parameter Description Notes Min Max Unit
VIL Input Low Voltage –0.3 0.8 V
VIH Input Hi gh Voltage 2.0 VCC + 2.6 V
VIH Clock Input High Voltage (X2, X1) VCC V
VOL Output Low Voltage IOL = 4.0 mA 0.45 V
VOH Output High Voltage IOH = –1.0 mA 2.4 V
ICC Power Supply Current Note 8 5.0 mA/
MHz
ILI Input Leakage Current Note 1
Note 2 ±15
±50 µA
IIH Input Leakage Current Note 3 200 µA
IIL Input Leakage Current Note 4 –400 µA
ILO Output Leakage Current Note 5
Note 6 ±15
±50 µA
CIN Input Capa ci tanc e FC=1 MHz (Note 7) 10 pF
COUT I/O Capacitance FC=1 MHz (Note 7) 14 pF
Am186TMER and Am188TMER Microcontrollers Data Sheet 61
DRAFT
THERMAL CHARACTERISTICS
TQFP Package
The Am186ER and Am188ER microcontrollers are
specified for operation with case temperature ranges
from 0°C to +100°C for a commercial temperature
device. Case temperature is measured at the top
center of the package as shown in Figure 16. The
various temperatures and thermal resistances can be
determined using the equations in Figure 17 with
information given in Table 10.
θJA is the sum of θJC and θCA . θJC is the internal
ther mal resista nce of the ass embly. θCA i s th e ca se t o
ambient thermal resistance.
The variable P is power in watts. Typical power
supply current (ICC) for the Am186ER and Am188ER
microcontrollers is 3.7 mA per MHz of clock frequency.
Figure 16. Thermal Resistance (°C/Watt)
Figure 17. Thermal Characteristics Equations
Table 10. Thermal Characteristics (°C/Watt)
θJA θCA
θJC
θJA = θJC + θCA
TC
Package/Board
Airflow
(Linear Feet
per Minute) θJC θCA θJA
PQFP/2-Layer
0 fpm 738 45
200 fpm 732 39
400 fpm 728 35
600 fpm 726 33
TQFP/2-Layer
0 fpm 10 46 56
200 fpm 10 36 46
400 fpm 10 30 40
600 fpm 10 28 38
PQFP/4-Layer
to 6-Layer
0 fpm 518 23
200 fpm 516 21
400 fpm 514 19
600 fpm 512 17
TQFP/4-Layer
to 6-Layer
0 fpm 624 30
200 fpm 622 28
400 fpm 620 26
600 fpm 618 24
θJA = θJC + θCA
P = ICC ⋅ freq (MHz) ⋅ VCC
TJ = TC + (P ⋅ θJC)
TJ = TA + (P ⋅ θJA)
TC = TJ – (P ⋅ θJC)
TC = TA + (P ⋅ θCA)
TA = TJ – (P ⋅ θJA)
TA = TC – (P ⋅ θCA)
62 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Typical Ambient Temperatures
The typical ambient temperature specifications are
based on the following assumptions and calculations:
The commer cial ope ratin g range of the Am186ER an d
Am188ER microcontrollers is a case temperature TC of
0 to 100 degrees Centig rade. TC is measured at the top
center of the package. An increase in the ambient
temperat ure causes a proportional increase in TC.
The 50-MH z mi croc ontro ller i s sp ecified as 3. 3 V, pl us
or minus 10%. Therefo re, 3.6 V is us ed for c alcula ting
typical power consumption on the 50-MHz
microcontroller.
Typical power supply current (ICC) in normal usage is
estimated at 3.7 mA per MHz of microcontroller clock
rate.
Typical power consumption can be calculated using the
following formula:
(Watts) = (3.7 mA/MHz) ⋅ 50 MHz ⋅ (3.6 V/1000)
Table 11 shows the variables that are used to calculate
the typical power consumption value for each version
of the Am186ER and Am188ER microcontrollers.
Table 1 1. T ypical Power Consumption Calculation
Thermal resistance is a measure of the ability of a
package to remove heat from a semiconductor device.
A safe operating range for the device can be calculated
using the following formulas from Figure 17 and the
var iables in Table 10.
By using the maximum case rating TC, the typical
power consumptio n value from Table 11, and θJC from
Table 10, the junction temperature TJ can be calculated
by using the following formula from Figure 17.
TJ = TC + (P ⋅ θJC)
Table 12 shows TJ values for the various versions of the
Am186ER and Am188ER microcontrollers. The
Speed/Pkg/Board column in Table 12 indicates the
clock speed in MHz, the ty pe of package (P for PQFP
and T for TQFP), and the type of board (2 for 2-layer
and 4–6 for 4-layer to 6-layer).
Table 12. Junction Temperature Calculation
By using TJ from Table 12, the typical power
consumption value from Table 11, and a θJA value from
Table 10, the typical ambient temperature TA can be
calculated using the following formula from Figure 17.
TA = TJ – (P ⋅ θJA)
For example, TA for a 50-MHz PQFP design with a
2-lay er board and 0 fpm airflow is calculated as follows:
TA = 104.6 – (0.662 ⋅ 45)
TA = 74.81
In this calculation, TJ comes from Table 12, P comes
from T able 11, and θJA comes from Table 10. See Table
13.
TA for a 33- M Hz TQFP de si gn wi th a 4-l aye r to 6- layer
board and 200 fpm airflow is calculated as follows:
TA = 102.6 – (0.432 ⋅ 28)
TA = 90.5
See Table 16 for the result of this calculation.
Table 13 through Table 16 and Figure 18 through
Figure 21 show TA based on the preceding
assumptions and calculations for a range of θJA values
with air flow from 0 linea r feet per mi nute to 60 0 linear
feet per minute.
P = MHz ⋅ ICC ⋅ Volts / 1000 Typical
Power (P)
in Watts
MHz Typical ICC Volts
50 3.7 3.6 0.662
40 3.7 3.6 0.522
33 3.7 3.6 0.432
25 3.7 3.6 0.342
Speed/
Pkg/
Board
TJ = TC + (P ⋅ θJC)
TJ
TCPθJC
50/P2 100 0.662 7104.6
50/T2 100 0.662 10 106.6
50/P4–6 100 0.662 5103.3
50/T4–6 100 0.662 6104.0
40/P2 100 0.522 7103.7
40/T2 100 0.522 10 105.2
40/P4–6 100 0.522 5102.6
40/T4–6 100 0.522 6103.1
33/P2 100 0.432 7103.0
33/T2 100 0.432 10 104.3
33/P4–6 100 0.432 5102.2
33/T4–6 100 0.432 6102.6
25/P2 100 0.342 7102.4
25/T2 100 0.342 10 103.4
25/P4–6 100 0.342 5101.7
25/T4–6 100 0.342 6102.1
Am186TMER and Am188TMER Microcontrollers Data Sheet 63
DRAFT
Table 13 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a
2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 18 illustrates the typical temperatures in Table 13.
Table 13. Typical Ambient Temperatures for PQFP with Two-Layer Board
Figure 18. Typical Ambient Temperatures for PQFP with Two-Layer Board
Microcontroller
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
50 MHz 0.662 74.81 78.8 81.43 82.8
40 MHz 0.522 80.2 83.3 85.4 86.5
33 MHz 0.432 83.56 86.2 87.9 88.7
25 MHz 0.342 87.0 89.1 90.4 91.1
Airflow (Linear Feet Per Minute)
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature (Degrees C)
■50 MHz
◆25 Mhz
✵33 MHz
●40 MHz
Legend:
74
78
82
86
90
94
●
●
●●
✶
✶
✶✶
◆
◆
◆◆
■
■
■
■
76
80
84
88
92
64 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a
2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 19 illustrates the typical temperatures in Table 14.
Table 14. Typical Ambient Temperatures for TQFP with Two-Layer Board
Figure 19. Typical Ambient Temperatures for TQFP with Two-Layer Board
Microcontroller
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
50 MHz 0.662 69.5 76.1 80.1 81.4
40 MHz 0.522 76.0 81.2 84.3 85.4
33 MHz 0.432 80.1 84.4 87.0 87.9
25 MHz 0.342 84.2 87.7 89.7 90.4
Airflow (Linear Feet Per Minute)
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature (Degrees C)
■50 MHz
◆25 Mhz
✵33 MHz
●40 MHz
Legend: 70
75
80
85
90
95
●
●
●●
✶
✶
✶✶
◆
◆
◆◆
■
■
■■
65
Am186TMER and Am188TMER Microcontrollers Data Sheet 65
DRAFT
Table 15 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a
4-layer to 6-layer board. The typ ical amb ient tem peratures are b ased on a 10 0-degree Ce ntigrade ma ximum cas e
temperature. Figure 20 illustrates the typical temperatures in Table 15.
Table 15. Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board
Figure 20. Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board
Microcontroller
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
50 MHz 0.662 88.0 89.4 90.7 92.0
40 MHz 0.522 90.6 91.6 92.7 93.7
33 MHz 0.432 92.3 93.1 93.9 94.9
25 MHz 0.342 93.8 94.5 95.2 95.9
Airflow (Linear Feet Per Minute)
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature (Degrees C)
■50 MHz
◆25 Mhz
✵33 MHz
●40 MHz
Legend:
87
89
91
93
95
97
●
●
●
●
✶
✶
✶
✶
◆
◆
◆
◆
■
■
■
■
88
90
92
94
96
66 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Table 16 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a
4-layer to 6-layer board. The typ ical amb ient tem peratures are b ased on a 10 0-degree Ce ntigrade ma ximum cas e
temperature. Figure 21 illustrates the typical temperatures in Table 16.
Table 16. Typical Ambient Temperatures for TQFP with Four-Layer to Six-Layer Board
Figure 21. Typical Ambient Temperatures for TQFP with Four-Layer to Six-Layer Board
Microcontroller
Speed Typical Power
(Watts)
Linear Feet per Minute Airflow
0 fpm 200 fpm 400 fpm 600 fpm
50 MHz 0.662 84.1 85.5 86.8 88.1
40 MHz 0.522 87.44 88.5 89.5 90.6
33 MHz 0.432 89.64 90.5 91.4 92.2
25 MHz 0.342 91.84 92.5 93.2 93.9
Airflow (Linear Feet Per Minute)
0 fpm 200 fpm 400 fpm 600 fpm
Typical Ambient Temperature (Degrees C)
■50 MHz
◆25 Mhz
✵33 MHz
●40 MHz
Legend:
87
89
91
93
95
97
●
●
●
●
✶
✶
✶
✶
◆
◆
◆
◆
■
■
■
■
88
90
92
94
96
86
85
84
Am186TMER and Am188TMER Microcontrollers Data Sheet 67
DRAFT
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbrev iations ar e used to indic ate the specif ic per iods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. When no bus cycle is pending, an idle (ti) state
occurs.
In the switching parameter descriptions, the
multiplexed
address is referred to as the AD address
bus; the
nonmultiplexed
address is referred to as the A
address bus.
Key to Switching Waveforms
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Ch an ge
Permitted
Will be
Steady
Will be
Changing
from H to L
Will be
Changi ng
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
Off
State
WAVEFORM INPUT OUTPUT
Invalid Invalid
68 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Alphabetical Key to Switching Parameter Symbols
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
Parameter
Symbol No. Description Parameter
Symbol No. Description
tARYCH 49 ARDY Resolution Transition Setup Time tCLDX 2Data in Hold
tARYCHL 51 ARDY Inactive Holding Time tCLEV 71 CLKOUTA Low to SDEN Valid
tARYLCL 52 ARDY Setup Time tCLHAV 62 HLDA Valid Delay
tAVBL 87 A Address Valid to WHB, WLB Low tCLRF 82 CLKOUTA High to RFSH Invalid
tAVCH 14 AD Address Valid to Clock High tCLRH 27 RD Inactive Delay
tAVLL 12 AD Address Valid to ALE Low tCLRL 25 RD Active Delay
tAVRL 66 A Address Valid to RD Low tCLSH 4Status Inactive Delay
tAVWL 65 A Address Valid to WR Low tCLSL 72 CLKOUTA Low to SCLK Low
tAZRL 24 AD Address Float to R D Active tCLSRY 48 SRDY Transition Hold Time
tCH1CH2 45 CLKOUTA Rise Time tCLTMV 55 Timer Output Delay
tCHAV 68 CLKOUTA High to A Address Valid tCOAOB 83 CLKOUTA to CLKOUTB Skew
tCHCK 38 X1 High Time tCVCTV 20 Control Active Delay 1
tCHCL 44 CLKOUTA Hig h Time tCVCTX 31 Control Inactive Delay
tCHCSV 67 CLKOUTA Hig h to LCS/UCS Valid tCVDEX 21 DEN Inactive Delay
tCHCSX 18 MCS/PCS Inactive Delay tCXCSX 17 MCS/PCS Hold from Command Inac tive
tCHCTV 22 Control Active Delay 2 tDVCL 1Data in Setup
tCHCV 64 Command Lines Valid Delay (after Float) tDVSH 75 Data Valid to SCLK High
tCHCZ 63 Command Lines Float Delay tDXDL 19 DEN Inactive to DT/R Low
tCHDX 8Status Hold Time tHVCL 58 HOLD Setup
tCHLH 9ALE Active Delay tINVCH 53 Peripheral Setup Time
tCHLL 11 ALE Inactive Delay tINVCL 54 DRQ Setup Time
tCHRFD 79 CLKOUTA High to RFSH Valid tLCRF 86 LCS Inactive to RFSH Active Delay
tCHSV 3Status Active Delay tLHAV 23 ALE High to Address Valid
tCICOA 69 X1 to CLKOUTA Skew tLHLL 10 ALE Width
tCICOB 70 X1 to CLKOUTB Skew tLLAX 13 AD Address Hold from ALE Inactive
tCKHL 39 X1 Fall Time tLOCK 61 Max imum PLL Lock Time
tCKIN 36 X1 Period tLRLL 84 LCS Precharge Pulse Width
tCKLH 40 X1 Rise Time tRESIN 57 RES Setup Time
tCL2CL1 46 CLKOUTA Fall Tim e tRFCY 85 RFSH Cycle Time
tCLARX 50 ARDY Active Hold Time tRHAV 29 RD Inactive to AD Address Active
tCLAV 5AD Address Valid Delay tRHDX 59 RD High to Data Hold on AD Bus
tCLAX 6Address Hold tRHLH 28 RD Inactive to ALE High
tCLAZ 15 AD Address Float Delay tRLRH 26 RD Puls e Wid t h
tCLCH 43 CLKOUTA Low Time tSHDX 77 SCLK High to SPI Data Hold
tCLCK 37 X1 Low Time tSLDV 78 SCLK Low to SPI Data Valid
tCLCL 42 CLKOUTA Peri od tSRYCL 47 SRDY Transition Setup Time
tCLCLX 80 LCS Inactive Delay tWHDEX 35 WR Inactive to DEN Inactive
tCLCSL 81 LCS Active Delay tWHDX 34 Data Hold after WR
tCLCSV 16 MCS/PCS Activ e Delay tWHLH 33 WR Inactive to ALE High
tCLDOX 30 Data Hold Time tWLWH 32 WR Pulse Width
tCLDV 7Data Valid Delay
Am186TMER and Am188TMER Microcontrollers Data Sheet 69
DRAFT
Numerical Key to Switching Parameter Symbols
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
Number Parameter
Symbol Description Number Parameter
Symbol Description
1 tDVCL Data in Setup 43 tCLCH CLKOUTA Low Time
2 tCLDX Data in Hold 44 tCHCL CLKOUTA High Time
3 tCHSV Status Active Delay 45 tCH1CH2 CLKOUTA Rise Time
4 tCLSH Status Inactive Delay 46 tCL2CL1 CLKOUTA Fall Time
5 tCLAV AD Addr ess Val id Delay 47 tSRYCL SRDY Transition Setup Time
6 tCLAX Address Hold 48 tCLSRY SRDY Transition Hold Time
7 tCLDV Data Valid Delay 49 tARYCH ARDY Resolution Transition Setup Time
8 tCHDX Status Hold Time 50 tCLARX ARDY Active Hold Time
9 tCHLH ALE Active Delay 51 tARYCHL ARDY Inactive Holding Time
10 tLHLL ALE Width 52 tARYLCL ARDY Setup Time
11 tCHLL ALE Inactive Delay 53 tINVCH Peripheral Setup Time
12 tAVLL AD Address Valid to ALE Low 54 tINVCL DRQ Setup Time
13 tLLAX AD Address Ho ld from ALE Inactiv e 55 tCLTMV Timer Output Delay
14 tAVCH AD Address Valid to Clock High 57 tRESIN RES Setup Time
15 tCLAZ AD Addres s Float Delay 58 tHVCL HOLD Setup
16 tCLCSV MCS/PCS Active Delay 59 tRHDX RD High to Data Hold on AD Bus
17 tCXCSX MCS/PCS Hold from Command
Inactive 61 tLOCK Maximum PLL Lock Time
18 tCHCSX MCS/PCS Inactive Delay 62 tCLHAV HLDA Valid Delay
19 tDXDL DEN Inactive to DT/R Low 63 tCHCZ Command Lines Float Delay
20 tCVCTV Control Active Delay 1 64 tCHCV Command Lines Valid Delay (after Float)
21 tCVDEX DEN Inactive Delay 65 tAVWL A Address Valid to WR Low
22 tCHCTV Control Active Delay 2 66 tAVRL A Address Valid to RD Lo w
23 tLHAV ALE High to Address Valid 67 tCHCSV CLKOUTA High to LCS/UCS Valid
24 tAZRL AD Addres s Float to RD Active 68 tCHAV CLKOUTA High to Address Valid
25 tCLRL RD Active Delay 69 tCICOA X1 to CLKOUTA Skew
26 tRLRH RD Pulse Width 70 tCICOB X1 to CLKOUTB Skew
27 tCLRH RD Inactive Delay 71 tCLEV CLKOUTA Low to SDEN Valid
28 tRHLH RD Inactive to ALE High 72 tCLSL CLKOUTA Low to SCLK Low
29 tRHAV RD Inactive to AD address Active 75 tDVSH Data Valid to SCLK High
30 tCLDOX Data Hold Time 77 tSHDX SCLK High to SPI Data Hold
31 tCVCTX Control Inactive Delay 78 tSLDV SCLK Low to SPI Data Valid
32 tWLWH WR Pulse Width 79 tCHRFD CLKOUTA High to RFSH Valid
33 tWHLH WR Inactive to ALE High 80 tCLCLX LCS Inactive Delay
34 tWHDX Data Hold after WR 81 tCLCSL LCS Active Delay
35 tWHDEX WR Inactive to DEN Inacti ve 82 tCLRF CLKOUTA High to RFSH In valid
36 tCKIN X1 Period 83 tCOAOB CLKOUTA to CLKOUTB Skew
37 tCLCK X1 Low Time 84 tLRLL LCS Precharge Pulse Width
38 tCHCK X1 High Time 85 tRFCY RFSH Cycle Time
39 tCKHL X1 Fall Time 86 tLCRF LCS Inactive to RFSH Active Delay
40 tCKLH X1 R ise Time 87 tAVBL A Address Valid to WHB, WLB Low
42 tCLCL CL KOUTA P e riod
70 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, IN TA1–INTA0, WR, WHB, and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Requirements
1 tDVCL Data in Setup 10 8ns
2 tCLDX Data in Hold(c) 3 3 ns
General Timing Responses
3 tCHSV Status Active Delay 020 015 ns
4 tCLSH Status Inac tive Delay 020 015 ns
5 tCLAV AD Address Valid Delay 020 015 ns
7 tCLDV Data Valid Delay 020 015 ns
8 tCHDX Status Hold Time 0 0 ns
9 tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inactive Delay 20 15 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns
13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL tCHCL ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
15 tCLAZ AD Address Float Delay tCLAX=0 20 tCLAX=0 15 ns
16 tCLCSV MCS/PCS Active Delay 020 015 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH tCLCH ns
18 tCHCSX MCS/PCS Inactive Delay 020 015 ns
19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns
20 tCVCTV Control Active Delay 1(b) 020 015 ns
21 tCVDEX DEN Inactive Delay 020 015 ns
22 tCHCTV Control Active Delay 2(b) 020 015 ns
23 tLHAV ALE High to Address Valid 15 10 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 020 015 ns
26 tRLRH RD Pulse Width 2tCLCL–15=65 2tCLCL–15=45 ns
27 tCLRH RD Inactive Delay 020 015 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns
29 tRHAV RD Inactive to AD Address Active(a) tCLCL–10=30 tCLCL–10=20 ns
59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns
66 tAVRL A Address Valid to RD Low 2tCLCL–15=65 2tCLCL–15=45 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid 020 015 ns
68 tCHAV CLKOUTA High to A Address Valid 020 015 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 71
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter 40 MHz 50 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Requirements
1 tDVCL Data in Setup 5 5 ns
2 tCLDX Data in Hold(c) 2 2 ns
General Timing Responses
3 tCHSV Status Active Delay 012 010 ns
4 tCLSH Status Inactive Delay 012 010 ns
5 tCLAV AD Address Valid Delay 012 010 ns
7 tCLDV Data Valid Delay 012 010 ns
8 tCHDX Status Hold Time 0 0 ns
9 tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inactive Delay 12 10 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns
13 tLLAX AD Address Hold from ALE
Inactive(a) tCHCL tCHCL ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
15 tCLAZ AD Address Float Delay tCLAX=0 12 010 ns
16 tCLCSV MCS/PCS Active Delay 012 010 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH tCLCH ns
18 tCHCSX MCS/PCS Inactive Delay 012 010 ns
19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns
20 tCVCTV Control Active Delay 1(b) 012 010 ns
21 tCVDEX DEN Inactive Delay 014 014 ns
22 tCHCTV Control Active Delay 2(b) 012 010 ns
23 tLHAV ALE High to Address Valid 7.5 5ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 010 010 ns
26 tRLRH RD Pulse Width 2tCLCL–10=40 35 ns
27 tCLRH RD Inactive Delay 012 010 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
29 tRHAV RD Inactive to AD Address
Active(a) tCLCL–5=20 15 ns
59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns
66 tAVRL A Address Valid to RD Lo w 2 • tCLCL–10=40 2 • tCLCL–10=30 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid 012 010 ns
68 tCHAV CLKOUTA High to A Address Valid 010 010 ns
72 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Read Cycl e Waveforms
CLKOUTA
t1t2t3t4
tW
S2–S0
LCS, UCS
AD15–AD0*,
AD7–AD0**
RD
MCS1–MCS0,
PCS6–PCS5,
PCS3–PCS0
Address
A19–A0
DEN
DT/R
S6
BHE*
ALE
1
2
3
4
5
7
8
9
13
14
15
16 17
18
19
20 21
2222
24
25
26 27
29
68
66
67
28
10
UZI
S6
AO15–AO8**
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
59
23
4
11
S6
Data
Status
BHE
Address
Address
12
7
Am186TMER and Am188TMER Microcontrollers Data Sheet 73
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, IN TA1–INTA0, WR, WHB, and WLB signals.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
3 tCHSV Status Active Delay 020 015 ns
4 tCLSH Status Inactive Delay 020 015 ns
5 tCLAV AD Address Valid Delay 020 015 ns
7 tCLDV Data Valid Delay 020 015 ns
8 tCHDX Status Hold Time 0 0 ns
9 tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inactive Delay 20 15 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns
13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL tCHCL ns
14 tAVCH AD Address Valid to Clock High 0 0 ns
16 tCLCSV MCS/PCS Active Delay 020 015 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH tCLCH ns
18 tCHCSX MCS/PCS Inactive Delay 020 015 ns
19 tDXDL DEN Inactive to DT/R Low (a) 0 0 ns
20 tCVCTV Control Active Delay 1(b) 020 015 ns
23 tLHAV ALE High to Address Valid 15 10 ns
Wr ite Cycle T im ing Resp onse s
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Control Inactive Delay(b) 020 015 ns
32 tWLWH WR Pulse Width 2tCLCL–10=70 2tCLCL–10=50 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=30 tCLCL–10=20 ns
35 tWHDEX WR Inactive to DEN Inacti ve(a) tCLCH–3 tCLCH–5 ns
65 tAVWL A Address Valid to WR Low tCLCL+tCHCL–3 tCLCL+tCHCL–3 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid 020 015 ns
68 tCHAV CLKOUTA High to A Address Valid 020 015 ns
87 tAVBL A Address Valid to WHB, WLB Low tCHCL–3 20 tCHCL–3 15 ns
74 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, IN TA1–INTA0, WR, WHB, and WLB signals.
Preliminary
Parameter 40 MHz 50 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
3 tCHSV Status Active Delay 012 010 ns
4 tCLSH Status Inactive Delay 012 010 ns
5 tCLAV AD Address Valid Delay 012 010 ns
7 tCLDV Data Valid Delay 012 010 ns
8 tCHDX Status Hold Time 0 0 ns
9 tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inactive Delay 12 10 ns
12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns
13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL tCHCL ns
14 tAVCH AD A ddress Valid t o Clock High 0 0 ns
16 tCLCSV MCS/PCS Active Delay 012 010 ns
17 tCXCSX MCS/PCS Hold from Command
Inactive(a) tCLCH tCLCH ns
18 tCHCSX MCS/PCS Inactive Delay 012 010 ns
19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns
20 tCVCTV Co ntrol Acti ve Delay 1(b) 012 010 ns
23 tLHAV ALE High to Address Valid 7.5 5ns
Wr ite Cycle T im ing Resp onse s
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Control Inactive Delay(b) 012 010 ns
32 tWLWH WR Pulse W idt h 2tCLCL–10=40 35 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=15 12 ns
35 tWHDEX WR Inactive to DEN Inactive(a) tCLCH tCLCH ns
65 tAVWL A Address Valid to WR Low tCLCL+tCHCL–1.25 tCLCL+tCHCL–1.25 ns
67 tCHCSV CLKOUTA High to LCS/UCS Valid 012 010 ns
68 tCHAV CLKOUTA High to A Address Valid 010 010 ns
87 tAVBL A Address Valid to WHB, WLB Low tCHCL–1.25 12 tCHCL–1.25 10 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 75
DRAFT
Write Cycle Waveforms
CLKOUTA
t1t2t3t4
tW
S2–S0Status
LCS, UCS
Address Data
AD15–AD0*,
AD7–AD0**
WR
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
Address
A19–A0
DEN
DT/R
S6 S6
ALE
WHB*, W LB
WB
BHE*BHE
34
5
7
8
9
10
11
12
13
14
16
17
18
19
67
68
65
35
31
20
30
34
32
31
33
UZI
S6
20 31
87
AO15–AO8** Address
23
4
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
7
76 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Internal RAM Show Read Cycle (25 MHz and 33 MHz)
Switching Characteristics over Commercial and Industrial Operating Ranges
Internal RAM Show Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter 25 MH z 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
5tCLAV AD Address Valid Delay 020 015 ns
7tCLDV Data Valid Delay 020 015 ns
9tCHLH ALE Active Delay 20 15 ns
11 tCHLL ALE Inactive Delay 20 15 ns
Read Cycle Timing Responses
25 tCLRL RD Active Delay 020 015 ns
27 tCLRH RD Inactive Delay 020 015 ns
68 tCHAV CLKOUTA High to A Address Valid 020 015 ns
Preliminary
Parameter 40 MHz 50 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
5tCLAV AD Address Valid Delay 012 010 ns
7tCLDV Data Valid Delay 012 010 ns
9tCHLH ALE Active Delay 12 10 ns
11 tCHLL ALE Inactive Delay 12 10 ns
Read Cycle Timing Responses
25 tCLRL RD Active Delay 010 010 ns
27 tCLRH RD Inactive Delay 012 010 ns
68 tCHAV CLKOUTA High to A Address Valid 010 010 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 77
DRAFT
Internal RAM Show Read Cycle Waveform
CLKOUTA
t1t2t3t4
AD15–AD0
RD
Address
A19–A0
ALE
Data
Address
68
7
68
5
911
25 27
5
LCS, UCS
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
78 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Requirements
1tDVCL Data in Setup 10 8ns
2tCLDX Data in Hold(b) 3 3 ns
General Timing Responses
5tCLAV AD Address Valid Delay 020 015 ns
7tCLDV Data Valid Delay 020 015 ns
8tCHDX Status Hold Time 0 0 ns
9tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inactive Delay 20 15 ns
23 tLHAV ALE High to Address Valid 15 10 ns
80 tCLCLX LCS Inactive Delay 020 015 ns
81 tCLCSL LCS Active Delay 020 015 ns
84 tLRLL LCS Pr echarge Pulse W idth tCLCL + tCLCH –3 tCLCL + tCLC H –3 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 020 015 ns
26 tRLRH RD Pulse Width 2tCLCL–15=65 2tCLCL–15=45 ns
27 tCLRH RD Inactive Delay 020 015 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns
59 tRHDX RD High to Data Hold on AD Bus(b) 0 0 ns
66 tAVRL A Address Valid to RD Low 2tCLCL–15=65 2tCLCL–15=45 ns
68 tCHAV CLK O UTA High to A A ddress Valid 020 015 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 79
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter 40 MH z 50 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Requirements
1tDVCL Data in Setup 5 5 ns
2tCLDX Data in Hold(b) 2 2 ns
General Timing Responses
5tCLAV AD Address Valid Delay 012 010 ns
7tCLDV Data Valid Delay 012 010 ns
8tCHDX Status Hold Time 0 0 ns
9tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inactive Delay 12 10 ns
23 tLHAV ALE High to Address Valid 7.5 5ns
80 tCLCLX LCS Inactive Delay 012 010 ns
81 tCLCSL LCS Activ e Delay 012 010 ns
84 tLRLL LCS Precharge Pulse Width tCLCL + tCL CH –1.25 tCLCL + tCLCH –1 ns
Read Cycle Timing Responses
24 tAZRL AD Address Float to RD Active 0 0 ns
25 tCLRL RD Active Delay 010 010 ns
26 tRLRH RD Pulse Width 2tCLCL–10=40 35 ns
27 tCLRH RD Inactive Delay 012 010 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–1.25 tCLCH–1 ns
59 tRHDX RD High to Data Hold on AD Bus(b) 0 0 ns
66 tAVRL A Address Valid to RD Low 2tCLCL–10=40 2tCLCL–10=30 ns
68 tCHAV CLKOUTA High to A Address Valid 010 010 ns
80 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
PSRAM Read Cycle Waveforms
Data
CLKOUTA
t1t2t3
tW
LCS
Address
AD15–AD0*,
AD7–AD0**
RD
Address
A19–A0
S6 S6
ALE
1
2
5
7
8
911
24
25
26
27
68
66
28
10
S6
t4
81
84
t1
Address
80
80
27
AO15–AO8** Address
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
59
23
Am186TMER and Am188TMER Microcontrollers Data Sheet 81
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, WR , WHB and WLB signals.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
5tCLAV AD Address Valid Delay 020 015 ns
7tCLDV Data Valid Delay 020 015 ns
8tCHDX Status Hold Time 0 0 ns
9tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inactive Delay 20 15 ns
23 tLHAV ALE High to Addres s Valid 15 015 ns
20 tCVCTV Co ntrol Acti ve Delay 1(b) 020 10 ns
80 tCLCLX LCS Inactiv e Delay 020 015 ns
81 tCLCSL LCS Active Delay 020 015 ns
84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –3 tCLCL + tCLCH –3
Wr ite Cycle T im ing Resp onse s
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Co ntrol Inactive Delay(b) 020 015 ns
32 tWLWH WR Pulse W idt h 2tCLCL–10=70 2tCLCL–10=50 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=30 tCLCL–10=20 ns
65 tAVWL A Address Valid to WR Low tCLCL+tCHCL–3 tCLCL+tCHCL–3 ns
68 tCHAV CLKOUTA High to A
Address Valid 020 015 ns
87 tAVBL A Address Valid to WHB , WLB
Low tCHCL–3 20 tCHCL–3 15 ns
82 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN, WR , WHB and WLB signals.
Preliminary
Parameter 40 MHz 50 MH z
No. Symbol Description Min Max Min Max Unit
General Timing Responses
5tCLAV AD Address Valid Delay 012 010 ns
7tCLDV Data Valid De lay 012 010 ns
8tCHDX Status Hold Time 0 0 ns
9tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inactive Delay 12 10 ns
20 tCVCTV Control Activ e Delay 1(b) 012 010 ns
23 tLHAV ALE High to Address Valid 7.5 5ns
80 tCLCLX LCS Inactive Delay 012 010 ns
81 tCLCSL LCS Active Delay 012 010 ns
84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –1.25 tCLCL + tCLCH –1
Wr ite Cycle T im ing Resp onse s
30 tCLDOX Data Hold Time 0 0 ns
31 tCVCTX Control Inactive Delay(b) 012 010 ns
32 tWLWH WR Pulse Width 2tCLCL–10=40 35 ns
33 tWHLH WR Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
34 tWHDX Data Hold after WR(a) tCLCL–10=15 12 ns
65 tAVWL A Address Valid to WR Lo w tCLCL+tCHCL–1.25 tCLCL+tCHCL–1.25 ns
68 tCHAV CLKOUTA High to A Address Valid 010 010 ns
87 tAVBL A Address V alid to WHB , WLB Low tCHCL–1.25 18 tCHCL–1.25 15 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 83
DRAFT
PSRA M Write Cycle Waveforms
CLKOUTA
t1t2t3t4
tW
LCS
Address Data
AD15–AD0*,
AD7–AD0**
WR
Address
A19–A0
S6 S6
ALE
WHB*, WLB*
WB**
5
7
8
9
10
11
68
65
20
30
34
32 33
t1
31
20
80
84 81
87
80
31
AO15–AO8** Address
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
23
Data
S6
84 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Refresh Cycle (25 MHz and 33 MHz)
Notes:
All timi ng paramet ers are measu red at V
CC
/2 with 50 pF loading on CLKOUTA unless ot herwise noted. All outpu t test cond itions
are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
Preliminary
Parameter 25 MH z 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
9tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inacti ve Delay 20 15 ns
Read/Write Cycle Timing Responses
25 tCLRL RD Active Delay 020 015 ns
26 tRLRH RD Pulse Width 2tCLCL–15=65 2tCLCL–15=45 ns
27 tCLRH RD Inactive Delay 020 015 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns
80 tCLCLX LCS Inactive Delay 020 015 ns
81 tCLCSL LCS Activ e Delay 020 015 ns
Refresh Ti ming Cycle Parameters
79 tCLRFD CLKOUTA Low to RFSH Valid 020 015 ns
82 tCLRF CLKOUTA High to RFSH Invalid 020 015 ns
85 tRFCY RFSH Cycle Time 6 x tCLCL 6 x tCLCL ns
86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL–3 2tCLCL –3 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 85
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Refresh Cycle (40 MHz and 50 MHz)
Notes:
All timi ng paramet ers are measu red at V
CC
/2 with 50 pF loading on CLKOUTA unless ot herwise noted. All outpu t test cond itions
are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
Preliminary
Parameter 40 MH z 50 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
9tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inacti ve Delay 12 10 ns
Read/Write Cycle Timing Responses
25 tCLRL RD Active Delay 010 010 ns
26 tRLRH RD Pulse Width 2tCLCL–10=40 35 ns
27 tCLRH RD Inactive Delay 012 010 ns
28 tRHLH RD Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns
80 tCLCLX LCS Inactive Delay 012 010 ns
81 tCLCSL LCS Activ e Delay 012 010 ns
Refresh Ti ming Cycle Parameters
79 tCLRFD CLKOUTA Low to RFSH Valid 012 010 ns
82 tCLRF CLKOUTA High to RFSH Invalid 012 010 ns
85 tRFCY RFSH Cycle Time 6 x tCLCL 6 x tCLCL ns
86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL –1.25 2tCLCL –1.25 ns
86 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
PSR AM Refresh Cycl e Waveforms
CLKOUTA
t1t2t3t4
tW *
LCS
RD
Address
A19–A0
ALE
9
25
26
27
28
10
RFSH
11
t1
79
85
82
80 81
86
*
The period t
w
is fixed at three wait states for PSRAM auto refresh only.
27
Note:
Am186TMER and Am188TMER Microcontrollers Data Sheet 87
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Interrupt Acknowledge Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the INTA1–INTA0 signals.
c This parameter applies to the DEN and DT/R signals.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Requirements
1tDVCL Data in Setup 10 8ns
2tCLDX Data in Hold 3 3 ns
General Timing Responses
3tCHSV Status Active Delay 020 015 ns
4tCLSH Status Inactive Delay 020 015 ns
7tCLDV Data Valid Delay 020 015 ns
8tCHDX Status Hold Time 0 0 ns
9tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inactive Delay 20 15 ns
12 tAVLL AD Address Invalid to ALE Low(a) tCLCH tCLCH ns
15 tCLAZ AD Address Float Delay tCLAX=0 20 tCLAX=0 15 ns
19 tDXDL DEN Inactive to DT/R Low (a) 0 0 ns
20 tCVCTV Control Active Delay 1(b) 020 015 ns
21 tCVDEX DEN Inactive Delay 020 015 ns
22 tCHCTV Control Active Delay 2(c) 020 015 ns
23 tLHAV ALE High to Address Valid 15 10 ns
31 tCVCTX Control Inactive Delay(b) 020 015 ns
68 tCHAV CLK OUTA High to A Address V alid 020 015 ns
88 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial Operating Ranges
Interrupt Acknowledge Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the INTA1–INTA0 signals.
c This parameter applies to the DEN and DT/R signals.
Preliminary
Parameter 40 MHz 50 MH z
No. Symbol Description Min Max Min Max Unit
General Timing Requirements
1tDVCL Data in Setup 5 5 ns
2tCLDX Data in Hold 2 2 ns
General Timing Responses
3tCHSV Status Active Delay 012 010 ns
4tCLSH Status Inactiv e De lay 012 010 ns
7tCLDV Data Valid De lay 012 010 ns
8tCHDX Status Hold Time 0 0 ns
9tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inactive Delay 12 12 ns
12 tAVLL AD Address Invalid to ALE Low(a) tCLCH tCLCH ns
15 tCLAZ AD Address Float Delay tCLAX=0 12 010 ns
19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns
20 tCVCTV Control Activ e Delay 1(b) 012 010 ns
21 tCVDEX DEN Inactive Delay 014 014 ns
22 tCHCTV Control Activ e Delay 2(c) 012 010 ns
23 tLHAV ALE High to Address Valid 7.5 5ns
31 tCVCTX Control Inactive Delay(b) 012 010 ns
68 tCHAV CLKOUTA High to A Address Valid 010 010 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 89
DRAFT
Interrupt Acknowledge Cycle Waveforms
CLKOUTA
t1t2t3t4
tW
S2–S0Status
ALE
AD15–AD0*,
AD7–AD0**
INTA1–INTA0
DEN
DT/R
Ptr
Address
A19–A0
S6 S6
BHE*BHE
8
12
3 4
7
9
10 11
12
15
19
20
22
22
22
68
31
(a)
(b)
(c)
(d)
S6
21
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
a The status bits become inactive in the state preceding t
4
.
b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to t
CLDX
(min).
c This parameter applies to an interrupt acknowledge cycle that follows a write cycl e.
d If followed by a write cycle, this change occurs in the state preceding that write cycle.
AO15–AO8** Address
23
4
90 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Software Halt Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN signal.
Switching Characteristics over Commercial and Industrial Operating Ranges
Software Halt Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a Testing is performed with equal loading on referenced pins.
b This parameter applies to the DEN signal.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
General Timing Responses
3tCHSV Status Active Delay 020 015 ns
4tCLSH Status Inactive Delay 020 015 ns
5tCLAV AD Address Invalid Delay 020 015 ns
9tCHLH ALE Active Delay 20 15 ns
10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns
11 tCHLL ALE Inactive Delay 20 15 ns
19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns
22 tCHCTV Co ntrol Active Delay 2(b) 020 015 ns
68 tCHAV CLK OUTA High to A Address Inv alid 020 015 ns
Preliminary
Parameter 40 MHz 50 MH z
No. Symbol Description Min Max Min Max Unit
General Timing Responses
3tCHSV Status Active Delay 012 010 ns
4tCLSH Status Inactiv e De lay 012 010 ns
5tCLAV AD Address Invalid Delay 012 010 ns
9tCHLH ALE Active Delay 12 10 ns
10 tLHLL ALE Width tCLCL–5=20 15 ns
11 tCHLL ALE Inactive Delay 12 10 ns
19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns
22 tCHCTV Control Activ e Delay 2(b) 012 010 ns
68 tCHAV CLK OUTA High to A Address In v alid 010 010 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 91
DRAFT
Software Halt Cycle Waveforms
CLKOUTA
t1t2titi
S2–S0Status
ALE
Invalid Address
S6, AD15–AD0*,
AD7–AD0**,
AO15-AO8**
DEN
DT/R
Invalid Address
A19–A0
3
4
5
9
10
11
19
22
68
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
92 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (25 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a The specifications for CLKIN are applicable to the Divide by Two and Times One mo des.
The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
Preliminary
Parameter 25 MHz
No. Symbol Description Min Max Unit
CLKIN Requirements for Times One Mode
36 tCKIN X1 Period(a) 40 60 ns
37 tCLCK X1 Low Time (1.5 V)(a) 15 ns
38 tCHCK X1 High Time (1.5 V)(a) 15 ns
39 tCKHL X1 Fall Time (3 .5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKIN Requirements for Divide by Two Mode
36 tCKIN X1 Period(a) 20 33 ns
37 tCLCK X1 Low Time (1.5 V)(a) 10 ns
38 tCHCK X1 High Time (1.5 V)(a) 10 ns
39 tCKHL X1 Fall Time (3 .5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKOUT Timing
42 tCLCL CLKOUTA Period 40 ns
43 tCLCH CL KOUTA Low Ti me (CL=50 pF) 0.5tCLCL–2=18 ns
44 tCHCL CLK O UTA High Time ( CL=50 pF) 0.5tCLCL–2=18 ns
45 tCH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V) 3ns
46 tCL2CL1 CLK OUTA F all Time (3.5 to 1.0 V) 3ns
61 tLOCK Maximum PLL Lock Time 1ms
69 tCICOA X1 to CLKOUTA Skew 20 ns
70 tCICOB X1 to CLKOUTB Skew 34 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 93
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
Preliminary
Parameter 33 MHz
No. Symbol Description Min Max Unit
CLKIN Requirements for Times Four Mode
36 tCKIN X1 Period(a) 120 125 ns
37 tCLCK X1 Low Time (1.5 V)(a) 55 ns
38 tCHCK X1 High Time (1.5 V)(a) 55 ns
39 tCKHL X1 Fa ll Time (3.5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKIN Requirements for Times One Mode
36 tCKIN X1 Period(a) 30 60 ns
37 tCLCK X1 Low Time (1.5 V)(a) 10 ns
38 tCHCK X1 High Time (1.5 V)(a) 10 ns
39 tCKHL X1 Fa ll Time (3.5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKIN Requirements for Divide by Two Mode
36 tCKIN X1 Period(a) 15 33 ns
37 tCLCK X1 Low Time (1.5 V)(a) 2.5 ns
38 tCHCK X1 High Time (1.5 V)(a) 2.5 ns
39 tCKHL X1 Fa ll Time (3.5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKOUT Timing
42 tCLCL CLKOUTA Pe riod 30 ns
43 tCLCH CLKOUTA Low Time (CL=50 pF) 0.5tCLCL–1.5=13.5 ns
44 tCHCL CLKOUTA High Time (CL=50 pF) 0.5tCLCL–1.5=13.5 ns
45 tCH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V) 3ns
46 tCL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V) 3ns
61 tLOCK Maximum PLL Lock Time 1ms
69 tCICOA X1 to CLKOUTA Skew 20 ns
70 tCICOB X1 to CLKOUTB Skew 26 ns
94 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
Preliminary
Parameter 40 MHz 50 MHz
No. Symbol Description Min Max Min Max Unit
CLKIN Requirements for Times Four Mode
36 tCKIN X1 Period(a) 100 125 80 125 ns
37 tCLCK X1 Low Time (1.5 V)(a) 45 35 ns
38 tCHCK X1 High Time (1.5 V)(a) 45 35 ns
39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5 5 ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 5 ns
CLKIN Requirements for Times One Mode
36 tCKIN X1 Period(a) 25 60
Not Supported
ns
37 tCLCK X1 Low Time (1.5 V)(a) 7.5 ns
38 tCHCK X1 High Time (1.5 V)(a) 7.5 ns
39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKIN Requirements for Divide by Two Mode
36 tCKIN X1 Period(a) 12.5 33
Not Supported
ns
37 tCLCK X1 Low Time (1.5 V)(a) 1.25 ns
38 tCHCK X1 High Time (1.5 V)(a) 1.25 ns
39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5ns
40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5ns
CLKOUT Timing
42 tCLCL CLKOUTA Pe riod 25 20 ns
43 tCLCH CLKOUTA Low Time (CL=50 pF) 0.5tCLCL–1.25=11.25 0.5tCLCL–1=9 ns
44 tCHCL CLKOUTA High Time (CL=50 pF) 0.5tCLCL–1.25=11.25 0.5tCLCL–1=9 ns
45 tCH1CH2 CLK OUTA Rise Time (1.0 to 3.5 V) 3 3 ns
46 tCL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V) 3 3 ns
61 tLOCK Maximum PLL Lock Time 1 1 ms
69 tCICOA X1 to CLKOUTA Skew 20 15 ns
70 tCICOB X1 to CLKOUTB Skew 24 21 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 95
DRAFT
Clock Waveforms—A c ti ve Mode
Clock Waveforms—Power-Save Mode
X1
X2
CLKOUTB
CLKOUTA
(Divide by one)
36 37
40 39
42 44
45
69
70
38
43
46
X1
CLKOUTA
(Divide by four)
X2
CLKOUTB **
CLKOUTB *
Notes:
*
The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 1.
** The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is cleared to 0.
96 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Ready and Peripheral Timing (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a This timing must be met to guarantee proper operation.
b This timing must be met to guarantee recognition at the clo c k edge.
Switching Characteristics over Commercial and Industrial Operating Ranges
Ready and Peripheral Timing (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a This timing must be met to guarantee proper operation.
b This timing must be met to guarantee recognition at the clo c k edge.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
Ready and Peripheral Timing Requirements
47 tSRYCL SRDY Transition Setup Time(a) 10 8ns
48 tCLSRY SRDY Transition Hold Time(a) 3 3 ns
49 tARYCH ARDY Resolution Transition Setup Time(b) 10 8ns
50 tCLARX ARDY Active Hold Time(a) 4 4 ns
51 tARYCHL ARDY Inactive Holding Time 4 4 ns
52 tARYLCL ARDY Setup Time(a) 15 10 ns
53 tINVCH Peripheral Setup Time(b) 10 8ns
54 tINVCL DRQ Setup Time(b) 10 8ns
Peripheral Timing Responses
55 tCLTMV Timer Output Delay 20 15 ns
Preliminary
Parameter 40 MH z 50 MHz
No. Symbol Description Min Max Min Max Unit
Ready and Peripheral Timing Requirements
47 tSRYCL SRDY Transition Setup Time(a) 5 5 ns
48 tCLSRY SRDY Transition Hold Time(a) 2 2 ns
49 tARYCH ARDY Resolution Transition Setup Time(b) 5 5 ns
50 tCLARX ARDY Active Hold Time(a) 3 3 ns
51 tARYCHL ARDY Inactive Holding Time 5 5 ns
52 tARYLCL ARDY Setup Time(a) 5 5 ns
53 tINVCH Peripheral Setup Time(b) 5 5 ns
54 tINVCL DRQ Setup Time(b) 5 5 ns
Peripheral Timing Responses
55 tCLTMV Timer Output Delay 12 10 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 97
DRAFT
Synchronous Ready Waveforms
Asynchronous Ready W a veforms
CLKOUTA
tWtWtWt4
SRDY (Normally Not-
Ready System)
t3tWtWt4
t2t3tWt4
t1t2t3t4
Case 21
Case 31
Case 41
47
48
Case 11
t1t2t3twCase 52t4
SRDY (Normally
Ready System)
Notes:
1. Normally not-ready sy stem.
2. Normally ready system.
CLKOUTA
tWtWtWt4
ARDY (Normally
Not-Ready System)
t3tWtWt4
t2t3tWt4
t1t2t3t4
Case 21
Case 31
Case 41
ARDY (Normally
Ready System)
49 50
49
51 50
52
Case 11
t1t2t3twCase 52t4
Notes:
1. Normally not-ready sy stem.
2. Normally ready system.
98 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Peripheral Waveforms
CLKOUTA
TMROUT1–
TMROUT0
DRQ1–DRQ0
INT4–INT0, NMI,
TMRIN1–TMRIN0
53
54
55
Am186TMER and Am188TMER Microcontrollers Data Sheet 99
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Reset and Bus Hold (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a This timing must be met to guarantee recognition at the nex t clock.
Switching Characteristics over Commercial and Industrial Operating Ranges
Reset and Bus Hold (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
a This timing must be met to guarantee recognition at the nex t clock.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
Reset and Bus Hold Timing Requirements
5tCLAV AD Address Valid Delay 020 015 ns
15 tCLAZ AD Address Floa t Delay 020 015 ns
57 tRESIN RES Setup Time 10 8ns
58 tHVCL HOLD Setup(a) 10 8ns
Reset and Bus Hold Timing Responses
62 tCLHAV HLDA Valid Delay 020 015 ns
63 tCHCZ Command Lines Float Delay 20 15 ns
64 tCHCV Command Lines Valid Delay (after Float) 20 15 ns
Preliminary
Parameter 40 MHz 50 MHz
No. Symbol Description Min Max Min Max Unit
Reset and Bus Hold Timing Requirements
5tCLAV AD Address Valid Delay 012 010 ns
15 tCLAZ AD Address Floa t Delay 012 010 ns
57 tRESIN RES Setup Time 5 5 ns
58 tHVCL HOLD Setup(a) 5 5 ns
Reset and Bus Hold Timing Responses
62 tCLHAV HLDA Valid Delay 012 010 ns
63 tCHCZ Command Lines Float Delay 12 10 ns
64 tCHCV Command Lines Valid Delay (after Float) 12 10 ns
100 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Reset Waveforms
Signals Related to Reset Waveforms
X1
RES
CLKOUTA
57 57
Note:
RES must be held Low for 1 ms duri ng pow e r -up to ensure prop er de vi ce initializat ion . Act iv atin g th e PL L w il l req ui r e 1 m s
to achieve a stable clock.
BHE/ADEN*,
RFSH2/ADEN*,
S6/CLKSEL1* **,
UZI/CLKSEL2**
S1/IMDIS*,
and S0/SREN*
RES
CLKOUTA
AD 15–AD0 (186)
AO15–AO8,
AD7–AD0 (188)
Notes:
* Becau se BHE , RFSH2, S6, UZI , S1, and S0 are not driven for 6.5 clocks after reset, their al ternate funct ions can be
asserted with external pulldown resistors.
** In Divide b y Two mode and Times One mode , S6/CLKSEL1 and UZI/CLKSEL2 must be held for 3 clock cycles after
reset negates.
***In Times Four mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 5 clock cycles after reset negates.
S6/CLKSEL1***,
UZI/CLKSEL2***
Three-State
Three-State
Divide by Two and Times One Modes
Times Four Mode Three-State
Am186TMER and Am188TMER Microcontrollers Data Sheet 101
DRAFT
Bus Hold Waveforms —Entering
Bus Hold Waveforms —Lea ving
CLKOUTA
tititi
AD15–AD0, DEN
HLDA
A19–A0, S6, RD,
WR, BHE,
DT/R, S2-S0
WHB, WLB
HOLD
t4titi
Case 2
58
62
15
63
Case 1
CLKOUTA
titit1
AD15–AD0, DEN
HLDA
A19–A0, S6, RD,
WR, BHE,
DT/R, S2–S0
WHB, WLB
HOLD
tit4t1
Case 2
ti
ti
58
62
64
5
Case 1
102 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Switching Characteristics over Commercial and Industrial Operating Ranges
Synchronous Serial Interface (SSI) (25 MHz and 33 MHz)
Note:
All timi ng parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unles s otherwis e noted. All ou tput test cond itions
are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
Switching Characteristics over Commercial and Industrial Operating Ranges
Synchronous Serial Interface (SSI) (40 MHz and 50 MHz)
Note:
All timi ng parameters are measured at V
CC
/2 with 50 pF loading on CLKOUTA, unles s otherwis e noted. All ou tput test cond itions
are with C
L
=50 pF. For switching tests, V
IL
=0.3 V and V
IH
=V
CC
–0.3 V.
Preliminary
Parameter 25 MHz 33 MHz
No. Symbol Description Min Max Min Max Unit
Synchronous Serial Port Timing Requirements
75 tDVSH Data Valid to SCLK High 10 8ns
77 tSHDX SCLK High to SPI Data Hold 3 2 ns
Synchronous Serial Port Timing Responses
71 tCLEV CLKOUTA Low to
SDEN1 or SDEN0 Valid 20 015 ns
72 tCLSL CLKOUTA Low to SCLK Low 20 015 ns
78 tSLDV SCLK Low to Data Valid 20 015 ns
Preliminary
Parameter 40 MHz 50 MHz
No. Symbol Description Min Max Min Max Unit
Synchronous Serial Port Timing Requirements
75 tDVSH Data Valid to SCLK High 5 5 ns
77 tSHDX SCLK High to SPI Data Hold 2 2 ns
Synchronous Serial Port Timing Responses
71 tCLEV CLKOUTA Low to
SDEN1 or SDEN0 Valid 012 010 ns
72 tCLSL CLKOUTA Low to SCLK Low 012 010 ns
78 tSLDV SCLK Low to Data Valid 012 010 ns
Am186TMER and Am188TMER Microcontrollers Data Sheet 103
DRAFT
Synchronous Serial Interface (SSI) Waveforms
Note:
SDATA is bidirectional an d used for either transmit (TX) or receive (RX). Timing is shown separately for each case.
CLKOUTA
SDATA (RX)
SCLK
SDEN1 or SDEN0
DATA
72
78
71
75 77
SDATA (TX) DATA
72
104 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
TQFP PHYSICAL DIMENSIONS
PQL 100, Trimmed and Formed
Thin Quad Flat Pack
1.00 REF.
1.60 MAX
11° – 13°
11° – 13°
0.50 BSC
100
1
1.35
1.45
15.80
16.20
13.80
14.20
15.80
16.20
13.80
14.20
0.17
0.27
16-038-PQT-2_AI
PQL100
9.3.96 lv
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
Am186TMER and Am188TMER Microcontrollers Data Sheet 105
DRAFT
PQFP PHYSICAL DIMENSIONS
PQR 100, Trimmed and Formed
Plastic Quad Flat Pack
Pin 100
Pin 50
Pin 30
Pin 1 I.D.
17.00
17.40
12.35
REF
13.90
14.10
18.85
REF19.90
20.1023.00
23.40
0.25
MIN
2.70
2.90 0.65 BASIC 3.35
MAX
SEATING PLANE
16-038-PQR-1_AH
PQR100
DP92
6-20-96 lv
Pin 80
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scal e; for reference only.
106 Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAFT
Am186™CC Communications Controller Data Sheet Index-1
INDEX
A
A17/PIO7, 30
A18/PIO8, 30
A19/PIO9, 30
absolute maximum ratings, 60
active mode
clock waveforms, 95
AD15–AD8, 30
AD7–AD0, 30
address bus
Am186ER
disable in effect, 42
nor m al opera tio n, 42
Am188ER
disable in effect, 43
ALE, 3 1
alphabetic PIO pin assignments, 36
ambient temperatures
ambient, 62
PQFP with four-to-six layer board, 65
PQFP with two-layer board, 63
TQFP with four-to-six layer boards, 66
TQFP with two-layer board, 64
A O15–AO8, 30
application considerations, 14
ARDY, 31
asynchronous ready waveforms, 97
asynchronous serial port, 56
B
BHE/ADEN, 31
block diagram
Am186ER, 2
Am188ER, 3
bus cycle enc odi ng , 37
bus hold waveforms
entering, 101
leaving, 101
bus interface unit , 41
bus operation, 41
byte write enables, 41
C
chip-select
low memory, 51
overlap, 51
timing, 49
unit, 49
upper memory, 51
chip-selects
midrange memory, 51
peripheral, 52
CLKOU TA, 3 1
CLKOU TB, 3 1
clock (25 MHz), 92
clock (33 MHz), 93
clock (40 and 50 MHz), 94
clock and power management, 44
clock frequencies
minimum and maximum, 44
clock generation, 14
clock organization, 48
clock source
crystal driven, 45
clock waveforms
active mode, 95
power-save mode, 95
clocking modes, 39
commercial operating ranges, 60
comparison
Am186ER and 80C186 mic roc ontr o ll ers, 15
crystal
selecting, 45
crystal-driven clock source, 45
customer support, 13
documentation and literature, 13
hotline and web, 13
literature ordering, 13
third-party development support products, 13
web home page, 13
Index-2 Am186™CC Communications Controller Data Sheet
D
DC characteristics, 60
demonstration board products, 13
DEN/PIO5, 31
description, 1
functiona l, 40
direct memory access, 54
DMA
Am186ER maximum transfer rates, 55
asynchronous serial port transfers, 55
chann el co ntrol regi ste rs, 55–56
operation, 5 5
pri or ity , 5 5–5 6
transfers through serial port, 56
unit bloc k diagram, 56
documentation
See
customer support.
DRQ1–DRQ0, 32
DT/R/PIO4, 3 2
E
emulator and debug modes, 52
internal memory disable, 52
show read enable, 52
external source clock, 45
F
features
3.3-V operation with 5-V-tolerant I/O, 14
available native development tools, applications, and
system software, 1
enhanced bus interface, 1
enhanced functionality, 1, 14
enhanced integrated peripherals, 1
enhanced performance, 14
faster access to memory and clock input modes, 1
integrated RAM, 14
memory integration, 1
software-comp ati ble, 1
x86 software compatibility, 14
four-pin interface, 57
functional description, 40
G
GND, 32
H
HLDA, 32
HOLD, 32
hotline and world wide web support, 13
I
I/O circuitry, 59
I/O space, 40
industrial operating ranges, 60
initialization and processor reset, 48
input/output circuitry, 59
INT0, 32
INT1/SELECT, 32
INT2/INTA0/PIO31, 33
INT3/INTA1/IRQ, 33
INT4/PIO30, 33
interaction with external RAM, 52
internal memory, 52
internal memory disable, 52
internal RAM show read cycle waveform, 77
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
interrupt acknowledge cycle waveforms, 89
interrupt control unit, 53
programming, 53
J
junction temperature calculation, 62
L
LCS/ONCE0, 33
literature
See
customer support.
logic diagram
ARDY and SRDY synchronization, 49
low memory chip select, 51
low-voltage operation, 57
low-voltage standard, 59
Am186™CC Communications Controller Data Sheet Index-3
M
MCS2–MCS0, 34
MCS3/RFSH/P IO25, 33
memory interface, 14
example, 15
memory maps, 50
diagram, 50
memory organization, 40
midrange memory chip selects, 51
modes
emulator and debug, 52
N
NMI, 3 4
nonmultip lexe d addr es s bus, 41
numeric PIO pin assignments, 36
O
operating ranges, 60
commercial and industrial, 60
operation
low-voltage, 57
ordering information, 4
oscill ato r con fig uration s, 4 5
output enable, 41
P
PCB, 44
reading and writing, 44
PCS0/PIO16, 34
PCS1/PIO17, 34
PCS2/PIO18, 34
PCS3/PIO19, 34
PCS3–PCS0, 34
PCS5/A1/P IO3, 34
PCS6/A2/P IO2, 34
peri phe ral ch ip se lec ts , 52
peripheral control block, 44
peripheral wa v eforms, 98
phase -locked loop, 44
pins
A19–A0, 3 0
AD15–AD8, 30
AD7–AD0, 30
ALE, 31
alphabetic PIO assignments, 36
A O15–AO8, 30
ARDY, 31
BHE/ADEN, 31
CLKOU TA, 3 1
CLKOU TB, 3 1
clocking modes, 39
DEN/PIO5, 31
descript i on s, 3 0
DRQ1–DRQ0, 32
DT/R/PIO4, 3 2
GND, 32
HLDA, 32
HOLD, 32
INT0, 32
INT1/SELECT, 32
INT2/INTA0/PIO31, 33
INT3/INTA1/IRQ, 33
INT4/PIO30, 33
LCS/ONCE0, 33
MCS2–MCS0, 34
MCS3/RFSH/PIO25, 33
NMI, 34
numeric PIO assignments, 36
PCS0/PIO16, 34
PCS1/PIO17, 34
PCS3–PCS0, 34
PCS6/A2/PIO2, 34
PIO, 57
PIO3 1–P IO0, 3 5
RD, 35
RES, 35
RFSH2/ADEN, 35
RXD/PIO28, 35
S0/SREN, 37
S1/IMDIS, 37
S2, 35
S6/CLKSEL1/PIO29, 37
SCLK/PIO20, 37
SDATA/PIO21, 37
SDEN0/PIO22, 37
SDEN1/PIO23, 37
SRDY/PIO6, 38
TMRIN0/PIO 11, 3 8
TMRIN1/PIO0, 38
TMROUT0/PIO10, 38
TMROUT1/PIO1, 38
TXD/PIO27, 38
UCS/ONCE1, 38
used by emulators, 30
UZI/CLKSEL2/P IO26, 38
VCC, 39
WB (Am188ER microcontroller only), 39
WHB, 3 9
WLB (Am186ER microcontroller only), 39
WR, 39
X1, 39
X2, 39
PIO31–PIO0, 35
plastic quad flat pack, 105
Index-4 Am186™CC Communications Controller Data Sheet
PLL, 44
power consumption calculation, 62
power savings, 59
power-save mode
clock waveforms, 95
power-save operatio n, 48
PQFP connection diagram and pinouts
Am186ER, 22
Am188ER, 25
PQFP physical dimensions, 105
PQFP pin assignments
Am186ER
sorted by pin name, 24
sorted by pin number, 23
Am188ER
sorted by pin name, 27
sorted by pin number, 26
programmable I/O (PIO) pins, 57
programming
interrupt control unit, 53
ready and wait-state, 49
pseudo static RAM
support, 44
PSRAM
support, 44
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM read cycle waveforms, 80
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM refresh cycle waveforms, 86
PSRAM write cycle
waveforms, 83
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
R
RAM
interaction with external, 52
RD, 35
read cycle waveform s, 72
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
ready and wait-state programming, 49
refresh control unit, 53
related documents, 13
RES, 35
reset
initialization and processor, 48
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
reset configuration register, 48
reset waveforms, 100
related signals, 100
revisi on hist ory, 10
RFSH2/ADEN, 35
RXD/PIO28, 35
S
S0/SREN, 37
S1/IMDIS, 37
S2, 35
S6/CLKSEL1/PIO29, 37
SCLK/PIO20, 37
SDATA/PIO21, 37
SDEN0/PIO22, 37
SDEN1/PIO23, 37
serial ports
DMA transfers, 55
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
software halt cycle waveforms, 91
source clock
external, 45
SRDY/PIO6, 38
SSI, 102
multiple read, 58
multiple write, 58
waveforms, 103
support, 13
switching characteristics
clock (25 MHz), 92
clock (33 MHz), 93
clock (40 and 50 MHz), 94
commercial, 67
industrial, 67
internal RAM show read cycle (25 and 33 MHz), 76
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
read cycle (25 and 33 MHz), 70
read cycle (40 and 50 MHz), 71
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
Am186™CC Communications Controller Data Sheet Index-5
synchronous serial interface (25 and 33 MHz), 102
synchronous serial interface (40 and 50 MHz), 102
write cycle (25 and 33 MHz), 72–73
write cycle (40 and 50 MHz), 74, 76
switching parameter symbols
alphabetical key, 68
numerical ke y, 69
switching waveforms
key, 67
synchronous ready waveforms, 97
synchronous serial interface, 56
multiple read, 58
multiple write, 58
synchronous serial interface (25 and 33 MHz), 102
synchronous serial interface (40 and 50 MHz), 102
synchronous serial interface waveforms, 103
T
thermal characteristics, 61
thermal characteristics equations, 61
thermal resistance, 61
thin quad flat pack, 104
third-party dev elopment support products, 13
timer control unit, 53
TMRIN0/PIO11, 3 8
TMRIN1/PIO0, 38
TMROUT0/PIO10, 38
TMROUT1/PIO1, 38
TQFP connection diagram and pinouts
Am186ER, 16
Am188ER, 19
TQFP package, 61
TQFP physical dimensions, 104
TQFP pin assignments
Am186ER, 19
sorted by pin name, 18
sorted by pin number, 17
Am188ER
sorted by pin name, 21
sorted by pin number, 20
two-component address, 40
TXD/PIO27, 38
typical ambient temperatures, 62
U
UCS/ONCE1, 38
upper memory chip select, 51
UZI/CLKSEL2/PIO26, 38
V
VCC, 39
W
watchdog timer, 54
waveform
internal RAM show read, 77
waveforms, 67
asynchronous ready, 97
bus hold
entering, 101
leaving, 1 01
interrupt acknowledge cycle, 89
peripheral, 98
PSRAM read cycle, 80
PSRAM refresh cycle, 86
PSRAM write cycle, 83
read cycle, 72
reset, 100
signals related to reset, 100
software halt cycle, 91
SSI, 103
synchronous ready, 97
synchron ous ser i al int erf ace, 103
write cycle, 75
WB (Am188ER microcontroller only), 39
WHB, 3 9
WLB (Am186ER microcontroller only), 39
world wide web support, 13
WR, 39
write cycle waveforms, 75
www
home page, 13
support, 13
X
X1, 39
X2, 39
Am186™CC Communications Controller Data Sheet
Trademarks
2006 Advanced Micro Devices, Inc. All rights reser ved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386, Am5x86, and Am486 are registered trademarks, and Am186, Am188, E86, Élan, and AMD-K6 are trademarks of Advanced Micro
Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and ma y be tr ademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection wit h Advanced Micro De vices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to speci-
fications and product descriptions at any time without notice. No licens e, whether express, implied, arising by estoppel or otherwise, to any in-
tellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
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AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
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situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue o r ma k e
changes to its products at any time without notice.
© 2006 Advanced Micro De vices, Inc.
All rights reserved.
