TL431, A, B Series, NCV431A, B Programmable Precision References The TL431, A, B integrated circuits are three-terminal programmable shunt regulator diodes. These monolithic IC voltage references operate as a low temperature coefficient zener which is programmable from Vref to 36 V with two external resistors. These devices exhibit a wide operating current range of 1.0 mA to 100 mA with a typical dynamic impedance of 0.22 W. The characteristics of these references make them excellent replacements for zener diodes in many applications such as digital voltmeters, power supplies, and op amp circuitry. The 2.5 V reference makes it convenient to obtain a stable reference from 5.0 V logic supplies, and since the TL431, A, B operates as a shunt regulator, it can be used as either a positive or negative voltage reference. Features * * * * * * * * http://onsemi.com TO-92 (TO-226) LP SUFFIX CASE 29 1 2 Pin 1. Reference 2. Anode 3. Cathode 3 PDIP-8 P SUFFIX CASE 626 8 Programmable Output Voltage to 36 V Voltage Reference Tolerance: 0.4%, Typ @ 25C (TL431B) Low Dynamic Output Impedance, 0.22 W Typical Sink Current Capability of 1.0 mA to 100 mA Equivalent Full-Range Temperature Coefficient of 50 ppm/C Typical Temperature Compensated for Operation over Full Rated Operating Temperature Range Low Output Noise Voltage These are Pb-Free and Halide-Free Devices 1 Micro8E DM SUFFIX CASE 846A 8 1 Cathode 1 8 Reference N/C 2 7 N/C N/C 3 6 Anode N/C 4 5 N/C (Top View) SOIC-8 D SUFFIX CASE 751 8 1 Cathode 1 8 2 7 3 6 N/C 4 5 Anode Reference Anode N/C (Top View) This is an internally modified SOIC-8 package. Pins 2, 3, 6 and 7 are electrically common to the die attach flag. This internal lead frame modification increases power dissipation capability when appropriately mounted on a printed circuit board. This modified package conforms to all external dimensions of the standard SOIC-8 package. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 14 of this data sheet. (c) Semiconductor Components Industries, LLC, 2012 April, 2012 - Rev. 34 1 Publication Order Number: TL431/D TL431, A, B Series, NCV431A, B Symbol Representative Schematic Diagram Component values are nominal Cathode (K) Cathode (K) Reference (R) 800 800 Reference (R) Anode (A) 20 pF Representative Block Diagram Reference (R) 4.0 k 20 pF Cathode (K) + 150 3.28 k 2.4 k 10 k 7.2 k 1.0 k 2.5 Vref 800 Anode (A) Anode (A) This device contains 12 active transistors. MAXIMUM RATINGS (Full operating ambient temperature range applies, unless otherwise noted.) Symbol Value Unit VKA 37 V Cathode Current Range, Continuous IK -100 to +150 mA Reference Input Current Range, Continuous Iref -0.05 to +10 mA Operating Junction Temperature TJ 150 C Operating Ambient Temperature Range TL431I, TL431AI, TL431BI TL431C, TL431AC, TL431BC NCV431AI, NCV431B, TL431BV TA Storage Temperature Range Tstg Total Power Dissipation @ TA = 25C Derate above 25C Ambient Temperature D, LP Suffix Plastic Package P Suffix Plastic Package DM Suffix Plastic Package PD Total Power Dissipation @ TC = 25C Derate above 25C Case Temperature D, LP Suffix Plastic Package P Suffix Plastic Package PD Rating Cathode to Anode Voltage C -40 to +85 0 to +70 -40 to +125 -65 to +150 C W 0.70 1.10 0.52 W 1.5 3.0 ESD Rating HBM MM >2000 >200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Condition Cathode to Anode Voltage Cathode Current Symbol Min Max Unit VKA Vref 36 V IK 1.0 100 mA THERMAL CHARACTERISTICS Symbol D, LP Suffix Package P Suffix Package DM Suffix Package Unit Thermal Resistance, Junction-to-Ambient RqJA 178 114 240 C/W Thermal Resistance, Junction-to-Case RqJC 83 41 - C/W Characteristic http://onsemi.com 2 TL431, A, B Series, NCV431A, B ELECTRICAL CHARACTERISTICS (TA = 25C, unless otherwise noted.) TL431I Min Symbol Characteristic Reference Input Voltage (Figure 1) VKA = Vref, IK = 10 mA TA = 25C TA = Tlow to Thigh (Note 1) TL431C Typ Max Min Typ Max Vref Reference Input Voltage Deviation Over Temperature Range (Figure 1, Notes 1, 2) VKA= Vref, IK = 10 mA V 2.44 2.41 2.495 - 2.55 2.58 2.44 2.423 2.495 - 2.55 2.567 - 7.0 30 - 3.0 17 DVref Ratio of Change in Reference Input Voltage to Change in Cathode to Anode Voltage IK = 10 mA (Figure 2), DVKA = 10 V to Vref DVKA = 36 V to 10 V DV DV Reference Input Current (Figure 2) IK = 10 mA, R1 = 10 k, R2 = TA = 25C TA = Tlow to Thigh (Note 1) Unit mV mV/V ref KA - - -1.4 -1.0 -2.7 -2.0 - - -1.4 -1.0 -2.7 -2.0 Iref mA - - 1.8 - 4.0 6.5 - - 1.8 - 4.0 5.2 Reference Input Current Deviation Over Temperature Range (Figure 2, Note 1, 4) IK = 10 mA, R1 = 10 k, R2 = DIref - 0.8 2.5 - 0.4 1.2 mA Minimum Cathode Current For Regulation VKA = Vref (Figure 1) Imin - 0.5 1.0 - 0.5 1.0 mA Off-State Cathode Current (Figure 3) VKA = 36 V, Vref = 0 V Ioff - 20 1000 - 20 1000 nA |ZKA| - 0.22 0.5 - 0.22 0.5 W Dynamic Impedance (Figure 1, Note 3) VKA = Vref, DIK = 1.0 mA to 100 mA f 1.0 kHz 1. Tlow = -40C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431AIDM, TL431IDM, TL431BIDM; = 0C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM 2. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. Vref max DVref = Vref max -Vref min DTA = T2 - T1 Vref min T1 Ambient Temperature T2 The average temperature coefficient of the reference input voltage, aVref is defined as: ppm V + ref _C DV V ref ref @ 25_C DT A X 106 + D V x 10 6 ref D T (V @ 25_C) A ref aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : DV V ref + 8.0 mV and slope is positive, @ 25_C + 2.495 V, DT + 70_C ref A aV ref + 0.008 x 106 + 45.8 ppm_C 70 (2.495) DV KA 3. The dynamic impedance ZKA is defined as: |Z KA| + . When the device is programmed with two external resistors, R1 and R2, DI K (refer to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KA| [ |Z KA| 1 ) R1 R2 http://onsemi.com 3 TL431, A, B Series, NCV431A, B ELECTRICAL CHARACTERISTICS (TA = 25C, unless otherwise noted.) TL431AI / NCV431AI Characteristic Symbol Reference Input Voltage (Figure 1) VKA = Vref, IK = 10 mA TA = 25C TA = Tlow to Thigh Min Typ Max TL431BC / TL431BI / TL431BV / NCV431BV TL431AC Min Typ Max Min Typ Max Unit Vref Reference Input Voltage Deviation Over Temperature Range (Figure 1, Notes 4, 5) VKA= Vref, IK = 10 mA DVref Ratio of Change in Reference Input Voltage to Change in Cathode to Anode Voltage IK = 10 mA (Figure 2), DVKA = 10 V to Vref DVKA = 36 V to 10 V DV DV Reference Input Current (Figure 2) IK = 10 mA, R1 = 10 k, R2 = TA = 25C TA = Tlow to Thigh (Note 4) V 2.47 2.44 2.495 - 2.52 2.55 2.47 2.453 2.495 - 2.52 2.537 2.485 2.475 2.495 2.495 2.505 2.515 - 7.0 30 - 3.0 17 - 3.0 17 mV/V ref KA mV - - -1.4 -1.0 -2.7 -2.0 - - -1.4 -1.0 -2.7 -2.0 - - -1.4 -1.0 -2.7 -2.0 Iref mA - - 1.8 - 4.0 6.5 - - 1.8 - 4.0 5.2 - - 1.1 - 2.0 4.0 Reference Input Current Deviation Over Temperature Range (Figure 2, Note 4) IK = 10 mA, R1 = 10 k, R2 = DIref - 0.8 2.5 - 0.4 1.2 - 0.8 2.5 mA Minimum Cathode Current For Regulation VKA = Vref (Figure 1) Imin - 0.5 1.0 - 0.5 1.0 - 0.5 1.0 mA Off-State Cathode Current (Figure 3) VKA = 36 V, Vref = 0 V Ioff - 20 1000 - 20 1000 - 0.23 500 nA |ZKA| - 0.22 0.5 - 0.22 0.5 - 0.14 0.3 W Dynamic Impedance (Figure 1, Note 6) VKA = Vref, DIK = 1.0 mA to 100 mA f 1.0 kHz 4. Tlow = -40C for TL431AIP TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431BV, TL431AIDM, TL431IDM, TL431BIDM, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDR2G = 0C for TL431ACP, TL431ACLP, TL431CP, TL431CLP, TL431CD, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM Thigh = +85C for TL431AIP, TL431AILP, TL431IP, TL431ILP, TL431BID, TL431BIP, TL431BILP, TL431IDM, TL431AIDM, TL431BIDM = +70C for TL431ACP, TL431ACLP, TL431CP, TL431ACD, TL431BCD, TL431BCP, TL431BCLP, TL431CDM, TL431ACDM, TL431BCDM = +125C TL431BV, NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G 5. The deviation parameter DVref is defined as the difference between the maximum and minimum values obtained over the full operating ambient temperature range that applies. Vref max DVref = Vref max -Vref min DTA = T2 - T1 Vref min T1 Ambient Temperature T2 The average temperature coefficient of the reference input voltage, aVref is defined as: ppm V + ref _C DV V ref ref @ 25_C DT A X 106 + x 10 6 ref D T (V @ 25_C) A ref DV aVref can be positive or negative depending on whether Vref Min or Vref Max occurs at the lower ambient temperature. (Refer to Figure 6.) Example : DV V ref + 8.0 mV and slope is positive, @ 25_C + 2.495 V, DT + 70_C ref A aV ref + 0.008 x 106 + 45.8 ppm_C 70 (2.495) DV KA 6. The dynamic impedance ZKA is defined as |Z KA| + When the device is programmed with two external resistors, R1 and R2, (refer DI K to Figure 2) the total dynamic impedance of the circuit is defined as: |Z KA| [ |Z KA| 1 ) R1 R2 7. NCV431AIDMR2G, NCV431AIDR2G, NCV431BVDMR2G, NCV431BVDR2G Tlow = -40C, Thigh = +125C. Guaranteed by design. NCV prefix is for automotive and other applications requiring unique site and control change requirements. http://onsemi.com 4 TL431, A, B Series, NCV431A, B Input Input VKA IK VKA Iref R1 Vref Input Ioff IK R2 V KA +V VKA 1 ) R1 ) I SR1 ref R2 ref Vref Figure 1. Test Circuit for VKA = Vref Figure 2. Test Circuit for VKA > Vref 800 VKA = Vref TA = 25C 100 Input IK IK , CATHODE CURRENT ( A) IK , CATHODE CURRENT (mA) 150 Figure 3. Test Circuit for Ioff VKA 50 0 -50 -100 -2.0 -1.0 0 1.0 2.0 VKA = Vref TA = 25C 600 Input 400 200 0 -200 -1.0 3.0 0 Vref , REFERENCE INPUT VOLTAGE (mV) VKA IK VKA = Vref IK = 10 mA Input 2560 Vref Vref Max = 2550 mV 2540 2520 Vref Typ = 2495 mV 2500 2480 2460 2440 Vref Min = 2440 mV 2420 2400 -55 -25 0 25 50 2.0 3.0 Figure 5. Cathode Current versus Cathode Voltage Iref , REFERENCE INPUT CURRENT ( A) Figure 4. Cathode Current versus Cathode Voltage 2580 1.0 VKA, CATHODE VOLTAGE (V) VKA, CATHODE VOLTAGE (V) 2600 IMin VKA IK 75 100 125 3.0 2.5 2.0 1.5 IK = 10 mA 1.0 VKA Input 10k Iref IK 0.5 0 -55 -25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C) TA, AMBIENT TEMPERATURE (C) Figure 6. Reference Input Voltage versus Ambient Temperature Figure 7. Reference Input Current versus Ambient Temperature http://onsemi.com 5 125 0 IK = 10 mA TA = 25C -8.0 -16 Input VKA IK R1 -24 -32 R2 Vref 0 10 30 20 1.0 k Ioff , OFF-STATE CATHODE CURRENT (nA) Vref , REFERENCE INPUT VOLTAGE (mV) TL431, A, B Series, NCV431A, B 100 10 1.0 Input 0.01 -55 40 -25 + GND 1.0 0.1 1.0 k 10 k 100 k 1.0 M 0.280 0.260 75 100 125 0.240 0.220 0.200 -55 10 M -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) Figure 10. Dynamic Impedance versus Frequency Figure 11. Dynamic Impedance versus Ambient Temperature 80 60 50 9.0 mF 40 Output IK 15k 230 NOISE VOLTAGE (nV/ Hz) A VOL, OPEN LOOP VOLTAGE GAIN (dB) 50 VKA = Vref D IK = 1.0 mA to 100 mA f 1.0 kHz Output 1.0k IK 50 + GND 0.300 f, FREQUENCY (MHz) 8.25k GND 30 20 10 25 0.320 TA = 25C D IK = 1.0 mA to 100 mA |ZKA|, DYNAMIC IMPEDANCE ( ) |ZKA|, DYNAMIC IMPEDANCE ( ) 10 0 Figure 9. Off-State Cathode Current versus Ambient Temperature 100 50 VKA TA, AMBIENT TEMPERATURE (5C) Figure 8. Change in Reference Input Voltage versus Cathode Voltage Output IK Ioff 0.1 VKA, CATHODE VOLTAGE (V) 1.0 k VKA = 36 V Vref = 0 V IK = 10 mA TA = 25C 60 VKA = Vref IK = 10 mA TA = 25C 40 Input 20 Output IK 0 -10 1.0 k 10 k 100 k 1.0 M 0 10 10 M 100 1.0 k 10 k f, FREQUENCY (Hz) f, FREQUENCY (MHz) Figure 12. Open-Loop Voltage Gain versus Frequency Figure 13. Spectral Noise Density http://onsemi.com 6 100 k TL431, A, B Series, NCV431A, B Input Monitor Output 2.0 220 Output Pulse Generator f = 100 kHz 1.0 50 GND 0 5.0 Input 0 0 4.0 12 8.0 16 Unstable Area A B C D 120 I K, CATHODE CURRENT (mA) VOLTAGE SWING (V) 140 TA = 25C 3.0 100 TA = 25C C 80 60 Stable 40 Stable D B B A 20 0 1.0 nF 20 Programmed VKA(V) Vref 5.0 10 15 10 nF t, TIME (ms) A 100 nF 1.0 mF 10 mF 100 mF CL, LOAD CAPACITANCE Figure 14. Pulse Response Figure 15. Stability Boundary Conditions 150 150 IK IK V+ 10 k V+ CL Figure 16. Test Circuit For Curve A of Stability Boundary Conditions CL Figure 17. Test Circuit For Curves B, C, And D of Stability Boundary Conditions TYPICAL APPLICATIONS V+ V+ Vout Vout R1 R1 R2 R2 V out + 1 ) R1 V R2 ref V out + 1 ) R1 V R2 ref Figure 18. Shunt Regulator Figure 19. High Current Shunt Regulator http://onsemi.com 7 TL431, A, B Series, NCV431A, B V+ V+ MC7805 Out In Common Vout R1 Vout R1 R2 R2 V out(min) +V ref V ) 5.0V Figure 20. Output Control for a Three-Terminal Fixed Regulator RCL V+ V out + 1 ) R1 V R2 ref V out + 1 ) R1 V R2 ref in(min) + V out ) V V +V out(min) be ref Figure 21. Series Pass Regulator V+ Iout Isink I V I out + ref R CL Sink V + ref R S RS Figure 22. Constant Current Source V+ Figure 23. Constant Current Sink V+ Vout Vout R1 R1 R2 R2 V + 1 ) R1 V out(trip) R2 ref V Figure 24. TRIAC Crowbar out(trip) + 1 ) R1 V R2 ref Figure 25. SRC Crowbar http://onsemi.com 8 TL431, A, B Series, NCV431A, B V+ Vout l R1 V+ R3 Vout Vin R2 R4 Vin Vth = Vref L.E.D. indicator is on' when V+ is between the upper and lower limits. UpperLimit + 1 ) R3V R4 ref LowerLimit + 1 ) R1 V R2 ref Figure 26. Voltage Monitor 5.0 k 1% 50 k 1% 10 kW V 500 k 1% 5.0 M 1% 100 kW 1.0 MW V V Range 1.0 kW V RX V+ > Vref 2.0 V Figure 27. Single-Supply Comparator with Temperature-Compensated Threshold 25 V 1N5305 Vout < Vref 38 V 2.0 mA TI 10 k Calibrate 25 V LM11 + 330 Tl = 330 to 8.0 W 8.0 W + 470 mF 360 k 1.0 mF * Vout * Thermalloy * THM 6024 * Heatsink on * LP Package -5.0 V W R x + V outD Range V Figure 28. Linear Ohmmeter 56 k 10 k 0.05 mF Tone 25 k Volume 47 k Figure 29. Simple 400 mW Phono Amplifier http://onsemi.com 9 TL431, A, B Series, NCV431A, B 150 mH @ 2.0 A Vin = 10 V to 20 V TIP115 Vout = 5.0 V Iout = 1.0 A 1.0 k 4.7 k + 4.7 k MPSA20 2200 mF 1N5823 100 k 0.01mF 470 mF 4.7 k 0.1 mF 2.2 k 10 51 k Figure 30. High Efficiency Step-Down Switching Converter Test Conditions Results Line Regulation Vin = 10 V to 20 V, Io = 1.0 A 53 mV (1.1%) Load Regulation Vin = 15 V, Io = 0 A to 1.0 A 25 mV (0.5%) Output Ripple Vin = 10 V, Io = 1.0 A 50 mVpp P.A.R.D. Output Ripple Vin = 20 V, Io = 1.0 A 100 mVpp P.A.R.D. Efficiency Vin = 15 V, Io = 1.0 A 82% http://onsemi.com 10 + TL431, A, B Series, NCV431A, B APPLICATIONS INFORMATION The TL431 is a programmable precision reference which is used in a variety of ways. It serves as a reference voltage in circuits where a non-standard reference voltage is needed. Other uses include feedback control for driving an optocoupler in power supplies, voltage monitor, constant current source, constant current sink and series pass regulator. In each of these applications, it is critical to maintain stability of the device at various operating currents and load capacitances. In some cases the circuit designer can estimate the stabilization capacitance from the stability boundary conditions curve provided in Figure 15. However, these typical curves only provide stability information at specific cathode voltages and at a specific load condition. Additional information is needed to determine the capacitance needed to optimize phase margin or allow for process variation. A simplified model of the TL431 is shown in Figure 31. When tested for stability boundaries, the load resistance is 150 W. The model reference input consists of an input transistor and a dc emitter resistance connected to the device anode. A dependent current source, Gm, develops a current whose amplitude is determined by the difference between the 1.78 V internal reference voltage source and the input transistor emitter voltage. A portion of Gm flows through compensation capacitance, CP2. The voltage across CP2 drives the output dependent current source, Go, which is connected across the device cathode and anode. P2 + Z1 + Example 1: C P1 + G+G R GoR M GM L I + 10 mA, R + 230 W, C + 0. Define the transfer gain. L L C The DC gain is: G+G R GoR + M GM L (2.138)(1.0 M)(1.25 m)(230) + 615 + 56 dB Loop gain + G 8.25 k + 218 + 47 dB 8.25 k ) 15 k The resulting transfer function Bode plot is shown in Figure 32. The asymptotic plot may be expressed as the following equation: 1 ) 500jfkHz Av + 615 1 ) 8.0jfkHz1 ) 60 jfkHz Resistor and capacitor typical values are shown on the model. Process tolerances are 20% for resistors, 10% for capacitors, and 40% for transconductances. An examination of the device model reveals the location of circuit poles and zeroes: 1 1 1 + + 500 kHz 2p * 15.9 k * 20 pF C Z1 P1 Also, the transfer dc voltage gain of the TL431 is: Go = 1.25 (Vcp2) mmhos. GM 2p R 1 P + L 2p R C L L where IC is the device cathode current and Gm is in mhos 2p R 1 1 + + 60 kHz 2p * 10 M * 0.265 pF C P2 P2 In addition, there is an external circuit pole defined by the load: Model component values are: Vref = 1.78 V Gm = 0.3 + 2.7 exp (-IC/26 mA) P1 + 2p R The Bode plot shows a unity gain crossover frequency of approximately 600 kHz. The phase margin, calculated from the equation, would be 55.9 degrees. This model matches the Open-Loop Bode Plot of Figure 12. The total loop would have a unity gain frequency of about 300 kHz with a phase margin of about 44 degrees. 1 + 7.96 kHz 2p * 1.0 M * 20 pF http://onsemi.com 11 TL431, A, B Series, NCV431A, B VCC RL CL Input 3 15 k Cathode 9.0 mF Ref RP2 10 M Vref 1.78 V 1 500 k CP1 20 pF GM + - Rref RGM 1.0 M 16 RZ1 15.9 k 8.25 k Anode Go 1.0 mmho CP2 0.265 pF 2 Figure 31. Simplified TL431 Device Model Note that the transfer function now has an extra pole formed by the load capacitance and load resistance. Note that the crossover frequency in this case is about 250 kHz, having a phase margin of about -46 degrees. Therefore, instability of this circuit is likely. TL431 OPEN-LOOP VOLTAGE GAIN VERSUS FREQUENCY 50 40 30 TL431 OPEN-LOOP BODE PLOT WITH LOAD CAP 20 80 10 Av, OPEN-LOOP GAIN (dB) Av, OPEN-LOOP VOLTAGE GAIN (dB) 60 0 -10 -20 101 102 103 104 105 106 107 f, FREQUENCY (Hz) Figure 32. Example 1 Circuit Open Loop Gain Plot Example 2. IC = 7.5 mA, RL = 2.2 kW, CL = 0.01 mF. Cathode tied to reference input pin. An examination of the data sheet stability boundary curve (Figure 15) shows that this value of load capacitance and cathode current is on the boundary. Define the transfer gain. The DC gain is: 60 40 20 0 -20 101 102 103 104 105 106 f, FREQUENCY (Hz) Figure 33. Example 2 Circuit Open Loop Gain Plot With three poles, this system is unstable. The only hope for stabilizing this circuit is to add a zero. However, that can only be done by adding a series resistance to the output capacitance, which will reduce its effectiveness as a noise filter. Therefore, practically, in reference voltage applications, the best solution appears to be to use a smaller value of capacitance in low noise applications or a very large value to provide noise filtering and a dominant pole rolloff of the system. G+G R GoR + M GM L (2.323)(1.0 M)(1.25 m)(2200) + 6389 + 76 dB The resulting open loop Bode plot is shown in Figure 33. The asymptotic plot may be expressed as the following equation: 1 ) 500jfkHz Av + 615 1 ) 8.0jfkHz1 ) 60 jfkHz1 ) 7.2jfkHz http://onsemi.com 12 TL431, A, B Series, NCV431A, B ORDERING INFORMATION Device Marking Code TL431ACDG AC TL431BCDG BC TL431CDG AC TL431BCDR2G BC C TL431ACDMR2G TAC TL431BCDMR2G TBC TL431CDMR2G T-C TL431ACPG ACP TL431BCPG BCP TL431CPG CP TL431ACLPG ACLP TL431BCLPG BCLP TL431CLPG Package Code C TL431ACDR2G TL431CDR2G Operating Temperature Range 0C to 70C CLP Shipping Information Tolerance 1.0% SOIC-8 (Pb-Free) 98 Units / Rail SOIC-8 (Pb-Free) 2500 Units / Tape & Reel Micro8 (Pb-Free) 4000 Units / Tape & Reel 0.4% 2.2% 1.0% 0.4% 2.2% 1.0% 0.4% 2.2% 1.0% PDIP-8 (Pb-Free) 50 Units / Rail TO-92 (Pb-Free) 2000 Units / Bag 0.4% 2.2% 1.0% 0.4% 2.2% TL431ACLPRAG ACLP 1.0% TL431BCLPRAG BCLP 0.4% TL431CLPRAG CLP TL431ACLPREG ACLP TL431BCLPREG BCLP TL431CLPREG TL431ACLPRPG TL431BCLPRMG CLP TL431AIDG AI TL431BIDG BI I TL431AIDR2G AI TL431BIDR2G BI I TL431AIDMR2G TAI TL431BIDMR2G TBI TL431IDMR2G T-I TL431AIPG AIP TL431BIPG BIP TL431IPG IP TL431AILPG AILP TL431BILPG BILP TL431ILPG AILP TL431BILPRAG BILP SC431ILPRAG ILP TL431ILPRAG ILP TL431AILPRMG TL431AILPRPG TL431ILPRPG -40C to 85C 2000 / Tape & Ammo Box 1.0% 0.4% TO-92 (Pb-Free) 2000 Units / Fan-Fold SOIC-8 (Pb-Free) 98 Units / Rail SOIC-8 (Pb-Free) 2500 Units / Tape & Reel Micro8 (Pb-Free) 4000 Units / Tape & Reel PDIP-8 (Pb-Free) 50 Units / Rail TO-92 (Pb-Free) ILP TL431AILPRAG 1.0% 2.2% TO-92 (Pb-Free) BCLP CLP 2.2% 0.4% ACLP TL431CLPRPG TL431IDR2G 2000 Units / Tape & Reel CLP TL431CLPRMG TL431IDG TO-92 (Pb-Free) 2.2% 2.2% 1.0% 0.4% 2.2% 1.0% 0.4% 2.2% 1.0% 0.4% 2.2% 1.0% 0.4% 2.2% 1.0% 2000 Units / Bag 0.4% 2.2% 1.0% TO-92 (Pb-Free) 2000 Units / Tape & Reel 0.4% 2.2% 2.2% AILP TO-92 (Pb-Free) ILP 1.0% 2000 / Tape & Ammo Box 1.0% 2.2% For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 13 TL431, A, B Series, NCV431A, B ORDERING INFORMATION Device TL431BVDG TL431BVDR2G TL431BVDMR2G TL431BVLPG TL431BVLPRAG TL431BVPG NCV431AIDMR2G NCV431AIDR2G NCV431BVDMR2G NCV431BVDR2G Marking Code Operating Temperature Range Package Code BV SOIC-8 (Pb-Free) TBV Micro8 (Pb-Free) BVLP TO-92 (Pb-Free) BVP Shipping Information 98 Units / Rail Tolerance 0.4% 2500 Units / Tape & Reel 0.4% 4000 Units / Tape & Reel 0.4% 2000 Units / Bag 0.4% 2000 Units / Tape & Reel 0.4% PDIP-8 (Pb-Free) 50 Units / Rail 0.4% RAN Micro8 (Pb-Free) 4000 Units / Tape & Reel 1% AV SOIC-8 (Pb-Free) 2500 Units / Tape & Reel 1% NVB Micro8 (Pb-Free) 4000 Units / Tape & Reel 0.4% BV SOIC-8 (Pb-Free) 2500 Units / Tape & Reel 0.4% -40C to 125C For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC-8 D SUFFIX CASE 751 8 Micro8 CASE 846A PDIP-8 CASE 626 8 8 431xx ALYW G 1 TL431xxx AWL YYWWG xxx AYWG G 1 8 TL431 ALYWx G 1 (Exception for the TL431CD and TL431ID only) TO-92 (TO-226) CASE 29 1 xxxx = See Specific Marking Code A = Assembly Location Y, YY = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) http://onsemi.com 14 TL431 xxxx YWW G G TL431, A, B Series, NCV431A, B PACKAGE DIMENSIONS TO-92 (TO-226) CASE 29-11 ISSUE AM 1 12 3 STRAIGHT LEAD BULK PACK 2 3 BENT LEAD TAPE & REEL AMMO PACK A B STRAIGHT LEAD BULK PACK R P L SEATING PLANE K D X X G J H V C SECTION X-X N 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. DIM A B C D G H J K L N P R V INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 --0.250 --0.080 0.105 --0.100 0.115 --0.135 --- MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 --6.35 --2.04 2.66 --2.54 2.93 --3.43 --- N A R BENT LEAD TAPE & REEL AMMO PACK B P T SEATING PLANE G K D X X J V 1 C N SECTION X-X http://onsemi.com 15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. DIM A B C D G J K N P R V MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.40 0.54 2.40 2.80 0.39 0.50 12.70 --2.04 2.66 1.50 4.00 2.93 --3.43 --- TL431, A, B Series, NCV431A, B PACKAGE DIMENSIONS PDIP-8 P SUFFIX CASE 626-05 ISSUE M D A D1 E 8 5 E1 1 4 NOTE 5 F c E2 END VIEW TOP VIEW NOTE 3 e/2 A L A1 C SEATING PLANE E3 e 8X SIDE VIEW b 0.010 M C A END VIEW http://onsemi.com 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSION E IS MEASURED WITH THE LEADS RESTRAINED PARALLEL AT WIDTH E2. 4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A A1 b C D D1 E E1 E2 E3 e L INCHES NOM MAX ---- 0.210 ---- ---- 0.018 0.022 0.010 0.014 0.365 0.400 ---- ---- 0.310 0.325 0.250 0.280 0.300 BSC ---- ---- 0.430 0.100 BSC 0.115 0.130 0.150 MIN ---- 0.015 0.014 0.008 0.355 0.005 0.300 0.240 MILLIMETERS MIN NOM MAX ---- ---- 5.33 0.38 ---- ---- 0.35 0.46 0.56 0.20 0.25 0.36 9.02 9.27 10.02 0.13 ---- ---- 7.62 7.87 8.26 6.10 6.35 7.11 7.62 BSC ---- ---- 10.92 2.54 BSC 2.92 3.30 3.81 TL431, A, B Series, NCV431A, B PACKAGE DIMENSIONS Micro8 DM SUFFIX CASE 846A-02 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846A-01 OBSOLETE, NEW STANDARD 846A-02. D HE PIN 1 ID E e b 8 PL 0.08 (0.003) T B M S A DIM A A1 b c D E e L HE S SEATING -T- PLANE 0.038 (0.0015) MILLIMETERS NOM MAX -- 1.10 0.08 0.15 0.33 0.40 0.18 0.23 3.00 3.10 3.00 3.10 0.65 BSC 0.40 0.55 0.70 4.75 4.90 5.05 MIN -- 0.05 0.25 0.13 2.90 2.90 A A1 L c SOLDERING FOOTPRINT* 8X 1.04 0.041 0.38 0.015 3.20 0.126 6X 8X 4.24 0.167 0.65 0.0256 5.28 0.208 SCALE 8:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 INCHES NOM -- 0.003 0.013 0.007 0.118 0.118 0.026 BSC 0.016 0.021 0.187 0.193 MIN -- 0.002 0.010 0.005 0.114 0.114 MAX 0.043 0.006 0.016 0.009 0.122 0.122 0.028 0.199 TL431, A, B Series, NCV431A, B PACKAGE DIMENSIONS SOIC-8 D SUFFIX CASE 751-07 ISSUE AK -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. A 8 5 S B 0.25 (0.010) M Y M 1 4 -Y- K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Micro8 is a trademark of International Rectifier. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 18 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative TL431/D