©2003 Integrated Device Technology, Inc.
1
SEPTEMBER 2003
DSC-4853/4
I/O
Control
Address
Decoder
128Kx9
MEMORY
ARRAY
70V19
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/W
L
A
16L
A
0L
I/O
0-8L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
R/W
L
CE
0L
OE
L
I/O
Control
Address
Decoder
OE
R
R/W
R
CE
0R
A
16R
A
0R
I/O
0-8R
SEM
R
INT
R
(2)
R
BUSY
(1,2)
M/S
(1)
CE
1L
R/W
R
CE
0R
OE
R
CE
1R
4853 drw 01
1L
CE
1R
CE
1717
Functional Block Diagram
◆◆
◆◆
◆M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆◆
◆◆
◆Busy and Interrupt Flags
◆◆
◆◆
◆On-chip port arbitration logic
◆◆
◆◆
◆Full on-chip hardware support of semaphore signaling
between ports
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆LVTTL-compatible, single 3.3V (±0.3V) power supply
◆◆
◆◆
◆Available in a 100-pin TQFP
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
◆◆
◆◆
◆True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆◆
◆◆
◆High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT70V19L
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆◆
◆◆
◆Dual chip enables allow for depth expansion without
external logic
◆◆
◆◆
◆IDT70V19 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
HIGH-SPEED 3.3V
128K x 9 DUAL-PORT
STATIC RAM
IDT70V19L
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V19 is a high-speed 128K x 9 Dual-Port Static RAM.
The IDT70V19 is designed to be used as a stand-alone 1152K-bit
Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM
for 18-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-
Port RAM approach in 18-bit or wider memory system applications
results in full-speed, error-free operation without the need for addi-
tional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by the chip enables (either CE0 or CE1)
permit the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 440mW of power.
The IDT70V19 is packaged in a 100-pin Thin Quad Flatpack
(TQFP).
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations(1,2,3)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100999897969594939291908988878685848382818079787776
IDT70V19PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
GND
GND
OE
R
R/W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
A
16R
4853 drw 02
NC
NC
GND
OE
L
R/W
L
SEM
L
CE
1L
CE
0L
NC
NC
NC
Vcc
A
16L
A
15L
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
NC
NC
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
0R
GND
Vcc
I/O
0L
I/O1
L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
3L
I/O
1R
I/O
7R
GND
I/O
8L
I/O
8R
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
BUSY
L
INT
L
NC
A
0L
GND
A
2L
A
3L
A
5L
A
6L
NC
NC
A
1L
A
4L
3
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1) Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage
Pin Names
Capacitance(1) (TA = +25°C, f = 1.0MHz)
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Symbol Rating Commercial
& I ndustri al Unit
V
TERM
(2)
Terminal Voltage
with Re sp e ct
to G ND
-0.5 to +4.6 V
T
BIAS
Temperature
Und e r Bias -55 to +125
o
C
T
STG
Storage
Temperature -65 to + 150
o
C
I
OUT
DC Outp ut
Current 50 mA
4853 tbl 02
Grade Ambient
Temperature
(1)
GND Vcc
Commercial 0
O
C to +70
O
C0V 3.3V
+
0. 3V
Industrial -40
O
C to + 85
O
C0V 3.3V
+
0. 3V
4853 tbl 03
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 9 pF
C
OUT
Outp ut Cap ac itance V
OUT
= 3dV 10 pF
4853 tbl 05
Left P or t Ri ght Por t Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enable s
R/W
L
R/W
R
Re ad /Write Enab le
OE
L
OE
R
Outp ut Enab le
A
0L
- A
16L
A
0R
- A
16R
Address
I/O
0L
- I/ O
8L
I/O
0R
- I/ O
8R
Data Inp ut/ Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Inte rrup t Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
4 8 53 tbl 01
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup ply Vo ltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
CC
+0.3
(2)
V
V
IL
Inp ut Low Vo ltag e -0.3
(1)
____
0.8 V
4853 tb l 04
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Truth Table III – Semaphore Read/Write Control(1)
Truth Table I – Chip Enable(1,2)
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.
Truth Table II – Non-Contention Read/Write Control
NOTES:
1. A0L — A16L ≠ A0R — A16R
2. Refer to Truth Table I - Chip Enable.
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O8). These eight semaphore flags are addressed by A0-A2.
2 . Refer to Truth Table I - Chip Enable.
CE CE
0
CE
1
Mode
LV
IL
V
IH
Port Selected (TTL Active)
< 0.2V >V
CC
-0.2V Port Selected (CMOS Active)
H
V
IH
X Port Deselected (TTL Inactive)
XV
IL
Port De selected (TTL Inactive)
>V
CC
-0.2V X
(3)
Port De selected (CMOS Inactive)
X
(3)
<0.2V Port Dese lected (CMOS Inactive)
4853 tbl 06
Inputs
(1)
Outputs
Mode
CE
(2)
R/WOE SEM I/O
0-8
H X X H Hi gh-Z Des e le cte d: Po we r-Do wn
LLXHDATA
IN
Write to Memory
LHLHDATA
OUT
Read Me mory
X X H X Hi g h-Z O utp u ts Di sa b le d
4853 tbl 07
Inputs Outputs
Mode
CE
(2)
R/WOE SEM I/O
0-8
HHLLDATA
OUT
Read Semaphore Flag Data Out
H↑XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL ______ No t A llo we d
4853 tbl 08
5
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5) (VCC = 3.3V ± 0.3V)
NOTES:
1. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2 . Refer to Truth Table I - Chip Enable.
Symbol Parameter Test Conditions
70V19L
UnitMin. Max.
|I
LI
| Inp ut Le ak ag e Curre nt
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
5µA
|I
LO
| Output Leakage Current CE
(2)
= V
IH
, V
OUT
= 0V to V
CC
___
5µA
V
OL
Outp ut Lo w Vol tage I
OL
= +4mA
___
0.4 V
V
OH
Outp ut Hig h Vo ltag e I
OH
= -4mA 2.4
___
V
4853 t bl 09
70V19L15
Com'l Only 70V19L20
Com'l
& Ind
Symbol Parameter Test Cond ition Version Typ.
(1)
Max. Typ.
(1)
Max. Unit
I
CC
Dy namic Op erating
Current
(B o th P orts Ac ti v e )
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(2)
COM'L L 145 235 135 205 mA
IND L --- --- 135 220
I
SB1
Standb y Current
(Both Ports - TTL Level
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(2)
COM'L L 40 70 35 55 mA
IND L --- --- 35 65
I
SB2
Standb y Current
(On e P o rt - TTL Le v e l
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(4)
Active Po rt Outp uts Disabled,
f=f
MAX
(2)
,
SEM
R
= SEM
L
= V
IH
COM'L L 100 155 90 140 mA
IND L --- --- 90 150
I
SB3
Full Stand by Current
(Bo th Po rts - A ll CMOS
Le ve l Inp uts)
Both Ports CE
L
and CE
R
> V
CC
- 0. 2V,
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V, f = 0
(3)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L L 0.2 3.0 0.2 3.0 mA
IND L --- --- 0.2 3.0
I
SB4
Full Stand by Current
(On e P o rt - Al l CMOS
Le ve l Inp uts)
CE
"A"
< 0. 2V and CE
"B"
> V
CC
- 0. 2V
(4)
,
SEM
R
= SEM
L
> V
CC
- 0. 2V,
V
IN
> V
CC
- 0. 2V o r V
IN
< 0.2V,
Active Po rt Outputs Disabled, f = f
MAX
(2)
COM'L L 95 150 90 135 mA
IND L --- --- 90 145
4853 tbl 1 0
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Truth Table I - Chip Enable.
CE
(6)
4853 drw 06
t
PU
I
CC
I
SB
t
PD
50% 50%
.
t
RC
R/W
CE
(6)
ADDR
t
AA
OE
4853 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
AC Test Conditions
Figure 1. AC Output Load
Input Pulse Levels
Inp ut Ris e /Fal l Time s
Inp ut Timing Re fe rence Le v els
Outp ut Re fe re nc e Le ve ls
Outp ut Lo ad
GND to 3.0V
3ns Max .
1.5V
1.5V
Fi gures 1 and 2
4853 tbl 11
4853 drw 04
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
4853 drw 03
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
7
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
70V19L15
Com'l Only 70V19L20
Com'l
& In d
UnitSymbol Parameter Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycl e Time 15
____
20
____
ns
t
AA
Address Access Time
____
15
____
20 ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
20 ns
t
AOE
Output Enable Acce ss Time
____
10
____
12 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Lo w-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output Hig h-Z Time
(1,2)
____
10
____
10 ns
t
PU
Chip Enab le to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disab le to Po we r Down Time
(2)
____
15
____
20 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20 ns
4853 t bl 1 2
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
Symbol Parameter
70V19L15
Com'l Only 70V19L20
Com'l
& In d
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cyc le Tim e 15
____
20
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
15
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
ns
t
WR
Write Re cove ry Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
15
____
ns
t
HZ
Outp ut Hig h-Z Time
(1,2)
____
10
____
10 ns
t
DH
Data Ho ld Tim e
(4)
0
____
0
____
ns
t
WZ
Write E nable to Output in Hig h-Z
(1,2)
____
10
____
10 ns
t
OW
Outp ut A c ti v e fr o m En d -of-Wri te
(1,2,4)
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time 5
____
5
____
ns
t
SPS
SEM Flag Conte ntio n Windo w 5
____
5
____
ns
4853 t bl 1 3
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
4853 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
(3)
(2)
(6)
CE or SEM(9,10)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
NOTES:
1. R/W or CE = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Truth Table I - Chip Enable.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
4853 drw 07
(7)
(7)
(9,10)
9
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A" .
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value.
SEM
4853 drw 09
t
AW
t
EW
I/O
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA VALID
IN
DATA
OUT
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
Read CycleWrite Cycle
A
0
-A
2
OE
VALID
(2)
t
SOP
t
SOP
SEM
"A"
4853 drw 10
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE "B"
(2)
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V19L15
Com'l Only 70V19L20
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time fro m Address Match ____ 15 ____ 20 ns
t
BDA
BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ns
t
BAC
BUSY Access Time from Chip Enable Low ____ 15 ____ 20 ns
t
BDC
BUSY Access Time from Chip Enable High ____ 15 ____ 17 ns
t
APS
Arb itratio n P rio rity Se t-up Time
(2)
5____ 5____ ns
t
BDD
BUSY Disable to Valid Data
(3)
____ 15 ____ 17 ns
t
WH
Wri te Ho ld A fte r BUSY
(5)
12 ____ 15 ____ ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Inp ut to Write
(4)
0____ 0____ ns
t
WH
Wri te Ho ld A fte r BUSY
(5)
12 ____ 15 ____ ns
PORT-TO-PORT DELAY TIMI NG
t
WDD
Wri te Puls e to Data De lay
(1)
____ 30 ____ 45 ns
t
DDD
Wri te Da ta Val i d to Read Da ta De l ay
(1)
____ 25 ____ 30 ns
4853 t bl 1 4
11
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4853 drw 1
1
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4853 drw 12
R/W
"A"
BUSY
"B"
t
WB
(3)
R/W
"B"
t
WH
(1)
(2)
t
WP
.
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V19L15
Com'l Only 70V19L20
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
INTERRUPT TIMI NG
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Reco very Time 0
____
0
____
ns
t
INS
Inte rrupt S et Time
____
15
____
20 ns
t
INR
Inte rrupt Re se t Time
____
15
____
20 ns
4853 t bl 1 5
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable.
4853 drw 13
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
4853 drw 14
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
13
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table IV — Interrupt Flag(1,4,5)
Waveform of Interrupt Timing(1,5)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/ W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Table I - Chip Enable.
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Truth Table I - Chip Enable.
4853 drw 15
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
4853 drw 16
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
16L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
16R
-A
0R
INT
R
L L X 1FFFF X X X X X L
(2)
S e t Rig ht INT
R
Flag
X X X X X X L L 1FFFF H
(3)
Re se t Rig ht INT
R
Flag
XXX XL
(3)
L L X 1FFFE X Se t Left INT
L
Flag
X L L 1FFFE H
(2)
X X X X X Reset Left INT
L
Flag
4853 tbl 16
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
14
Functional Description
The IDT70V19 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V19 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby
mode when not selected (CE = HIGH). When a port is enabled, access
to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
1FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 1FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location 1FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 1FFFF. The
message (9 bits) at 1FFFE or 1FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations 1FFFE and 1FFFF are not used as mail boxes, but
as part of the random access memory. Refer to Truth Table IV for the
interrupt operation.
Truth Table V —
Address BUSY Arbitration(4)
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V19 are push-
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Truth Table I - Chip Enable.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V19.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
16L
A
OR
-A
16R
BUSY
L
(1)
BUSY
R
(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
LL MATCH (2) (2) Write Inhibit
(3)
4853 tbl 17
Functions D
0
- D
8
Left D
0
- D
8
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Rig ht Po rt Writes "0" to Se map hore 0 1 No chang e . Right s id e has no write ac ce s s to s e mapho re
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
4853 tbl 18
15
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT 70V19 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V19 is an extremely fast Dual-Port 128K x 9 CMOS
Static RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port RAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
III where CE and SEM are both HIGH.
Systems which can best use the IDT70V19 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V19s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V19 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V19 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V19 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration on a master is based on the chip enable and
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V19 RAMs.
4853 drw 17
MASTER
Dual Port RAM
BUSY
R
CE
0
MASTER
Dual Port RAM
BUSY
R
SLAVE
Dual Port RAM
BUSY
R
SLAVE
Dual Port RAM
BUSY
R
CE
1
CE
1
CE
0
A
17
BUSY
L
BUSY
L
BUSY
L
BUSY
L
.
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
16
D
4853 drw 18
0DQ
WRITE
D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ
SEMAPHORE
READ
verifies its success in setting the latch by reading it. If it was successful,
it proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V19 in a
separate memory space from the Dual-Port RAM. This address space
is accessed by placing a low input on the SEM pin (which acts as a chip
select for the semaphore flags) and using the other control pins
(Address, CE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to a
zero on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thor-
ough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
the first side.
When a semaphore flag is read, its value is spread into all data bits
so that a flag that is a one reads as a one in all data bits and a flag
containing a zero reads as all zeros. The read value is latched into one
side’s output register when that side's semaphore select (SEM) and
output enable (OE) signals go active. This serves to disallow the
semaphore from changing state in the middle of a read cycle due to a
write cycle from the other side. Because of this latch, a repeated read
of a semaphore in a test loop must cause either signal (SEM or OE) to
go inactive or the output will never change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table VI). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one,
all semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
Figure 4. IDT70V19 Semaphore Logic
17
IDT70V19L
High-Speed 3.3V 128K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Ordering Information
4853 drw 19
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
PF 100-pin TQFP (PN100-1)
15
20
LLowPower
XXXXX
Device
Type
1152K (128K x 9) Dual-Port RAM70V19
IDT
Speed in nanoseconds
Commercial Only
Commercial & Industrial
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History:
09/30/99: Initial Public Offering
04/10/00: Page 2 Fixed incorrect pin number
01/02/02: Page 3 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Added Truth Table I - Chip Enable as note 5 on page 5
Page 7 Corrected ±200mV to 0mV in notes
Page 5, 7, 10 & 12 Added industrial temp values for 20ns to DC & AC Electrical Characteristics
Page 3, 5, 7, 10 & 12 Removed industrial temp option footnote from all tables
Page 1 & 17 Replaced IDT TM logo with IDT ® logo
08/29/03: Removed Preliminary status
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
NOTE:
1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers.
