Typical Connection
HALF-BRIDGE DRIVER
Features
•Floating channel designed for bootstrap operation
•Fully operational to +600 V
•Tolerant to negative transient voltage, dV/dt
immune
•Gate drive supply range from 10 V to 20 V
•Undervoltage lockout for both channels
•3.3 V, 5 V, and 15 V input logic compatible
•Cross-conduction prevention logic
•Matched propagation delay for both channels
•High-side output in phase with IN input
•Logic and power ground +/- 5 V offset
•Internal 500 ns deadtime, and programmable
up to 5 µs with one external RDT resistor
•Lower di/dt gate driver for better noise immunity
•The dual function DT/SD input turns off both
channels
•RoHS compliant
IRS21091(S)PbF
Data Sheet No. PD60311
V
OFFSET
600 V max.
IO+/- 120 mA / 250 mA
VOUT 10 V - 20 V
t
on/off (typ.) 750 ns & 200 ns
Deadtime 540 ns
Product Summary
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Description
The IRS21091 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high- and
low-side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a
high pulse current buffer stage designed for minimum
driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in
the high-side configuration which operates up to 600 V.
(Refer to Lead Assignments for
correct configuration). These dia-
grams show electrical connec-
tions only. Please refer to our
Application Notes and DesignTips
for proper circuit board layout.
VCC VB
VS
HO
LOCOM
IN
DT/SD
DT/SD
IN
up to 600 V
TO
LOAD
VCC
Packages
8 Lead SOIC
IRS21091S
8 Lead PDIP
IRS21091
IRS21091(S)PbF
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Symbol Definition Min. Max. Units
VBHigh-side floating absolute voltage -0.3 625
VSHigh-side floating supply offset voltage VB - 25 VB + 0.3
VHO High-side floating output voltage VS - 0.3 VB + 0.3
VCC Low-side and logic fixed supply voltage -0.3 25
VLO Low-side output voltage -0.3 VCC + 0.3
DT/SD Programmable deadtime and shutdown pin voltage VSS - 0.3 VCC + 0.3
VIN
Logic input voltage (IN & DT/SD) VSS - 0.3 VCC + 0.3
dVS/dt Allowable offset supply voltage transient — 50 V/ns
(8 Lead PDIP) — 1.0
PD
Package power dissipation @ TA ≤ +25 °C(8 Lead SOIC) — 0.625
(8 Lead PDIP) — 125
RthJA Thermal resistance, junction to ambient
(8 Lead SOIC) — 200
TJJunction temperature — 150
TSStorage temperature -50 150
TLLead temperature (soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
V
°C
°C/W
W
IRS21091(S)PbF
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Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF, TA = 25 °C, unless otherwise specified.
Symbol Definition Min. Typ. Max.UnitsTest Conditions
ton Turn-on propagation delay — 750 950 VS = 0 V
toff Turn-off propagation delay — 200 280 VS = 0 V or 600 V
tsd Shutdown propagation delay — 550 715
MT Delay matching, HS & LS turn-on/off — 0 70
trTurn-on rise time — 100 220
tfTurn-off fall time — 35 80
DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 400 540 680 RDT= 0 Ω
HO turn-off to LO turn-on (DTHO-LO) 4 5 6 µs RDT = 200 kΩ
MDT Deadtime matching = DTLO - HO - DTHO-LO — 0 60 RDT= 0 Ω
— 0 600 RDT = 200 kΩ
ns
ns
Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
VBHigh-side floating supply absolute voltage VS + 10 VS + 20
VSHigh-side floating supply offset voltage (Note 1) 600
VHO High-side floating output voltage VSVB
VCC Low-side and logic fixed supply voltage 10 20
VLO Low-side output voltage 0 VCC
VIN
Logic input voltage (IN & DT/SD) VSS VCC
DT/SD Programmable deadtime and shutdown pin voltage VSS VCC
TAAmbient temperature -40 125 °C
Symbol Definition Min. Max. Units
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig.1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supply biased at a 15 V differential.
V
VS = 0 V
IRS21091(S)PbF
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Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, and TA = 25 °C unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to
COM and are applicable to the respective input leads: IN and DT/SD. The VO, IO, and Ron parameters are referenced to
COM and are applicable to the respective output leads: HO and LO.
Symbol Definition Min. Typ.Max.UnitsTest Conditions
VIH Logic “1” input voltage for HO & logic “0” for LO 2.5 — —
VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8
VSD,TH DT/SD input threshold 11.5 13 14.5
VOH High level output voltage, VBIAS - VO—0.05 0.2
VOL Low level output voltage, VO—0.02 0.1
ILK Offset supply leakage current — — 50 VB = VS = 600 V
IQBS
Quiescent VBS supply current 20 75 130
IN = 0 V or 5 V
IQCC Quiescent VCC supply current 0.4 1.0 1.6 mA IN = 0 V or 5 V
RDT = 0 Ω
IIN+
Logic “1” input bias current — 5 20 IN = 5 V, DT/SD = 0 V
IIN- Logic “0” input bias current — — 5 IN = 0 V, DT/SD = 5 V
VCCUV+ VCC and VBS supply undervoltage positive going 8.0 8.9 9.8
VBSUV+ threshold
VCCUV- VCC and VBS supply undervoltage negative going 7.4 8.2 9.0
VBSUV- threshold
VCCUVH Hysteresis 0.3 0.7 —
VBSUVH
IO+ Output high short circuit pulsed current 120 290 — VO = 0 V, PW ≤ 10 µs
IO- Output low short circuit pulsed current 250 600 — VO = 15 V,PW ≤ 10 µs
V
µA
V
µA
mA
VCC = 10 V to 20 V
IO = 2 mA
Lead Assignments
8 Lead PDIP 8 Lead SOIC
1
2
3
4
8
7
6
5
VCC
IN
DT/SD
COM
VB
HO
VS
LO
IRS21091PbF IRS21091SPbF
1
2
3
4
8
7
6
5
VCC
IN
DT/SD
COM
VB
HO
VS
LO
IRS21091(S)PbF
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Functional Block Diagrams
UV
DETECT
DELAY COM
LO
VCC
IN VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
VSS/COM
LEVEL
SHIFT
VSS/COM
LEVEL
SHIFT
DEADTIME
DT/SD
Lead Definitions
SymbolDescription
IN Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO
DT/SD Programmable deadtime lead,disables input/output logic when tied to VCC
VBHigh-side floating supply
HO High-side gate drive output
VSHigh-side floating supply return
VCC Low-side and logic fixed supply
LO Low-side gate drive output
COM Low-side return
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Figure 2. Switching Time Waveform Definitions
Figure 4. Deadtime Waveform Definitions
IN
HO
50% 50%
90%
10%
LO 90%
10%
DTLO-HO
DTLO-HO
MDT= - DTHO-LO
DTHO-LO
IN(HO)
tr
ton tf
toff
LO
HO
50% 50%
90% 90%
10% 10%
IN(LO)
Figure 5. Delay Matching Waveform Definitions
HO
50% 50%
10%
LO
90%
MT
HOLO
MT
IN (LO)
IN (HO)
Figure 1. Input/Output Timing Diagram
Figure 3. Shutdown Waveform Definitions
DT/SD
HO
LO
50%
90%
tsd
IN
HO
LO
DT/SD
IRS21091(S)PbF
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500
700
900
1100
1300
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn-on Propagation Delay (ns)
Typ.
Max
.
Figure 6A. Turn-on Propagation Delay
500
700
900
1100
1300
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn-on Propagation Delay (ns)
Typ.
Max.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn- of f Pr opagation Delay ( ns )
Max.
Typ.
Figure 7A. Turn-off Propagation Delay
0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn-off Propagation Delay (ns)
Figure 7B. Turn-off Propagation Delay
Typ.
Max.
Figure 6A. Turn-On Propagation Delay
vs. Temperature
Figure 6B. Turn-On Propagation Delay
vs. Supply Voltage
Figure 7A. Turn-Off Propagation Delay
vs. Temperature
Figure 7B. Turn-Off Propagation Delay
vs. Supply Voltage
Note: For the following figures the VBIAS (VCC
, VBS
) = 15 V and T
A = 25 OC unless otherwise specified.
IRS21091(S)PbF
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Figure 9A. Turn-On Rise Time
vs. Temperature
Figure 9B. Turn-On Rise Time
vs. Supply Voltage
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
SD Propagation Delay (ns)
M ax.
Typ.
0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Supply Voltage (V)
SD Propagation Delay (ns)
Typ.
Max.
Figure 8A. SD Propagation Delay
vs. Temperature
Figure 8B. SD Propagation Delay
vs. Supply Voltage
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature(oC)
T u rn -O n R ise Time (ns)
0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Supply Voltage (V)
T u rn -O n R ise Time (ns)
Turn-On Rise Time (ns)
Turn-On Rise Time (ns)
Max.
Typ.
Typ.
Max.
IRS21091(S)PbF
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200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (oC)
Deadtime (ns )
Min.
Typ.
Max.
200
400
600
800
1000
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Deadtime (ns)
Max.
Typ.
Min.
Figure 10A. Turn-Off Fall Time
vs. Temperature
Figure 10B. Turn-Off Fall Time
vs. Supply Voltage
Figure 11A. Deadtime vs. Temperature Figure 11B. Deadtime vs. Supply Voltage
0
50
100
150
200
-50 -25 0 25 50 75 100 125
Temperature (
o
C)
Tu rn -Off Fall T ime (n s)
Tu rn -Off Fall T ime (n s)
Max.
Typ.
Max.
Typ.
0
50
100
150
200
10 12 14 16 18 20
V
BIAS
Supply Voltage (V)
Turn-Off Fall Time
ns
IRS21091(S)PbF
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Figure 11C. Deadtime vs. RDT
Figure 12A. Logic “1” Input Voltage
vs. Temperature
Figure 12B. Logic “1” Input Voltage
vs. Supply Voltage
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (°C)
Input Voltage (V)
1
2
3
4
5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Input Voltage (V)
Min.
Min.
0
1
2
3
4
5
6
7
050 100 150 200
R
DT
(KΩ)
Deadtime ( s)
Typ.
Max.
Min.
Deadtime (µs)
RDT (kΩ)
Max
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Lo gic "0" Input Bia s Current ( µA)
Figure 13A. Logic "0" Input Bias Current
IRS21091(S)PbF
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SD Input threshold (+) (V)
Max
0
1
2
3
4
5
6
10 12 14 16 18 20
Supply Voltage (V)
Logic "0" Input Bias Current (µA)
Figure 13B. Logic "0" Input Bias Current
vs. Voltage
Figure 15A. High Level Output Voltage
vs. Temperature
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Max.
Typ.
-50 -25 0 25 50 75 100 125
Temperature (oC)
0.0
0.1
0.2
0.3
0.4
0.5
10
High Level Output Voltage (V)
Max.
8
10
12
14
16
18
-50 -25 0 25 50 75 100 125
Temperature (oC)
SD Input threshold (+) (V)
Figure 14A. SD Input Positive Going
Threshold (+) vs. Temperature
Max.
8
10
12
14
16
18
10 12 14 16 18 20
VCC Supply Voltage (V)
Figure 14B. SD Input Positive Going
Threshold (+) vs. Supply Voltage
IRS21091(S)PbF
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0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Offset Supply Leakage Current ( A)
Max.
Figure 16B. Low Level Output Voltage
vs. Supply Voltage
Figure 17A. Offset Supply Leakage Current
vs. Temperature
0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Low Level Output Voltage (V)
Max.
Typ.
Offset Supply Leakage Current (µA)
Figure 15B. High Level Output Voltage
vs. Supply Voltage
Figure 16A. Low Level Output Voltage
vs. Temperature
0.0
0.1
0.2
0.3
0.4
0.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
High Level Output Voltage (V)
Max.
Typ.
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
L o w L e v e l O u t p u t V o lta g e (V )
Max.
Typ.
IRS21091(S)PbF
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Figure 17B. Offset Supply Leakage Current
vs. Boost Voltage
Offset Supply Leakage Current (µA)
Figure 19A. V
CC Supply Current
vs. Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
V c c S u p p l y C u r r e n ( m A )
Max.
Typ.
Min.
VC C S u p p l y C u r r e n t (m A )
0
100
200
300
400
-50 -25 0 25 50 75 100 125
Temperature (oC)
VB S
Supply Current (μA)
Figure 18A. VBS Supply Current vs.
Temperature
0
100
200
300
400
500
0100 200 300 400 500 600
VB Boost Voltage (V)
Max.
0
100
200
300
400
10 12 14 16 18 20
Supply Voltage (V)
VBS
Supply Current (μA)
Figure 18B. VBS Supply Current vs. Supply
Voltage
Typ.
Min.
Max.
Max.
Typ.
Min.
IRS21091(S)PbF
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Figure 20B. Logic “1” Input Current
vs. Supply Voltage
0
10
20
30
40
50
60
10 12 14 16 18 20
VCC Supply Voltage (V)
Logic "1" Input Current ( A)
Figure 21B. Logic "1" Input Current
Max.
Typ.
Logic “1” Input Current (mA)
Logic 0” Input Current (µA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
10 12 14 16 18 20
VCC Supply Voltage (V)
VCC Supply Current (mA)
Figure 20B. V
Supply Current
Max.
Typ.
Min.
Figure 19B. VCC Supply Current
vs. VCC Supply Voltage
0
10
20
30
40
50
60
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logic " 1" Inp ut Cur r ent ( A )
Typ.
Max.
Figure 20A. Logic “1” Input Current
vs. Temperature
Logic “1” Input Current (mA)
Figure 21A. Logic “0” Input Current
vs. Temperature
Max.
0
2
4
6
8
10
-50 -25 0 25 50 75 100 125
Temperature (oC)
IRS21091(S)PbF
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7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
VC C UV LO Thr es h old ( +) ( V )
Typ.
Max.
Min.
Figure 22. V
CC Undervoltage Threshold (+)
vs. Temperature
Figure 21B. Logic “0” Input Currentt
vs. Supply Voltage
Logic 0” Input Current (µA)
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
VC C UV LO Thr es hold ( - ) (V )
Typ.
Max.
Min.
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (oC)
VB S UV LO Thr es hold ( +) ( V)
Typ.
Max.
Min.
Figure 23. V
CC Undervoltage Threshold (-)
vs. Temperature
Figure 24. V
BS Undervoltage Threshold (+)
vs. Temperature
Max.
0
2
4
6
8
10
10 12 14 16 18 20
VCC Supply Voltage (V)
IRS21091(S)PbF
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Figure 26B. Output Source Current
vs. Supply Voltage
Figure 27A. Output Sink Current
vs. Temperature
0
200
400
600
800
1000
-50 -25 0 25 50 75 100 125
Temperature (oC)
O u t p u t S i n k C u r r e n )
Typ.
Min.
Output Sink Current (m A)
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
VB S UV LO Thr es hold ( -) ( V )
Typ.
Max.
Min.
Figure 25. VBS Undervoltage Threshold (-)
vs. Temperature
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (oC)
Output Source Current (mA)
Figure 26A. Output Source Current vs.
Temperature
0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Output Source Current (mA)
Typ.
Min.
Typ.
Min.
IRS21091(S)PbF
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-10
-8
-6
-4
-2
0
10 12 14 16 18 20
VBS Floating Supply Voltage (V)
VS Offset Supply Voltage (V)
Typ.
Figure 27B. Output Sink Currentt
vs. Supply Voltage
Figure 28. Maximum VS Negative Offset
vs. Supply Voltage
0
200
400
600
800
1000
10 12 14 16 18 20
VBIAS Supply Voltage (V)
O u t p u t S i n k C u r r e n
Typ.
Min.
Output Sink Current (m A)
IRS21091(S)PbF
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Case Outlines
01-6027
01-0021 11 (MS-012AA)
8 Lead SOIC
87
5
65
D B
E
A
e
6X
H
0. 25 [. 010] A
6
4312
4. OUTLINE CONFORMS T O JEDEC OUT LINE MS- 012 AA.
NOTES:
1. DIMENSIONING & T OLERANCI NG PER ASME Y14.5M- 19 94.
2. CO NTRO LL ING DIM E N SION: MILL IM ETER
3. DIMENSIONS ARE SHOWN IN MILLIMET ERS [INCHES].
7
K x 4 5 °
8X L 8X c
y
FOOTPRINT
8X 0. 72 [.028]
6.46 [.255]
3X 1. 27 [.050] 8X 1. 78 [.070]
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROT RUSIONS NOT T O EXCEED 0. 25 [ . 01 0].
7 DIMENSIO N IS TH E LE NG TH OF LEAD FO R SO LDE RING TO
A SUBSTRATE.
MOLD PROT RUSIONS NOT T O EXCEED 0. 15 [ . 00 6].
0. 25 [. 010 ] C A B
e1 A
A1
8X b
C
0. 10 [. 004 ]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSIN C H ES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC
01-6014
01-3003 01 (MS-001AB)
8 Lead PDIP
IRS21091(S)PbF
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CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A 7 .9 0 8.1 0 0 .31 1 0 .3 18
B 3 .90 4.10 0.153 0.161
C 11.70 12.30 0.46 0.484
D 5 .4 5 5.5 5 0. 21 4 0 .2 18
E 6 .3 0 6.5 0 0 .24 8 0 .2 55
F 5 .1 0 5.3 0 0. 20 0 0 .2 08
G 1.50 n/a 0.059 n/a
H 1 .5 0 1.6 0 0. 05 9 0 .0 62
M etr ic Im p erial
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1 .9 5 2.4 5 0. 76 7 0 .0 96
E 98.00 102.00 3.858 4.015
F n /a 1 8.40 n /a 0 .7 24
G 14.50 17.10 0.570 0.673
H 12.40 14.40 0.488 0.566
M etr ic Im p erial
E
F
A
C
D
G
A
BH
N
OTE : CO NTROLLING
D
IMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
Tape & Reel
8-lead SOIC
IRS21091(S)PbF
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The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/22/2007
LEADFREE PART MARKING INFORMATION
Lead Free Released
Non-Lead Free
Released
Part number
Date code
IRxxxxxx
YWW?
?XXXX
Pin 1
Identifier
IR logo
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
P
?MARKING CODE
S
8-Lead PDIP IRS21091PbF
8-Lead SOIC IRS21091SPbF
8-Lead SOIC Tape & Reel IRS21091STRPbF
ORDER INFORMATION