Precision, Low Noise, CMOS, Rail-to-Rail,
Input/Output Operational Amplifiers
AD8605/AD8606/AD8608
Rev. J
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
Low offset voltage: 65 μV maximum
Low input bias currents: 1 pA maximum
Low noise: 8 nV/√Hz
Wide bandwidth: 10 MHZ
High open-loop gain: 1000 V/mV
Unity gain stable
Single-supply operation: 2.7 V to 5.5 V
5-ball WLCSP for single (AD8605) and 8-ball WLCSP for
dual (AD8606)
APPLICATIONS
Photodiode amplification
Battery-powered instrumentation
Multipole filters
Sensors
Barcode scanners
Audio
GENERAL DESCRIPTION
The AD8605, AD8606, and AD86081 are single, dual, and quad
rail-to-rail input and output, single-supply amplifiers. They
feature very low offset voltage, low input voltage and current
noise, and wide signal bandwidth. They use the Analog Devices,
Inc. patented DigiTrim® trimming technique, which achieves
superior precision without laser trimming.
The combination of low offsets, low noise, very low input bias
currents, and high speed makes these amplifiers useful in a
wide variety of applications. Filters, integrators, photodiode
amplifiers, and high impedance sensors all benefit from the
combination of performance features. Audio and other ac
applications benefit from the wide bandwidth and low
distortion. Applications for these amplifiers include optical
control loops, portable and loop-powered instrumentation,
and audio amplification for portable devices.
The AD8605, AD8606, and AD8608 are specified over the
extended industrial temperature range (−40°C to +125°C). The
AD8605 single is available in 5-lead SOT-23 and 5-ball WLCSP
packages. The AD8606 dual is available in an 8-lead MSOP, an
8-ball WLSCP, and a narrow SOIC surface-mounted package.
The AD8608 quad is available in a 14-lead TSSOP package and
a narrow 14-lead SOIC package. The 5-ball and 8-ball WLCSP
offer the smallest available footprint for any surface-mounted
operational amplifier. The WLCSP, SOT-23, MSOP, and TSSOP
versions are available in tape-and-reel only.
1 Protected by U.S. Patent No. 5,969,657.;
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
5
4–IN
+IN
V+
OUT
AD8605
TOP V IEW
(Not to Scale)
V–
02731-001
02731-057
TOP VIEW
(BAL L S IDE DO WN)
BALL A1
CORNER
A1 A2 A3
B1 B3
C1 C2 C3
AD8606
+INA V– +INB
–INA –INB
OUTA V+ OUTB
Figure 1. 5-Lead SOT-23 (RJ Suffix) Figure 2. 8-Ball WLCSP (CB Suffix)
AD8605 ONLY
OUT V+
V–
+IN –IN
1
3
5
4
2
TOP VIEW
(BUM P S IDE DOWN)
02731-006
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OUT A
1
2
3
4
5
6
7
14
13
12
11
10
9
8
02731-004
AD8608
TOP VIEW
(No t t o Scale)
Figure 3. 5-Ball WLCSP (CB Suffix) Figure 4. 14-Lead SOIC_N (R Suffix)
–IN A
+IN A
V–
OUT B
–IN B
+IN B
V+
18
OUT A
45
02731-003
AD8606
TOP VIEW
(Not to Scal e)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
–IN D
+IN D
V–
OUT D
–IN C
OUT C
+IN C
14
8
1
7
02731-002
AD8608
TOP VIEW
(No t t o S cale)
Figure 5. 8-Lead MSOP (RM Suffix),
8-Lead SOIC_N (R Suffix)
Figure 6. 14-Lead TSSOP (RU Suffix)
AD8605/AD8606/AD8608
Rev. J | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
5 V Electrical Specifications ............................................................ 4
2.7 V Electrical Specifications ......................................................... 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Typical Performance Characteristics ............................................. 9
Applications Information .............................................................. 15
Output Phase Reversal ............................................................... 15
Maximum Power Dissipation ................................................... 15
Input Overvoltage Protection ................................................... 15
THD + Noise ............................................................................... 15
Total Noise Including Source Resistors ................................... 16
Channel Separation .................................................................... 16
Capacitive Load Drive ............................................................... 16
Light Sensitivity .......................................................................... 17
WLCSP Assembly Considerations ........................................... 17
I-V Conversion Applications ........................................................ 18
Photodiode Preamplifier Applications .................................... 18
Audio and PDA Applications ................................................... 18
Instrumentation Amplifiers ...................................................... 19
DAC Conversion ........................................................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 23
AD8605/AD8606/AD8608
Rev. J | Page 3 of 24
REVISION HISTORY
8/10—Rev. I to Rev. J
Changes to Figure 10 and Figure 11 .......................................... 9
Changes to Figure 15 ................................................................. 10
Changes to Figure 36 ................................................................. 13
Changes to Figure 42 ................................................................. 14
Updated Outline Dimensions ................................................... 20
Changes to Ordering Guide ...................................................... 23
9/08—Rev. H to Rev. I
Changes to Input Overvoltage Protection Section ................ 15
Changes to Ordering Guide ...................................................... 22
2/08—Rev. G to Rev. H
Changes to Features ..................................................................... 1
Changes to Table 1 ....................................................................... 4
Changes to Table 2 ....................................................................... 6
Changes to Figure 11 ................................................................... 9
Changes to Figure 13, Figure 14, and Figure 16 Captions .... 10
Changes to Figure 15, Figure 17, and Figure 18 ..................... 10
Changes to Figure 34 and Figure 35 Captions ........................ 13
Changes to Figure 36 ................................................................. 13
Changes to Figure 37 Caption .................................................. 14
Changes to Figure 38 and Figure 41 ........................................ 14
Changes to Figure 45 ................................................................. 15
Changes to Audio and PDA Applications Section ................. 18
Changes to Figure 52 ................................................................. 18
Changes to Ordering Guide ...................................................... 22
10/07—Rev. F to Rev. G
Changes to Figure 2 ...................................................................... 1
Updated Outline Dimensions ................................................... 20
8/07—Rev. E to Rev. F
Added 8-Ball WLCSP Package ..................................... Universal
Changes to Features ..................................................................... 1
Changes to Table 1 ....................................................................... 3
Changes to Table 2 ....................................................................... 5
Changes to Table 4 ....................................................................... 7
Updated Outline Dimensions ................................................... 19
Changes to Ordering Guide ...................................................... 21
1/06—Rev. D to Rev. E
Changes to Table 1 ........................................................................ 3
Changes to Table 2 ........................................................................ 5
Changes to Table 4 ........................................................................ 6
Changes to Figure 12 Caption ..................................................... 8
Changes to Figure 26 and Figure 27 Captions ....................... 11
Changes to Figure 33 Caption .................................................. 12
Changes to Figure 44 ................................................................. 14
Updated Outline Dimensions ................................................... 19
Changes to Ordering Guide ...................................................... 20
5/04—Rev. C to Rev. D
Updated Format ............................................................. Universal
Edit to Light Sensitivity Section ............................................... 16
Updated Outline Dimensions ................................................... 19
Changes to Ordering Guide ...................................................... 20
7/03—Rev. B to Rev. C
Changes to Features ....................................................................... 1
Change to General Description .................................................... 1
Addition to Functional Block Diagrams ..................................... 1
Addition to Absolute Maximum Ratings .................................... 4
Addition to Ordering Guide ......................................................... 4
Change to Equation in Maximum Power Dissipation
Section .......................................................................................... 11
Added Light Sensitivity Section ................................................ 12
Added New Figure 8; Renumbered Subsequently .................. 13
Added New MicroCSP Assembly Considerations Section .... 13
Changes to Figure 9 .................................................................... 13
Change to Equation in Photodiode Preamplifier
Applications Section .................................................................. 13
Changes to Figure 12 .................................................................. 14
Change to Equation in D/A Conversion Section .................... 14
Updated Outline Dimensions ................................................... 15
3/03—Rev. A to Rev. B
Changes to Functional Block Diagram ....................................... 1
Changes to Absolute Maximum Ratings..................................... 4
Changes to Ordering Guide ........................................................ 4
Changes to Figure 9 ................................................................... 13
Updated Outline Dimensions .................................................... 15
11/02—Rev. 0 to Rev. A
Change to Electrical Characteristics ............................................ 2
Changes to Absolute Maximum Ratings..................................... 4
Changes to Ordering Guide ......................................................... 4
Change to TPC 6 ........................................................................... 5
Updated Outline Dimensions .................................................... 15
5/02—Revision 0: Initial Version
AD8605/AD8606/AD8608
Rev. J | Page 4 of 24
5 V ELECTRICAL SPECIFICATIONS
VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
AD8605/AD8606 (Except WLCSP) VS = 3.5 V, VCM = 3 V 20 65 μV
AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 μV
AD8605/AD8606/AD8608 VS = 5 V, VCM = 0 V to 5 V 80 300 μV
−40°C < TA < +125°C 750 μV
Input Bias Current IB 0.2 1 pA
AD8605/AD8606 −40°C < TA < +85°C 50 pA
AD8605/AD8606 −40°C < TA < +125°C 250 pA
AD8608 −40°C < TA < +85°C 100 pA
AD8608 −40°C < TA < +125°C 300 pA
Input Offset Current IOS 0.1 0.5 pA
−40°C < TA < +85°C 20 pA
−40°C < TA < +125°C 75 pA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 85 100 dB
−40°C < TA < +125°C 75 90 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VO = 0.5 V to 4.5 V 300 1000 V/mV
Offset Voltage Drift
AD8605/AD8606 ΔVOS/ΔT −40°C < TA < +125°C 1 4.5 μV/°C
AD8608 ΔVOS/ΔT −40°C < TA < +125°C 1.5 6.0 μV/°C
INPUT CAPACITANCE
Common-Mode Input Capacitance CCOM 8.8 pF
Differential Input Capacitance CDIFF 2.6 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1 mA 4.96 4.98 V
I
L = 10 mA 4.7 4.79 V
−40°C < TA < +125°C 4.6 V
Output Voltage Low VOL IL = 1 mA 20 40 mV
I
L= 10 mA 170 210 mV
−40°C < TA < +125°C 290 mV
Output Current IOUT ±80 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR
AD8605/AD8606 VS = 2.7 V to 5.5 V 80 95 dB
AD8605/AD8606 WLCSP VS = 2.7 V to 5.5 V 75 92 dB
AD8608 VS = 2.7 V to 5.5 V 77 92 dB
−40°C < TA < +125°C 70 90 dB
Supply Current/Amplifier ISY IOUT = 0 mA 1 1.2 mA
−40°C < TA < +125°C 1.4 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ, CL = 16 pF 5 V/μs
Settling Time tS To 0.01%, 0 V to 2 V step, AV = 1 <1 μs
Unity Gain Bandwidth Product GBP 10 MHz
Phase Margin ΦM 65 Degrees
AD8605/AD8606/AD8608
Rev. J | Page 5 of 24
Parameter Symbol Conditions Min Typ Max Unit
NOISE PERFORMANCE
Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 μV p-p
Voltage Noise Density en f = 1 kHz 8 12 nV/√Hz
e
n f = 10 kHz 6.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.01 pA/√Hz
AD8605/AD8606/AD8608
Rev. J | Page 6 of 24
2.7 V ELECTRICAL SPECIFICATIONS
VS = 2.7 V, VCM = VS/2, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
AD8605/AD8606 (Except WLCSP) VS = 3.5 V, VCM = 3 V 20 65 μV
AD8608 VS = 3.5 V, VCM = 2.7 V 20 75 μV
AD8605/AD8606/AD8608 VS = 2.7 V, VCM = 0 V to 2.7 V 80 300 μV
−40°C < TA < +125°C 750 μV
Input Bias Current IB 0.2 1 pA
AD8605/AD8606 −40°C < TA < +85°C 50 pA
AD8605/AD8606 −40°C < TA < +125°C 250 pA
AD8608 −40°C < TA < +85°C 100 pA
AD8608 −40°C < TA < +125°C 300 pA
Input Offset Current IOS 0.1 0.5 pA
−40°C < TA < +85°C 20 pA
−40°C < TA < +125°C 75 pA
Input Voltage Range 0 2.7 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.7 V 80 95 dB
−40°C < TA < +125°C 70 85 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VO = 0.5 V to 2.2 V 110 350 V/mV
Offset Voltage Drift
AD8605/AD8606 ΔVOS/ΔT −40°C < TA < +125°C 1 4.5 μV/°C
AD8608 ΔVOS/ΔT −40°C < TA < +125°C 1.5 6.0 μV/°C
INPUT CAPACITANCE
Common-Mode Input Capacitance CCOM 8.8 pF
Differential Input Capacitance CDIFF 2.6 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1 mA 2.6 2.66 V
−40°C < TA < +125°C 2.6 V
Output Voltage Low VOL IL = 1 mA 25 40 mV
−40°C < TA < +125°C 50 mV
Output Current IOUT ±30 mA
Closed-Loop Output Impedance ZOUT f = 1 MHz, AV = 1 1.2 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR
AD8605/AD8606 VS = 2.7 V to 5.5 V 80 95 dB
AD8605/AD8606 WLCSP VS = 2.7 V to 5.5 V 75 92 dB
AD8608 VS = 2.7 V to 5.5 V 77 92 dB
−40°C < TA < +125°C 70 90 dB
Supply Current/Amplifier ISY I
OUT = 0 mA 1.15 1.4 mA
−40°C < TA < +125°C 1.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ, CL = 16 pF 5 V/μs
Settling Time tS To 0.01%, 0 V to 1 V step, AV = 1 <0.5 μs
Unity Gain Bandwidth Product GBP 9 MHz
Phase Margin ΦM 50 Degrees
AD8605/AD8606/AD8608
Rev. J | Page 7 of 24
Parameter Symbol Conditions Min Typ Max Unit
NOISE PERFORMANCE
Peak-to-Peak Noise en p-p f = 0.1 Hz to 10 Hz 2.3 3.5 μV p-p
Voltage Noise Density en f = 1 kHz 8 12 nV/√Hz
e
n f = 10 kHz 6.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.01 pA/√Hz
AD8605/AD8606/AD8608
Rev. J | Page 8 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 6 V
Input Voltage GND to VS
Differential Input Voltage 6 V
Output Short-Circuit Duration to GND Observe Derating Curves
Storage Temperature Range
All Packages −65°C to +150°C
Operating Temperature Range
All Packages −40°C to +125°C
Junction Temperature Range
All Packages −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Table 4.
Package Type θJA1 θ
JC Unit
5-Ball WLCSP (CB) 170 °C/W
5-Lead SOT-23 (RJ) 240 92 °C/W
8-Ball WLCSP (CB) 115 °C/W
8-Lead MSOP (RM) 206 44 °C/W
8-Lead SOIC_N (R) 157 56 °C/W
14-Lead SOIC_N (R) 105 36 °C/W
14-Lead TSSOP (RU) 148 23 °C/W
1 θJA is specified for the worst-case conditions, that is, a device soldered in a
circuit board for surface-mount packages.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD8605/AD8606/AD8608
Rev. J | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE (µV)
NUMBER O F AMPL IFIERS
4500
4000
0
2000
1500
1000
500
3000
2500
3500
300–200 –100 0 100 200
–300
V
S
= 5V
T
A
= 25°C
V
CM
= 0V TO 5V
02731-007
Figure 7. Input Offset Voltage Distribution
TCVOS ( µ V/°C)
12
04.80.4
NUMBER OF AMPLIFIERS
0.8 1.6 2.4 3.2 4.0
16
8
4
24
20
4.4
V
S
= 5V
T
A
= –40°C TO +125°C
V
CM
= 2. 5V
0 1.2 2.0 2.8 3.6
02731-008
Figure 8. AD8608 Input Offset Voltage Drift Distribution
TCVO S ( µ V /°C)
20
10
02.60.2
NUMBER OF AMPL IF IERS
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
14
6
2
2.2 2.4
12
16
8
4
18
0
VS = 5V
TA = –40° C TO + 125°C
VCM = 2.5V
02731-009
Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution
0
02731-010
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0.05
0.10
0.15
0.20
0.25
0.30
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
CM
(V)
V
OS
(
m
V)
V
S
= 5V
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
TE M P ERATURE (°C)
360
160
00125
INPUT BIAS CURRE NT (p A)
50 75 100
240
80
200
280
120
40
320
25
AD8605/AD8606
AD8608
02731-011
V
S
= 5V
Figure 11. Input Bias Current vs. Temperature
LOAD CURRENT (mA)
1k
10
0.1
0.001 100.01
OUTPUT SAT URATION VOLTAGE (mV)
0.1
1
100
1
SINKSOURCE
VS = 5V
TA = 25°C
02731-012
Figure 12. Output Saturation Voltage vs. Load Current
AD8605/AD8606/AD8608
Rev. J | Page 10 of 24
TE MPE RATURE (°C)
5.00
4.95
4.70
OUTPUT V OLTAGE ( V )
4.85
4.75
4.90
4.80
V
OH
@ 1mA LO AD
V
S
= 5V
V
OH
@ 10mA L OAD
–40 –25 –10 5 20 35 50 65 80 95 110 125
02731-013
Figure 13. Output Voltage Swing High vs. Temperature
0.25
0
0.15
0.05
0.20
0.10
TE MPE RATURE (°C)
OUTPUT VOL
T
AGE ( V)
V
OL
@ 1mA LOAD
V
S
= 5V V
OL
@ 10mA LOAD
–40 –25 –10 5 20 35 50 65 80 95 110 125
02731-014
Figure 14. Output Voltage Swing Low vs. Temperature
GAIN (dB)
100
80
–100
60
40
20
0
–20
–40
–60
–80
225
180
–225
135
90
45
0
–45
–90
–135
–180
PHASE ( D egrees)
FREQUENCY ( Hz)
10k 40M100k 1M 10M
VS = ±2.5V
RL = 2kΩ
CL = 20p F
ΦM = 64°
02731-015
PHASE
GAIN
Figure 15. Open-Loop Gain and Phase vs. Frequency
FRE QUENC Y ( Hz )
6
5
01k 10M10k
OUTPUT SWING (V p-p)
100k 1M
4
3
1
2
V
S
= 5V
V
IN
= 4.9V p-p
T
A
= 25°C
R
L
= 2kΩ
A
V
= 1
02731-016
Figure 16. Closed-Loop Output Voltage Swing (FPBW)
FREQUENCY (Hz)
100
90
01k 100M10k 100k 1M 10M
80
70
20
60
50
30
10
40
V
S
= 5V
A
V
= 100
A
V
= 1
A
V
= 10
02731-017
OUT PUT I M PE DANCE (Ω)
Figure 17. Output Impedance vs. Frequency
FRE QUENC Y ( Hz )
10k
CMRR (d B)
100k 1M
20
120
1k 10M
90
80
70
60
50
40
30
110
100
V
S
= 5V
02731-018
Figure 18. Common-Mode Rejection Ratio (CMRR) vs. Frequency
AD8605/AD8606/AD8608
Rev. J | Page 11 of 24
FREQUENCY (Hz)
140
80
–601k 10M10k
PSRR (dB)
100k 1M
40
0
–40
100
120
60
20
–20
V
S
= 5V
02731-019
Figure 19. PSRR vs. Frequency
CAPACITANCE (p F)
45
40
010 1k100
SMALL SIGN
A
L OVERSHOOT (%)
35
30
10
25
20
15
5
V
S
= 5V
R
L
=
∞
T
A
= 25°C
A
V
= 1
+OS
–OS
02731-020
Figure 20. Small Signal Overshoot vs. Load Capacitance
TEMPERATURE (°C)
2.0
0
SUPP LY CURRENT/AMPLI F IER (m A)
–40 125–25 –10 95 110
1.5
1.0
0.5
52035506580
02731-021
V
S
= 2. 7V
V
S
= 5V
Figure 21. Supply Current/Amplifier vs. Temperature
SUPPLY VOLTAGE (V)
1.0
0.4
0
SUPP LY CURRENT/AM PL I FI ER (mA)
0.9
0.5
0.3
0.1
0.7
0.6
0.2
0.8
054.54.03.53.02.52.01.51.00.5
02731-022
.0
Figure 22. Supply Current/Amplifier vs. Supply Voltage
TIME ( 1s/DIV)
VOL
T
AGE NOISE (1µV/DIV)
V
S
= 5V
02731-023
Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise
TI M E ( 200n s/DI V)
VOLTAGE (50mV/DIV)
02731-024
V
S
= ±2.5V
R
L
= 10kΩ
C
L
= 200p F
A
V
= 1
Figure 24. Small Signal Transient Response
AD8605/AD8606/AD8608
Rev. J | Page 12 of 24
TIME (400ns/DIV)
VOLTAG E (1V/ DI V )
VS = ±2.5V
RL = 10kΩ
CL = 200pF
AV = 1
02731-025
Figure 25. Large Signal Transient Response
TIME ( 400ns/DIV )
2.5V
–50mV
0V
V
OUT
V
IN
0V
V
S
= ±2.5V
R
L
= 10kΩ
A
V
= –100
V
IN
= 50mV
02731-026
Figure 26. Positive Overload Recovery
V
S
= ±2.5V
R
L
= 10kΩ
A
V
= –100
V
IN
= 50mV
TIME (1µs/DIV)
–2.5V
50mV
0V
0V
02731-027
Figure 27. Negative Overload Recovery
FREQ U ENCY (k Hz)
36
20
4
32
28
12
8
24
16
VS = ±2.5V
VOLTAGE NOIS E DENSITY (nV / Hz)
010.90.80.70.60.50.40.30.20.1
02731-028
.0
Figure 28. Voltage Noise Density vs. Frequency
0
6.7
20.1
13.4
26.8
40.2
33.5
53.6
46.9
FREQ U ENCY (k Hz)
V
S
= ±2.5V
VOL
T
AGE NOISE DENSITY (nV/ Hz)
01987654321
02731-029
0
Figure 29. Voltage Noise Density vs. Frequency
0
14.9
44.7
29.8
59.6
89.4
74.5
119.2
104.3
FREQUENCY (Hz)
V
S
= ±2.5V
VOLTAGE NOISE DENSITY (nV/ Hz)
0 100908070605040302010
02731-030
Figure 30. Voltage Noise Density vs. Frequency
AD8605/AD8606/AD8608
Rev. J | Page 13 of 24
1800
1600
0
NUMBER OF AMPLIFIERS
800
600
400
200
1200
1000
1400
OFFSET VOLTAGE (µV) 300–200 –100 200
–300
V
S
= 2.7V
T
A
= 25°C
V
CM
= 0V TO 2.7V
0100
02731-031
Figure 31. Input Offset Voltage Distribution
COMMON-MODE VOLTAGE (V)
300
200
–300
0
2.7
INPUT OFFSET VOLTAGE (µV)
100
0
–200
–100
1.80.90
V
S
= 2. 7V
T
A
= 25°C
02731-032
Figure 32. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
LO AD CURRENT (mA)
1k
10
0.1
0.001 100.01
OUTPUT S
A
TUR
A
TION VOLTAGE (mV)
0.1
1
100
1
SOURCE
SINK
V
S
= 2.7V
T
A
= 25°C
02731-033
Figure 33. Output Saturation Voltage vs. Load Current
TEMPERATURE (°C)
2.680
2.675
2.650 5 20 1255035
OUTPUT VOLTAGE (V)
65 80 95 110
2.665
2.655
2.670
2.660
–10–25–40
V
S
= 2.7V
V
OH
@ 1mA LO AD
02731-034
Figure 34. Output Voltage Swing High vs. Temperature
0.045
0.025
0
0.035
0.015
0.005
0.030
0.040
0.020
0.010
TEM PE RATURE (°C)
520 1255035
OUTPUT V OLTAGE ( V )
65 80 95 110–10–25–40
V
S
= 2. 7V
V
OL
@ 1mA LOAD
02731-035
Figure 35. Output Voltage Swing Low vs. Temperature
FREQUENCY ( Hz )
10k 40M100k
GAIN (dB)
100
80
–100
60
40
20
0
–20
–40
–60
–80
225
180
–225
135
90
45
0
–45
–90
–135
–180
PHASE ( Deg rees)
1M 10M
02731-036
V
S
= 2.7V
R
L
= 2kΩ
C
L
= 20pF
Φ
M
= 52.5°
PHASE
GAIN
Figure 36. Open-Loop Gain and Phase vs. Frequency
AD8605/AD8606/AD8608
Rev. J | Page 14 of 24
FRE QUENC Y (Hz)
3.0
2.5
01k 10M10k
OUTPUT SWING (V p-p)
100k 1M
2.0
1.5
0.5
1.0
02731-037
V
S
= 2. 7V
V
IN
= 2. 6V p-p
T
A
= 25°C
R
L
= 2kΩ
A
V
= 1
Figure 37. Closed-Loop Output Voltage Swing vs. Frequency (FPBW)
FREQUENCY (Hz)
100
90
01k 100M10k 100k 1M 10M
80
70
20
60
50
30
10
40
A
V
= 100
A
V
= 10
A
V
= 1
V
S
= 2. 7V
02731-038
OUTPUT IMPE DANCE ( Ω)
Figure 38. Output Impedance vs. Frequency
CAPACI TANCE (pF )
60
50
010 1k100
SM
A
LL SIGN
A
L OVERSHOOT (%)
30
20
10
40
–OS
+OS
V
S
= 2. 7V
T
A
= 25°C
A
V
= 1
02731-039
Figure 39. Small Signal Overshoot vs. Load Capacitance
TI ME ( 1s/DIV)
V
S
= 2.7V
VOLTAGE NOISE (1µV/DIV)
02731-040
Figure 40. 0.1 Hz to 10 Hz Input Voltage Noise
TI ME ( 200ns/ DIV)
VOLTAGE (50mV/DI V)
02731-041
V
S
= ±1.35V
R
L
= 10kΩ
C
L
= 200pF
A
V
= 1
Figure 41. Small Signal Transient Response
TI ME ( 400ns/ DIV)
VOLTAGE (500mV/DIV)
V
S
= ±1.35V
R
L
= 10kΩ
C
L
= 200p F
A
V
= 1
02731-042
Figure 42. Large Signal Transient Response
AD8605/AD8606/AD8608
Rev. J | Page 15 of 24
APPLICATIONS INFORMATION
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change in polarity at the output of
the amplifier when a voltage that exceeds the maximum input
common-mode voltage drives the input.
Phase reversal can cause permanent damage to the amplifier; it
can also cause system lockups in feedback loops. The AD8605
does not exhibit phase reversal even for inputs exceeding the
supply voltage by more than 2 V.
MAXIMUM POWER DISSIPATION
Power dissipated in an IC causes the die temperature to
increase, which can affect the behavior of the IC and the
application circuit performance.
The absolute maximum junction temperature of the AD8605/
AD8606/AD8608 is 150°C. Exceeding this temperature could
damage or destroy the device.
The maximum power dissipation of the amplifier is calculated
according to
JA
A
J
DISS
TT
Pθ
−
=
where:
TJ is the junction temperature.
TA is the ambient temperature.
θJA is the junction-to-ambient thermal resistance.
Figure 44 compares the maximum power dissipation with
temperature for the various AD860x family packages.
INPUT OVERVOLTAGE PROTECTION
The AD8605 has internal protective circuitry. However, if the
voltage applied at either input exceeds the supplies by more
than 0.5 V, external resistors should be placed in series with
the inputs. The resistor values can be determined by
mA5≤
−
S
S
IN
R
VV
The remarkable low input offset current of the AD8605 (<1 pA)
allows the use of larger value resistors. With a 10 kΩ resistor at
the input, the output voltage has less than 10 nV of error voltage.
A 10 kΩ resistor has less than 13 nV/√Hz of thermal noise at
room temperature.
THD + NOISE
Total harmonic distortion is the ratio of the input signal in V rms
to the total harmonics in V rms throughout the spectrum.
Harmonic distortion adds errors to precision measurements
and adds unpleasant sonic artifacts to audio systems.
The AD8605 has a low total harmonic distortion. Figure 45 shows
that the AD8605 has less than 0.005% or −86 dB of THD + N
over the entire audio frequency range. The AD8605 is configured
in positive unity gain, which is the worst case, and with a load
of 10 kΩ.
TIME (4µs/DIV)
VOLTAGE (2V/DIV)
V
OUT
V
IN
V
S
= ±2.5V
V
IN
= 6V p-p
A
V
= 1
R
L
= 10kΩ
02731-043
Figure 43. No Phase Reversal
AMBIEN T TEMPERATURE (° C )
1.0
0.8
0
–45 130–20
POWER DI SSIP
A
TION (W)
30 80 105
0.6
0.4
0.2
1.7
1.8
1.6
1.4
1.2
02731-044
TSSOP-14
555
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
5-LEAD SO T-23
MSOP-8
SOIC-14
WLCSP-5
SOIC-8
Figure 44. Maximum Power Dissipation vs. Ambient Temperature
FRE QUENC Y ( Hz )
0.1
0.01
0.000120 20k100
THD + NOISE (%)
1k
0.001
10k
V
SY
= ±2.5V
A
V
= 1
B
W
= 80kHz
02731-045
Figure 45. THD + Noise vs. Frequency
AD8605/AD8606/AD8608
Rev. J | Page 16 of 24
TOTAL NOISE INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the
AD8605 make it the ideal amplifier for circuits with substantial
input source resistance, such as photodiodes. Input offset voltage
increases by less than 0.5 nV per 1 kΩ of source resistance at
room temperature and increases to 10 nV at 85°C. The total
noise density of the circuit is
()
SS
nn
TOTAL
nTRkRiee 4
2
2
,++=
where:
en is the input voltage noise density of the AD8605.
in is the input current noise density of the AD8605.
RS is the source resistance at the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (T = 273 + °C).
For example, with RS = 10 kΩ, the total voltage noise density is
roughly 15 nV/√Hz.
For RS < 3.9 kΩ, en dominates and en, TOTAL ≈ en.
The current noise of the AD8605 is so low that its total density does
not become a significant term unless RS is greater than 6 MΩ.
The total equivalent rms noise over a specific bandwidth is
expressed as
(
)
BWeE TOTALn
n,
=
where BW is the bandwidth in hertz.
Note that the previous analysis is valid for frequencies greater
than 100 Hz and assumes relatively flat noise, above 10 kHz.
For lower frequencies, flicker noise (1/f) must be considered.
CHANNEL SEPARATION
Channel separation, or inverse crosstalk, is a measure of the signal
feed from one amplifier (channel) to another on the same IC.
The AD8606 has a channel separation of greater than −160 dB
up to frequencies of 1 MHz, allowing the two amplifiers to
amplify ac signals independently in most applications.
CAPACITIVE LOAD DRIVE
The AD860x can drive large capacitive loads without oscillation.
Figure 47 shows the output of the AD8606 in response to a
200 mV input signal. In this case, the amplifier is configured
in positive unity gain, worst case for stability, while driving a
1000 pF load at its output. Driving larger capacitive loads in
unity gain can require the use of additional circuitry.
A snubber network, shown in Figure 48, helps reduce the signal
overshoot to a minimum and maintain stability. Although this
circuit does not recover the loss of bandwidth induced by large
capacitive loads, it greatly reduces the overshoot and ringing.
This method does not reduce the maximum output swing of the
amplifier.
CHANNEL SEPAR
A
TION (dB)
FREQUENCY (Hz) 10M1M100k10k1k100 100M
–20
0
–40
–60
–80
–100
–120
–140
–160
–180
02731-046
Figure 46. Channel Separation vs. Frequency
TI ME ( 10µs/ DIV)
VOLTAG E (100mV/ DIV)
02731-047
V
S
= ±2.5V
A
V
= 1
R
L
= 10kΩ
C
L
= 1000pF
Figure 47. AD8606 Capacitive Load Drive Without Snubber
R
S
C
S
R
L
C
L
V
+
V–
4
2
3
8
1
AD8605
V
IN
200mV
02731-049
Figure 48. Snubber Network Configuration
AD8605/AD8606/AD8608
Rev. J | Page 17 of 24
WAVELENGTH (nm)
3500
0350
INPUT BIAS CURRENT ( pA)
2500
3000
2000
500
1000
1500
450 550 650 750 850
1mW/cm
2
4000
4500
5000
3mW/cm
2
2mW/cm
2
02731-050
Figure 49 shows a scope of the output at the snubber circuit.
The overshoot is reduced from over 70% to less than 5%, and
the ringing is eliminated by the snubber. Optimum values for
RS and CS are determined experimentally.
TI M E ( 10µ s/ DIV)
VOL
T
A
GE (100mV/ DIV)
V
S
= ±2.5V
A
V
= 1
R
L
= 10kΩ
R
S
= 90Ω
C
L
= 1000pF
C
S
= 700p F
02731-048
Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination of
Varying Intensity and Wavelength
When the WLCSP package is assembled on the board with the
bump side of the die facing the PCB, reflected light from the
PCB surface is incident on active silicon circuit areas and results
in the increased IB. No performance degradation occurs due to
illumination of the backside (substrate) of the AD8605ACB.
The AD8605ACB is particularly sensitive to incident light with
wavelengths in the near infrared range (NIR, 700 nm to 1000 nm).
Photons in this waveband have a longer wavelength and lower
energy than photons in the visible (400 nm to 700 nm) and near
ultraviolet (NUV, 200 nm to 400 nm) bands; therefore, they can
penetrate more deeply into the active silicon. Incident light with
wavelengths greater than 1100 nm has no photoelectric effect
on the AD8605ACB because silicon is transparent to wavelengths
in this range. The spectral content of conventional light sources
varies. Sunlight has a broad spectral range, with peak intensity
in the visible band that falls off in the NUV and NIR bands;
fluorescent lamps have significant peaks in the visible but not
the NUV or NIR bands.
Figure 49. Capacitive Load Drive with Snubber
Table 5 summarizes a few optimum values for capacitive loads.
Table 5.
CL (pF) RS (Ω) CS (pF)
500 100 1000
1000 70 1000
2000 60 800
An alternate technique is to insert a series resistor inside the
feedback loop at the output of the amplifier. Typically, the value
of this resistor is approximately 100 Ω. This method also reduces
overshoot and ringing but causes a reduction in the maximum
output swing.
LIGHT SENSITIVITY
The AD8605ACB (WLCSP package option) is essentially a
silicon die with additional postfabrication dielectric and
intermetallic processing designed to contact solder bumps
on the active side of the chip. With this package type, the die
is exposed to ambient light and is subject to photoelectric
effects. Light sensitivity analysis of the AD8605ACB mounted
on standard PCB material reveals that only the input bias
current (IB) parameter is impacted when the package is
illuminated directly by high intensity light. No degradation in
electrical performance is observed due to illumination by low
intensity (0.1 mW/cm2) ambient light. Figure 50 shows that IB
increases with increasing wavelength and intensity of incident
light; IB can reach levels as high as 4500 pA at a light intensity of
3 mW/cm2 and a wavelength of 850 nm. The light intensities
shown in Figure 50 are not normal for most applications, that is,
even though direct sunlight can have intensities of 50 mW/cm2,
office ambient light can be as low as 0.1 mW/cm2.
Efforts have been made at a product level to reduce the effect of
ambient light; the under bump metal (UBM) has been designed
to shield the sensitive circuit areas on the active side (bump
side) of the die. However, if an application encounters any light
sensitivity with the AD8605ACB, shielding the bump side of the
WLCSP package with opaque material should eliminate this
effect. Shielding can be accomplished using materials such as
silica-filled liquid epoxies that are used in flip-chip underfill
techniques.
WLCSP ASSEMBLY CONSIDERATIONS
For detailed information on the WLCSP PCB assembly and
reliability, see Application Note AN-617, MicroCSP™ Wafer
Level Chip Scale Package.
AD8605/AD8606/AD8608
Rev. J | Page 18 of 24
I-V CONVERSION APPLICATIONS
PHOTODIODE PREAMPLIFIER APPLICATIONS
The low offset voltage and input current of the AD8605 make
it an excellent choice for photodiode applications. In addition,
the low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.
R
D
I
D
C
D
50pF
AD8605
V
OUT
PHOTODIODE V
OS
R
F
10MΩ
C
F
10pF
02731-051
Figure 51. Equivalent Circuit for Photodiode Preamp
The input bias current of the amplifier contributes an error
term that is proportional to the value of RF.
The offset voltage causes a dark current induced by the shunt
resistance of the Diode RD. These error terms are combined at
the output of the amplifier. The error voltage is written as
BF
D
F
OSO IR
R
R
VE +
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+= 1
Typically, RF is smaller than RD, thus RF/RD can be ignored.
At room temperature, the AD8605 has an input bias current of
0.2 pA and an offset voltage of 100 μV. Typical values of RD are
in the range of 1 GΩ.
For the circuit shown in Figure 51, the output error voltage is
approximately 100 μV at room temperature, increasing to about
1 mV at 85°C.
The maximum achievable signal bandwidth is
FF
t
MAX CR
f
f
π
2
=
where ft is the unity gain frequency of the amplifier.
AUDIO AND PDA APPLICATIONS
The low distortion and wide dynamic range of the AD860x
make it a great choice for audio and PDA applications,
including microphone amplification and line output buffering.
Figure 52 shows a typical application circuit for headphone/
line-out amplification.
R1 and R2 are used to bias the input voltage at half the supply,
which maximizes the signal bandwidth range. C1 and C2 are
used to ac couple the input signal. C1, R1, and R2 form a high-
pass filter whose corner frequency is 1/[2π(R1||R2)C1].
The high output current of the AD8606 allows it to drive heavy
resistive loads.
The circuit in Figure 52 is tested to drive a 16 Ω headphone. The
THD + N is maintained at approximately −60 dB throughout the
audio range.
5
V
4
2
3
8
1HEADPHONES
5V
4
6
5
8
7
C1
1µF
V1
500mV
1/2
AD8606
C3
100µF
1/2
AD8606
C4
100µF
C2
1µF
V2
500mV
02731-052
R1
20kΩ
R2
20kΩ
R7
20kΩ
R8
20kΩ
R4
20Ω
R3
1kΩ
R6
20Ω
R5
1kΩ
Figure 52. Single-Supply Headphone/Speaker Amplifier
AD8605/AD8606/AD8608
Rev. J | Page 19 of 24
INSTRUMENTATION AMPLIFIERS
The low offset voltage and low noise of the AD8605 make it an
ideal amplifier for instrumentation applications.
Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio. Figure 53 shows
a simple difference amplifier. Figure 54 shows the common-
mode rejection for a unity gain configuration and for a gain of 10.
Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.
AD8605
5V
V2
V1
R1
1kΩ
R3
1kΩ
R2
10kΩ
R4
10kΩ
V
OUT
R4
R3 R2
R1
=
V
OUT
= (V2 – V1)
R2
R1
02731-053
Figure 53. Difference Amplifier, AV = 10
FREQUENCY (Hz)
120
100
0
100 10M1k
CMRR (d B)
10k 100k 1M
60
40
20
80
A
V
= 10
V
SY
= ±2.5V
A
V
= 1
02731-054
Figure 54. Difference Amplifier CMRR vs. Frequency
DAC CONVERSION
The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.
Figure 55 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.
The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.
R2
AD8605
V
OS
R
F
C
F
R2 R2 V+
V–
02731-055
RRR
V
REF
Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer
To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
for the pole introduced by the output capacitance of the DAC.
Typical values for CF range from 10 pF to 30 pF; it can be adjusted
for the best frequency response. The total error at the output of
the op amp can be computed by
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+=
1Req
R
VE F
OSO
where Req is the equivalent resistance seen at the output of the
DAC. As previously mentioned, Req is code dependent and
varies with the input. A typical value for Req is 15 kΩ.
Choosing a feedback resistor of 10 kΩ yields an error of less
than 200 μV.
Figure 56 shows the implementation of a dual-stage buffer
at the output of a DAC. The first stage is used as a buffer.
Capacitor C1 with Req creates a low-pass filter, and thus,
provides phase lead to compensate for frequency response.
The second stage of the AD8606 is used to provide voltage
gain at the output of the buffer.
Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.
R
FB
V
DD
DB11
OUT1
AD7545
AGND
R
CS
R
P
V
IN
15V
V
OUT
V
REF
1/2
AD8606 1/2
AD8606
C1
33pF
02731-056
R4
5kΩ
R2
10kΩ
R1
10kΩ
R3
20kΩ
Figure 56. Bipolar Operation
AD8605/AD8606/AD8608
Rev. J | Page 20 of 24
OUTLINE DIMENSIONS
SEATING
PLANE
0.50 REF
0.87
0.37
0.36
0.35
0.17
0.14
0.12
0.21
0.50 0.20
0.50
0.23
0.18
0.14
BOTTO M VIE W
(BAL L SIDE UP)
0.94
0.90
0.86
1.33
1.29
1.25
TOP VIEW
(BALL S IDE DOW N)
BALL 1
IDENTIFIER
A
12
B
C
101607-A
Figure 57. 5-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-5-1)
Dimensions shown in millimeters
COMP LI ANT TO JEDE C STANDARDS MO-178- AA
121608-A
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.20
BSC
5
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
AD8605/AD8606/AD8608
Rev. J | Page 21 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 59. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 60. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
090706-B
SEATING
PLANE
0.50
BALL PITCH
1.480
1.430
1.380
1.825
1.775
1.725
0.27
0.24
0.21
0.380
0.355
0.330
0.340
0.320
0.300
0.675
0.595
0.515
BOTTOM VIEW
( BALL SIDE U P)
TOP VIEW
( BALL SIDE D OW N)
A
123
B
C
BALL 1
IDENTIFIER
Figure 61. 8-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-8-1)
Dimensions shown in millimeters
AD8605/AD8606/AD8608
Rev. J | Page 22 of 24
CONTROL LI NG DIM E NSIO NS ARE IN M ILLI M E T ERS; INCH DIM E NSIONS
(I N PARE NT HE S E S ) ARE RO UNDE D-OF F MI LL IMET ER EQ UIVAL ENTS FOR
REFE RE NCE ONLYAND ARE NOT APPROPRIAT E F OR USE IN DES IGN.
COMP LI ANT TO JE DE C S TANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 62. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
COMP LI ANT TO JEDE C S TANDARDS MO -153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BS C
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 63. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD8605/AD8606/AD8608
Rev. J | Page 23 of 24
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8605ACBZ-REEL −40°C to +125°C 5-Ball WLCSP CB-5-1 A1J
AD8605ACBZ-REEL7 −40°C to +125°C 5-Ball WLCSP CB-5-1 A1J
AD8605ART-REEL −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A
AD8605ART-REEL7 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A
AD8605ARTZ-R2 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A#
AD8605ARTZ-REEL −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A#
AD8605ARTZ-REEL7 −40°C to +125°C 5-Lead SOT-23 RJ-5 B3A#
AD8606ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A
AD8606ARMZ-R7 −40°C to +125°C 8-Lead MSOP RM-8 B6A#
AD8606ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B6A#
AD8606AR −40°C to +125°C 8-Lead SOIC_N R-8
AD8606AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8606AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
AD8606ACBZ-REEL −40°C to +125°C 8-Ball WLCSP CB-8-1 B6A#
AD8606ACBZ-REEL7 −40°C to +125°C 8-Ball WLCSP CB-8-1 B6A#
AD8608AR −40°C to +125°C 14-Lead SOIC_N R-14
AD8608AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8608AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARZ −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
AD8608ARU −40°C to +125°C 14-Lead TSSOP RU-14
AD8608ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
AD8608ARUZ −40°C to +125°C 14-Lead TSSOP RU-14
AD8608ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14
1 Z = RoHS Compliant Part, # denotes RoHS compliant product (except for CB-5-1) may be top or bottom marked.
AD8605/AD8606/AD8608
Rev. J | Page 24 of 24
NOTES
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02731-0-8/10(J)
