IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 1
DR018-0C 04/23/2004
Document Title
256Kx16 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No History Draft Date Remark
0A Initial Draft August 9,2001
0B Revise for typo on page 20 December 18,2001
0C Add Pb-free package April 23,2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
FEATURES
• Extended Data-Out (EDO) Page Mode access cycle
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 512 cycles /8 ms
• Refresh Mode: RAS-Only, CAS-before-RAS (CBR),
Hidden
• Single power supply:
5V ± 10% (IC41C16256)
3.3V ± 10% (IC41LV16256)
• Byte Write and Byte Read operation via two CAS
• Industrail Temperature Range -40oC to 85oC
•Pb-free package is available
DESCRIPTION
The ICSI IC41C16256 and IC41LV16256 is a 262,144 x 16-
bit high-performance CMOS Dynamic Random Access Memo-
ries. The IC41C16256 offer an accelerated cycle access
called EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as short
as 10 ns per 16-bit word. The Byte Write control, of upper and
lower byte, makes the IC41C16256 ideal for use in
16-, 32-bit wide data bus systems.
These features make the IC41C16256and IC41LV16256 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IC41C16256 is packaged in a 40-pin 400mil SOJ and
400mil TSOP-2.
IC41C16256
IC41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -25(5V) -35 -50 -60 Unit
Max. RAS Access Time (tRAC) 25355060ns
Max. CAS Access Time (tCAC) 8 10 14 15 ns
Max. Column Address Access Time (tAA) 12182530ns
Min. EDO Page Mode Cycle Time (tPC) 10122025ns
Min. Read/Write Cycle Time (tRC) 456090110ns
40-Pin SOJ
PIN CONFIGURATIONS
40-Pin TSOP-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
R
AS
NC
A0
A1
A2
A3
V
CC
GND
I/O1
5
I/O1
4
I/O1
3
I/O1
2
GND
I/O1
1
I/O1
0
I/O9
I/O8
NC
LCA
S
UCA
S
OE
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A8 Address Inputs
I/O0-15 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
Vcc Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
I/O0
I/O1
I/O2
I/O3
V
CC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
R
AS
NC
A0
A1
A2
A3
V
CC
GND
I/O1
5
I/O1
4
I/O1
3
I/O1
2
GND
I/O1
1
I/O1
0
I/O9
I/O8
NC
LCA
S
UCA
S
OE
A8
A7
A6
A5
A4
GND
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 3
DR018-0C 04/23/2004
FUNCTIONAL BLOCK DIAGRAM
OE
WE
L
CAS
U
CAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
262,144 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O1
5
RAS
RAS
A
0-A8
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41C16256
IC41LV16256
4Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
TRUTH TABLE
Function RASRAS
RASRAS
RAS LCASLCAS
LCASLCAS
LCAS UCASUCAS
UCASUCAS
UCAS WEWE
WEWE
WE OEOE
OEOE
OE Address tR/tCI/O
Standby H H H X X X High-Z
Read: Word L L L H L ROW/COL DOUT
Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write) L L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write
(1,2)
LLLH
→
LL
→
H ROW/COL DOUT, DIN
EDO Page-Mode Read
(2)
1st Cycle: L H
→
LH
→
L H L ROW/COL DOUT
2nd Cycle: L H
→
LH
→
L H L NA/COL DOUT
Any Cycle: L L
→
HL
→
H H L NA/NA DOUT
EDO Page-Mode Write
(1)
1st Cycle: L H
→
LH
→
L L X ROW/COL DIN
2nd Cycle: L H
→
LH
→
L L X NA/COL DIN
EDO Page-Mode 1st Cycle: L H
→
LH
→
LH
→
LL
→
H ROW/COL DOUT, DIN
Read-Write
(1,2)
2nd Cycle: L H
→
LH
→
LH
→
LL
→
H NA/COL DOUT, DIN
Hidden Refresh
(2)
Read L
→
H
→
L L L H L ROW/COL DOUT
Write L
→
H
→
L L L L X ROW/COL DOUT
RAS-Only Refresh L H H X X ROW/NA High-Z
CBR Refresh
(3)
H
→
L L L X X X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 5
DR018-0C 04/23/2004
Functional Description
The IC41C16256 and IC41LV16256 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are en-
tered 9 bits (A0-A8) at a time. The row address is latched
by the Row Address Strobe (RAS). The column address
is latched by the Column Address Strobe (CAS) .
The IC41C16256 and IC41LV16256 has two CAS controls,
LCAS and UCAS. The LCAS and UCAS inputs internally
generates a CAS signal functioning in an identical man-
ner to the single CAS input on the other 256K x 16
DRAMs. The key difference is that each CAS controls its
corresponding I/O tristate logic (in conjunction with OE
and WE and RAS). LCAS controls I/O0 through I/O7 and
UCAS controls I/O8 through I/O15.
The IC41C16256 and IC41LV16256 CAS function is
determined by the first CAS (LCAS or UCAS) transitioning
LOW and the last transitioning back HIGH. The two CAS
controls give the IC41C16256 both BYTE READ and
BYTE WRITE cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOE are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs first.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the
addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the CAS cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
IC41C16256
IC41LV16256
6Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
VTVoltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
VCC Supply Voltage 5V –1.0 to +7.0 V
3.3V –0.5 to +4.6
IOUT Output Current 50 mA
PDPower Dissipation 1 W
TACommercial Operation Temperature 0 to +70 °C
Industrial Operationg Temperature –40 to +85 °C
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TACommercial Ambient Temperature 0 — 70 °C
Industrial Ambient Temperature –40 — 85 °C
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
CIN1Input Capacitance: A0-A8 5 pF
CIN2Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 7
DR018-0C 04/23/2004
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V < VIN < Vcc –10 10 µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) –10 10 µA
0V < VOUT < Vcc
VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V
VOL Output Low Voltage Level IOL =+2.1mA — 0.4 V
ICC1Standby Current: TTL RAS, LCAS, UCAS > VIH Commerical 5V — 2 mA
Industrial 5V — 3
Commerical 3.3V — 1
Industrial 3.3V — 2
ICC2Standby Current: CMOS RAS, LCAS, UCAS > VCC – 0.2V 5V — 1 mA
3.3V — 0.5
ICC3Operating Current: RAS, LCAS, UCAS, -25 — 260 mA
Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -35 — 230
Average Power Supply Current -50 — 180
-60 — 170
ICC4Operating Current: RAS = VIL, LCAS, UCAS, -25 — 250 mA
EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -35 — 220
Average Power Supply Current -50 — 170
-60 — 160
ICC5Refresh Current: RAS Cycling, LCAS, UCAS > VIH -25 — 260 mA
RAS-Only(2,3) tRC = tRC (min.) -35 — 230
Average Power Supply Current -50 — 180
-60 — 170
ICC6Refresh Current: RAS, LCAS, UCAS Cycling -25 — 260 mA
CBR(2,3,5) tRC = tRC (min.) -35 — 230
Average Power Supply Current -50 — 180
-60 — 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
IC41C16256
IC41LV16256
8Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25 -35 -50 -60
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 45 — 60 — 90 — 110 — ns
tRAC Access Time from RAS(6, 7) — 25 — 35 — 50 — 60 ns
tCAC Access Time from CAS(6, 8, 15) —8 —10 —14—15ns
tAA Access Time from Column-Address(6) — 12 — 18 — 25 — 30 ns
tRAS RAS Pulse Width 25 10K 35 10K 50 10K 60 10K ns
tRP RAS Precharge Time 15 — 20 — 30 — 40 — ns
tCAS CAS Pulse Width(26) 4 10K 6 10K 8 10K 10 10K ns
tCP CAS Precharge Time(9, 25) 4— 5— 8—10—ns
tCSH CAS Hold Time (21) 25 — 35 — 50 — 60 — ns
tRCD RAS to CAS Delay Time(10, 20) 10 17 11 28 19 36 20 45 ns
tASR Row-Address Setup Time 0 — 0 — 0 — 0 — ns
tRAH Row-Address Hold Time 6 — 6 — 8 — 10 — ns
tASC Column-Address Setup Time(20) 0— 0— 0— 0—ns
tCAH Column-Address Hold Time(20) 5— 6— 8—10—ns
tAR Column-Address Hold Time 19 — 30 — 40 — 40 — ns
(referenced to RAS)
tRAD RAS to Column-Address Delay Time(11) 8201020 14251530ns
tRAL Column-Address to RAS Lead Time 12 — 18 — 25 — 30 — ns
tRPC RAS to CAS Precharge Time 0 — 0 — 0 — 0 — ns
tRSH RAS Hold Time(27) 7— 8— 14—15—ns
tCLZ CAS to Output in Low-Z(15, 29) 3— 3— 3— 3—ns
tCRP CAS to RAS Precharge Time(21) 5— 5— 5— 5—ns
tOD Output Disable Time(19, 28, 29) 2 12 3 12 3 12 3 12 ns
tOE Output Enable Time(15, 16) 08 010 015—15ns
tOEHC OE HIGH Hold Time from CAS HIGH 10 — 10 — 10 — 10 — ns
tOEP OE HIGH Pulse Width 10 — 10 — 10 — 10 — ns
tOES OE LOW to CAS HIGH Setup Time 5 — 5 — 5 — 5 — ns
tRCS Read Command Setup Time(17, 20) 0— 0— 0— 0—ns
tRRH Read Command Hold Time 0 — 0 — 0 — 0 — ns
(referenced to RAS)(12)
tRCH Read Command Hold Time 0 — 0 — 0 — 0 — ns
(referenced to CAS)(12, 17, 21)
tWCH Write Command Hold Time(17, 27) 5— 5— 8—10—ns
tWCR Write Command Hold Time 19 — 30 — 40 — 50 — ns
(referenced to RAS)(17)
tWP Write Command Pulse Width(17) 5— 5— 8—10—ns
tWPZ WE Pulse Widths to Disable Outputs 10 — 10 — 10 — 10 — ns
tRWL Write Command to RAS Lead Time(17) 7— 8— 14—15—ns
tCWL Write Command to CAS Lead Time(17, 21) 5— 8— 14—15—ns
tWCS Write Command Setup Time(14, 17, 20) 0— 0— 0— 0—ns
tDHR Data-in Hold Time (referenced to RAS) 19 — 30 — 40 — 40 — ns
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 9
DR018-0C 04/23/2004
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-25 -35 -50 -60
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units
tACH Column-Address Setup Time to CAS 15 — 15 — 15 — 15 — ns
Precharge during WRITE Cycle
tOEH OE Hold Time from WE during 5 — 8 — 10 — 15 — ns
READ-MODIFY-WRITE cycle(18)
tDS Data-In Setup Time(15, 22) 0— 0— 0— 0—ns
tDH Data-In Hold Time(15, 22) 5— 6— 8— 10—ns
tRWC READ-MODIFY-WRITE Cycle Time 65 — 80 — 125 — 140 — ns
tRWD RAS to WE Delay Time during 35 — 45 — 70 — 80 — ns
READ-MODIFY-WRITE Cycle(14)
tCWD CAS to WE Delay Time(14, 20) 17 — 25 — 34 — 36 — ns
tAWD Column-Address to WE Delay Time(14) 21 — 30 — 42 — 49 — ns
tPC EDO Page Mode READ or WRITE 10 — 12 — 20 — 25 — ns
Cycle Time(24)
tRASP RAS Pulse Width in EDO Page Mode 25 100K 35 100K 50 100K 50 100K ns
tCPA Access Time from CAS Precharge(15) —14 —21 —27 —34 ns
tPRWC EDO Page Mode READ-WRITE 32 — 40 — 47 — 56 — ns
Cycle Time(24)
tCOH Data Output Hold after CAS LOW 5— 5— 5— 5—ns
tOFF Output Buffer Turn-Off Delay from 3 15 3 15 3 15 3 15 ns
CAS or RAS(13,15,19, 29)
tWHZ Output Disable Delay from WE 3 15 3 15 3 15 3 15 ns
tCLCH Last CAS going LOW to First CAS 10 — 10 — 10 — 10 — ns
returning HIGH(23)
tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5— 8— 10— 10—ns
tCHR CAS Hold Time (CBR REFRESH)(30, 21) 7— 8— 10— 10—ns
tORD OE Setup Time prior to RAS during 0 — 0 — 0 — 0 — ns
HIDDEN REFRESH Cycle
tREF Refresh Period (512 Cycles) — 8 — 8 8 — 8 — ms
tTTransition Time (Rise or Fall)(2, 3) 1 50 1 50 1 50 1 50 ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);
VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
IC41C16256
IC41LV16256
10 Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 11
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READ CYCLE
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS tRC tRP
tAR
tCAH
tASC
tRAD tRAL
OE
I/O
WE
ADDRESS
U
CAS-LCAS
RAS
Row Column Row
Open Open
Valid Data
tCSH
tCAS
tRSH
tCRP tCLCH
tRCD
tRAHtASR
tRRH
tRCHtRCS
tAA
tCAC tOFF(1)
tRAC
tCLZ
tOES
tOE tOD
Undefine
d
Don’t Ca
re
IC41C16256
IC41LV16256
12 Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
U
CAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don’t Ca
re
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 13
DR018-0C 04/23/2004
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
R
P
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
U
CAS-LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid D
OUT
Valid D
IN
Undefine
d
Don’t Ca
re
IC41C16256
IC41LV16256
14 Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
EDO-PAGE-MODE READ CYCLE
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
t
RASP
t
R
P
ADDRESS
U
CAS/LCAS
RAS
Row Ro
w
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
C
P
t
CP
t
PC
(1)
t
ASR
t
RAH
t
RAD
t
AR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Open Op
en
Valid Data
t
AA
t
AA
t
CPA
t
CAC
t
CAC
t
RAC
t
COH
t
CLZ
t
OEP
t
OE
t
OES
t
OES
t
OD
t
OE
t
OEHC
Valid Data
t
RCH
t
RRH
t
AA
t
CPA
t
CAC
t
OFF
t
CLZ
Valid Data
t
OD
t
ASC
t
RCS
Undefine
d
Don’t Ca
re
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 15
DR018-0C 04/23/2004
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
ADDRESS
CAS/LCAS
RAS
Row Ro
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
t
ASR
t
RAH
t
RAD
t
AR
t
ACH
Column Column
t
ACH
t
ACH
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Valid Data
t
ASC
t
WCS
t
WCH
t
CWL
t
WP
t
WCS
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
DHR
t
WCR
t
WCS
t
WCH
t
CWL
t
WP
Valid Data
t
DS
t
DH
Valid Data
t
DS
t
RWL
t
DH
Don’t Ca
re
IC41C16256
IC41LV16256
16 Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
Note:
1. tPC is for LATE write cycles only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of
CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
tRASP tRP
ADDRESS
U
CAS/LCAS
RAS
Row Row
tCRP tRCD
tCSH tCP
tCAH
tCAS, tCLCH
tRAL
tRSH tCPtCP
tRAH
tRAD
tAR
tASR
Column Column
tCAHtCAH
Column
tASCtASC
tCAS, tCLCHtCAS, tCLCH
OE
I/O
WE
tASC
tRWD
tRCS tCWL
tWP
tAWD
tCWD
tDH
tDS
tCAC
tCLZ
tAWD
tCWD
tCWL
tWP tAWD
tCWD
tCWL
tRWL
tWP
Open Open
DINDOUT
tOE tOE tOE tOD tOEH
tOD tOD
tDH
tDS tCPA
tAA
tCAC
tCLZ
DINDOUT
tDH
tDS
tCAC
tCLZ
DINDOUT
tCPA
tAA
tRAC tAA
tPC / tPRWC(1)
Undefine
d
Don’t Ca
re
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 17
DR018-0C 04/23/2004
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP tRP
ADDRESS
U
CAS/LCAS
RAS
Row Row
tCRP tRCD
tPC
tCSH
tCP
tCAH
tCAS
tRAL
tRSH tCPtCP
tACH
tRAH
tRAD
tAR
tASR
Column (A) Column (N)
tCAHtCAH
Column (B)
tASCtASC
tCAS tCAS
OE
I/O
WE
tASC
tCAC
tRCH
tDH
Open Open
Valid Data (A)
tOE
tWCS
tCAC
tCOH
DIN
tCPA
tWCH
tRAC tAA
tPC
Valid Data (B)
tWHZ
tDS
tRCS
tAA
Don’t Ca
re
IC41C16256
IC41LV16256
18 Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RASRAS
RASRAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
U
CAS/LCAS
RAS
Row Column
Open Open
Valid Data
tCSH tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCStWPZ
tRCS
tAA
tCAC tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
U
CAS/LCAS
RAS
Row Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Undefine
d
Don’t Ca
re
Don’t Ca
re
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 19
DR018-0C 04/23/2004
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RAS
t
RP
t
RP
I/O
U
CAS/LCAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
tRAS tRAS
tRP
U
CAS/LCAS
RAS
tCRP tRCD tRSH tCHR
tAR
tASC
tRAD
ADDRESS Row Column
tRAHtASR tRAL tCAH
I/O Open Open
Valid Data
tAA
tCAC
tRAC
tCLZ tOFF
(2)
OE
tOE tORD tOD
Undefine
d
Don’t Ca
re
IC41C16256
IC41LV16256
20 Integrated Circuit Solution Inc.
DR018-0C 04/23/2004
ORDERING INFORMATION (Pb-free)
IC41C16256
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
25 IC41C16256-25K(G) 400mil SOJ(Pb-free)
IC41C16256-25T(G) 400mil TSOP-2(Pb-free)
35 IC41C16256-35K(G) 400mil SOJ(Pb-free)
IC41C16256-35T(G) 400mil TSOP-2(Pb-free)
50 IC41C16256-50K(G) 400mil SOJ(Pb-free)
IC41C16256-50T(G) 400mil TSOP-2(Pb-free)
60 IC41C16256-60K(G) 400mil SOJ(Pb-free)
IC41C16256-60T(G) 400mil TSOP-2(Pb-free)
ORDERING INFORMATION (Pb-free)
IC41C16256
Industrial Range: -40°C to 85°C
Speed (ns) Order Part No. Package
25 IC41C16256-25KI(G) 400mil SOJ(Pb-free)
IC41C16256-25TI(G) 400mil TSOP-2(Pb-free)
35 IC41C16256-35KI(G) 400mil SOJ(Pb-free)
IC41C16256-35TI(G) 400mil TSOP-2(Pb-free)
50 IC41C16256-50KI(G) 400mil SOJ(Pb-free)
IC41C16256-50TI(G) 400mil TSOP-2(Pb-free)
60 IC41C16256-60KI(G) 400mil SOJ(Pb-free)
IC41C16256-60TI(G) 400mil TSOP-2(Pb-free)
IC41C16256
IC41LV16256
Integrated Circuit Solution Inc. 21
DR018-0C 04/23/2004
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION (Pb-free)
IC41LV16256
Commercial Range: 0°C to 70°C
Speed (ns) Order Part No. Package
35 IC41LV16256-35K(G) 400mil SOJ(Pb-free)
IC41LV16256-35T(G) 400mil TSOP-2(Pb-free)
50 IC41LV16256-50K(G) 400mil SOJ(Pb-free)
IC41LV16256-50T(G) 400mil TSOP-2(Pb-free)
60 IC41LV16256-60K(G) 400mil SOJ(Pb-free)
IC41LV16256-60T(G) 400mil TSOP-2(Pb-free)
ORDERING INFORMATION (Pb-free)
IC41LV16256
Industrial Range: -40°C to 85°C
Speed (ns) Order Part No. Package
35 IC41LV16256-35KI(G) 400mil SOJ(Pb-free)
IC41LV16256-35TI(G) 400mil TSOP-2(Pb-free)
50 IC41LV16256-50KI(G) 400mil SOJ(Pb-free)
IC41LV16256-50TI(G) 400mil TSOP-2(Pb-free)
60 IC41LV16256-60KI(G) 400mil SOJ(Pb-free)
IC41LV16256-60TI(G) 400mil TSOP-2(Pb-free)