MM74HCT273N_NL - Fairchild Semiconductor

Februa ry 198 4

Revised May 2005

MM74HCT273 Octal D-Type Flip-Flop wit h Clear

MM74HCT273

Octal D-Type Flip-Flop with Clear

General Descript ion

The MM74HCT273 utilizes advanced silicon-gate CMOS

technology. It has an input threshold and output drive simi-

lar to LS-TTL with the low standby power of CMOS.

These positive edge-triggered flip-flops have a common

clock and clear- indepe ndent Q outp uts. Data on a D input,

having the specified set-up an d hold time, is tra nsferred to

the corresp onding Q output on th e po siti ve- goin g tr ansition

of the clock pulse. The asynchronous clear forces all out-

puts LOW when it is LOW.

All inputs to this device are protec ted from dama ge due to

electrostatic discharge by diodes to VCC and ground.

MM74HCT devices are intended to interface TTL and

NMOS components to CMOS components. These parts

can be used as plug-in replacements to reduce system

power consumption in existing designs.

Features

■Typical propagation delay: 20 ns

■Low quiescent current: 80

A maximum (74HCT series)

■Fanout of 10 LS-TTL loads

Ordering Code:

Devices also available in Tape and R eel. Specify by ap pending th e s uffix let t er “X” to the or dering code.

Connection Diagram

Pin Assignments for DIP, S OIC, SOP an d TSSOP

Top View

Orde r Number Package

Number Packag e Desc ri ption

MM74HCT273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

MM74HCT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HCT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM7 4HCT273N N20A 20-Lead Plasti c Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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MM74HCT273

Tr uth Table (Each Flip-Flop)

HIGH Level (steady-state)

LOW Level (steady-state)

Don’t Care

Transition from LOW-to-HIGH level

The level of Q before the indicated steady-state input

conditions were established.

Logic Diagram

Inputs Outputs

Clear Clock D Q

LXXL

HLXQ0

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MM74HCT273

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unl es s ot herwise s pecified all v olt ages are ref erenced t o ground.

Note 3: Power diss ipation tem per ature der ating—plastic “N” package:



mW/

C from 65

C to 85

DC Electrical Characteristics

VCC

10% unless otherwise specified

Note 4: Measured per pin, all other inputs held at VCC or GND.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Voltage (VIN)



1.5V to VCC



1.5V

DC Output Voltage (VOUT)



0.5V to VCC



0.5V

Clamp Diode Current (IIK, IOK)

20 mA

DC Output Current, per Pin (IOUT)

25 mA

DC VCC or GND Current, per Pin (ICC)

50 mA

Storage Temperature Range (TSTG)



C to



150

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds ) 260

Min Max Units

Supply Voltage (VCC)4.55.5V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operati ng Temperature Range (TA)





Input Rise or Fall Times

(tr, tf) 500 ns

Symbol Parameter Conditions TA



C to 85



C to 125

CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0 2.0 2.0 V

Input V olt age

VIL Maximum LOW Level 0.8 0.8 0.8 V

Input V olt age

VOH Minimum HIGH Level VIN

VIH or VIL

Output Voltage |IOUT|

CC VCC



0.1 VCC



0.1 VCC



0.1 V

|IOUT|

4.0 mA, VCC

4.5V 4.2 3.98 3.84 3.7 V

|IOUT|

4.8 mA, VCC

5.5V 5.2 4.98 4.84 4.7 V

VOL Minimum LOW Level VIN

VIH or VIL

Voltage |IOUT|

A 0 0.1 0.1 0.1 V

|IOUT|

4.0 mA, VCC

4.5V 0.2 0.26 0.33 0.4 V

|IOUT|

4.8 mA, VCC

5.5V 0.2 0.26 0.33 0.4 V

IIN Maximum Input VIN

VCC or GND,

0.1

1.0

Current VIH or VIL

ICC Maximum Quiescent VIN

VCC or GND 8 80 160

Supply Current IOUT

VIN

2.4V or 0.5V (Note 4) 0.6 0.8 0.9 mA

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MM74HCT273

AC Electrical Characteristics

VCC

5V, TA

C, CL

15 pF, tr

6 ns

AC Electrical Characteristics

VCC

5.0V

10%, CL

50 pF, tr

6 ns unless otherwise specified

Note 5: CPD determines the no load dynam ic pow er cons um ption, PD

CPD VCC2 f



ICC VCC, and t he no load dy namic cu rrent con su m pt ion,

CPD VCC2 f



ICC.

Symbol Parameter Conditions Typ Guaranteed Units

Limits

fMAX Maximum Operating Frequency 68 30 MHz

tPHL, tPLH Maximum Propagation Delay from Clock to Q 18 30 ns

tPHL, tPLH Maximum Propagation Delay from Clear to Q 21 30 ns

tREM Minimum Removal Time, Clear to Clock



15ns

tSMinimum Set-Up Time D to Clock 6 20 ns

tHMinimum Hold Time Clock to D



35ns

tWMinimu m Pu lse Width Clock or Cl ear 10 16 ns

Symbol Parameter Conditions TA



C to 85



C to 125

CUnits

Typ Guaranteed Limits

fMAX Maximum Operating 68 27 21 18 MHz

Frequency

tPHL, tPLH Maximum Propagation 22 37 46 56 ns

Delay from Clock to Q

tPHL, tPLH Maximum Propagation 25 35 44 52 ns

Delay from Clear to Q

tREM Minimum Removal



15 6 7 ns

Time Clear to Clock

tSMinimum Set-Up Time 6 20 25 30 ns

D to Clock

tHMinimum Hold Time



35 5 5 ns

Clock to D

tWMinimum Pulse Width 10 16 25 30 ns

Clock or Clear

tr, tfMaximum Input Rise 500 500 500 ns

and Fall Time, Clock

tTHL, tTLH Maximum Output Rise 11 15 19 22 ns

and Fall Time

CPD Power Dissipation (Per Flip-Flop) 50 pF

Capacitance (Note 5)

CIN Maximum Input 6 10 10 10 pF

Capacitance

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MM74HCT273

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

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MM74HCT273

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Pack age (SOP), EIAJ TYPE II, 5 .3mm Wide

Package Number M20D

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MM74HCT273

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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MM74HCT273 Octal D-Type Flip-Flop with Clear

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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