© 2005 Fairchild Semiconductor Corporation DS005760 www.fairchildsemi.com
Februa ry 198 4
Revised May 2005
MM74HCT273 Octal D-Type Flip-Flop wit h Clear
MM74HCT273
Octal D-Type Flip-Flop with Clear
General Descript ion
The MM74HCT273 utilizes advanced silicon-gate CMOS
technology. It has an input threshold and output drive simi-
lar to LS-TTL with the low standby power of CMOS.
These positive edge-triggered flip-flops have a common
clock and clear- indepe ndent Q outp uts. Data on a D input,
having the specified set-up an d hold time, is tra nsferred to
the corresp onding Q output on th e po siti ve- goin g tr ansition
of the clock pulse. The asynchronous clear forces all out-
puts LOW when it is LOW.
All inputs to this device are protec ted from dama ge due to
electrostatic discharge by diodes to VCC and ground.
MM74HCT devices are intended to interface TTL and
NMOS components to CMOS components. These parts
can be used as plug-in replacements to reduce system
power consumption in existing designs.
Features
■Typical propagation delay: 20 ns
■Low quiescent current: 80
P
A maximum (74HCT series)
■Fanout of 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and R eel. Specify by ap pending th e s uffix let t er “X” to the or dering code.
Connection Diagram
Pin Assignments for DIP, S OIC, SOP an d TSSOP
Top View
Orde r Number Package
Number Packag e Desc ri ption
MM74HCT273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HCT273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM7 4HCT273N N20A 20-Lead Plasti c Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide